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\chapter{RISC-V Assembly Programmer's Handbook}
\label{assembly}
This chapter is a placeholder for an assembly programmer's manual.
Tables~\ref{pseudos} and \ref{csr-pseudos} contain a listing of standard
RISC-V pseudoinstructions.
\begin{table}[h]
\begin{small}
\begin{center}
\begin{tabular}{l l l}
Pseudoinstruction & Base Instruction(s) & Meaning \\ \hline
\multirow{2}{*}{\tt la rd, symbol} & {\tt auipc rd, symbol[31:12]} & \multirow{2}{*}{Load address} \\
& {\tt addi rd, rd, symbol[11:0]} \\
\multirow{2}{*}{\tt l\{b|h|w|d\} rd, symbol} & {\tt auipc rd, symbol[31:12]} & \multirow{2}{*}{Load global} \\
& {\tt l\{b|h|w|d\} rd, symbol[11:0](rd)} \\
\multirow{2}{*}{\tt s\{b|h|w|d\} rd, symbol, rt} & {\tt auipc rt, symbol[31:12]} & \multirow{2}{*}{Store global} \\
& {\tt s\{b|h|w|d\} rd, symbol[11:0](rt)} \\
\multirow{2}{*}{\tt fl\{w|d\} rd, symbol, rt} & {\tt auipc rt, symbol[31:12]} & \multirow{2}{*}{Floating-point load global} \\
& {\tt fl\{w|d\} rd, symbol[11:0](rt)} \\
\multirow{2}{*}{\tt fs\{w|d\} rd, symbol, rt} & {\tt auipc rt, symbol[31:12]} & \multirow{2}{*}{Floating-point store global} \\
& {\tt fs\{w|d\} rd, symbol[11:0](rt)} \\
\hline
{\tt nop} & {\tt addi x0, x0, 0} & No operation \\
{\tt li rd, immediate} & {\em Myriad sequences} & Load immediate \\
{\tt mv rd, rs} & {\tt addi rd, rs, 0} & Copy register \\
{\tt not rd, rs} & {\tt xori rd, rs, -1} & One's complement \\
{\tt neg rd, rs} & {\tt sub rd, x0, rs} & Two's complement \\
{\tt negw rd, rs} & {\tt subw rd, x0, rs} & Two's complement word \\
{\tt sext.w rd, rs} & {\tt addiw rd, rs, 0} & Sign extend word \\
{\tt seqz rd, rs} & {\tt sltiu rd, rs, 1} & Set if $=$ zero \\
{\tt snez rd, rs} & {\tt sltu rd, x0, rs} & Set if $\neq$ zero \\
{\tt sltz rd, rs} & {\tt slt rd, rs, x0} & Set if $<$ zero \\
{\tt sgtz rd, rs} & {\tt slt rd, x0, rs} & Set if $>$ zero \\
\hline
{\tt fmv.s rd, rs} & {\tt fsgnj.s rd, rs, rs} & Copy single-precision register \\
{\tt fabs.s rd, rs} & {\tt fsgnjx.s rd, rs, rs} & Single-precision absolute value \\
{\tt fneg.s rd, rs} & {\tt fsgnjn.s rd, rs, rs} & Single-precision negate \\
{\tt fmv.d rd, rs} & {\tt fsgnj.d rd, rs, rs} & Copy double-precision register \\
{\tt fabs.d rd, rs} & {\tt fsgnjx.d rd, rs, rs} & Double-precision absolute value \\
{\tt fneg.d rd, rs} & {\tt fsgnjn.d rd, rs, rs} & Double-precision negate \\
\hline
{\tt beqz rs, offset} & {\tt beq rs, x0, offset} & Branch if $=$ zero \\
{\tt bnez rs, offset} & {\tt bne rs, x0, offset} & Branch if $\neq$ zero \\
{\tt blez rs, offset} & {\tt bge x0, rs, offset} & Branch if $\leq$ zero \\
{\tt bgez rs, offset} & {\tt bge rs, x0, offset} & Branch if $\geq$ zero \\
{\tt bltz rs, offset} & {\tt blt rs, x0, offset} & Branch if $<$ zero \\
{\tt bgtz rs, offset} & {\tt blt x0, rs, offset} & Branch if $>$ zero \\
\hline
{\tt bgt rs, rt, offset} & {\tt blt rt, rs, offset} & Branch if $>$ \\
{\tt ble rs, rt, offset} & {\tt bge rt, rs, offset} & Branch if $\leq$ \\
{\tt bgtu rs, rt, offset} & {\tt bltu rt, rs, offset} & Branch if $>$, unsigned \\
{\tt bleu rs, rt, offset} & {\tt bgeu rt, rs, offset} & Branch if $\leq$, unsigned \\
\hline
{\tt j offset} & {\tt jal x0, offset} & Jump \\
{\tt jal offset} & {\tt jal x1, offset} & Jump and link \\
{\tt jr rs} & {\tt jalr x0, rs, 0} & Jump register \\
{\tt jalr rs} & {\tt jalr x1, rs, 0} & Jump and link register \\
{\tt ret} & {\tt jalr x0, x1, 0} & Return from subroutine \\
\multirow{2}{*}{\tt call offset} & {\tt auipc x6, offset[31:12]} & \multirow{2}{*}{Call far-away subroutine} \\
& {\tt jalr x1, x6, offset[11:0]} \\
\multirow{2}{*}{\tt tail offset} & {\tt auipc x6, offset[31:12]} & \multirow{2}{*}{Tail call far-away subroutine} \\
& {\tt jalr x0, x6, offset[11:0]} & \\
\hline
{\tt fence} & {\tt fence iorw, iorw} & Fence on all memory and I/O \\
\hline
\end{tabular}
\end{center}
\end{small}
\caption{RISC-V pseudoinstructions.}
\label{pseudos}
\end{table}
\begin{table}[h]
\begin{small}
\begin{center}
\begin{tabular}{l l l}
Pseudoinstruction & Base Instruction & Meaning \\ \hline
{\tt rdinstret[h] rd} & {\tt csrrs rd, instret[h], x0} & Read instructions-retired counter \\
{\tt rdcycle[h] rd} & {\tt csrrs rd, cycle[h], x0} & Read cycle counter \\
{\tt rdtime[h] rd} & {\tt csrrs rd, time[h], x0} & Read real-time clock \\
\hline
{\tt csrr rd, csr} & {\tt csrrs rd, csr, x0} & Read CSR \\
{\tt csrw csr, rs} & {\tt csrrw x0, csr, rs} & Write CSR \\
{\tt csrs csr, rs} & {\tt csrrs x0, csr, rs} & Set bits in CSR \\
{\tt csrc csr, rs} & {\tt csrrc x0, csr, rs} & Clear bits in CSR \\
\hline
{\tt csrwi csr, imm} & {\tt csrrwi x0, csr, imm} & Write CSR, immediate \\
{\tt csrsi csr, imm} & {\tt csrrsi x0, csr, imm} & Set bits in CSR, immediate \\
{\tt csrci csr, imm} & {\tt csrrci x0, csr, imm} & Clear bits in CSR, immediate \\
\hline
{\tt frcsr rd} & {\tt csrrs rd, fcsr, x0} & Read FP control/status register \\
{\tt fscsr rd, rs} & {\tt csrrw rd, fcsr, rs} & Swap FP control/status register \\
{\tt fscsr rs} & {\tt csrrw x0, fcsr, rs} & Write FP control/status register \\
\hline
{\tt frrm rd} & {\tt csrrs rd, frm, x0} & Read FP rounding mode \\
{\tt fsrm rd, rs} & {\tt csrrw rd, frm, rs} & Swap FP rounding mode \\
{\tt fsrm rs} & {\tt csrrw x0, frm, rs} & Write FP rounding mode \\
{\tt fsrmi rd, imm} & {\tt csrrwi rd, frm, imm} & Swap FP rounding mode, immediate \\
{\tt fsrmi imm} & {\tt csrrwi x0, frm, imm} & Write FP rounding mode, immediate \\
\hline
{\tt frflags rd} & {\tt csrrs rd, fflags, x0} & Read FP exception flags \\
{\tt fsflags rd, rs} & {\tt csrrw rd, fflags, rs} & Swap FP exception flags \\
{\tt fsflags rs} & {\tt csrrw x0, fflags, rs} & Write FP exception flags \\
{\tt fsflagsi rd, imm} & {\tt csrrwi rd, fflags, imm} & Swap FP exception flags, immediate \\
{\tt fsflagsi imm} & {\tt csrrwi x0, fflags, imm} & Write FP exception flags, immediate \\
\hline
\end{tabular}
\end{center}
\end{small}
\caption{Pseudoinstructions for accessing control and status registers.}
\label{csr-pseudos}
\end{table}
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