<<<
[#insns-cm_mvsa01,reftext="Move a0-a1 into two different s0-s7 registers"]
=== cm.mvsa01

Synopsis::
Move a0-a1 into two registers of s0-s7

Mnemonic::
cm.mvsa01 _r1s'_, _r2s'_

Encoding (RV32, RV64)::
[wavedrom, , svg]
....
{reg:[
    { bits:  2, name: 0x2,      attr: ['C2'] },
    { bits:  3, name: 'r2s\'',  attr: [] },
    { bits:  2, name: 0x1,      attr: [] },
    { bits:  3, name: 'r1s\'',  attr: [] },
    { bits:  3, name: 0x3,      attr: [] },
    { bits:  3, name: 0x5,      attr: ['FUNCT3'] },
],config:{bits:16}}
....

[NOTE]
  For the encoding to be legal _r1s'_ != _r2s'_.

Assembly Syntax::

[source,sail]
--
cm.mvsa01 r1s', r2s'
--

Description::
This instruction moves _a0_ into _r1s'_ and _a1_ into _r2s'_.  _r1s'_ and _r2s'_ must be different.
The execution is atomic, so it is not possible to observe state where only one of _r1s'_ or _r2s'_ has been updated.

The encoding uses _sreg_ number specifiers instead of _xreg_ number specifiers to save encoding space. 
The mapping between them is specified in the pseudo-code below.

[NOTE]

  The _s_ register mapping is taken from the UABI, and may not match the currently unratified EABI. _cm.mvsa01.e_ may be included in the future.

Prerequisites::
None

32-bit equivalent::
No direct equivalent encoding exists.

Operation::
[source,sail]
--
//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
if (RV32E && (r1sc>1 || r2sc>1)) {
  reserved();
}
xreg1 = {r1sc[2:1]>0,r1sc[2:1]==0,r1sc[2:0]};
xreg2 = {r2sc[2:1]>0,r2sc[2:1]==0,r2sc[2:0]};
X[xreg1] = X[10];
X[xreg2] = X[11];
--

include::Zcmp_footer.adoc[]

