<<< [#insns-c_lh,reftext="Load signed halfword, 16-bit encoding"] === c.lh Synopsis:: Load signed halfword, 16-bit encoding Mnemonic:: c.lh _rd'_, _uimm_(_rs1'_) Encoding (RV32, RV64):: [wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rd\'' }, { bits: 1, name: 'uimm[1]' }, { bits: 1, name: 0x1 }, { bits: 3, name: 'rs1\'' }, { bits: 3, name: 0x1 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} .... include::c_lhsh_imm_offset.adoc[] Description:: This instruction loads a halfword from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting halfword is sign extended to XLEN bits and is written to _rd'_. [NOTE] _rd'_ and _rs1'_ are from the standard 8-register set x8-x15. Prerequisites:: None 32-bit equivalent:: <> Operation:: [source,sail] -- //This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]); -- include::Zcb_footer.adoc[]