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"b9f09a50481f55b2f93437bb3ab9036b" }, "model/riscv_vmem.sail": { "md5": "5e237446ac5b7e3c48f0889551e1b4b9" }, "model/riscv_vmem_common.sail": { "md5": "6b1fff043a8b80fa02642ea95e9c5447" }, "model/riscv_vmem_pte.sail": { "md5": "71712b3ec2f2174969efdc60874773d2" }, "model/riscv_vmem_ptw.sail": { "md5": "22f5ea78903c175265ee9c805094d5b4" }, "model/riscv_vmem_tlb.sail": { "md5": "23b5ec16d7e7830212fc87b031e61e67" }, "model/riscv_vmem_types.sail": { "md5": "da62dea8c464357edfb10ecca74ba5c1" }, "model/riscv_vreg_type.sail": { "md5": "85755a28bf739cd052790f4b3083e913" }, "model/riscv_xlen64.sail": { "md5": "974842de167c0af1f8c575e09a64218c" } }, "functions": { "Architecture_of_num": { "function": { "number": 0, "source": "Architecture_of_num arg# = $[complete] match arg# {\n 0 => RV32,\n 1 => RV64,\n _ => RV128\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RV32,\n 1 => RV64,\n _ => RV128\n}" } }, "ExtStatus_of_num": { "function": { "number": 0, "source": "ExtStatus_of_num arg# = $[complete] match arg# {\n 0 => Off,\n 1 => Initial,\n 2 => Clean,\n _ => Dirty\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => Off,\n 1 => Initial,\n 2 => Clean,\n _ => Dirty\n}" } }, "FRegStr": { "function": { "number": 0, "source": "function FRegStr(r) = BitStr(r)", "pattern": { "type": "id", "id": "r" }, "body": "BitStr(r)" }, "links": [ { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "GPRstr": { "function": { "number": 0, "source": "function GPRstr(i: bits(5)) -> string = GPRstrs[unsigned(i)]", "pattern": { "type": "id", "id": "i" }, "body": "GPRstrs[unsigned(i)]" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_analysis.sail", "loc": [ 1048, 1056 ] } ] }, "InterruptType_of_num": { "function": { "number": 0, "source": "InterruptType_of_num arg# = $[complete] match arg# {\n 0 => I_U_Software,\n 1 => I_S_Software,\n 2 => I_M_Software,\n 3 => I_U_Timer,\n 4 => I_S_Timer,\n 5 => I_M_Timer,\n 6 => I_U_External,\n 7 => I_S_External,\n _ => I_M_External\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => I_U_Software,\n 1 => I_S_Software,\n 2 => I_M_Software,\n 3 => I_U_Timer,\n 4 => I_S_Timer,\n 5 => I_M_Timer,\n 6 => I_U_External,\n 7 => I_S_External,\n _ => I_M_External\n}" } }, "MemoryOpResult_add_meta": { "function": { "number": 0, "source": "function MemoryOpResult_add_meta(r, m) = match r {\n MemValue(v) => MemValue(v, m),\n MemException(e) => MemException(e)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "r" }, { "type": "id", "id": "m" } ] }, "body": "match r {\n MemValue(v) => MemValue(v, m),\n MemException(e) => MemException(e)\n}" }, "links": [ { "type": "function", "id": "MemException", "file": "model/riscv_sys_control.sail", "loc": [ 21927, 21939 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_sys_control.sail", "loc": [ 21890, 21898 ] } ] }, "MemoryOpResult_drop_meta": { "function": { "number": 0, "source": "function MemoryOpResult_drop_meta(r) = match r {\n MemValue(v, m) => MemValue(v),\n MemException(e) => MemException(e)\n}", "pattern": { "type": "id", "id": "r" }, "body": "match r {\n MemValue(v, m) => MemValue(v),\n MemException(e) => MemException(e)\n}" }, "links": [ { "type": "function", "id": "MemException", "file": "model/riscv_sys_control.sail", "loc": [ 22154, 22166 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_sys_control.sail", "loc": [ 22120, 22128 ] } ] }, "PPNs_of_PTE": { "function": { "number": 0, "source": "function PPNs_of_PTE(sv_params : SV_Params, pte : bits(64)) -> bits(64) = {\n let mask : bits(64) = zero_extend(ones(sv_params.pte_PPNs_size_bits));\n (pte >> sv_params.pte_PPNs_lsb_index) & mask\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "pte" } ] }, "body": " let mask : bits(64) = zero_extend(ones(sv_params.pte_PPNs_size_bits));\n (pte >> sv_params.pte_PPNs_lsb_index) & mask" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem_pte.sail", "loc": [ 1539, 1550 ] }, { "type": "function", "id": "ones", "file": "model/riscv_vmem_pte.sail", "loc": [ 1551, 1555 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] } ] }, "PmpAddrMatchType_of_num": { "function": { "number": 0, "source": "PmpAddrMatchType_of_num arg# = $[complete] match arg# {\n 0 => OFF,\n 1 => TOR,\n 2 => NA4,\n _ => NAPOT\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => OFF,\n 1 => TOR,\n 2 => NA4,\n _ => NAPOT\n}" } }, "Privilege_of_num": { "function": { "number": 0, "source": "Privilege_of_num arg# = $[complete] match arg# {\n 0 => User,\n 1 => Supervisor,\n _ => Machine\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => User,\n 1 => Supervisor,\n _ => Machine\n}" } }, "RegStr": { "function": { "number": 0, "source": "function RegStr(r) = BitStr(r)", "pattern": { "type": "id", "id": "r" }, "body": "BitStr(r)" }, "links": [ { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "Retired_of_num": { "function": { "number": 0, "source": "Retired_of_num arg# = $[complete] match arg# {\n 0 => RETIRE_SUCCESS,\n _ => RETIRE_FAIL\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RETIRE_SUCCESS,\n _ => RETIRE_FAIL\n}" } }, "SATPMode_of_num": { "function": { "number": 0, "source": "SATPMode_of_num arg# = $[complete] match arg# {\n 0 => Sbare,\n 1 => Sv32,\n 2 => Sv39,\n _ => Sv48\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => Sbare,\n 1 => Sv32,\n 2 => Sv39,\n _ => Sv48\n}" } }, "TrapVectorMode_of_num": { "function": { "number": 0, "source": "TrapVectorMode_of_num arg# = $[complete] match arg# {\n 0 => TV_Direct,\n 1 => TV_Vector,\n _ => TV_Reserved\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => TV_Direct,\n 1 => TV_Vector,\n _ => TV_Reserved\n}" } }, "__ReadRAM_Meta": { "function": { "number": 0, "source": "function __ReadRAM_Meta(addr, width) = ()", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": "()" } }, "__WriteRAM_Meta": { "function": { "number": 0, "source": "function __WriteRAM_Meta(addr, width, meta) = ()", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "meta" } ] }, "body": "()" } }, "__id": { "function": { "number": 0, "source": "__id x : int('n) = x", "pattern": { "type": "id", "id": "x" }, "body": "x" } }, "_shl_int_general": { "function": { "number": 0, "source": "_shl_int_general (m : int, n : int) = if gteq_int(n, 0) then _shl_int(m, n) else _shr_int(m, negate_atom(n))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "n" } ] }, "body": "if gteq_int(n, 0) then _shl_int(m, n) else _shr_int(m, negate_atom(n))" } }, "_shr_int_general": { "function": { "number": 0, "source": "_shr_int_general (m : int, n : int) = if gteq_int(n, 0) then _shr_int(m, n) else _shl_int(m, negate_atom(n))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "n" } ] }, "body": "if gteq_int(n, 0) then _shr_int(m, n) else _shl_int(m, negate_atom(n))" } }, "a64_barrier_domain_of_num": { "function": { "number": 0, "source": "a64_barrier_domain_of_num arg# = $[complete] match arg# {\n 0 => A64_FullShare,\n 1 => A64_InnerShare,\n 2 => A64_OuterShare,\n _ => A64_NonShare\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => A64_FullShare,\n 1 => A64_InnerShare,\n 2 => A64_OuterShare,\n _ => A64_NonShare\n}" } }, "a64_barrier_type_of_num": { "function": { "number": 0, "source": "a64_barrier_type_of_num arg# = $[complete] match arg# {\n 0 => A64_barrier_all,\n 1 => A64_barrier_LD,\n _ => A64_barrier_ST\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => A64_barrier_all,\n 1 => A64_barrier_LD,\n _ => A64_barrier_ST\n}" } }, "accessToFault": { "function": { "number": 0, "source": "function accessToFault(acc : AccessType(ext_access_type)) -> ExceptionType =\n match acc {\n Read(_) => E_Load_Access_Fault(),\n Write(_) => E_SAMO_Access_Fault(),\n ReadWrite(_) => E_SAMO_Access_Fault(),\n Execute() => E_Fetch_Access_Fault(),\n }", "pattern": { "type": "id", "id": "acc" }, "body": "match acc {\n Read(_) => E_Load_Access_Fault(),\n Write(_) => E_SAMO_Access_Fault(),\n ReadWrite(_) => E_SAMO_Access_Fault(),\n Execute() => E_Fetch_Access_Fault(),\n }" }, "links": [ { "type": "function", "id": "E_Fetch_Access_Fault", "file": "model/riscv_pmp_control.sail", "loc": [ 4037, 4057 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_pmp_control.sail", "loc": [ 3994, 4013 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_pmp_control.sail", "loc": [ 3951, 3970 ] }, { "type": "function", "id": "E_Load_Access_Fault", "file": "model/riscv_pmp_control.sail", "loc": [ 3908, 3927 ] } ] }, "accessType_to_str": { "function": { "number": 0, "source": "function accessType_to_str (a) =\n match (a) {\n Read(_) => \"R\",\n Write(_) => \"W\",\n ReadWrite(_, _) => \"RW\",\n Execute() => \"X\"\n }", "pattern": { "type": "id", "id": "a" }, "body": "match (a) {\n Read(_) => \"R\",\n Write(_) => \"W\",\n ReadWrite(_, _) => \"RW\",\n Execute() => \"X\"\n }" } }, "accrue_fflags": { "function": { "number": 0, "source": "function accrue_fflags(flags) = {\n let f = fcsr[FFLAGS] | flags;\n if fcsr[FFLAGS] != f\n then {\n fcsr[FFLAGS] = f;\n dirty_fd_context_if_present();\n }\n}", "pattern": { "type": "id", "id": "flags" }, "body": " let f = fcsr[FFLAGS] | flags;\n if fcsr[FFLAGS] != f\n then {\n fcsr[FFLAGS] = f;\n dirty_fd_context_if_present();\n }" }, "links": [ { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_regs.sail", "loc": [ 12294, 12298 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_regs.sail", "loc": [ 12322, 12326 ] }, { "type": "function", "id": "dirty_fd_context_if_present", "file": "model/riscv_fdext_regs.sail", "loc": [ 12375, 12402 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_regs.sail", "loc": [ 12353, 12357 ] } ] }, "add_to_TLB": { "function": { "number": 0, "source": "function add_to_TLB(asid : asidbits,\n vAddr : bits(64),\n pAddr : bits(64),\n pte : bits(64),\n pteAddr : bits(64),\n level : nat,\n global : bool,\n levelBitSize : nat,\n PAGESIZE_BITS : nat) -> unit = {\n let shift = PAGESIZE_BITS + (level * levelBitSize);\n assert(shift <= 64);\n let vAddrMask : bits(64) = zero_extend(ones(shift));\n let vMatchMask : bits(64) = ~ (vAddrMask);\n let entry : TLB_Entry = struct{asid = asid,\n global = global,\n pte = pte,\n pteAddr = pteAddr,\n vAddrMask = vAddrMask,\n vMatchMask = vMatchMask,\n vAddr = vAddr & vMatchMask,\n pAddr = shiftl(shiftr(pAddr, shift), shift),\n age = mcycle};\n tlb = Some(entry)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "asid" }, { "type": "id", "id": "vAddr" }, { "type": "id", "id": "pAddr" }, { "type": "id", "id": "pte" }, { "type": "id", "id": "pteAddr" }, { "type": "id", "id": "level" }, { "type": "id", "id": "global" }, { "type": "id", "id": "levelBitSize" }, { "type": "id", "id": "PAGESIZE_BITS" } ] }, "body": " let shift = PAGESIZE_BITS + (level * levelBitSize);\n assert(shift <= 64);\n let vAddrMask : bits(64) = zero_extend(ones(shift));\n let vMatchMask : bits(64) = ~ (vAddrMask);\n let entry : TLB_Entry = struct{asid = asid,\n global = global,\n pte = pte,\n pteAddr = pteAddr,\n vAddrMask = vAddrMask,\n vMatchMask = vMatchMask,\n vAddr = vAddr & vMatchMask,\n pAddr = shiftl(shiftr(pAddr, shift), shift),\n age = mcycle};\n tlb = Some(entry)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem_tlb.sail", "loc": [ 3289, 3300 ] }, { "type": "function", "id": "ones", "file": "model/riscv_vmem_tlb.sail", "loc": [ 3301, 3305 ] }, { "type": "function", "id": "not_vec", "file": "model/prelude.sail", "loc": [ 997, 1004 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_vmem_tlb.sail", "loc": [ 3928, 3934 ] }, { "type": "function", "id": "shiftl", "file": "model/riscv_vmem_tlb.sail", "loc": [ 3840, 3846 ] }, { "type": "function", "id": "shiftr", "file": "model/riscv_vmem_tlb.sail", "loc": [ 3847, 3853 ] }, { "type": "register", "id": "tlb", "file": "model/riscv_vmem_tlb.sail", "loc": [ 3939, 3942 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vmem_tlb.sail", "loc": [ 3945, 3949 ] } ] }, "aes_apply_fwd_sbox_to_each_byte": { "function": { "number": 0, "source": "function aes_apply_fwd_sbox_to_each_byte(x) = {\n aes_sbox_fwd(x[63..56]) @\n aes_sbox_fwd(x[55..48]) @\n aes_sbox_fwd(x[47..40]) @\n aes_sbox_fwd(x[39..32]) @\n aes_sbox_fwd(x[31..24]) @\n aes_sbox_fwd(x[23..16]) @\n aes_sbox_fwd(x[15.. 8]) @\n aes_sbox_fwd(x[ 7.. 0])\n}", "pattern": { "type": "id", "id": "x" }, "body": " aes_sbox_fwd(x[63..56]) @\n aes_sbox_fwd(x[55..48]) @\n aes_sbox_fwd(x[47..40]) @\n aes_sbox_fwd(x[39..32]) @\n aes_sbox_fwd(x[31..24]) @\n aes_sbox_fwd(x[23..16]) @\n aes_sbox_fwd(x[15.. 8]) @\n aes_sbox_fwd(x[ 7.. 0])" }, "links": [ { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 10756, 10768 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 10728, 10740 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 10700, 10712 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 10672, 10684 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 10644, 10656 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 10616, 10628 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 10588, 10600 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 10560, 10572 ] } ] }, "aes_apply_inv_sbox_to_each_byte": { "function": { "number": 0, "source": "function aes_apply_inv_sbox_to_each_byte(x) = {\n aes_sbox_inv(x[63..56]) @\n aes_sbox_inv(x[55..48]) @\n aes_sbox_inv(x[47..40]) @\n aes_sbox_inv(x[39..32]) @\n aes_sbox_inv(x[31..24]) @\n aes_sbox_inv(x[23..16]) @\n aes_sbox_inv(x[15.. 8]) @\n aes_sbox_inv(x[ 7.. 0])\n}", "pattern": { "type": "id", "id": "x" }, "body": " aes_sbox_inv(x[63..56]) @\n aes_sbox_inv(x[55..48]) @\n aes_sbox_inv(x[47..40]) @\n aes_sbox_inv(x[39..32]) @\n aes_sbox_inv(x[31..24]) @\n aes_sbox_inv(x[23..16]) @\n aes_sbox_inv(x[15.. 8]) @\n aes_sbox_inv(x[ 7.. 0])" }, "links": [ { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 11190, 11202 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 11162, 11174 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 11134, 11146 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 11106, 11118 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 11078, 11090 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 11050, 11062 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 11022, 11034 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 10994, 11006 ] } ] }, "aes_decode_rcon": { "function": { "number": 0, "source": "function aes_decode_rcon(r) = {\n assert(r <_u 0xA);\n match r {\n 0x0 => 0x00000001,\n 0x1 => 0x00000002,\n 0x2 => 0x00000004,\n 0x3 => 0x00000008,\n 0x4 => 0x00000010,\n 0x5 => 0x00000020,\n 0x6 => 0x00000040,\n 0x7 => 0x00000080,\n 0x8 => 0x0000001b,\n 0x9 => 0x00000036,\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AES r\") /* unreachable -- required to silence Sail warning */\n }\n}", "pattern": { "type": "id", "id": "r" }, "body": "function aes_decode_rcon(r) = {\n assert(r <_u 0xA);\n match r {\n 0x0 => 0x00000001,\n 0x1 => 0x00000002,\n 0x2 => 0x00000004,\n 0x3 => 0x00000008,\n 0x4 => 0x00000010,\n 0x5 => 0x00000020,\n 0x6 => 0x00000040,\n 0x7 => 0x00000080,\n 0x8 => 0x0000001b,\n 0x9 => 0x00000036,\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AES r\") /* unreachable -- required to silence Sail warning */\n }" }, "links": [ { "type": "function", "id": "internal_error", "file": "model/riscv_types_kext.sail", "loc": [ 3899, 3913 ] }, { "type": "function", "id": "(operator <_u)", "file": "model/riscv_types_kext.sail", "loc": [ 3636, 3639 ] } ] }, "aes_get_column": { "function": { "number": 0, "source": "function aes_get_column(state,c) = (state >> (to_bits(7, 32 * c)))[31..0]", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "state" }, { "type": "id", "id": "c" } ] }, "body": "(state >> (to_bits(7, 32 * c)))[31..0]" }, "links": [ { "type": "function", "id": "shift_bits_right", "file": "model/prelude.sail", "loc": [ 6319, 6335 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_types_kext.sail", "loc": [ 10320, 10327 ] } ] }, "aes_mixcolumn_byte_fwd": { "function": { "number": 0, "source": "function aes_mixcolumn_byte_fwd(so) = {\n gfmul(so, 0x3) @ so @ so @ gfmul(so, 0x2)\n}", "pattern": { "type": "id", "id": "so" }, "body": " gfmul(so, 0x3) @ so @ so @ gfmul(so, 0x2)" }, "links": [ { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 1750, 1755 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 1723, 1728 ] } ] }, "aes_mixcolumn_byte_inv": { "function": { "number": 0, "source": "function aes_mixcolumn_byte_inv(so) = {\n gfmul(so, 0xb) @ gfmul(so, 0xd) @ gfmul(so, 0x9) @ gfmul(so, 0xe)\n}", "pattern": { "type": "id", "id": "so" }, "body": " gfmul(so, 0xb) @ gfmul(so, 0xd) @ gfmul(so, 0x9) @ gfmul(so, 0xe)" }, "links": [ { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 1963, 1968 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 1946, 1951 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 1929, 1934 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 1912, 1917 ] } ] }, "aes_mixcolumn_fwd": { "function": { "number": 0, "source": "function aes_mixcolumn_fwd(x) = {\n let s0 : bits (8) = x[ 7.. 0];\n let s1 : bits (8) = x[15.. 8];\n let s2 : bits (8) = x[23..16];\n let s3 : bits (8) = x[31..24];\n let b0 : bits (8) = xt2(s0) ^ xt3(s1) ^ (s2) ^ (s3);\n let b1 : bits (8) = (s0) ^ xt2(s1) ^ xt3(s2) ^ (s3);\n let b2 : bits (8) = (s0) ^ (s1) ^ xt2(s2) ^ xt3(s3);\n let b3 : bits (8) = xt3(s0) ^ (s1) ^ (s2) ^ xt2(s3);\n b3 @ b2 @ b1 @ b0 /* Return value */\n}", "pattern": { "type": "id", "id": "x" }, "body": " let s0 : bits (8) = x[ 7.. 0];\n let s1 : bits (8) = x[15.. 8];\n let s2 : bits (8) = x[23..16];\n let s3 : bits (8) = x[31..24];\n let b0 : bits (8) = xt2(s0) ^ xt3(s1) ^ (s2) ^ (s3);\n let b1 : bits (8) = (s0) ^ xt2(s1) ^ xt3(s2) ^ (s3);\n let b2 : bits (8) = (s0) ^ (s1) ^ xt2(s2) ^ xt3(s3);\n let b3 : bits (8) = xt3(s0) ^ (s1) ^ (s2) ^ xt2(s3);\n b3 @ b2 @ b1 @ b0" }, "links": [ { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xt3", "file": "model/riscv_types_kext.sail", "loc": [ 2269, 2272 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 2259, 2262 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xt3", "file": "model/riscv_types_kext.sail", "loc": [ 2340, 2343 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 2330, 2333 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xt3", "file": "model/riscv_types_kext.sail", "loc": [ 2411, 2414 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 2401, 2404 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 2472, 2475 ] }, { "type": "function", "id": "xt3", "file": "model/riscv_types_kext.sail", "loc": [ 2442, 2445 ] } ] }, "aes_mixcolumn_inv": { "function": { "number": 0, "source": "function aes_mixcolumn_inv(x) = {\n let s0 : bits (8) = x[ 7.. 0];\n let s1 : bits (8) = x[15.. 8];\n let s2 : bits (8) = x[23..16];\n let s3 : bits (8) = x[31..24];\n let b0 : bits (8) = gfmul(s0, 0xE) ^ gfmul(s1, 0xB) ^ gfmul(s2, 0xD) ^ gfmul(s3, 0x9);\n let b1 : bits (8) = gfmul(s0, 0x9) ^ gfmul(s1, 0xE) ^ gfmul(s2, 0xB) ^ gfmul(s3, 0xD);\n let b2 : bits (8) = gfmul(s0, 0xD) ^ gfmul(s1, 0x9) ^ gfmul(s2, 0xE) ^ gfmul(s3, 0xB);\n let b3 : bits (8) = gfmul(s0, 0xB) ^ gfmul(s1, 0xD) ^ gfmul(s2, 0x9) ^ gfmul(s3, 0xE);\n b3 @ b2 @ b1 @ b0 /* Return value */\n}", "pattern": { "type": "id", "id": "x" }, "body": " let s0 : bits (8) = x[ 7.. 0];\n let s1 : bits (8) = x[15.. 8];\n let s2 : bits (8) = x[23..16];\n let s3 : bits (8) = x[31..24];\n let b0 : bits (8) = gfmul(s0, 0xE) ^ gfmul(s1, 0xB) ^ gfmul(s2, 0xD) ^ gfmul(s3, 0x9);\n let b1 : bits (8) = gfmul(s0, 0x9) ^ gfmul(s1, 0xE) ^ gfmul(s2, 0xB) ^ gfmul(s3, 0xD);\n let b2 : bits (8) = gfmul(s0, 0xD) ^ gfmul(s1, 0x9) ^ gfmul(s2, 0xE) ^ gfmul(s3, 0xB);\n let b3 : bits (8) = gfmul(s0, 0xB) ^ gfmul(s1, 0xD) ^ gfmul(s2, 0x9) ^ gfmul(s3, 0xE);\n b3 @ b2 @ b1 @ b0" }, "links": [ { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2852, 2857 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2835, 2840 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2818, 2823 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2801, 2806 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2941, 2946 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2924, 2929 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2907, 2912 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2890, 2895 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 3030, 3035 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 3013, 3018 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2996, 3001 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 2979, 2984 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 3119, 3124 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 3102, 3107 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 3085, 3090 ] }, { "type": "function", "id": "gfmul", "file": "model/riscv_types_kext.sail", "loc": [ 3068, 3073 ] } ] }, "aes_mixcolumns_fwd": { "function": { "number": 0, "source": "function aes_mixcolumns_fwd(x) = {\n let oc0 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 0));\n let oc1 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 1));\n let oc2 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 2));\n let oc3 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 3));\n (oc3 @ oc2 @ oc1 @ oc0) /* Return value */\n}", "pattern": { "type": "id", "id": "x" }, "body": " let oc0 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 0));\n let oc1 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 1));\n let oc2 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 2));\n let oc3 : bits(32) = aes_mixcolumn_fwd(aes_get_column(x, 3));\n (oc3 @ oc2 @ oc1 @ oc0)" }, "links": [ { "type": "function", "id": "aes_mixcolumn_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 14691, 14708 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 14709, 14723 ] }, { "type": "function", "id": "aes_mixcolumn_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 14755, 14772 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 14773, 14787 ] }, { "type": "function", "id": "aes_mixcolumn_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 14819, 14836 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 14837, 14851 ] }, { "type": "function", "id": "aes_mixcolumn_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 14883, 14900 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 14901, 14915 ] } ] }, "aes_mixcolumns_inv": { "function": { "number": 0, "source": "function aes_mixcolumns_inv(x) = {\n let oc0 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 0));\n let oc1 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 1));\n let oc2 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 2));\n let oc3 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 3));\n (oc3 @ oc2 @ oc1 @ oc0) /* Return value */\n}", "pattern": { "type": "id", "id": "x" }, "body": " let oc0 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 0));\n let oc1 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 1));\n let oc2 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 2));\n let oc3 : bits(32) = aes_mixcolumn_inv(aes_get_column(x, 3));\n (oc3 @ oc2 @ oc1 @ oc0)" }, "links": [ { "type": "function", "id": "aes_mixcolumn_inv", "file": "model/riscv_types_kext.sail", "loc": [ 15180, 15197 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 15198, 15212 ] }, { "type": "function", "id": "aes_mixcolumn_inv", "file": "model/riscv_types_kext.sail", "loc": [ 15244, 15261 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 15262, 15276 ] }, { "type": "function", "id": "aes_mixcolumn_inv", "file": "model/riscv_types_kext.sail", "loc": [ 15308, 15325 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 15326, 15340 ] }, { "type": "function", "id": "aes_mixcolumn_inv", "file": "model/riscv_types_kext.sail", "loc": [ 15372, 15389 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 15390, 15404 ] } ] }, "aes_rv64_shiftrows_fwd": { "function": { "number": 0, "source": "function aes_rv64_shiftrows_fwd(rs2, rs1) = {\n getbyte(rs1, 3) @\n getbyte(rs2, 6) @\n getbyte(rs2, 1) @\n getbyte(rs1, 4) @\n getbyte(rs2, 7) @\n getbyte(rs2, 2) @\n getbyte(rs1, 5) @\n getbyte(rs1, 0)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" } ] }, "body": " getbyte(rs1, 3) @\n getbyte(rs2, 6) @\n getbyte(rs2, 1) @\n getbyte(rs1, 4) @\n getbyte(rs2, 7) @\n getbyte(rs2, 2) @\n getbyte(rs1, 5) @\n getbyte(rs1, 0)" }, "links": [ { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11617, 11624 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11597, 11604 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11577, 11584 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11557, 11564 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11537, 11544 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11517, 11524 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11497, 11504 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11477, 11484 ] } ] }, "aes_rv64_shiftrows_inv": { "function": { "number": 0, "source": "function aes_rv64_shiftrows_inv(rs2, rs1) = {\n getbyte(rs2, 3) @\n getbyte(rs2, 6) @\n getbyte(rs1, 1) @\n getbyte(rs1, 4) @\n getbyte(rs1, 7) @\n getbyte(rs2, 2) @\n getbyte(rs2, 5) @\n getbyte(rs1, 0)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" } ] }, "body": " getbyte(rs2, 3) @\n getbyte(rs2, 6) @\n getbyte(rs1, 1) @\n getbyte(rs1, 4) @\n getbyte(rs1, 7) @\n getbyte(rs2, 2) @\n getbyte(rs2, 5) @\n getbyte(rs1, 0)" }, "links": [ { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11886, 11893 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11866, 11873 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11846, 11853 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11826, 11833 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11806, 11813 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11786, 11793 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11766, 11773 ] }, { "type": "function", "id": "getbyte", "file": "model/riscv_types_kext.sail", "loc": [ 11746, 11753 ] } ] }, "aes_sbox_fwd": { "function": { "number": 0, "source": "function aes_sbox_fwd(x) = sbox_lookup(x, aes_sbox_fwd_table)", "pattern": { "type": "id", "id": "x" }, "body": "sbox_lookup(x, aes_sbox_fwd_table)" }, "links": [ { "type": "function", "id": "sbox_lookup", "file": "model/riscv_types_kext.sail", "loc": [ 9271, 9282 ] } ] }, "aes_sbox_inv": { "function": { "number": 0, "source": "function aes_sbox_inv(x) = sbox_lookup(x, aes_sbox_inv_table)", "pattern": { "type": "id", "id": "x" }, "body": "sbox_lookup(x, aes_sbox_inv_table)" }, "links": [ { "type": "function", "id": "sbox_lookup", "file": "model/riscv_types_kext.sail", "loc": [ 9444, 9455 ] } ] }, "aes_shift_rows_fwd": { "function": { "number": 0, "source": "function aes_shift_rows_fwd(x) = {\n let ic3 : bits(32) = aes_get_column(x, 3);\n let ic2 : bits(32) = aes_get_column(x, 2);\n let ic1 : bits(32) = aes_get_column(x, 1);\n let ic0 : bits(32) = aes_get_column(x, 0);\n let oc0 : bits(32) = ic0[31..24] @ ic1[23..16] @ ic2[15.. 8] @ ic3[ 7.. 0];\n let oc1 : bits(32) = ic1[31..24] @ ic2[23..16] @ ic3[15.. 8] @ ic0[ 7.. 0];\n let oc2 : bits(32) = ic2[31..24] @ ic3[23..16] @ ic0[15.. 8] @ ic1[ 7.. 0];\n let oc3 : bits(32) = ic3[31..24] @ ic0[23..16] @ ic1[15.. 8] @ ic2[ 7.. 0];\n (oc3 @ oc2 @ oc1 @ oc0) /* Return value */\n}", "pattern": { "type": "id", "id": "x" }, "body": " let ic3 : bits(32) = aes_get_column(x, 3);\n let ic2 : bits(32) = aes_get_column(x, 2);\n let ic1 : bits(32) = aes_get_column(x, 1);\n let ic0 : bits(32) = aes_get_column(x, 0);\n let oc0 : bits(32) = ic0[31..24] @ ic1[23..16] @ ic2[15.. 8] @ ic3[ 7.. 0];\n let oc1 : bits(32) = ic1[31..24] @ ic2[23..16] @ ic3[15.. 8] @ ic0[ 7.. 0];\n let oc2 : bits(32) = ic2[31..24] @ ic3[23..16] @ ic0[15.. 8] @ ic1[ 7.. 0];\n let oc3 : bits(32) = ic3[31..24] @ ic0[23..16] @ ic1[15.. 8] @ ic2[ 7.. 0];\n (oc3 @ oc2 @ oc1 @ oc0)" }, "links": [ { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 12192, 12206 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 12237, 12251 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 12282, 12296 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 12327, 12341 ] } ] }, "aes_shift_rows_inv": { "function": { "number": 0, "source": "function aes_shift_rows_inv(x) = {\n let ic3 : bits(32) = aes_get_column(x, 3); /* In column 3 */\n let ic2 : bits(32) = aes_get_column(x, 2);\n let ic1 : bits(32) = aes_get_column(x, 1);\n let ic0 : bits(32) = aes_get_column(x, 0);\n let oc0 : bits(32) = ic0[31..24] @ ic3[23..16] @ ic2[15.. 8] @ ic1[ 7.. 0];\n let oc1 : bits(32) = ic1[31..24] @ ic0[23..16] @ ic3[15.. 8] @ ic2[ 7.. 0];\n let oc2 : bits(32) = ic2[31..24] @ ic1[23..16] @ ic0[15.. 8] @ ic3[ 7.. 0];\n let oc3 : bits(32) = ic3[31..24] @ ic2[23..16] @ ic1[15.. 8] @ ic0[ 7.. 0];\n (oc3 @ oc2 @ oc1 @ oc0) /* Return value */\n}", "pattern": { "type": "id", "id": "x" }, "body": " let ic3 : bits(32) = aes_get_column(x, 3); /* In column 3 */\n let ic2 : bits(32) = aes_get_column(x, 2);\n let ic1 : bits(32) = aes_get_column(x, 1);\n let ic0 : bits(32) = aes_get_column(x, 0);\n let oc0 : bits(32) = ic0[31..24] @ ic3[23..16] @ ic2[15.. 8] @ ic1[ 7.. 0];\n let oc1 : bits(32) = ic1[31..24] @ ic0[23..16] @ ic3[15.. 8] @ ic2[ 7.. 0];\n let oc2 : bits(32) = ic2[31..24] @ ic1[23..16] @ ic0[15.. 8] @ ic3[ 7.. 0];\n let oc3 : bits(32) = ic3[31..24] @ ic2[23..16] @ ic1[15.. 8] @ ic0[ 7.. 0];\n (oc3 @ oc2 @ oc1 @ oc0)" }, "links": [ { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 12996, 13010 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 13059, 13073 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 13104, 13118 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 13149, 13163 ] } ] }, "aes_subbytes_fwd": { "function": { "number": 0, "source": "function aes_subbytes_fwd(x) = {\n let oc0 : bits(32) = aes_subword_fwd(aes_get_column(x, 0));\n let oc1 : bits(32) = aes_subword_fwd(aes_get_column(x, 1));\n let oc2 : bits(32) = aes_subword_fwd(aes_get_column(x, 2));\n let oc3 : bits(32) = aes_subword_fwd(aes_get_column(x, 3));\n (oc3 @ oc2 @ oc1 @ oc0) /* Return value */\n}", "pattern": { "type": "id", "id": "x" }, "body": " let oc0 : bits(32) = aes_subword_fwd(aes_get_column(x, 0));\n let oc1 : bits(32) = aes_subword_fwd(aes_get_column(x, 1));\n let oc2 : bits(32) = aes_subword_fwd(aes_get_column(x, 2));\n let oc3 : bits(32) = aes_subword_fwd(aes_get_column(x, 3));\n (oc3 @ oc2 @ oc1 @ oc0)" }, "links": [ { "type": "function", "id": "aes_subword_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 13734, 13749 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 13750, 13764 ] }, { "type": "function", "id": "aes_subword_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 13796, 13811 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 13812, 13826 ] }, { "type": "function", "id": "aes_subword_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 13858, 13873 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 13874, 13888 ] }, { "type": "function", "id": "aes_subword_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 13920, 13935 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 13936, 13950 ] } ] }, "aes_subbytes_inv": { "function": { "number": 0, "source": "function aes_subbytes_inv(x) = {\n let oc0 : bits(32) = aes_subword_inv(aes_get_column(x, 0));\n let oc1 : bits(32) = aes_subword_inv(aes_get_column(x, 1));\n let oc2 : bits(32) = aes_subword_inv(aes_get_column(x, 2));\n let oc3 : bits(32) = aes_subword_inv(aes_get_column(x, 3));\n (oc3 @ oc2 @ oc1 @ oc0) /* Return value */\n}", "pattern": { "type": "id", "id": "x" }, "body": " let oc0 : bits(32) = aes_subword_inv(aes_get_column(x, 0));\n let oc1 : bits(32) = aes_subword_inv(aes_get_column(x, 1));\n let oc2 : bits(32) = aes_subword_inv(aes_get_column(x, 2));\n let oc3 : bits(32) = aes_subword_inv(aes_get_column(x, 3));\n (oc3 @ oc2 @ oc1 @ oc0)" }, "links": [ { "type": "function", "id": "aes_subword_inv", "file": "model/riscv_types_kext.sail", "loc": [ 14210, 14225 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 14226, 14240 ] }, { "type": "function", "id": "aes_subword_inv", "file": "model/riscv_types_kext.sail", "loc": [ 14272, 14287 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 14288, 14302 ] }, { "type": "function", "id": "aes_subword_inv", "file": "model/riscv_types_kext.sail", "loc": [ 14334, 14349 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 14350, 14364 ] }, { "type": "function", "id": "aes_subword_inv", "file": "model/riscv_types_kext.sail", "loc": [ 14396, 14411 ] }, { "type": "function", "id": "aes_get_column", "file": "model/riscv_types_kext.sail", "loc": [ 14412, 14426 ] } ] }, "aes_subword_fwd": { "function": { "number": 0, "source": "function aes_subword_fwd(x) = {\n aes_sbox_fwd(x[31..24]) @\n aes_sbox_fwd(x[23..16]) @\n aes_sbox_fwd(x[15.. 8]) @\n aes_sbox_fwd(x[ 7.. 0])\n}", "pattern": { "type": "id", "id": "x" }, "body": " aes_sbox_fwd(x[31..24]) @\n aes_sbox_fwd(x[23..16]) @\n aes_sbox_fwd(x[15.. 8]) @\n aes_sbox_fwd(x[ 7.. 0])" }, "links": [ { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 9757, 9769 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 9729, 9741 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 9701, 9713 ] }, { "type": "function", "id": "aes_sbox_fwd", "file": "model/riscv_types_kext.sail", "loc": [ 9673, 9685 ] } ] }, "aes_subword_inv": { "function": { "number": 0, "source": "function aes_subword_inv(x) = {\n aes_sbox_inv(x[31..24]) @\n aes_sbox_inv(x[23..16]) @\n aes_sbox_inv(x[15.. 8]) @\n aes_sbox_inv(x[ 7.. 0])\n}", "pattern": { "type": "id", "id": "x" }, "body": " aes_sbox_inv(x[31..24]) @\n aes_sbox_inv(x[23..16]) @\n aes_sbox_inv(x[15.. 8]) @\n aes_sbox_inv(x[ 7.. 0])" }, "links": [ { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 10044, 10056 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 10016, 10028 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 9988, 10000 ] }, { "type": "function", "id": "aes_sbox_inv", "file": "model/riscv_types_kext.sail", "loc": [ 9960, 9972 ] } ] }, "agtype_of_num": { "function": { "number": 0, "source": "agtype_of_num arg# = $[complete] match arg# {\n 0 => UNDISTURBED,\n _ => AGNOSTIC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => UNDISTURBED,\n _ => AGNOSTIC\n}" } }, "amo_width_valid": { "function": { "number": 0, "source": "function amo_width_valid(size : word_width) -> bool = {\n match(size) {\n WORD => true,\n DOUBLE => sizeof(xlen) >= 64,\n _ => false\n }\n}", "pattern": { "type": "id", "id": "size" }, "body": " match(size) {\n WORD => true,\n DOUBLE => sizeof(xlen) >= 64,\n _ => false\n }" } }, "amoop_of_num": { "function": { "number": 0, "source": "amoop_of_num arg# = $[complete] match arg# {\n 0 => AMOSWAP,\n 1 => AMOADD,\n 2 => AMOXOR,\n 3 => AMOAND,\n 4 => AMOOR,\n 5 => AMOMIN,\n 6 => AMOMAX,\n 7 => AMOMINU,\n _ => AMOMAXU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => AMOSWAP,\n 1 => AMOADD,\n 2 => AMOXOR,\n 3 => AMOAND,\n 4 => AMOOR,\n 5 => AMOMIN,\n 6 => AMOMAX,\n 7 => AMOMINU,\n _ => AMOMAXU\n}" } }, "aqrl_str": { "function": { "number": 0, "source": "function aqrl_str(aq : bool, rl : bool) -> string =\n match (aq, rl) {\n (false, false) => \"\",\n (false, true) => \".rl\",\n (true, false) => \".aq\",\n (true, true) => \".aqrl\"\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" } ] }, "body": "match (aq, rl) {\n (false, false) => \"\",\n (false, true) => \".rl\",\n (true, false) => \".aq\",\n (true, true) => \".aqrl\"\n }" } }, "arch_to_bits": { "function": { "number": 0, "source": "function arch_to_bits(a : Architecture) -> arch_xlen =\n match (a) {\n RV32 => 0b01,\n RV64 => 0b10,\n RV128 => 0b11\n }", "pattern": { "type": "id", "id": "a" }, "body": "match (a) {\n RV32 => 0b01,\n RV64 => 0b10,\n RV128 => 0b11\n }" } }, "architecture": { "function": { "number": 0, "source": "function architecture(a : arch_xlen) -> option(Architecture) =\n match (a) {\n 0b01 => Some(RV32),\n 0b10 => Some(RV64),\n 0b11 => Some(RV128),\n _ => None()\n }", "pattern": { "type": "id", "id": "a" }, "body": "match (a) {\n 0b01 => Some(RV32),\n 0b10 => Some(RV64),\n 0b11 => Some(RV128),\n _ => None()\n }" }, "links": [ { "type": "function", "id": "None", "file": "model/riscv_types.sail", "loc": [ 2172, 2176 ] }, { "type": "function", "id": "Some", "file": "model/riscv_types.sail", "loc": [ 2147, 2151 ] }, { "type": "function", "id": "Some", "file": "model/riscv_types.sail", "loc": [ 2123, 2127 ] }, { "type": "function", "id": "Some", "file": "model/riscv_types.sail", "loc": [ 2099, 2103 ] } ] }, "assert_vstart": { "function": { "number": 0, "source": "function assert_vstart(i) = {\n unsigned(vstart) == i\n}", "pattern": { "type": "id", "id": "i" }, "body": " unsigned(vstart) == i" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 1826, 1834 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 1835, 1841 ] } ] }, "biop_zbs_of_num": { "function": { "number": 0, "source": "biop_zbs_of_num arg# = $[complete] match arg# {\n 0 => RISCV_BCLRI,\n 1 => RISCV_BEXTI,\n 2 => RISCV_BINVI,\n _ => RISCV_BSETI\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_BCLRI,\n 1 => RISCV_BEXTI,\n 2 => RISCV_BINVI,\n _ => RISCV_BSETI\n}" } }, "bit_str": { "function": { "number": 0, "source": "function bit_str(b: bit) -> string =\n match b {\n bitzero => \"0b0\",\n bitone => \"0b1\"\n }", "pattern": { "type": "id", "id": "b" }, "body": "match b {\n bitzero => \"0b0\",\n bitone => \"0b1\"\n }" } }, "bit_to_bool": { "function": { "number": 0, "source": "function bit_to_bool b = match b {\n bitone => true,\n bitzero => false\n}", "pattern": { "type": "id", "id": "b" }, "body": "match b {\n bitone => true,\n bitzero => false\n}" } }, "bool_to_bit": { "function": { "number": 0, "source": "function bool_to_bit x = if x then bitone else bitzero", "pattern": { "type": "id", "id": "x" }, "body": "if x then bitone else bitzero" } }, "bool_to_bits": { "function": { "number": 0, "source": "function bool_to_bits x = [bool_to_bit(x)]", "pattern": { "type": "id", "id": "x" }, "body": "[bool_to_bit(x)]" }, "links": [ { "type": "function", "id": "bool_to_bit", "file": "model/prelude.sail", "loc": [ 4686, 4697 ] } ] }, "bop_of_num": { "function": { "number": 0, "source": "bop_of_num arg# = $[complete] match arg# {\n 0 => RISCV_BEQ,\n 1 => RISCV_BNE,\n 2 => RISCV_BLT,\n 3 => RISCV_BGE,\n 4 => RISCV_BLTU,\n _ => RISCV_BGEU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_BEQ,\n 1 => RISCV_BNE,\n 2 => RISCV_BLT,\n 3 => RISCV_BGE,\n 4 => RISCV_BLTU,\n _ => RISCV_BGEU\n}" } }, "brop_zba_of_num": { "function": { "number": 0, "source": "brop_zba_of_num arg# = $[complete] match arg# {\n 0 => RISCV_SH1ADD,\n 1 => RISCV_SH2ADD,\n _ => RISCV_SH3ADD\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_SH1ADD,\n 1 => RISCV_SH2ADD,\n _ => RISCV_SH3ADD\n}" } }, "brop_zbb_of_num": { "function": { "number": 0, "source": "brop_zbb_of_num arg# = $[complete] match arg# {\n 0 => RISCV_ANDN,\n 1 => RISCV_ORN,\n 2 => RISCV_XNOR,\n 3 => RISCV_MAX,\n 4 => RISCV_MAXU,\n 5 => RISCV_MIN,\n 6 => RISCV_MINU,\n 7 => RISCV_ROL,\n _ => RISCV_ROR\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_ANDN,\n 1 => RISCV_ORN,\n 2 => RISCV_XNOR,\n 3 => RISCV_MAX,\n 4 => RISCV_MAXU,\n 5 => RISCV_MIN,\n 6 => RISCV_MINU,\n 7 => RISCV_ROL,\n _ => RISCV_ROR\n}" } }, "brop_zbkb_of_num": { "function": { "number": 0, "source": "brop_zbkb_of_num arg# = $[complete] match arg# {\n 0 => RISCV_PACK,\n _ => RISCV_PACKH\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_PACK,\n _ => RISCV_PACKH\n}" } }, "brop_zbs_of_num": { "function": { "number": 0, "source": "brop_zbs_of_num arg# = $[complete] match arg# {\n 0 => RISCV_BCLR,\n 1 => RISCV_BEXT,\n 2 => RISCV_BINV,\n _ => RISCV_BSET\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_BCLR,\n 1 => RISCV_BEXT,\n 2 => RISCV_BINV,\n _ => RISCV_BSET\n}" } }, "bropw_zba_of_num": { "function": { "number": 0, "source": "bropw_zba_of_num arg# = $[complete] match arg# {\n 0 => RISCV_ADDUW,\n 1 => RISCV_SH1ADDUW,\n 2 => RISCV_SH2ADDUW,\n _ => RISCV_SH3ADDUW\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_ADDUW,\n 1 => RISCV_SH1ADDUW,\n 2 => RISCV_SH2ADDUW,\n _ => RISCV_SH3ADDUW\n}" } }, "bropw_zbb_of_num": { "function": { "number": 0, "source": "bropw_zbb_of_num arg# = $[complete] match arg# {\n 0 => RISCV_ROLW,\n _ => RISCV_RORW\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_ROLW,\n _ => RISCV_RORW\n}" } }, "cache_op_kind_of_num": { "function": { "number": 0, "source": "cache_op_kind_of_num arg# = $[complete] match arg# {\n 0 => Cache_op_D_IVAC,\n 1 => Cache_op_D_ISW,\n 2 => Cache_op_D_CSW,\n 3 => Cache_op_D_CISW,\n 4 => Cache_op_D_ZVA,\n 5 => Cache_op_D_CVAC,\n 6 => Cache_op_D_CVAU,\n 7 => Cache_op_D_CIVAC,\n 8 => Cache_op_I_IALLUIS,\n 9 => Cache_op_I_IALLU,\n _ => Cache_op_I_IVAU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => Cache_op_D_IVAC,\n 1 => Cache_op_D_ISW,\n 2 => Cache_op_D_CSW,\n 3 => Cache_op_D_CISW,\n 4 => Cache_op_D_ZVA,\n 5 => Cache_op_D_CVAC,\n 6 => Cache_op_D_CVAU,\n 7 => Cache_op_D_CIVAC,\n 8 => Cache_op_I_IALLUIS,\n 9 => Cache_op_I_IALLU,\n _ => Cache_op_I_IVAU\n}" } }, "canonical_NaN": { "function": { "number": 0, "source": "function canonical_NaN('m) = {\n match 'm {\n 16 => canonical_NaN_H(),\n 32 => canonical_NaN_S(),\n 64 => canonical_NaN_D()\n }\n}", "pattern": { "type": "var", "pattern": { "type": "id", "id": "m" } }, "body": " match 'm {\n 16 => canonical_NaN_H(),\n 32 => canonical_NaN_S(),\n 64 => canonical_NaN_D()\n }" }, "links": [ { "type": "function", "id": "canonical_NaN_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18134, 18149 ] }, { "type": "function", "id": "canonical_NaN_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18105, 18120 ] }, { "type": "function", "id": "canonical_NaN_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18076, 18091 ] } ] }, "canonical_NaN_D": { "function": { "number": 0, "source": "function canonical_NaN_D() -> bits(64) = 0x_7ff8_0000_0000_0000", "pattern": { "type": "literal", "value": "()" }, "body": "0x_7ff8_0000_0000_0000" } }, "canonical_NaN_H": { "function": { "number": 0, "source": "function canonical_NaN_H() -> bits(16) = 0x_7e00", "pattern": { "type": "literal", "value": "()" }, "body": "0x_7e00" } }, "canonical_NaN_S": { "function": { "number": 0, "source": "function canonical_NaN_S() -> bits(32) = 0x_7fc0_0000", "pattern": { "type": "literal", "value": "()" }, "body": "0x_7fc0_0000" } }, "check_CSR": { "function": { "number": 0, "source": "function check_CSR(csr : csreg, p : Privilege, isWrite : bool) -> bool =\n is_CSR_defined(csr, p)\n & check_CSR_access(csrAccess(csr), csrPriv(csr), p, isWrite)\n & check_TVM_SATP(csr, p)\n & check_Counteren(csr, p)\n & check_seed_CSR(csr, p, isWrite)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "p" }, { "type": "id", "id": "isWrite" } ] }, "body": "is_CSR_defined(csr, p)\n & check_CSR_access(csrAccess(csr), csrPriv(csr), p, isWrite)\n & check_TVM_SATP(csr, p)\n & check_Counteren(csr, p)\n & check_seed_CSR(csr, p, isWrite)" }, "links": [ { "type": "function", "id": "check_seed_CSR", "file": "model/riscv_sys_control.sail", "loc": [ 6096, 6110 ] }, { "type": "function", "id": "check_Counteren", "file": "model/riscv_sys_control.sail", "loc": [ 6068, 6083 ] }, { "type": "function", "id": "check_TVM_SATP", "file": "model/riscv_sys_control.sail", "loc": [ 6041, 6055 ] }, { "type": "function", "id": "check_CSR_access", "file": "model/riscv_sys_control.sail", "loc": [ 5978, 5994 ] }, { "type": "function", "id": "csrPriv", "file": "model/riscv_sys_control.sail", "loc": [ 6011, 6018 ] }, { "type": "function", "id": "csrAccess", "file": "model/riscv_sys_control.sail", "loc": [ 5995, 6004 ] }, { "type": "function", "id": "is_CSR_defined", "file": "model/riscv_sys_control.sail", "loc": [ 5951, 5965 ] } ] }, "check_CSR_access": { "function": { "number": 0, "source": "function check_CSR_access(csrrw, csrpr, p, isWrite) =\n not(isWrite == true & csrrw == 0b11) /* read/write */\n & (privLevel_to_bits(p) >=_u csrpr)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "csrrw" }, { "type": "id", "id": "csrpr" }, { "type": "id", "id": "p" }, { "type": "id", "id": "isWrite" } ] }, "body": "not(isWrite == true & csrrw == 0b11) /* read/write */\n & (privLevel_to_bits(p) >=_u csrpr)" }, "links": [ { "type": "function", "id": "(operator >=_u)", "file": "model/riscv_sys_control.sail", "loc": [ 4550, 4554 ] }, { "type": "function", "id": "privLevel_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 4529, 4546 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 4469, 4472 ] } ] }, "check_Counteren": { "function": { "number": 0, "source": "function check_Counteren(csr : csreg, p : Privilege) -> bool =\n match(csr, p) {\n (0xC00, Supervisor) => mcounteren[CY] == 0b1,\n (0xC01, Supervisor) => mcounteren[TM] == 0b1,\n (0xC02, Supervisor) => mcounteren[IR] == 0b1,\n\n (0xC00, User) => mcounteren[CY] == 0b1 & (not(haveSupMode()) | scounteren[CY] == 0b1),\n (0xC01, User) => mcounteren[TM] == 0b1 & (not(haveSupMode()) | scounteren[TM] == 0b1),\n (0xC02, User) => mcounteren[IR] == 0b1 & (not(haveSupMode()) | scounteren[IR] == 0b1),\n\n (_, _) => /* no HPM counters for now */\n if 0xC03 <=_u csr & csr <=_u 0xC1F\n then false\n else true\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "p" } ] }, "body": "match(csr, p) {\n (0xC00, Supervisor) => mcounteren[CY] == 0b1,\n (0xC01, Supervisor) => mcounteren[TM] == 0b1,\n (0xC02, Supervisor) => mcounteren[IR] == 0b1,\n\n (0xC00, User) => mcounteren[CY] == 0b1 & (not(haveSupMode()) | scounteren[CY] == 0b1),\n (0xC01, User) => mcounteren[TM] == 0b1 & (not(haveSupMode()) | scounteren[TM] == 0b1),\n (0xC02, User) => mcounteren[IR] == 0b1 & (not(haveSupMode()) | scounteren[IR] == 0b1),\n\n (_, _) => /* no HPM counters for now */\n if 0xC03 <=_u csr & csr <=_u 0xC1F\n then false\n else true\n }" }, "links": [ { "type": "function", "id": "(operator <=_u)", "file": "model/riscv_sys_control.sail", "loc": [ 5297, 5301 ] }, { "type": "function", "id": "(operator <=_u)", "file": "model/riscv_sys_control.sail", "loc": [ 5282, 5286 ] }, { "type": "register", "id": "scounteren", "file": "model/riscv_sys_control.sail", "loc": [ 5188, 5198 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 5167, 5170 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 5171, 5182 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_sys_control.sail", "loc": [ 5142, 5152 ] }, { "type": "register", "id": "scounteren", "file": "model/riscv_sys_control.sail", "loc": [ 5097, 5107 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 5076, 5079 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 5080, 5091 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_sys_control.sail", "loc": [ 5051, 5061 ] }, { "type": "register", "id": "scounteren", "file": "model/riscv_sys_control.sail", "loc": [ 5006, 5016 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 4985, 4988 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 4989, 5000 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_sys_control.sail", "loc": [ 4960, 4970 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_sys_control.sail", "loc": [ 4915, 4925 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_sys_control.sail", "loc": [ 4865, 4875 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_sys_control.sail", "loc": [ 4815, 4825 ] } ] }, "check_PTE_permission": { "function": { "number": 0, "source": "function check_PTE_permission(ac : AccessType(ext_access_type),\n priv : Privilege,\n mxr : bool,\n do_sum : bool,\n pte_flags : PTE_Flags,\n ext : extPte,\n ext_ptw : ext_ptw) -> PTE_Check = {\n let pte_U = pte_flags[U];\n let pte_R = pte_flags[R];\n let pte_W = pte_flags[W];\n let pte_X = pte_flags[X];\n let success : bool =\n match (ac, priv) {\n (Read(_), User) => (pte_U == 0b1)\n & ((pte_R == 0b1)\n | ((pte_X == 0b1 & mxr))),\n (Write(_), User) => (pte_U == 0b1) & (pte_W == 0b1),\n (ReadWrite(_, _), User) => (pte_U == 0b1)\n & (pte_W == 0b1)\n & ((pte_R == 0b1) | ((pte_X == 0b1) & mxr)),\n (Execute(), User) => (pte_U == 0b1) & (pte_X == 0b1),\n (Read(_), Supervisor) => ((pte_U == 0b0) | do_sum)\n & ((pte_R == 0b1) | ((pte_X == 0b1) & mxr)),\n (Write(_), Supervisor) => ((pte_U == 0b0) | do_sum)\n & (pte_W == 0b1),\n (ReadWrite(_, _), Supervisor) => ((pte_U == 0b0) | do_sum)\n & (pte_W == 0b1)\n & ((pte_R == 0b1)\n | ((pte_X == 0b1) & mxr)),\n (Execute(), Supervisor) => (pte_U == 0b0) & (pte_X == 0b1),\n (_, Machine) => internal_error(__FILE__, __LINE__,\n \"m-mode mem perm check\")};\n if success then PTE_Check_Success(())\n else PTE_Check_Failure((), ())\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "ac" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "mxr" }, { "type": "id", "id": "do_sum" }, { "type": "id", "id": "pte_flags" }, { "type": "id", "id": "ext" }, { "type": "id", "id": "ext_ptw" } ] }, "body": " let pte_U = pte_flags[U];\n let pte_R = pte_flags[R];\n let pte_W = pte_flags[W];\n let pte_X = pte_flags[X];\n let success : bool =\n match (ac, priv) {\n (Read(_), User) => (pte_U == 0b1)\n & ((pte_R == 0b1)\n | ((pte_X == 0b1 & mxr))),\n (Write(_), User) => (pte_U == 0b1) & (pte_W == 0b1),\n (ReadWrite(_, _), User) => (pte_U == 0b1)\n & (pte_W == 0b1)\n & ((pte_R == 0b1) | ((pte_X == 0b1) & mxr)),\n (Execute(), User) => (pte_U == 0b1) & (pte_X == 0b1),\n (Read(_), Supervisor) => ((pte_U == 0b0) | do_sum)\n & ((pte_R == 0b1) | ((pte_X == 0b1) & mxr)),\n (Write(_), Supervisor) => ((pte_U == 0b0) | do_sum)\n & (pte_W == 0b1),\n (ReadWrite(_, _), Supervisor) => ((pte_U == 0b0) | do_sum)\n & (pte_W == 0b1)\n & ((pte_R == 0b1)\n | ((pte_X == 0b1) & mxr)),\n (Execute(), Supervisor) => (pte_U == 0b0) & (pte_X == 0b1),\n (_, Machine) => internal_error(__FILE__, __LINE__,\n \"m-mode mem perm check\")};\n if success then PTE_Check_Success(())\n else PTE_Check_Failure((), ())" }, "links": [ { "type": "function", "id": "internal_error", "file": "model/riscv_vmem_pte.sail", "loc": [ 4635, 4649 ] }, { "type": "function", "id": "PTE_Check_Success", "file": "model/riscv_vmem_pte.sail", "loc": [ 4769, 4786 ] }, { "type": "function", "id": "PTE_Check_Failure", "file": "model/riscv_vmem_pte.sail", "loc": [ 4809, 4826 ] } ] }, "check_TVM_SATP": { "function": { "number": 0, "source": "function check_TVM_SATP(csr : csreg, p : Privilege) -> bool =\n not(csr == 0x180 & p == Supervisor & mstatus[TVM] == 0b1)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "p" } ] }, "body": "not(csr == 0x180 & p == Supervisor & mstatus[TVM] == 0b1)" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 4648, 4651 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 4685, 4692 ] } ] }, "check_misaligned": { "function": { "number": 0, "source": "function check_misaligned(vaddr : xlenbits, width : word_width) -> bool =\n if plat_enable_misaligned_access() then false\n else match width {\n BYTE => false,\n HALF => vaddr[0] == bitone,\n WORD => vaddr[0] == bitone | vaddr[1] == bitone,\n DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vaddr" }, { "type": "id", "id": "width" } ] }, "body": "if plat_enable_misaligned_access() then false\n else match width {\n BYTE => false,\n HALF => vaddr[0] == bitone,\n WORD => vaddr[0] == bitone | vaddr[1] == bitone,\n DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone\n }" }, "links": [ { "type": "function", "id": "plat_enable_misaligned_access", "file": "model/riscv_insts_base.sail", "loc": [ 12159, 12188 ] } ] }, "check_seed_CSR": { "function": { "number": 0, "source": "function check_seed_CSR (csr : csreg, p : Privilege, isWrite : bool) -> bool = {\n if not(csr == 0x015) then {\n true\n } else if not(isWrite) then {\n /* Read-only access to the seed CSR is not allowed */\n false\n } else {\n match (p) {\n Machine => true,\n Supervisor => false, /* TODO: base this on mseccfg */\n User => false, /* TODO: base this on mseccfg */\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "p" }, { "type": "id", "id": "isWrite" } ] }, "body": " if not(csr == 0x015) then {\n true\n } else if not(isWrite) then {\n /* Read-only access to the seed CSR is not allowed */\n false\n } else {\n match (p) {\n Machine => true,\n Supervisor => false, /* TODO: base this on mseccfg */\n User => false, /* TODO: base this on mseccfg */\n }\n }" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 5563, 5566 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 5609, 5612 ] } ] }, "checked_mem_read": { "function": { "number": 0, "source": "function checked_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), paddr : xlenbits, width : int('n), aq : bool, rl : bool, res: bool, meta : bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) =\n if within_mmio_readable(paddr, width)\n then MemoryOpResult_add_meta(mmio_read(t, paddr, width), default_meta)\n else if within_phys_mem(paddr, width)\n then match ext_check_phys_mem_read(t, paddr, width, aq, rl, res, meta) {\n Ext_PhysAddr_OK() => phys_mem_read(t, paddr, width, aq, rl, res, meta),\n Ext_PhysAddr_Error(e) => MemException(e)\n } else match t {\n Execute() => MemException(E_Fetch_Access_Fault()),\n Read(Data) => MemException(E_Load_Access_Fault()),\n _ => MemException(E_SAMO_Access_Fault())\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "t" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "res" }, { "type": "id", "id": "meta" } ] }, "body": "if within_mmio_readable(paddr, width)\n then MemoryOpResult_add_meta(mmio_read(t, paddr, width), default_meta)\n else if within_phys_mem(paddr, width)\n then match ext_check_phys_mem_read(t, paddr, width, aq, rl, res, meta) {\n Ext_PhysAddr_OK() => phys_mem_read(t, paddr, width, aq, rl, res, meta),\n Ext_PhysAddr_Error(e) => MemException(e)\n } else match t {\n Execute() => MemException(E_Fetch_Access_Fault()),\n Read(Data) => MemException(E_Load_Access_Fault()),\n _ => MemException(E_SAMO_Access_Fault())\n }" }, "links": [ { "type": "function", "id": "within_mmio_readable", "file": "model/riscv_mem.sail", "loc": [ 3605, 3625 ] }, { "type": "function", "id": "MemoryOpResult_add_meta", "file": "model/riscv_mem.sail", "loc": [ 3647, 3670 ] }, { "type": "function", "id": "mmio_read", "file": "model/riscv_mem.sail", "loc": [ 3671, 3680 ] }, { "type": "function", "id": "within_phys_mem", "file": "model/riscv_mem.sail", "loc": [ 3723, 3738 ] }, { "type": "function", "id": "ext_check_phys_mem_read", "file": "model/riscv_mem.sail", "loc": [ 3766, 3789 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 3937, 3949 ] }, { "type": "function", "id": "phys_mem_read", "file": "model/riscv_mem.sail", "loc": [ 3857, 3870 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 4101, 4113 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_mem.sail", "loc": [ 4114, 4133 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 4046, 4058 ] }, { "type": "function", "id": "E_Load_Access_Fault", "file": "model/riscv_mem.sail", "loc": [ 4059, 4078 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 3990, 4002 ] }, { "type": "function", "id": "E_Fetch_Access_Fault", "file": "model/riscv_mem.sail", "loc": [ 4003, 4023 ] } ] }, "checked_mem_write": { "function": { "number": 0, "source": "function checked_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk : write_kind, paddr : xlenbits, width : int('n), data: bits(8 * 'n), meta: mem_meta) -> MemoryOpResult(bool) =\n if within_mmio_writable(paddr, width)\n then mmio_write(paddr, width, data)\n else if within_phys_mem(paddr, width)\n then match ext_check_phys_mem_write (wk, paddr, width, data, meta) {\n Ext_PhysAddr_OK() => phys_mem_write(wk, paddr, width, data, meta),\n Ext_PhysAddr_Error(e) => MemException(e)\n }\n else MemException(E_SAMO_Access_Fault())", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "wk" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "data" }, { "type": "id", "id": "meta" } ] }, "body": "if within_mmio_writable(paddr, width)\n then mmio_write(paddr, width, data)\n else if within_phys_mem(paddr, width)\n then match ext_check_phys_mem_write (wk, paddr, width, data, meta) {\n Ext_PhysAddr_OK() => phys_mem_write(wk, paddr, width, data, meta),\n Ext_PhysAddr_Error(e) => MemException(e)\n }\n else MemException(E_SAMO_Access_Fault())" }, "links": [ { "type": "function", "id": "within_mmio_writable", "file": "model/riscv_mem.sail", "loc": [ 10977, 10997 ] }, { "type": "function", "id": "mmio_write", "file": "model/riscv_mem.sail", "loc": [ 11019, 11029 ] }, { "type": "function", "id": "within_phys_mem", "file": "model/riscv_mem.sail", "loc": [ 11060, 11075 ] }, { "type": "function", "id": "ext_check_phys_mem_write", "file": "model/riscv_mem.sail", "loc": [ 11103, 11127 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 11262, 11274 ] }, { "type": "function", "id": "phys_mem_write", "file": "model/riscv_mem.sail", "loc": [ 11186, 11200 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 11289, 11301 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_mem.sail", "loc": [ 11302, 11321 ] } ] }, "clint_dispatch": { "function": { "number": 0, "source": "function clint_dispatch() -> unit = {\n if get_config_print_platform()\n then print_platform(\"clint::tick mtime <- \" ^ BitStr(mtime));\n mip[MTI] = 0b0;\n if mtimecmp <=_u mtime then {\n if get_config_print_platform()\n then print_platform(\" clint timer pending at mtime \" ^ BitStr(mtime));\n mip[MTI] = 0b1\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " if get_config_print_platform()\n then print_platform(\"clint::tick mtime <- \" ^ BitStr(mtime));\n mip[MTI] = 0b0;\n if mtimecmp <=_u mtime then {\n if get_config_print_platform()\n then print_platform(\" clint timer pending at mtime \" ^ BitStr(mtime));\n mip[MTI] = 0b1\n }" }, "links": [ { "type": "function", "id": "(operator <=_u)", "file": "model/riscv_platform.sail", "loc": [ 9736, 9740 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 9741, 9746 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 9727, 9735 ] }, { "type": "register", "id": "mip", "file": "model/riscv_platform.sail", "loc": [ 9870, 9873 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 9763, 9788 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 9800, 9814 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 9857, 9862 ] }, { "type": "register", "id": "mip", "file": "model/riscv_platform.sail", "loc": [ 9706, 9709 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 9612, 9637 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 9647, 9661 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 9695, 9700 ] } ] }, "clint_load": { "function": { "number": 0, "source": "function clint_load(t, addr, width) = {\n let addr = addr - plat_clint_base ();\n /* FIXME: For now, only allow exact aligned access. */\n if addr == MSIP_BASE & ('n == 8 | 'n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mip[MSI]));\n MemValue(sail_zero_extend(mip[MSI], sizeof(8 * 'n)))\n }\n else if addr == MTIMECMP_BASE & ('n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint<4>[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtimecmp[31..0]));\n /* FIXME: Redundant zero_extend currently required by Lem backend */\n MemValue(sail_zero_extend(mtimecmp[31..0], 32))\n }\n else if addr == MTIMECMP_BASE & ('n == 8)\n then {\n if get_config_print_platform()\n then print_platform(\"clint<8>[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtimecmp));\n /* FIXME: Redundant zero_extend currently required by Lem backend */\n MemValue(sail_zero_extend(mtimecmp, 64))\n }\n else if addr == MTIMECMP_BASE_HI & ('n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint-hi<4>[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtimecmp[63..32]));\n /* FIXME: Redundant zero_extend currently required by Lem backend */\n MemValue(sail_zero_extend(mtimecmp[63..32], 32))\n }\n else if addr == MTIME_BASE & ('n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtime));\n MemValue(sail_zero_extend(mtime[31..0], 32))\n }\n else if addr == MTIME_BASE & ('n == 8)\n then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtime));\n MemValue(sail_zero_extend(mtime, 64))\n }\n else if addr == MTIME_BASE_HI & ('n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtime));\n MemValue(sail_zero_extend(mtime[63..32], 32))\n }\n else {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \");\n match t {\n Execute() => MemException(E_Fetch_Access_Fault()),\n Read(Data) => MemException(E_Load_Access_Fault()),\n _ => MemException(E_SAMO_Access_Fault())\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "t" }, { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": " let addr = addr - plat_clint_base ();\n /* FIXME: For now, only allow exact aligned access. */\n if addr == MSIP_BASE & ('n == 8 | 'n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mip[MSI]));\n MemValue(sail_zero_extend(mip[MSI], sizeof(8 * 'n)))\n }\n else if addr == MTIMECMP_BASE & ('n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint<4>[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtimecmp[31..0]));\n /* FIXME: Redundant zero_extend currently required by Lem backend */\n MemValue(sail_zero_extend(mtimecmp[31..0], 32))\n }\n else if addr == MTIMECMP_BASE & ('n == 8)\n then {\n if get_config_print_platform()\n then print_platform(\"clint<8>[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtimecmp));\n /* FIXME: Redundant zero_extend currently required by Lem backend */\n MemValue(sail_zero_extend(mtimecmp, 64))\n }\n else if addr == MTIMECMP_BASE_HI & ('n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint-hi<4>[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtimecmp[63..32]));\n /* FIXME: Redundant zero_extend currently required by Lem backend */\n MemValue(sail_zero_extend(mtimecmp[63..32], 32))\n }\n else if addr == MTIME_BASE & ('n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtime));\n MemValue(sail_zero_extend(mtime[31..0], 32))\n }\n else if addr == MTIME_BASE & ('n == 8)\n then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtime));\n MemValue(sail_zero_extend(mtime, 64))\n }\n else if addr == MTIME_BASE_HI & ('n == 4)\n then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \" ^ BitStr(mtime));\n MemValue(sail_zero_extend(mtime[63..32], 32))\n }\n else {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] -> \");\n match t {\n Execute() => MemException(E_Fetch_Access_Fault()),\n Read(Data) => MemException(E_Load_Access_Fault()),\n _ => MemException(E_SAMO_Access_Fault())\n }\n }" }, "links": [ { "type": "function", "id": "sub_vec", "file": "model/prelude.sail", "loc": [ 1712, 1719 ] }, { "type": "function", "id": "plat_clint_base", "file": "model/riscv_platform.sail", "loc": [ 7380, 7395 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 7631, 7639 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 7640, 7656 ] }, { "type": "register", "id": "mip", "file": "model/riscv_platform.sail", "loc": [ 7657, 7660 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 7520, 7545 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 7557, 7571 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mip", "file": "model/riscv_platform.sail", "loc": [ 7615, 7618 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 7944, 7952 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 7953, 7969 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 7970, 7978 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 7750, 7775 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 7787, 7801 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 7848, 7856 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 8245, 8253 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 8254, 8270 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 8271, 8279 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 8058, 8083 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 8095, 8109 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 8156, 8164 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 8553, 8561 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 8562, 8578 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 8579, 8587 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 8355, 8380 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 8392, 8406 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 8456, 8464 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 8773, 8781 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 8782, 8798 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 8799, 8804 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 8665, 8690 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 8702, 8716 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 8760, 8765 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 8989, 8997 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 8998, 9014 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 9015, 9020 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 8881, 8906 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 8918, 8932 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 8976, 8981 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 9201, 9209 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 9210, 9226 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 9227, 9232 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 9093, 9118 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 9130, 9144 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 9188, 9193 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 9518, 9530 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 9531, 9550 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 9461, 9473 ] }, { "type": "function", "id": "E_Load_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 9474, 9493 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 9403, 9415 ] }, { "type": "function", "id": "E_Fetch_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 9416, 9436 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 9269, 9294 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 9306, 9320 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "clint_store": { "function": { "number": 0, "source": "function clint_store(addr, width, data) = {\n let addr = addr - plat_clint_base ();\n if addr == MSIP_BASE & ('n == 8 | 'n == 4) then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" (mip.MSI <- \" ^ BitStr(data[0]) ^ \")\");\n mip[MSI] = [data[0]];\n clint_dispatch();\n MemValue(true)\n } else if addr == MTIMECMP_BASE & 'n == 8 then {\n if get_config_print_platform()\n then print_platform(\"clint<8>[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" (mtimecmp)\");\n mtimecmp = sail_zero_extend(data, 64); /* FIXME: Redundant zero_extend currently required by Lem backend */\n clint_dispatch();\n MemValue(true)\n } else if addr == MTIMECMP_BASE & 'n == 4 then {\n if get_config_print_platform()\n then print_platform(\"clint<4>[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" (mtimecmp)\");\n mtimecmp = vector_update_subrange(mtimecmp, 31, 0, sail_zero_extend(data, 32)); /* FIXME: Redundant zero_extend currently required by Lem backend */\n clint_dispatch();\n MemValue(true)\n } else if addr == MTIMECMP_BASE_HI & 'n == 4 then {\n if get_config_print_platform()\n then print_platform(\"clint<4>[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" (mtimecmp)\");\n mtimecmp = vector_update_subrange(mtimecmp, 63, 32, sail_zero_extend(data, 32)); /* FIXME: Redundant zero_extend currently required by Lem backend */\n clint_dispatch();\n MemValue(true)\n } else {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" ()\");\n MemException(E_SAMO_Access_Fault())\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "data" } ] }, "body": " let addr = addr - plat_clint_base ();\n if addr == MSIP_BASE & ('n == 8 | 'n == 4) then {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" (mip.MSI <- \" ^ BitStr(data[0]) ^ \")\");\n mip[MSI] = [data[0]];\n clint_dispatch();\n MemValue(true)\n } else if addr == MTIMECMP_BASE & 'n == 8 then {\n if get_config_print_platform()\n then print_platform(\"clint<8>[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" (mtimecmp)\");\n mtimecmp = sail_zero_extend(data, 64); /* FIXME: Redundant zero_extend currently required by Lem backend */\n clint_dispatch();\n MemValue(true)\n } else if addr == MTIMECMP_BASE & 'n == 4 then {\n if get_config_print_platform()\n then print_platform(\"clint<4>[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" (mtimecmp)\");\n mtimecmp = vector_update_subrange(mtimecmp, 31, 0, sail_zero_extend(data, 32)); /* FIXME: Redundant zero_extend currently required by Lem backend */\n clint_dispatch();\n MemValue(true)\n } else if addr == MTIMECMP_BASE_HI & 'n == 4 then {\n if get_config_print_platform()\n then print_platform(\"clint<4>[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" (mtimecmp)\");\n mtimecmp = vector_update_subrange(mtimecmp, 63, 32, sail_zero_extend(data, 32)); /* FIXME: Redundant zero_extend currently required by Lem backend */\n clint_dispatch();\n MemValue(true)\n } else {\n if get_config_print_platform()\n then print_platform(\"clint[\" ^ BitStr(addr) ^ \"] <- \" ^ BitStr(data) ^ \" ()\");\n MemException(E_SAMO_Access_Fault())\n }" }, "links": [ { "type": "function", "id": "sub_vec", "file": "model/prelude.sail", "loc": [ 1712, 1719 ] }, { "type": "function", "id": "plat_clint_base", "file": "model/riscv_platform.sail", "loc": [ 10098, 10113 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 10376, 10384 ] }, { "type": "function", "id": "clint_dispatch", "file": "model/riscv_platform.sail", "loc": [ 10354, 10368 ] }, { "type": "register", "id": "mip", "file": "model/riscv_platform.sail", "loc": [ 10328, 10331 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 10179, 10204 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 10216, 10230 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bit_str", "file": "model/prelude.sail", "loc": [ 1312, 1319 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 10711, 10719 ] }, { "type": "function", "id": "clint_dispatch", "file": "model/riscv_platform.sail", "loc": [ 10689, 10703 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 10577, 10585 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 10588, 10604 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 10451, 10476 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 10488, 10502 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 11088, 11096 ] }, { "type": "function", "id": "clint_dispatch", "file": "model/riscv_platform.sail", "loc": [ 11066, 11080 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 10912, 10920 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 10963, 10979 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 10946, 10954 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 10786, 10811 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 10823, 10837 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 11468, 11476 ] }, { "type": "function", "id": "clint_dispatch", "file": "model/riscv_platform.sail", "loc": [ 11446, 11460 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 11292, 11300 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 11344, 11360 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 11326, 11334 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 11166, 11191 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 11203, 11217 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 11628, 11640 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 11641, 11660 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 11503, 11528 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 11540, 11554 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "concat_str_bits": { "function": { "number": 0, "source": "concat_str_bits (str, x) = concat_str(str, bits_str(x))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "str" }, { "type": "id", "id": "x" } ] }, "body": "concat_str(str, bits_str(x))" } }, "concat_str_dec": { "function": { "number": 0, "source": "concat_str_dec (str, x) = concat_str(str, dec_str(x))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "str" }, { "type": "id", "id": "x" } ] }, "body": "concat_str(str, dec_str(x))" } }, "count_leadingzeros": { "function": { "number": 0, "source": "function count_leadingzeros (sig, len) = {\n idx : int = -1;\n assert(len == 10 | len == 23 | len == 52);\n foreach (i from 0 to (len - 1)) {\n if sig[i] == bitone then idx = i;\n };\n len - idx - 1\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sig" }, { "type": "id", "id": "len" } ] }, "body": "function count_leadingzeros (sig, len) = {\n idx : int = -1;\n assert(len == 10 | len == 23 | len == 52);\n foreach (i from 0 to (len - 1)) {\n if sig[i] == bitone then idx = i;\n };\n len - idx - 1\n}" } }, "creg2reg_idx": { "function": { "number": 0, "source": "function creg2reg_idx(creg) = 0b01 @ creg", "pattern": { "type": "id", "id": "creg" }, "body": "0b01 @ creg" } }, "csrAccess": { "function": { "number": 0, "source": "function csrAccess(csr : csreg) -> csrRW = csr[11..10]", "pattern": { "type": "id", "id": "csr" }, "body": "csr[11..10]" } }, "csrPriv": { "function": { "number": 0, "source": "function csrPriv(csr : csreg) -> priv_level = csr[9..8]", "pattern": { "type": "id", "id": "csr" }, "body": "csr[9..8]" } }, "csr_name": { "function": { "number": 0, "source": "function csr_name(csr) = csr_name_map(csr)", "pattern": { "type": "id", "id": "csr" }, "body": "csr_name_map(csr)" } }, "csrop_of_num": { "function": { "number": 0, "source": "csrop_of_num arg# = $[complete] match arg# {\n 0 => CSRRW,\n 1 => CSRRS,\n _ => CSRRC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => CSRRW,\n 1 => CSRRS,\n _ => CSRRC\n}" } }, "cur_Architecture": { "function": { "number": 0, "source": "function cur_Architecture() -> Architecture = {\n let a : arch_xlen =\n match (cur_privilege) {\n Machine => misa[MXL],\n Supervisor => get_mstatus_SXL(mstatus),\n User => get_mstatus_UXL(mstatus)\n };\n match architecture(a) {\n Some(a) => a,\n None() => internal_error(__FILE__, __LINE__, \"Invalid current architecture\")\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " let a : arch_xlen =\n match (cur_privilege) {\n Machine => misa[MXL],\n Supervisor => get_mstatus_SXL(mstatus),\n User => get_mstatus_UXL(mstatus)\n };\n match architecture(a) {\n Some(a) => a,\n None() => internal_error(__FILE__, __LINE__, \"Invalid current architecture\")\n }" }, "links": [ { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_regs.sail", "loc": [ 9867, 9880 ] }, { "type": "function", "id": "get_mstatus_UXL", "file": "model/riscv_sys_regs.sail", "loc": [ 9981, 9996 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 9997, 10004 ] }, { "type": "function", "id": "get_mstatus_SXL", "file": "model/riscv_sys_regs.sail", "loc": [ 9935, 9950 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 9951, 9958 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 9904, 9908 ] }, { "type": "function", "id": "architecture", "file": "model/riscv_sys_regs.sail", "loc": [ 10021, 10033 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_sys_regs.sail", "loc": [ 10072, 10086 ] } ] }, "decode_agtype": { "function": { "number": 0, "source": "function decode_agtype(ag) = {\n match ag {\n 0b0 => UNDISTURBED,\n 0b1 => AGNOSTIC\n }\n}", "pattern": { "type": "id", "id": "ag" }, "body": " match ag {\n 0b0 => UNDISTURBED,\n 0b1 => AGNOSTIC\n }" } }, "def_spc_backwards": { "function": { "number": 0, "source": "function def_spc_backwards _ = ()", "pattern": { "type": "wildcard" }, "body": "()" } }, "def_spc_backwards_matches": { "function": { "number": 0, "source": "function def_spc_backwards_matches s = n_leading_spaces(s) == string_length(s)", "pattern": { "type": "id", "id": "s" }, "body": "n_leading_spaces(s) == string_length(s)" }, "links": [ { "type": "function", "id": "string_length", "file": "model/mapping.sail", "loc": [ 7121, 7134 ] }, { "type": "function", "id": "n_leading_spaces", "file": "model/mapping.sail", "loc": [ 7098, 7114 ] } ] }, "def_spc_forwards": { "function": { "number": 0, "source": "function def_spc_forwards() = \" \"", "pattern": { "type": "literal", "value": "()" }, "body": "\" \"" } }, "def_spc_forwards_matches": { "function": { "number": 0, "source": "function def_spc_forwards_matches() = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "dirty_fd_context": { "function": { "number": 0, "source": "function dirty_fd_context() -> unit = {\n assert(sys_enable_fdext());\n mstatus[FS] = extStatus_to_bits(Dirty);\n mstatus[SD] = 0b1\n}", "pattern": { "type": "literal", "value": "()" }, "body": "function dirty_fd_context() -> unit = {\n assert(sys_enable_fdext());\n mstatus[FS] = extStatus_to_bits(Dirty);\n mstatus[SD] = 0b1" }, "links": [ { "type": "register", "id": "mstatus", "file": "model/riscv_fdext_regs.sail", "loc": [ 3882, 3889 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_fdext_regs.sail", "loc": [ 3840, 3847 ] }, { "type": "function", "id": "extStatus_to_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 3854, 3871 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 3817, 3833 ] } ] }, "dirty_fd_context_if_present": { "function": { "number": 0, "source": "function dirty_fd_context_if_present() -> unit = {\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext() then dirty_fd_context()\n}", "pattern": { "type": "literal", "value": "()" }, "body": "function dirty_fd_context_if_present() -> unit = {\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext() then dirty_fd_context()" }, "links": [ { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 4011, 4027 ] }, { "type": "function", "id": "dirty_fd_context", "file": "model/riscv_fdext_regs.sail", "loc": [ 4035, 4051 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 3985, 4001 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 3963, 3979 ] } ] }, "dirty_v_context": { "function": { "number": 0, "source": "function dirty_v_context() -> unit = {\n assert(sys_enable_vext());\n mstatus[VS] = extStatus_to_bits(Dirty);\n mstatus[SD] = 0b1\n}", "pattern": { "type": "literal", "value": "()" }, "body": "function dirty_v_context() -> unit = {\n assert(sys_enable_vext());\n mstatus[VS] = extStatus_to_bits(Dirty);\n mstatus[SD] = 0b1" }, "links": [ { "type": "register", "id": "mstatus", "file": "model/riscv_vext_regs.sail", "loc": [ 2356, 2363 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_vext_regs.sail", "loc": [ 2314, 2321 ] }, { "type": "function", "id": "extStatus_to_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 2328, 2345 ] }, { "type": "function", "id": "sys_enable_vext", "file": "model/riscv_vext_regs.sail", "loc": [ 2292, 2307 ] } ] }, "dirty_v_context_if_present": { "function": { "number": 0, "source": "function dirty_v_context_if_present() -> unit = {\n if sys_enable_vext() then dirty_v_context()\n}", "pattern": { "type": "literal", "value": "()" }, "body": " if sys_enable_vext() then dirty_v_context()" }, "links": [ { "type": "function", "id": "sys_enable_vext", "file": "model/riscv_vext_regs.sail", "loc": [ 2432, 2447 ] }, { "type": "function", "id": "dirty_v_context", "file": "model/riscv_vext_regs.sail", "loc": [ 2455, 2470 ] } ] }, "dispatchInterrupt": { "function": { "number": 0, "source": "function dispatchInterrupt(priv : Privilege) -> option((InterruptType, Privilege)) = {\n /* If we don't have different privilege levels, we don't need to check delegation.\n * Absence of U-mode implies absence of S-mode.\n */\n if not(haveUsrMode()) | (not(haveSupMode()) & not(haveNExt())) then {\n assert(priv == Machine, \"invalid current privilege\");\n let enabled_pending = mip.bits & mie.bits;\n match findPendingInterrupt(enabled_pending) {\n Some(i) => let r = (i, Machine) in Some(r),\n None() => None()\n }\n } else {\n match getPendingSet(priv) {\n None() => None(),\n Some(ip, p) => match findPendingInterrupt(ip) {\n None() => None(),\n Some(i) => let r = (i, p) in Some(r)\n }\n }\n }\n}", "pattern": { "type": "id", "id": "priv" }, "body": " if not(haveUsrMode()) | (not(haveSupMode()) & not(haveNExt())) then {\n assert(priv == Machine, \"invalid current privilege\");\n let enabled_pending = mip.bits & mie.bits;\n match findPendingInterrupt(enabled_pending) {\n Some(i) => let r = (i, Machine) in Some(r),\n None() => None()\n }\n } else {\n match getPendingSet(priv) {\n None() => None(),\n Some(ip, p) => match findPendingInterrupt(ip) {\n None() => None(),\n Some(i) => let r = (i, p) in Some(r)\n }\n }\n }" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 12011, 12014 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_control.sail", "loc": [ 12015, 12023 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 11990, 11993 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 11994, 12005 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 11968, 11971 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 11972, 11983 ] }, { "type": "register", "id": "mie", "file": "model/riscv_sys_control.sail", "loc": [ 12130, 12133 ] }, { "type": "register", "id": "mip", "file": "model/riscv_sys_control.sail", "loc": [ 12119, 12122 ] }, { "type": "function", "id": "findPendingInterrupt", "file": "model/riscv_sys_control.sail", "loc": [ 12150, 12170 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 12257, 12261 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 12231, 12235 ] }, { "type": "function", "id": "getPendingSet", "file": "model/riscv_sys_control.sail", "loc": [ 12291, 12304 ] }, { "type": "function", "id": "findPendingInterrupt", "file": "model/riscv_sys_control.sail", "loc": [ 12369, 12389 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 12490, 12494 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 12430, 12434 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 12334, 12338 ] } ] }, "dzFlag": { "function": { "number": 0, "source": "function dzFlag() -> bits(5) = 0b_01000", "pattern": { "type": "literal", "value": "()" }, "body": "0b_01000" } }, "effectivePrivilege": { "function": { "number": 0, "source": "function effectivePrivilege(t : AccessType(ext_access_type), m : Mstatus, priv : Privilege) -> Privilege =\n if t != Execute() & m[MPRV] == 0b1\n then privLevel_of_bits(m[MPP])\n else priv", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "t" }, { "type": "id", "id": "m" }, { "type": "id", "id": "priv" } ] }, "body": "if t != Execute() & m[MPRV] == 0b1\n then privLevel_of_bits(m[MPP])\n else priv" }, "links": [ { "type": "function", "id": "Execute", "file": "model/riscv_sys_regs.sail", "loc": [ 7414, 7421 ] }, { "type": "function", "id": "privLevel_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 7448, 7465 ] } ] }, "effective_fence_set": { "function": { "number": 0, "source": "function effective_fence_set(set : bits(4), fiom : bool) -> bits(4) = {\n // The bits are IORW. If FIOM is set then I implies R and O implies W.\n if fiom then {\n set[3 .. 2] @ (set[1 .. 0] | set[3 .. 2])\n } else set\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "set" }, { "type": "id", "id": "fiom" } ] }, "body": " if fiom then {\n set[3 .. 2] @ (set[1 .. 0] | set[3 .. 2])\n } else set" } }, "eq_unit": { "function": { "number": 0, "source": "eq_unit (_, _) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "wildcard" }, { "type": "wildcard" } ] }, "body": "true" } }, "exceptionType_to_bits": { "function": { "number": 0, "source": "function exceptionType_to_bits(e) =\n match (e) {\n E_Fetch_Addr_Align() => 0x00,\n E_Fetch_Access_Fault() => 0x01,\n E_Illegal_Instr() => 0x02,\n E_Breakpoint() => 0x03,\n E_Load_Addr_Align() => 0x04,\n E_Load_Access_Fault() => 0x05,\n E_SAMO_Addr_Align() => 0x06,\n E_SAMO_Access_Fault() => 0x07,\n E_U_EnvCall() => 0x08,\n E_S_EnvCall() => 0x09,\n E_Reserved_10() => 0x0a,\n E_M_EnvCall() => 0x0b,\n E_Fetch_Page_Fault() => 0x0c,\n E_Load_Page_Fault() => 0x0d,\n E_Reserved_14() => 0x0e,\n E_SAMO_Page_Fault() => 0x0f,\n\n /* extensions */\n E_Extension(e) => ext_exc_type_to_bits(e)\n }", "pattern": { "type": "id", "id": "e" }, "body": "match (e) {\n E_Fetch_Addr_Align() => 0x00,\n E_Fetch_Access_Fault() => 0x01,\n E_Illegal_Instr() => 0x02,\n E_Breakpoint() => 0x03,\n E_Load_Addr_Align() => 0x04,\n E_Load_Access_Fault() => 0x05,\n E_SAMO_Addr_Align() => 0x06,\n E_SAMO_Access_Fault() => 0x07,\n E_U_EnvCall() => 0x08,\n E_S_EnvCall() => 0x09,\n E_Reserved_10() => 0x0a,\n E_M_EnvCall() => 0x0b,\n E_Fetch_Page_Fault() => 0x0c,\n E_Load_Page_Fault() => 0x0d,\n E_Reserved_14() => 0x0e,\n E_SAMO_Page_Fault() => 0x0f,\n\n /* extensions */\n E_Extension(e) => ext_exc_type_to_bits(e)\n }" }, "links": [ { "type": "function", "id": "ext_exc_type_to_bits", "file": "model/riscv_types.sail", "loc": [ 5818, 5838 ] } ] }, "exceptionType_to_str": { "function": { "number": 0, "source": "function exceptionType_to_str(e) =\n match (e) {\n E_Fetch_Addr_Align() => \"misaligned-fetch\",\n E_Fetch_Access_Fault() => \"fetch-access-fault\",\n E_Illegal_Instr() => \"illegal-instruction\",\n E_Breakpoint() => \"breakpoint\",\n E_Load_Addr_Align() => \"misaligned-load\",\n E_Load_Access_Fault() => \"load-access-fault\",\n E_SAMO_Addr_Align() => \"misaligned-store/amo\",\n E_SAMO_Access_Fault() => \"store/amo-access-fault\",\n E_U_EnvCall() => \"u-call\",\n E_S_EnvCall() => \"s-call\",\n E_Reserved_10() => \"reserved-0\",\n E_M_EnvCall() => \"m-call\",\n E_Fetch_Page_Fault() => \"fetch-page-fault\",\n E_Load_Page_Fault() => \"load-page-fault\",\n E_Reserved_14() => \"reserved-1\",\n E_SAMO_Page_Fault() => \"store/amo-page-fault\",\n\n /* extensions */\n E_Extension(e) => ext_exc_type_to_str(e)\n }", "pattern": { "type": "id", "id": "e" }, "body": "match (e) {\n E_Fetch_Addr_Align() => \"misaligned-fetch\",\n E_Fetch_Access_Fault() => \"fetch-access-fault\",\n E_Illegal_Instr() => \"illegal-instruction\",\n E_Breakpoint() => \"breakpoint\",\n E_Load_Addr_Align() => \"misaligned-load\",\n E_Load_Access_Fault() => \"load-access-fault\",\n E_SAMO_Addr_Align() => \"misaligned-store/amo\",\n E_SAMO_Access_Fault() => \"store/amo-access-fault\",\n E_U_EnvCall() => \"u-call\",\n E_S_EnvCall() => \"s-call\",\n E_Reserved_10() => \"reserved-0\",\n E_M_EnvCall() => \"m-call\",\n E_Fetch_Page_Fault() => \"fetch-page-fault\",\n E_Load_Page_Fault() => \"load-page-fault\",\n E_Reserved_14() => \"reserved-1\",\n E_SAMO_Page_Fault() => \"store/amo-page-fault\",\n\n /* extensions */\n E_Extension(e) => ext_exc_type_to_str(e)\n }" }, "links": [ { "type": "function", "id": "ext_exc_type_to_str", "file": "model/riscv_types.sail", "loc": [ 7509, 7528 ] } ] }, "exception_delegatee": { "function": { "number": 0, "source": "function exception_delegatee(e : ExceptionType, p : Privilege) -> Privilege = {\n let idx = num_of_ExceptionType(e);\n let super = bit_to_bool(medeleg.bits[idx]);\n /* if S-mode is absent, medeleg delegates to U-mode if 'N' is supported. */\n let user = if haveSupMode()\n then super & haveNExt() & bit_to_bool(sedeleg.bits[idx])\n else super & haveNExt();\n let deleg = if haveUsrMode() & user then User\n else if haveSupMode() & super then Supervisor\n else Machine;\n /* We cannot transition to a less-privileged mode. */\n if privLevel_to_bits(deleg) <_u privLevel_to_bits(p)\n then p else deleg\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "e" }, { "type": "id", "id": "p" } ] }, "body": " let idx = num_of_ExceptionType(e);\n let super = bit_to_bool(medeleg.bits[idx]);\n /* if S-mode is absent, medeleg delegates to U-mode if 'N' is supported. */\n let user = if haveSupMode()\n then super & haveNExt() & bit_to_bool(sedeleg.bits[idx])\n else super & haveNExt();\n let deleg = if haveUsrMode() & user then User\n else if haveSupMode() & super then Supervisor\n else Machine;\n /* We cannot transition to a less-privileged mode. */\n if privLevel_to_bits(deleg) <_u privLevel_to_bits(p)\n then p else deleg" }, "links": [ { "type": "function", "id": "num_of_ExceptionType", "file": "model/riscv_sys_control.sail", "loc": [ 7567, 7587 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_sys_control.sail", "loc": [ 7606, 7617 ] }, { "type": "register", "id": "medeleg", "file": "model/riscv_sys_control.sail", "loc": [ 7618, 7625 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 7735, 7746 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_sys_control.sail", "loc": [ 7789, 7800 ] }, { "type": "register", "id": "sedeleg", "file": "model/riscv_sys_control.sail", "loc": [ 7801, 7808 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_control.sail", "loc": [ 7776, 7784 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_control.sail", "loc": [ 7847, 7855 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 7881, 7892 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 7935, 7946 ] }, { "type": "function", "id": "(operator <_u)", "file": "model/riscv_sys_control.sail", "loc": [ 8119, 8122 ] }, { "type": "function", "id": "privLevel_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 8123, 8140 ] }, { "type": "function", "id": "privLevel_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 8094, 8111 ] } ] }, "exception_handler": { "function": { "number": 0, "source": "function exception_handler(cur_priv : Privilege, ctl : ctl_result,\n pc: xlenbits) -> xlenbits = {\n match (cur_priv, ctl) {\n (_, CTL_TRAP(e)) => {\n let del_priv = exception_delegatee(e.trap, cur_priv);\n if get_config_print_platform()\n then print_platform(\"trapping from \" ^ to_str(cur_priv) ^ \" to \" ^ to_str(del_priv)\n ^ \" to handle \" ^ to_str(e.trap));\n trap_handler(del_priv, false, exceptionType_to_bits(e.trap), pc, e.excinfo, e.ext)\n },\n (_, CTL_MRET()) => {\n let prev_priv = cur_privilege;\n mstatus[MIE] = mstatus[MPIE];\n mstatus[MPIE] = 0b1;\n cur_privilege = privLevel_of_bits(mstatus[MPP]);\n mstatus[MPP] = privLevel_to_bits(if haveUsrMode() then User else Machine);\n if cur_privilege != Machine\n then mstatus[MPRV] = 0b0;\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n if get_config_print_platform()\n then print_platform(\"ret-ing from \" ^ to_str(prev_priv) ^ \" to \" ^ to_str(cur_privilege));\n\n cancel_reservation();\n prepare_xret_target(Machine) & pc_alignment_mask()\n },\n (_, CTL_SRET()) => {\n let prev_priv = cur_privilege;\n mstatus[SIE] = mstatus[SPIE];\n mstatus[SPIE] = 0b1;\n cur_privilege = if mstatus[SPP] == 0b1 then Supervisor else User;\n mstatus[SPP] = 0b0;\n if cur_privilege != Machine\n then mstatus[MPRV] = 0b0;\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n if get_config_print_platform()\n then print_platform(\"ret-ing from \" ^ to_str(prev_priv)\n ^ \" to \" ^ to_str(cur_privilege));\n\n cancel_reservation();\n prepare_xret_target(Supervisor) & pc_alignment_mask()\n },\n (_, CTL_URET()) => {\n let prev_priv = cur_privilege;\n mstatus[UIE] = mstatus[UPIE];\n mstatus[UPIE] = 0b1;\n cur_privilege = User;\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n if get_config_print_platform()\n then print_platform(\"ret-ing from \" ^ to_str(prev_priv) ^ \" to \" ^ to_str(cur_privilege));\n\n cancel_reservation();\n prepare_xret_target(User) & pc_alignment_mask()\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "cur_priv" }, { "type": "id", "id": "ctl" }, { "type": "id", "id": "pc" } ] }, "body": " match (cur_priv, ctl) {\n (_, CTL_TRAP(e)) => {\n let del_priv = exception_delegatee(e.trap, cur_priv);\n if get_config_print_platform()\n then print_platform(\"trapping from \" ^ to_str(cur_priv) ^ \" to \" ^ to_str(del_priv)\n ^ \" to handle \" ^ to_str(e.trap));\n trap_handler(del_priv, false, exceptionType_to_bits(e.trap), pc, e.excinfo, e.ext)\n },\n (_, CTL_MRET()) => {\n let prev_priv = cur_privilege;\n mstatus[MIE] = mstatus[MPIE];\n mstatus[MPIE] = 0b1;\n cur_privilege = privLevel_of_bits(mstatus[MPP]);\n mstatus[MPP] = privLevel_to_bits(if haveUsrMode() then User else Machine);\n if cur_privilege != Machine\n then mstatus[MPRV] = 0b0;\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n if get_config_print_platform()\n then print_platform(\"ret-ing from \" ^ to_str(prev_priv) ^ \" to \" ^ to_str(cur_privilege));\n\n cancel_reservation();\n prepare_xret_target(Machine) & pc_alignment_mask()\n },\n (_, CTL_SRET()) => {\n let prev_priv = cur_privilege;\n mstatus[SIE] = mstatus[SPIE];\n mstatus[SPIE] = 0b1;\n cur_privilege = if mstatus[SPP] == 0b1 then Supervisor else User;\n mstatus[SPP] = 0b0;\n if cur_privilege != Machine\n then mstatus[MPRV] = 0b0;\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n if get_config_print_platform()\n then print_platform(\"ret-ing from \" ^ to_str(prev_priv)\n ^ \" to \" ^ to_str(cur_privilege));\n\n cancel_reservation();\n prepare_xret_target(Supervisor) & pc_alignment_mask()\n },\n (_, CTL_URET()) => {\n let prev_priv = cur_privilege;\n mstatus[UIE] = mstatus[UPIE];\n mstatus[UPIE] = 0b1;\n cur_privilege = User;\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n if get_config_print_platform()\n then print_platform(\"ret-ing from \" ^ to_str(prev_priv) ^ \" to \" ^ to_str(cur_privilege));\n\n cancel_reservation();\n prepare_xret_target(User) & pc_alignment_mask()\n }\n }" }, "links": [ { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 17409, 17422 ] }, { "type": "function", "id": "pc_alignment_mask", "file": "model/riscv_sys_control.sail", "loc": [ 17816, 17833 ] }, { "type": "function", "id": "prepare_xret_target", "file": "model/riscv_sys_control.sail", "loc": [ 17788, 17807 ] }, { "type": "function", "id": "cancel_reservation", "file": "model/riscv_sys_control.sail", "loc": [ 17760, 17778 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 17628, 17653 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 17667, 17681 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 17736, 17749 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 17530, 17550 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 17564, 17573 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 17601, 17608 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 17494, 17507 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 17467, 17474 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 17430, 17437 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 17446, 17453 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 16754, 16767 ] }, { "type": "function", "id": "pc_alignment_mask", "file": "model/riscv_sys_control.sail", "loc": [ 17332, 17349 ] }, { "type": "function", "id": "prepare_xret_target", "file": "model/riscv_sys_control.sail", "loc": [ 17298, 17317 ] }, { "type": "function", "id": "cancel_reservation", "file": "model/riscv_sys_control.sail", "loc": [ 17270, 17288 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 17112, 17137 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 17151, 17165 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 17246, 17259 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 17014, 17034 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 17048, 17057 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 17085, 17092 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 16945, 16958 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16981, 16988 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16913, 16920 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 16839, 16852 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16860, 16867 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16812, 16819 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16775, 16782 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16791, 16798 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 16090, 16103 ] }, { "type": "function", "id": "pc_alignment_mask", "file": "model/riscv_sys_control.sail", "loc": [ 16677, 16694 ] }, { "type": "function", "id": "prepare_xret_target", "file": "model/riscv_sys_control.sail", "loc": [ 16646, 16665 ] }, { "type": "function", "id": "cancel_reservation", "file": "model/riscv_sys_control.sail", "loc": [ 16618, 16636 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 16486, 16511 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 16525, 16539 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 16594, 16607 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 16388, 16408 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 16422, 16431 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16459, 16466 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 16319, 16332 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16355, 16362 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16232, 16239 ] }, { "type": "function", "id": "privLevel_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 16248, 16265 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 16269, 16280 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 16175, 16188 ] }, { "type": "function", "id": "privLevel_of_bits", "file": "model/riscv_sys_control.sail", "loc": [ 16193, 16210 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16211, 16218 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16148, 16155 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16111, 16118 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 16127, 16134 ] }, { "type": "function", "id": "exception_delegatee", "file": "model/riscv_sys_control.sail", "loc": [ 15715, 15734 ] }, { "type": "function", "id": "trap_handler", "file": "model/riscv_sys_control.sail", "loc": [ 15950, 15962 ] }, { "type": "function", "id": "exceptionType_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 15980, 16001 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 15765, 15790 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 15804, 15818 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "exceptionType_to_str", "file": "model/riscv_types.sail", "loc": [ 7556, 7576 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] } ] }, "execute": { "function": [ { "number": 0, "source": "function clause execute UTYPE(imm, rd, op) = {\n let off : xlenbits = sign_extend(imm @ 0x000);\n let ret : xlenbits = match op {\n RISCV_LUI => off,\n RISCV_AUIPC => get_arch_pc() + off\n };\n X(rd) = ret;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "UTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let off : xlenbits = sign_extend(imm @ 0x000);\n let ret : xlenbits = match op {\n RISCV_LUI => off,\n RISCV_AUIPC => get_arch_pc() + off\n };\n X(rd) = ret;\n RETIRE_SUCCESS" }, { "number": 1, "source": "function clause execute (RISCV_JAL(imm, rd)) = {\n let t : xlenbits = PC + sign_extend(imm);\n /* Extensions get the first checks on the prospective target address. */\n match ext_control_check_pc(t) {\n Ext_ControlAddr_Error(e) => {\n ext_handle_control_check_error(e);\n RETIRE_FAIL\n },\n Ext_ControlAddr_OK(target) => {\n /* Perform standard alignment check */\n if bit_to_bool(target[1]) & not(haveRVC())\n then {\n handle_mem_exception(target, E_Fetch_Addr_Align());\n RETIRE_FAIL\n } else {\n X(rd) = get_next_pc();\n set_next_pc(target);\n RETIRE_SUCCESS\n }\n }\n }\n}", "pattern": { "type": "app", "id": "RISCV_JAL", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let t : xlenbits = PC + sign_extend(imm);\n /* Extensions get the first checks on the prospective target address. */\n match ext_control_check_pc(t) {\n Ext_ControlAddr_Error(e) => {\n ext_handle_control_check_error(e);\n RETIRE_FAIL\n },\n Ext_ControlAddr_OK(target) => {\n /* Perform standard alignment check */\n if bit_to_bool(target[1]) & not(haveRVC())\n then {\n handle_mem_exception(target, E_Fetch_Addr_Align());\n RETIRE_FAIL\n } else {\n X(rd) = get_next_pc();\n set_next_pc(target);\n RETIRE_SUCCESS\n }\n }\n }" }, { "number": 2, "source": "function clause execute (BTYPE(imm, rs2, rs1, op)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let taken : bool = match op {\n RISCV_BEQ => rs1_val == rs2_val,\n RISCV_BNE => rs1_val != rs2_val,\n RISCV_BLT => rs1_val <_s rs2_val,\n RISCV_BGE => rs1_val >=_s rs2_val,\n RISCV_BLTU => rs1_val <_u rs2_val,\n RISCV_BGEU => rs1_val >=_u rs2_val\n };\n let t : xlenbits = PC + sign_extend(imm);\n if taken then {\n /* Extensions get the first checks on the prospective target address. */\n match ext_control_check_pc(t) {\n Ext_ControlAddr_Error(e) => {\n ext_handle_control_check_error(e);\n RETIRE_FAIL\n },\n Ext_ControlAddr_OK(target) => {\n if bit_to_bool(target[1]) & not(haveRVC()) then {\n handle_mem_exception(target, E_Fetch_Addr_Align());\n RETIRE_FAIL;\n } else {\n set_next_pc(target);\n RETIRE_SUCCESS\n }\n }\n }\n } else RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "BTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let taken : bool = match op {\n RISCV_BEQ => rs1_val == rs2_val,\n RISCV_BNE => rs1_val != rs2_val,\n RISCV_BLT => rs1_val <_s rs2_val,\n RISCV_BGE => rs1_val >=_s rs2_val,\n RISCV_BLTU => rs1_val <_u rs2_val,\n RISCV_BGEU => rs1_val >=_u rs2_val\n };\n let t : xlenbits = PC + sign_extend(imm);\n if taken then {\n /* Extensions get the first checks on the prospective target address. */\n match ext_control_check_pc(t) {\n Ext_ControlAddr_Error(e) => {\n ext_handle_control_check_error(e);\n RETIRE_FAIL\n },\n Ext_ControlAddr_OK(target) => {\n if bit_to_bool(target[1]) & not(haveRVC()) then {\n handle_mem_exception(target, E_Fetch_Addr_Align());\n RETIRE_FAIL;\n } else {\n set_next_pc(target);\n RETIRE_SUCCESS\n }\n }\n }\n } else RETIRE_SUCCESS" }, { "number": 3, "source": "function clause execute (ITYPE (imm, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let immext : xlenbits = sign_extend(imm);\n let result : xlenbits = match op {\n RISCV_ADDI => rs1_val + immext,\n RISCV_SLTI => zero_extend(bool_to_bits(rs1_val <_s immext)),\n RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)),\n RISCV_ANDI => rs1_val & immext,\n RISCV_ORI => rs1_val | immext,\n RISCV_XORI => rs1_val ^ immext\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ITYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let immext : xlenbits = sign_extend(imm);\n let result : xlenbits = match op {\n RISCV_ADDI => rs1_val + immext,\n RISCV_SLTI => zero_extend(bool_to_bits(rs1_val <_s immext)),\n RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)),\n RISCV_ANDI => rs1_val & immext,\n RISCV_ORI => rs1_val | immext,\n RISCV_XORI => rs1_val ^ immext\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 4, "source": "function clause execute (SHIFTIOP(shamt, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n /* the decoder guard should ensure that shamt[5] = 0 for RV32 */\n let result : xlenbits = match op {\n RISCV_SLLI => if sizeof(xlen) == 32\n then rs1_val << shamt[4..0]\n else rs1_val << shamt,\n RISCV_SRLI => if sizeof(xlen) == 32\n then rs1_val >> shamt[4..0]\n else rs1_val >> shamt,\n RISCV_SRAI => if sizeof(xlen) == 32\n then shift_right_arith32(rs1_val, shamt[4..0])\n else shift_right_arith64(rs1_val, shamt)\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHIFTIOP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n /* the decoder guard should ensure that shamt[5] = 0 for RV32 */\n let result : xlenbits = match op {\n RISCV_SLLI => if sizeof(xlen) == 32\n then rs1_val << shamt[4..0]\n else rs1_val << shamt,\n RISCV_SRLI => if sizeof(xlen) == 32\n then rs1_val >> shamt[4..0]\n else rs1_val >> shamt,\n RISCV_SRAI => if sizeof(xlen) == 32\n then shift_right_arith32(rs1_val, shamt[4..0])\n else shift_right_arith64(rs1_val, shamt)\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 5, "source": "function clause execute (RTYPE(rs2, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let result : xlenbits = match op {\n RISCV_ADD => rs1_val + rs2_val,\n RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)),\n RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)),\n RISCV_AND => rs1_val & rs2_val,\n RISCV_OR => rs1_val | rs2_val,\n RISCV_XOR => rs1_val ^ rs2_val,\n RISCV_SLL => if sizeof(xlen) == 32\n then rs1_val << (rs2_val[4..0])\n else rs1_val << (rs2_val[5..0]),\n RISCV_SRL => if sizeof(xlen) == 32\n then rs1_val >> (rs2_val[4..0])\n else rs1_val >> (rs2_val[5..0]),\n RISCV_SUB => rs1_val - rs2_val,\n RISCV_SRA => if sizeof(xlen) == 32\n then shift_right_arith32(rs1_val, rs2_val[4..0])\n else shift_right_arith64(rs1_val, rs2_val[5..0])\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let result : xlenbits = match op {\n RISCV_ADD => rs1_val + rs2_val,\n RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)),\n RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)),\n RISCV_AND => rs1_val & rs2_val,\n RISCV_OR => rs1_val | rs2_val,\n RISCV_XOR => rs1_val ^ rs2_val,\n RISCV_SLL => if sizeof(xlen) == 32\n then rs1_val << (rs2_val[4..0])\n else rs1_val << (rs2_val[5..0]),\n RISCV_SRL => if sizeof(xlen) == 32\n then rs1_val >> (rs2_val[4..0])\n else rs1_val >> (rs2_val[5..0]),\n RISCV_SUB => rs1_val - rs2_val,\n RISCV_SRA => if sizeof(xlen) == 32\n then shift_right_arith32(rs1_val, rs2_val[4..0])\n else shift_right_arith64(rs1_val, rs2_val[5..0])\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 6, "source": "function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = {\n let offset : xlenbits = sign_extend(imm);\n /* Get the address, X(rs1) + offset.\n Some extensions perform additional checks on address validity. */\n match ext_data_get_addr(rs1, offset, Read(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(paddr, _) =>\n match (width) {\n BYTE =>\n process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned),\n HALF =>\n process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned),\n WORD =>\n process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned),\n DOUBLE if sizeof(xlen) >= 64 =>\n process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned),\n _ => report_invalid_width(__FILE__, __LINE__, width, \"load\")\n }\n }\n }\n}", "pattern": { "type": "app", "id": "LOAD", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "is_unsigned" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" } ] } ] }, "body": " let offset : xlenbits = sign_extend(imm);\n /* Get the address, X(rs1) + offset.\n Some extensions perform additional checks on address validity. */\n match ext_data_get_addr(rs1, offset, Read(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(paddr, _) =>\n match (width) {\n BYTE =>\n process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned),\n HALF =>\n process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned),\n WORD =>\n process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned),\n DOUBLE if sizeof(xlen) >= 64 =>\n process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned),\n _ => report_invalid_width(__FILE__, __LINE__, width, \"load\")\n }\n }\n }" }, { "number": 7, "source": "function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) = {\n let offset : xlenbits = sign_extend(imm);\n /* Get the address, X(rs1) + offset.\n Some extensions perform additional checks on address validity. */\n match ext_data_get_addr(rs1, offset, Write(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = match width {\n BYTE => mem_write_ea(paddr, 1, aq, rl, false),\n HALF => mem_write_ea(paddr, 2, aq, rl, false),\n WORD => mem_write_ea(paddr, 4, aq, rl, false),\n DOUBLE => mem_write_ea(paddr, 8, aq, rl, false)\n };\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(_) => {\n let rs2_val = X(rs2);\n let res : MemoryOpResult(bool) = match (width) {\n BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false),\n HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false),\n WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false),\n DOUBLE if sizeof(xlen) >= 64\n => mem_write_value(paddr, 8, rs2_val, aq, rl, false),\n _ => report_invalid_width(__FILE__, __LINE__, width, \"store\"),\n };\n match (res) {\n MemValue(true) => RETIRE_SUCCESS,\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n}", "pattern": { "type": "app", "id": "STORE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" } ] } ] }, "body": " let offset : xlenbits = sign_extend(imm);\n /* Get the address, X(rs1) + offset.\n Some extensions perform additional checks on address validity. */\n match ext_data_get_addr(rs1, offset, Write(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = match width {\n BYTE => mem_write_ea(paddr, 1, aq, rl, false),\n HALF => mem_write_ea(paddr, 2, aq, rl, false),\n WORD => mem_write_ea(paddr, 4, aq, rl, false),\n DOUBLE => mem_write_ea(paddr, 8, aq, rl, false)\n };\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(_) => {\n let rs2_val = X(rs2);\n let res : MemoryOpResult(bool) = match (width) {\n BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false),\n HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false),\n WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false),\n DOUBLE if sizeof(xlen) >= 64\n => mem_write_value(paddr, 8, rs2_val, aq, rl, false),\n _ => report_invalid_width(__FILE__, __LINE__, width, \"store\"),\n };\n match (res) {\n MemValue(true) => RETIRE_SUCCESS,\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }\n }\n }\n }\n }\n }" }, { "number": 8, "source": "function clause execute (ADDIW(imm, rs1, rd)) = {\n let result : xlenbits = sign_extend(imm) + X(rs1);\n X(rd) = sign_extend(result[31..0]);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ADDIW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let result : xlenbits = sign_extend(imm) + X(rs1);\n X(rd) = sign_extend(result[31..0]);\n RETIRE_SUCCESS" }, { "number": 9, "source": "function clause execute (RTYPEW(rs2, rs1, rd, op)) = {\n let rs1_val = (X(rs1))[31..0];\n let rs2_val = (X(rs2))[31..0];\n let result : bits(32) = match op {\n RISCV_ADDW => rs1_val + rs2_val,\n RISCV_SUBW => rs1_val - rs2_val,\n RISCV_SLLW => rs1_val << (rs2_val[4..0]),\n RISCV_SRLW => rs1_val >> (rs2_val[4..0]),\n RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0])\n };\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RTYPEW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = (X(rs1))[31..0];\n let rs2_val = (X(rs2))[31..0];\n let result : bits(32) = match op {\n RISCV_ADDW => rs1_val + rs2_val,\n RISCV_SUBW => rs1_val - rs2_val,\n RISCV_SLLW => rs1_val << (rs2_val[4..0]),\n RISCV_SRLW => rs1_val >> (rs2_val[4..0]),\n RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0])\n };\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 10, "source": "function clause execute (SHIFTIWOP(shamt, rs1, rd, op)) = {\n let rs1_val = (X(rs1))[31..0];\n let result : bits(32) = match op {\n RISCV_SLLIW => rs1_val << shamt,\n RISCV_SRLIW => rs1_val >> shamt,\n RISCV_SRAIW => shift_right_arith32(rs1_val, shamt)\n };\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHIFTIWOP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = (X(rs1))[31..0];\n let result : bits(32) = match op {\n RISCV_SLLIW => rs1_val << shamt,\n RISCV_SRLIW => rs1_val >> shamt,\n RISCV_SRAIW => shift_right_arith32(rs1_val, shamt)\n };\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 11, "source": "function clause execute (FENCE(pred, succ)) = {\n // If the FIOM bit in menvcfg/senvcfg is set then the I/O bits can imply R/W.\n let fiom = is_fiom_active();\n let pred = effective_fence_set(pred, fiom);\n let succ = effective_fence_set(succ, fiom);\n\n match (pred, succ) {\n (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_rw_rw()),\n (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_r_rw()),\n (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_r_r()),\n (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_rw_w()),\n (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_w_w()),\n (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_w_rw()),\n (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_rw_r()),\n (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_r_w()),\n (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_w_r()),\n\n (_ : bits(4) , _ : bits(2) @ 0b00) => (),\n (_ : bits(2) @ 0b00, _ : bits(4) ) => (),\n\n _ => { print(\"FIXME: unsupported fence\");\n () }\n };\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FENCE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" } ] } ] }, "body": " let fiom = is_fiom_active();\n let pred = effective_fence_set(pred, fiom);\n let succ = effective_fence_set(succ, fiom);\n\n match (pred, succ) {\n (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_rw_rw()),\n (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_r_rw()),\n (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_r_r()),\n (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_rw_w()),\n (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_w_w()),\n (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_w_rw()),\n (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_rw_r()),\n (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_r_w()),\n (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_w_r()),\n\n (_ : bits(4) , _ : bits(2) @ 0b00) => (),\n (_ : bits(2) @ 0b00, _ : bits(4) ) => (),\n\n _ => { print(\"FIXME: unsupported fence\");\n () }\n };\n RETIRE_SUCCESS" }, { "number": 12, "source": "function clause execute (FENCE_TSO(pred, succ)) = {\n match (pred, succ) {\n (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_tso()),\n (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => (),\n\n _ => { print(\"FIXME: unsupported fence\");\n () }\n };\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FENCE_TSO", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" } ] } ] }, "body": " match (pred, succ) {\n (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_tso()),\n (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => (),\n\n _ => { print(\"FIXME: unsupported fence\");\n () }\n };\n RETIRE_SUCCESS" }, { "number": 13, "source": "function clause execute FENCEI() = { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS }", "pattern": { "type": "app", "id": "FENCEI", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": "function clause execute FENCEI() = { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS" }, { "number": 14, "source": "function clause execute ECALL() = {\n let t : sync_exception =\n struct { trap = match (cur_privilege) {\n User => E_U_EnvCall(),\n Supervisor => E_S_EnvCall(),\n Machine => E_M_EnvCall()\n },\n excinfo = (None() : option(xlenbits)),\n ext = None() };\n set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC));\n RETIRE_FAIL\n}", "pattern": { "type": "app", "id": "ECALL", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": " let t : sync_exception =\n struct { trap = match (cur_privilege) {\n User => E_U_EnvCall(),\n Supervisor => E_S_EnvCall(),\n Machine => E_M_EnvCall()\n },\n excinfo = (None() : option(xlenbits)),\n ext = None() };\n set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC));\n RETIRE_FAIL" }, { "number": 15, "source": "function clause execute MRET() = {\n if cur_privilege != Machine\n then { handle_illegal(); RETIRE_FAIL }\n else if not(ext_check_xret_priv (Machine))\n then { ext_fail_xret_priv(); RETIRE_FAIL }\n else {\n set_next_pc(exception_handler(cur_privilege, CTL_MRET(), PC));\n RETIRE_SUCCESS\n }\n}", "pattern": { "type": "app", "id": "MRET", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": " if cur_privilege != Machine\n then { handle_illegal(); RETIRE_FAIL }\n else if not(ext_check_xret_priv (Machine))\n then { ext_fail_xret_priv(); RETIRE_FAIL }\n else {\n set_next_pc(exception_handler(cur_privilege, CTL_MRET(), PC));\n RETIRE_SUCCESS\n }" }, { "number": 16, "source": "function clause execute SRET() = {\n let sret_illegal : bool = match cur_privilege {\n User => true,\n Supervisor => not(haveSupMode ()) | mstatus[TSR] == 0b1,\n Machine => not(haveSupMode ())\n };\n if sret_illegal\n then { handle_illegal(); RETIRE_FAIL }\n else if not(ext_check_xret_priv (Supervisor))\n then { ext_fail_xret_priv(); RETIRE_FAIL }\n else {\n set_next_pc(exception_handler(cur_privilege, CTL_SRET(), PC));\n RETIRE_SUCCESS\n }\n}", "pattern": { "type": "app", "id": "SRET", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": " let sret_illegal : bool = match cur_privilege {\n User => true,\n Supervisor => not(haveSupMode ()) | mstatus[TSR] == 0b1,\n Machine => not(haveSupMode ())\n };\n if sret_illegal\n then { handle_illegal(); RETIRE_FAIL }\n else if not(ext_check_xret_priv (Supervisor))\n then { ext_fail_xret_priv(); RETIRE_FAIL }\n else {\n set_next_pc(exception_handler(cur_privilege, CTL_SRET(), PC));\n RETIRE_SUCCESS\n }" }, { "number": 17, "source": "function clause execute EBREAK() = {\n handle_mem_exception(PC, E_Breakpoint());\n RETIRE_FAIL\n}", "pattern": { "type": "app", "id": "EBREAK", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": " handle_mem_exception(PC, E_Breakpoint());\n RETIRE_FAIL" }, { "number": 18, "source": "function clause execute WFI() =\n match cur_privilege {\n Machine => { platform_wfi(); RETIRE_SUCCESS },\n Supervisor => if mstatus[TW] == 0b1\n then { handle_illegal(); RETIRE_FAIL }\n else { platform_wfi(); RETIRE_SUCCESS },\n User => { handle_illegal(); RETIRE_FAIL }\n }", "pattern": { "type": "app", "id": "WFI", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": "match cur_privilege {\n Machine => { platform_wfi(); RETIRE_SUCCESS },\n Supervisor => if mstatus[TW] == 0b1\n then { handle_illegal(); RETIRE_FAIL }\n else { platform_wfi(); RETIRE_SUCCESS },\n User => { handle_illegal(); RETIRE_FAIL }\n }" }, { "number": 19, "source": "function clause execute SFENCE_VMA(rs1, rs2) = {\n let addr : option(xlenbits) = if rs1 == 0b00000 then None() else Some(X(rs1));\n let asid : option(xlenbits) = if rs2 == 0b00000 then None() else Some(X(rs2));\n match cur_privilege {\n User => { handle_illegal(); RETIRE_FAIL },\n Supervisor => match (architecture(get_mstatus_SXL(mstatus)), mstatus[TVM]) {\n (Some(_), 0b1) => { handle_illegal(); RETIRE_FAIL },\n (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS },\n (_, _) => internal_error(__FILE__, __LINE__, \"unimplemented sfence architecture\")\n },\n Machine => { flush_TLB(asid, addr); RETIRE_SUCCESS }\n }\n}", "pattern": { "type": "app", "id": "SFENCE_VMA", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let addr : option(xlenbits) = if rs1 == 0b00000 then None() else Some(X(rs1));\n let asid : option(xlenbits) = if rs2 == 0b00000 then None() else Some(X(rs2));\n match cur_privilege {\n User => { handle_illegal(); RETIRE_FAIL },\n Supervisor => match (architecture(get_mstatus_SXL(mstatus)), mstatus[TVM]) {\n (Some(_), 0b1) => { handle_illegal(); RETIRE_FAIL },\n (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS },\n (_, _) => internal_error(__FILE__, __LINE__, \"unimplemented sfence architecture\")\n },\n Machine => { flush_TLB(asid, addr); RETIRE_SUCCESS }\n }" }, { "number": 20, "source": "function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {\n if haveAtomics() then {\n /* Get the address, X(rs1) (no offset).\n * Extensions might perform additional checks on address validity.\n */\n match ext_data_get_addr(rs1, zeros(), Read(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) => {\n let aligned : bool =\n /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt\n * to treat them as valid here; otherwise we'd need to throw an internal_error.\n */\n match width {\n BYTE => true,\n HALF => vaddr[0..0] == 0b0,\n WORD => vaddr[1..0] == 0b00,\n DOUBLE => vaddr[2..0] == 0b000\n };\n /* \"LR faults like a normal load, even though it's in the AMO major opcode space.\"\n * - Andrew Waterman, isa-dev, 10 Jul 2018.\n */\n if not(aligned)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) =>\n match (width, sizeof(xlen)) {\n (BYTE, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 1, aq, aq & rl, true), false),\n (HALF, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 2, aq, aq & rl, true), false),\n (WORD, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 4, aq, aq & rl, true), false),\n (DOUBLE, 64) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 8, aq, aq & rl, true), false),\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AMO width\")\n }\n }\n }\n }\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n}", "pattern": { "type": "app", "id": "LOADRES", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "rd" } ] } ] }, "body": " if haveAtomics() then {\n /* Get the address, X(rs1) (no offset).\n * Extensions might perform additional checks on address validity.\n */\n match ext_data_get_addr(rs1, zeros(), Read(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) => {\n let aligned : bool =\n /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt\n * to treat them as valid here; otherwise we'd need to throw an internal_error.\n */\n match width {\n BYTE => true,\n HALF => vaddr[0..0] == 0b0,\n WORD => vaddr[1..0] == 0b00,\n DOUBLE => vaddr[2..0] == 0b000\n };\n /* \"LR faults like a normal load, even though it's in the AMO major opcode space.\"\n * - Andrew Waterman, isa-dev, 10 Jul 2018.\n */\n if not(aligned)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) =>\n match (width, sizeof(xlen)) {\n (BYTE, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 1, aq, aq & rl, true), false),\n (HALF, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 2, aq, aq & rl, true), false),\n (WORD, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 4, aq, aq & rl, true), false),\n (DOUBLE, 64) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 8, aq, aq & rl, true), false),\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AMO width\")\n }\n }\n }\n }\n } else {\n handle_illegal();\n RETIRE_FAIL\n }" }, { "number": 21, "source": "function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {\n if speculate_conditional () == false then {\n /* should only happen in rmem\n * rmem: allow SC to fail very early\n */\n X(rd) = zero_extend(0b1); RETIRE_SUCCESS\n } else {\n if haveAtomics() then {\n /* normal non-rmem case\n * rmem: SC is allowed to succeed (but might fail later)\n */\n /* Get the address, X(rs1) (no offset).\n * Extensions might perform additional checks on address validity.\n */\n match ext_data_get_addr(rs1, zeros(), Write(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) => {\n let aligned : bool =\n /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt\n * to treat them as valid here; otherwise we'd need to throw an internal_error.\n */\n match width {\n BYTE => true,\n HALF => vaddr[0..0] == 0b0,\n WORD => vaddr[1..0] == 0b00,\n DOUBLE => vaddr[2..0] == 0b000\n };\n if not(aligned)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }\n else {\n if match_reservation(vaddr) == false then {\n /* cannot happen in rmem */\n X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS\n } else {\n match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here:\n * both result in a SAMO exception */\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) => {\n let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {\n (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),\n (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),\n (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true),\n (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true),\n _ => internal_error(__FILE__, __LINE__, \"STORECON expected word or double\")\n };\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(_) => {\n rs2_val = X(rs2);\n let res : MemoryOpResult(bool) = match (width, sizeof(xlen)) {\n (BYTE, _) => mem_write_value(addr, 1, rs2_val[7..0], aq & rl, rl, true),\n (HALF, _) => mem_write_value(addr, 2, rs2_val[15..0], aq & rl, rl, true),\n (WORD, _) => mem_write_value(addr, 4, rs2_val[31..0], aq & rl, rl, true),\n (DOUBLE, 64) => mem_write_value(addr, 8, rs2_val, aq & rl, rl, true),\n _ => internal_error(__FILE__, __LINE__, \"STORECON expected word or double\")\n };\n match (res) {\n MemValue(true) => { X(rd) = zero_extend(0b0); cancel_reservation(); RETIRE_SUCCESS },\n MemValue(false) => { X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n }\n}", "pattern": { "type": "app", "id": "STORECON", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "rd" } ] } ] }, "body": " if speculate_conditional () == false then {\n /* should only happen in rmem\n * rmem: allow SC to fail very early\n */\n X(rd) = zero_extend(0b1); RETIRE_SUCCESS\n } else {\n if haveAtomics() then {\n /* normal non-rmem case\n * rmem: SC is allowed to succeed (but might fail later)\n */\n /* Get the address, X(rs1) (no offset).\n * Extensions might perform additional checks on address validity.\n */\n match ext_data_get_addr(rs1, zeros(), Write(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) => {\n let aligned : bool =\n /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt\n * to treat them as valid here; otherwise we'd need to throw an internal_error.\n */\n match width {\n BYTE => true,\n HALF => vaddr[0..0] == 0b0,\n WORD => vaddr[1..0] == 0b00,\n DOUBLE => vaddr[2..0] == 0b000\n };\n if not(aligned)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }\n else {\n if match_reservation(vaddr) == false then {\n /* cannot happen in rmem */\n X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS\n } else {\n match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here:\n * both result in a SAMO exception */\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) => {\n let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {\n (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),\n (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),\n (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true),\n (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true),\n _ => internal_error(__FILE__, __LINE__, \"STORECON expected word or double\")\n };\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(_) => {\n rs2_val = X(rs2);\n let res : MemoryOpResult(bool) = match (width, sizeof(xlen)) {\n (BYTE, _) => mem_write_value(addr, 1, rs2_val[7..0], aq & rl, rl, true),\n (HALF, _) => mem_write_value(addr, 2, rs2_val[15..0], aq & rl, rl, true),\n (WORD, _) => mem_write_value(addr, 4, rs2_val[31..0], aq & rl, rl, true),\n (DOUBLE, 64) => mem_write_value(addr, 8, rs2_val, aq & rl, rl, true),\n _ => internal_error(__FILE__, __LINE__, \"STORECON expected word or double\")\n };\n match (res) {\n MemValue(true) => { X(rd) = zero_extend(0b0); cancel_reservation(); RETIRE_SUCCESS },\n MemValue(false) => { X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n }" }, { "number": 22, "source": "function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {\n if haveAtomics() then {\n /* Get the address, X(rs1) (no offset).\n * Some extensions perform additional checks on address validity.\n */\n match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) => {\n match translateAddr(vaddr, ReadWrite(Data, Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) => {\n let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {\n (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),\n (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),\n (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true),\n (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true),\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AMO width\")\n };\n let is_unsigned : bool = match op {\n AMOMINU => true,\n AMOMAXU => true,\n _ => false\n };\n let rs2_val : xlenbits = match width {\n BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]),\n HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]),\n WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]),\n DOUBLE => X(rs2)\n };\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(_) => {\n let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) {\n (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)),\n (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)),\n (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)),\n (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)),\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AMO width\")\n };\n match (mval) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(loaded) => {\n let result : xlenbits =\n match op {\n AMOSWAP => rs2_val,\n AMOADD => rs2_val + loaded,\n AMOXOR => rs2_val ^ loaded,\n AMOAND => rs2_val & loaded,\n AMOOR => rs2_val | loaded,\n\n /* These operations convert bitvectors to integer values using [un]signed,\n * and back using to_bits().\n */\n AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))),\n AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))),\n AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))),\n AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded)))\n };\n let rval : xlenbits = match width {\n BYTE => sign_extend(loaded[7..0]),\n HALF => sign_extend(loaded[15..0]),\n WORD => sign_extend(loaded[31..0]),\n DOUBLE => loaded\n };\n let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) {\n (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true),\n (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true),\n (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true),\n (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true),\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AMO width\")\n };\n match (wval) {\n MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS },\n MemValue(false) => { internal_error(__FILE__, __LINE__, \"AMO got false from mem_write_value\") },\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n}", "pattern": { "type": "app", "id": "AMO", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "op" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "rd" } ] } ] }, "body": " if haveAtomics() then {\n /* Get the address, X(rs1) (no offset).\n * Some extensions perform additional checks on address validity.\n */\n match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) => {\n match translateAddr(vaddr, ReadWrite(Data, Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) => {\n let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {\n (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),\n (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),\n (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true),\n (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true),\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AMO width\")\n };\n let is_unsigned : bool = match op {\n AMOMINU => true,\n AMOMAXU => true,\n _ => false\n };\n let rs2_val : xlenbits = match width {\n BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]),\n HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]),\n WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]),\n DOUBLE => X(rs2)\n };\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(_) => {\n let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) {\n (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)),\n (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)),\n (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)),\n (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)),\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AMO width\")\n };\n match (mval) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(loaded) => {\n let result : xlenbits =\n match op {\n AMOSWAP => rs2_val,\n AMOADD => rs2_val + loaded,\n AMOXOR => rs2_val ^ loaded,\n AMOAND => rs2_val & loaded,\n AMOOR => rs2_val | loaded,\n\n /* These operations convert bitvectors to integer values using [un]signed,\n * and back using to_bits().\n */\n AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))),\n AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))),\n AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))),\n AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded)))\n };\n let rval : xlenbits = match width {\n BYTE => sign_extend(loaded[7..0]),\n HALF => sign_extend(loaded[15..0]),\n WORD => sign_extend(loaded[31..0]),\n DOUBLE => loaded\n };\n let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) {\n (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true),\n (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true),\n (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true),\n (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true),\n _ => internal_error(__FILE__, __LINE__, \"Unexpected AMO width\")\n };\n match (wval) {\n MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS },\n MemValue(false) => { internal_error(__FILE__, __LINE__, \"AMO got false from mem_write_value\") },\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n } else {\n handle_illegal();\n RETIRE_FAIL\n }" }, { "number": 23, "source": "function clause execute C_NOP() = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_NOP", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 24, "source": "function clause execute (C_ADDI4SPN(rdc, nzimm)) = {\n let imm : bits(12) = (0b00 @ nzimm @ 0b00);\n let rd = creg2reg_idx(rdc);\n execute(ITYPE(imm, sp, rd, RISCV_ADDI))\n}", "pattern": { "type": "app", "id": "C_ADDI4SPN", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rdc" }, { "type": "id", "id": "nzimm" } ] } ] }, "body": " let imm : bits(12) = (0b00 @ nzimm @ 0b00);\n let rd = creg2reg_idx(rdc);\n execute(ITYPE(imm, sp, rd, RISCV_ADDI))" }, { "number": 25, "source": "function clause execute (C_LW(uimm, rsc, rdc)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b00);\n let rd = creg2reg_idx(rdc);\n let rs = creg2reg_idx(rsc);\n execute(LOAD(imm, rs, rd, false, WORD, false, false))\n}", "pattern": { "type": "app", "id": "C_LW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc" }, { "type": "id", "id": "rdc" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b00);\n let rd = creg2reg_idx(rdc);\n let rs = creg2reg_idx(rsc);\n execute(LOAD(imm, rs, rd, false, WORD, false, false))" }, { "number": 26, "source": "function clause execute (C_LD(uimm, rsc, rdc)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b000);\n let rd = creg2reg_idx(rdc);\n let rs = creg2reg_idx(rsc);\n execute(LOAD(imm, rs, rd, false, DOUBLE, false, false))\n}", "pattern": { "type": "app", "id": "C_LD", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc" }, { "type": "id", "id": "rdc" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b000);\n let rd = creg2reg_idx(rdc);\n let rs = creg2reg_idx(rsc);\n execute(LOAD(imm, rs, rd, false, DOUBLE, false, false))" }, { "number": 27, "source": "function clause execute (C_SW(uimm, rsc1, rsc2)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b00);\n let rs1 = creg2reg_idx(rsc1);\n let rs2 = creg2reg_idx(rsc2);\n execute(STORE(imm, rs2, rs1, WORD, false, false))\n}", "pattern": { "type": "app", "id": "C_SW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc1" }, { "type": "id", "id": "rsc2" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b00);\n let rs1 = creg2reg_idx(rsc1);\n let rs2 = creg2reg_idx(rsc2);\n execute(STORE(imm, rs2, rs1, WORD, false, false))" }, { "number": 28, "source": "function clause execute (C_SD(uimm, rsc1, rsc2)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b000);\n let rs1 = creg2reg_idx(rsc1);\n let rs2 = creg2reg_idx(rsc2);\n execute(STORE(imm, rs2, rs1, DOUBLE, false, false))\n}", "pattern": { "type": "app", "id": "C_SD", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc1" }, { "type": "id", "id": "rsc2" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b000);\n let rs1 = creg2reg_idx(rsc1);\n let rs2 = creg2reg_idx(rsc2);\n execute(STORE(imm, rs2, rs1, DOUBLE, false, false))" }, { "number": 29, "source": "function clause execute (C_ADDI(nzi, rsd)) = {\n let imm : bits(12) = sign_extend(nzi);\n execute(ITYPE(imm, rsd, rsd, RISCV_ADDI))\n}", "pattern": { "type": "app", "id": "C_ADDI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nzi" }, { "type": "id", "id": "rsd" } ] } ] }, "body": " let imm : bits(12) = sign_extend(nzi);\n execute(ITYPE(imm, rsd, rsd, RISCV_ADDI))" }, { "number": 30, "source": "function clause execute (C_JAL(imm)) =\n execute(RISCV_JAL(sign_extend(imm @ 0b0), ra))", "pattern": { "type": "app", "id": "C_JAL", "patterns": [ { "type": "id", "id": "imm" } ] }, "body": "execute(RISCV_JAL(sign_extend(imm @ 0b0), ra))" }, { "number": 31, "source": "function clause execute (C_ADDIW(imm, rsd)) =\n execute(ADDIW(sign_extend(imm), rsd, rsd))", "pattern": { "type": "app", "id": "C_ADDIW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rsd" } ] } ] }, "body": "execute(ADDIW(sign_extend(imm), rsd, rsd))" }, { "number": 32, "source": "function clause execute (C_LI(imm, rd)) = {\n let imm : bits(12) = sign_extend(imm);\n execute(ITYPE(imm, zreg, rd, RISCV_ADDI))\n}", "pattern": { "type": "app", "id": "C_LI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let imm : bits(12) = sign_extend(imm);\n execute(ITYPE(imm, zreg, rd, RISCV_ADDI))" }, { "number": 33, "source": "function clause execute (C_ADDI16SP(imm)) = {\n let imm : bits(12) = sign_extend(imm @ 0x0);\n execute(ITYPE(imm, sp, sp, RISCV_ADDI))\n}", "pattern": { "type": "app", "id": "C_ADDI16SP", "patterns": [ { "type": "id", "id": "imm" } ] }, "body": " let imm : bits(12) = sign_extend(imm @ 0x0);\n execute(ITYPE(imm, sp, sp, RISCV_ADDI))" }, { "number": 34, "source": "function clause execute (C_LUI(imm, rd)) = {\n let res : bits(20) = sign_extend(imm);\n execute(UTYPE(res, rd, RISCV_LUI))\n}", "pattern": { "type": "app", "id": "C_LUI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let res : bits(20) = sign_extend(imm);\n execute(UTYPE(res, rd, RISCV_LUI))" }, { "number": 35, "source": "function clause execute (C_SRLI(shamt, rsd)) = {\n let rsd = creg2reg_idx(rsd);\n execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRLI))\n}", "pattern": { "type": "app", "id": "C_SRLI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rsd" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRLI))" }, { "number": 36, "source": "function clause execute (C_SRAI(shamt, rsd)) = {\n let rsd = creg2reg_idx(rsd);\n execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRAI))\n}", "pattern": { "type": "app", "id": "C_SRAI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rsd" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRAI))" }, { "number": 37, "source": "function clause execute (C_ANDI(imm, rsd)) = {\n let rsd = creg2reg_idx(rsd);\n execute(ITYPE(sign_extend(imm), rsd, rsd, RISCV_ANDI))\n}", "pattern": { "type": "app", "id": "C_ANDI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rsd" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n execute(ITYPE(sign_extend(imm), rsd, rsd, RISCV_ANDI))" }, { "number": 38, "source": "function clause execute (C_SUB(rsd, rs2)) = {\n let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPE(rs2, rsd, rsd, RISCV_SUB))\n}", "pattern": { "type": "app", "id": "C_SUB", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPE(rs2, rsd, rsd, RISCV_SUB))" }, { "number": 39, "source": "function clause execute (C_XOR(rsd, rs2)) = {\n let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPE(rs2, rsd, rsd, RISCV_XOR))\n}", "pattern": { "type": "app", "id": "C_XOR", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPE(rs2, rsd, rsd, RISCV_XOR))" }, { "number": 40, "source": "function clause execute (C_OR(rsd, rs2)) = {\n let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPE(rs2, rsd, rsd, RISCV_OR))\n}", "pattern": { "type": "app", "id": "C_OR", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPE(rs2, rsd, rsd, RISCV_OR))" }, { "number": 41, "source": "function clause execute (C_AND(rsd, rs2)) = {\n let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPE(rs2, rsd, rsd, RISCV_AND))\n}", "pattern": { "type": "app", "id": "C_AND", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPE(rs2, rsd, rsd, RISCV_AND))" }, { "number": 42, "source": "function clause execute (C_SUBW(rsd, rs2)) = {\n let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPEW(rs2, rsd, rsd, RISCV_SUBW))\n}", "pattern": { "type": "app", "id": "C_SUBW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPEW(rs2, rsd, rsd, RISCV_SUBW))" }, { "number": 43, "source": "function clause execute (C_ADDW(rsd, rs2)) = {\n let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPEW(rs2, rsd, rsd, RISCV_ADDW))\n}", "pattern": { "type": "app", "id": "C_ADDW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let rsd = creg2reg_idx(rsd);\n let rs2 = creg2reg_idx(rs2);\n execute(RTYPEW(rs2, rsd, rsd, RISCV_ADDW))" }, { "number": 44, "source": "function clause execute (C_J(imm)) =\n execute(RISCV_JAL(sign_extend(imm @ 0b0), zreg))", "pattern": { "type": "app", "id": "C_J", "patterns": [ { "type": "id", "id": "imm" } ] }, "body": "execute(RISCV_JAL(sign_extend(imm @ 0b0), zreg))" }, { "number": 45, "source": "function clause execute (C_BEQZ(imm, rs)) =\n execute(BTYPE(sign_extend(imm @ 0b0), zreg, creg2reg_idx(rs), RISCV_BEQ))", "pattern": { "type": "app", "id": "C_BEQZ", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs" } ] } ] }, "body": "execute(BTYPE(sign_extend(imm @ 0b0), zreg, creg2reg_idx(rs), RISCV_BEQ))" }, { "number": 46, "source": "function clause execute (C_BNEZ(imm, rs)) =\n execute(BTYPE(sign_extend(imm @ 0b0), zreg, creg2reg_idx(rs), RISCV_BNE))", "pattern": { "type": "app", "id": "C_BNEZ", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs" } ] } ] }, "body": "execute(BTYPE(sign_extend(imm @ 0b0), zreg, creg2reg_idx(rs), RISCV_BNE))" }, { "number": 47, "source": "function clause execute (C_SLLI(shamt, rsd)) =\n execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SLLI))", "pattern": { "type": "app", "id": "C_SLLI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rsd" } ] } ] }, "body": "execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SLLI))" }, { "number": 48, "source": "function clause execute (C_LWSP(uimm, rd)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b00);\n execute(LOAD(imm, sp, rd, false, WORD, false, false))\n}", "pattern": { "type": "app", "id": "C_LWSP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b00);\n execute(LOAD(imm, sp, rd, false, WORD, false, false))" }, { "number": 49, "source": "function clause execute (C_LDSP(uimm, rd)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b000);\n execute(LOAD(imm, sp, rd, false, DOUBLE, false, false))\n}", "pattern": { "type": "app", "id": "C_LDSP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b000);\n execute(LOAD(imm, sp, rd, false, DOUBLE, false, false))" }, { "number": 50, "source": "function clause execute (C_SWSP(uimm, rs2)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b00);\n execute(STORE(imm, rs2, sp, WORD, false, false))\n}", "pattern": { "type": "app", "id": "C_SWSP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b00);\n execute(STORE(imm, rs2, sp, WORD, false, false))" }, { "number": 51, "source": "function clause execute (C_SDSP(uimm, rs2)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b000);\n execute(STORE(imm, rs2, sp, DOUBLE, false, false))\n}", "pattern": { "type": "app", "id": "C_SDSP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b000);\n execute(STORE(imm, rs2, sp, DOUBLE, false, false))" }, { "number": 52, "source": "function clause execute (C_JR(rs1)) =\n execute(RISCV_JALR(zero_extend(0b0), rs1, zreg))", "pattern": { "type": "app", "id": "C_JR", "patterns": [ { "type": "id", "id": "rs1" } ] }, "body": "execute(RISCV_JALR(zero_extend(0b0), rs1, zreg))" }, { "number": 53, "source": "function clause execute (C_JALR(rs1)) =\n execute(RISCV_JALR(zero_extend(0b0), rs1, ra))", "pattern": { "type": "app", "id": "C_JALR", "patterns": [ { "type": "id", "id": "rs1" } ] }, "body": "execute(RISCV_JALR(zero_extend(0b0), rs1, ra))" }, { "number": 54, "source": "function clause execute (C_MV(rd, rs2)) =\n execute(RTYPE(rs2, zreg, rd, RISCV_ADD))", "pattern": { "type": "app", "id": "C_MV", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "rs2" } ] } ] }, "body": "execute(RTYPE(rs2, zreg, rd, RISCV_ADD))" }, { "number": 55, "source": "function clause execute C_EBREAK() =\n execute(EBREAK())", "pattern": { "type": "app", "id": "C_EBREAK", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": "execute(EBREAK())" }, { "number": 56, "source": "function clause execute (C_ADD(rsd, rs2)) =\n execute(RTYPE(rs2, rsd, rsd, RISCV_ADD))", "pattern": { "type": "app", "id": "C_ADD", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] } ] }, "body": "execute(RTYPE(rs2, rsd, rsd, RISCV_ADD))" }, { "number": 57, "source": "function clause execute (MUL(rs2, rs1, rd, high, signed1, signed2)) = {\n if haveMulDiv() | haveZmmul() then {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val);\n let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int);\n let result = if high\n then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)]\n else result_wide[(sizeof(xlen) - 1) .. 0];\n X(rd) = result;\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n}", "pattern": { "type": "app", "id": "MUL", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "high" }, { "type": "id", "id": "signed1" }, { "type": "id", "id": "signed2" } ] } ] }, "body": " if haveMulDiv() | haveZmmul() then {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val);\n let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int);\n let result = if high\n then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)]\n else result_wide[(sizeof(xlen) - 1) .. 0];\n X(rd) = result;\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }" }, { "number": 58, "source": "function clause execute (DIV(rs2, rs1, rd, s)) = {\n if haveMulDiv() then {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);\n let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int);\n /* check for signed overflow */\n let q': int = if s & q > xlen_max_signed then xlen_min_signed else q;\n X(rd) = to_bits(sizeof(xlen), q');\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n}", "pattern": { "type": "app", "id": "DIV", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] } ] }, "body": " if haveMulDiv() then {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);\n let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int);\n /* check for signed overflow */\n let q': int = if s & q > xlen_max_signed then xlen_min_signed else q;\n X(rd) = to_bits(sizeof(xlen), q');\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }" }, { "number": 59, "source": "function clause execute (REM(rs2, rs1, rd, s)) = {\n if haveMulDiv() then {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);\n let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int);\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n X(rd) = to_bits(sizeof(xlen), r);\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n}", "pattern": { "type": "app", "id": "REM", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] } ] }, "body": " if haveMulDiv() then {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);\n let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int);\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n X(rd) = to_bits(sizeof(xlen), r);\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }" }, { "number": 60, "source": "function clause execute (MULW(rs2, rs1, rd)) = {\n if haveMulDiv() | haveZmmul() then {\n let rs1_val = X(rs1)[31..0];\n let rs2_val = X(rs2)[31..0];\n let rs1_int : int = signed(rs1_val);\n let rs2_int : int = signed(rs2_val);\n /* to_bits requires expansion to 64 bits followed by truncation */\n let result32 = to_bits(64, rs1_int * rs2_int)[31..0];\n let result : xlenbits = sign_extend(result32);\n X(rd) = result;\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n}", "pattern": { "type": "app", "id": "MULW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " if haveMulDiv() | haveZmmul() then {\n let rs1_val = X(rs1)[31..0];\n let rs2_val = X(rs2)[31..0];\n let rs1_int : int = signed(rs1_val);\n let rs2_int : int = signed(rs2_val);\n /* to_bits requires expansion to 64 bits followed by truncation */\n let result32 = to_bits(64, rs1_int * rs2_int)[31..0];\n let result : xlenbits = sign_extend(result32);\n X(rd) = result;\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }" }, { "number": 61, "source": "function clause execute (DIVW(rs2, rs1, rd, s)) = {\n if haveMulDiv() then {\n let rs1_val = X(rs1)[31..0];\n let rs2_val = X(rs2)[31..0];\n let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);\n let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int);\n /* check for signed overflow */\n let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q;\n X(rd) = sign_extend(to_bits(32, q'));\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n}", "pattern": { "type": "app", "id": "DIVW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] } ] }, "body": " if haveMulDiv() then {\n let rs1_val = X(rs1)[31..0];\n let rs2_val = X(rs2)[31..0];\n let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);\n let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int);\n /* check for signed overflow */\n let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q;\n X(rd) = sign_extend(to_bits(32, q'));\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }" }, { "number": 62, "source": "function clause execute (REMW(rs2, rs1, rd, s)) = {\n if haveMulDiv() then {\n let rs1_val = X(rs1)[31..0];\n let rs2_val = X(rs2)[31..0];\n let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);\n let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int);\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n X(rd) = sign_extend(to_bits(32, r));\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }\n}", "pattern": { "type": "app", "id": "REMW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] } ] }, "body": " if haveMulDiv() then {\n let rs1_val = X(rs1)[31..0];\n let rs2_val = X(rs2)[31..0];\n let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);\n let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);\n let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int);\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n X(rd) = sign_extend(to_bits(32, r));\n RETIRE_SUCCESS\n } else {\n handle_illegal();\n RETIRE_FAIL\n }" }, { "number": 63, "source": "function clause execute CSR(csr, rs1, rd, is_imm, op) = {\n let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1);\n let isWrite : bool = match op {\n CSRRW => true,\n _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0\n };\n if not(check_CSR(csr, cur_privilege, isWrite))\n then { handle_illegal(); RETIRE_FAIL }\n else if not(ext_check_CSR(csr, cur_privilege, isWrite))\n then { ext_check_CSR_fail(); RETIRE_FAIL }\n else {\n let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */\n if isWrite then {\n let new_val : xlenbits = match op {\n CSRRW => rs1_val,\n CSRRS => csr_val | rs1_val,\n CSRRC => csr_val & ~(rs1_val)\n };\n writeCSR(csr, new_val)\n };\n X(rd) = csr_val;\n RETIRE_SUCCESS\n }\n}", "pattern": { "type": "app", "id": "CSR", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "is_imm" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1);\n let isWrite : bool = match op {\n CSRRW => true,\n _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0\n };\n if not(check_CSR(csr, cur_privilege, isWrite))\n then { handle_illegal(); RETIRE_FAIL }\n else if not(ext_check_CSR(csr, cur_privilege, isWrite))\n then { ext_check_CSR_fail(); RETIRE_FAIL }\n else {\n let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */\n if isWrite then {\n let new_val : xlenbits = match op {\n CSRRW => rs1_val,\n CSRRS => csr_val | rs1_val,\n CSRRC => csr_val & ~(rs1_val)\n };\n writeCSR(csr, new_val)\n };\n X(rd) = csr_val;\n RETIRE_SUCCESS\n }" }, { "number": 64, "source": "function clause execute URET() = {\n if not(haveUsrMode()) | not(sys_enable_next())\n then handle_illegal()\n else if not(ext_check_xret_priv(User))\n then ext_fail_xret_priv()\n else set_next_pc(exception_handler(cur_privilege, CTL_URET(), PC));\n RETIRE_FAIL\n}", "pattern": { "type": "app", "id": "URET", "patterns": [ { "type": "literal", "value": "()" } ] }, "body": " if not(haveUsrMode()) | not(sys_enable_next())\n then handle_illegal()\n else if not(ext_check_xret_priv(User))\n then ext_fail_xret_priv()\n else set_next_pc(exception_handler(cur_privilege, CTL_URET(), PC));\n RETIRE_FAIL" }, { "number": 65, "source": "function clause execute C_NOP_HINT(imm) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_NOP_HINT", "patterns": [ { "type": "id", "id": "imm" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 66, "source": "function clause execute (C_ADDI_HINT(rsd)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_ADDI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 67, "source": "function clause execute (C_LI_HINT(imm)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_LI_HINT", "patterns": [ { "type": "id", "id": "imm" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 68, "source": "function clause execute (C_LUI_HINT(imm)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_LUI_HINT", "patterns": [ { "type": "id", "id": "imm" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 69, "source": "function clause execute (C_MV_HINT(rs2)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_MV_HINT", "patterns": [ { "type": "id", "id": "rs2" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 70, "source": "function clause execute (C_ADD_HINT(rs2)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_ADD_HINT", "patterns": [ { "type": "id", "id": "rs2" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 71, "source": "function clause execute (C_SLLI_HINT(shamt, rsd)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_SLLI_HINT", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rsd" } ] } ] }, "body": "RETIRE_SUCCESS" }, { "number": 72, "source": "function clause execute (C_SRLI_HINT(rsd)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_SRLI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 73, "source": "function clause execute (C_SRAI_HINT(rsd)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "C_SRAI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "body": "RETIRE_SUCCESS" }, { "number": 74, "source": "function clause execute (FENCE_RESERVED(fm, pred, succ, rs, rd)) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "FENCE_RESERVED", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "fm" }, { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" }, { "type": "id", "id": "rs" }, { "type": "id", "id": "rd" } ] } ] }, "body": "RETIRE_SUCCESS" }, { "number": 75, "source": "function clause execute FENCEI_RESERVED(imm, rs, rd) = RETIRE_SUCCESS", "pattern": { "type": "app", "id": "FENCEI_RESERVED", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs" }, { "type": "id", "id": "rd" } ] } ] }, "body": "RETIRE_SUCCESS" }, { "number": 76, "source": "function clause execute(LOAD_FP(imm, rs1, rd, width)) = {\n let offset : xlenbits = sign_extend(imm);\n /* Get the address, X(rs1) + offset.\n Some extensions perform additional checks on address validity. */\n match ext_data_get_addr(rs1, offset, Read(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) => {\n let (aq, rl, res) = (false, false, false);\n match (width) {\n BYTE => { handle_illegal(); RETIRE_FAIL },\n HALF =>\n process_fload16(rd, vaddr, mem_read(Read(Data), addr, 2, aq, rl, res)),\n WORD =>\n process_fload32(rd, vaddr, mem_read(Read(Data), addr, 4, aq, rl, res)),\n DOUBLE if sizeof(flen) >= 64 =>\n process_fload64(rd, vaddr, mem_read(Read(Data), addr, 8, aq, rl, res)),\n _ => report_invalid_width(__FILE__, __LINE__, width, \"floating point load\"),\n }\n }\n }\n }\n}", "pattern": { "type": "app", "id": "LOAD_FP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "width" } ] } ] }, "body": " let offset : xlenbits = sign_extend(imm);\n /* Get the address, X(rs1) + offset.\n Some extensions perform additional checks on address validity. */\n match ext_data_get_addr(rs1, offset, Read(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) => {\n let (aq, rl, res) = (false, false, false);\n match (width) {\n BYTE => { handle_illegal(); RETIRE_FAIL },\n HALF =>\n process_fload16(rd, vaddr, mem_read(Read(Data), addr, 2, aq, rl, res)),\n WORD =>\n process_fload32(rd, vaddr, mem_read(Read(Data), addr, 4, aq, rl, res)),\n DOUBLE if sizeof(flen) >= 64 =>\n process_fload64(rd, vaddr, mem_read(Read(Data), addr, 8, aq, rl, res)),\n _ => report_invalid_width(__FILE__, __LINE__, width, \"floating point load\"),\n }\n }\n }\n }" }, { "number": 77, "source": "function clause execute (STORE_FP(imm, rs2, rs1, width)) = {\n let offset : xlenbits = sign_extend(imm);\n let (aq, rl, con) = (false, false, false);\n /* Get the address, X(rs1) + offset.\n Some extensions perform additional checks on address validity. */\n match ext_data_get_addr(rs1, offset, Write(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) => {\n let eares : MemoryOpResult(unit) = match width {\n BYTE => MemValue () /* bogus placeholder for illegal size */,\n HALF => mem_write_ea(addr, 2, aq, rl, false),\n WORD => mem_write_ea(addr, 4, aq, rl, false),\n DOUBLE => mem_write_ea(addr, 8, aq, rl, false)\n };\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(_) => {\n let rs2_val = F(rs2);\n match (width) {\n BYTE => { handle_illegal(); RETIRE_FAIL },\n HALF => process_fstore (vaddr, mem_write_value(addr, 2, rs2_val[15..0], aq, rl, con)),\n WORD => process_fstore (vaddr, mem_write_value(addr, 4, rs2_val[31..0], aq, rl, con)),\n DOUBLE if sizeof(flen) >= 64 =>\n process_fstore (vaddr, mem_write_value(addr, 8, rs2_val, aq, rl, con)),\n _ => report_invalid_width(__FILE__, __LINE__, width, \"floating point store\"),\n };\n }\n }\n }\n }\n }\n}", "pattern": { "type": "app", "id": "STORE_FP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" } ] } ] }, "body": " let offset : xlenbits = sign_extend(imm);\n let (aq, rl, con) = (false, false, false);\n /* Get the address, X(rs1) + offset.\n Some extensions perform additional checks on address validity. */\n match ext_data_get_addr(rs1, offset, Write(Data), width) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n TR_Address(addr, _) => {\n let eares : MemoryOpResult(unit) = match width {\n BYTE => MemValue () /* bogus placeholder for illegal size */,\n HALF => mem_write_ea(addr, 2, aq, rl, false),\n WORD => mem_write_ea(addr, 4, aq, rl, false),\n DOUBLE => mem_write_ea(addr, 8, aq, rl, false)\n };\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },\n MemValue(_) => {\n let rs2_val = F(rs2);\n match (width) {\n BYTE => { handle_illegal(); RETIRE_FAIL },\n HALF => process_fstore (vaddr, mem_write_value(addr, 2, rs2_val[15..0], aq, rl, con)),\n WORD => process_fstore (vaddr, mem_write_value(addr, 4, rs2_val[31..0], aq, rl, con)),\n DOUBLE if sizeof(flen) >= 64 =>\n process_fstore (vaddr, mem_write_value(addr, 8, rs2_val, aq, rl, con)),\n _ => report_invalid_width(__FILE__, __LINE__, width, \"floating point store\"),\n };\n }\n }\n }\n }\n }" }, { "number": 78, "source": "function clause execute (F_MADD_TYPE_S(rs3, rs2, rs1, rm, rd, op)) = {\n let rs1_val_32b = F_or_X_S(rs1);\n let rs2_val_32b = F_or_X_S(rs2);\n let rs3_val_32b = F_or_X_S(rs3);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_32b) : (bits(5), bits(32)) =\n match op {\n FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b),\n FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)),\n FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b),\n FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b))\n };\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_32b;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_MADD_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val_32b = F_or_X_S(rs1);\n let rs2_val_32b = F_or_X_S(rs2);\n let rs3_val_32b = F_or_X_S(rs3);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_32b) : (bits(5), bits(32)) =\n match op {\n FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b),\n FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)),\n FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b),\n FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b))\n };\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_32b;\n RETIRE_SUCCESS\n }\n }" }, { "number": 79, "source": "function clause execute (F_BIN_RM_TYPE_S(rs2, rs1, rm, rd, op)) = {\n let rs1_val_32b = F_or_X_S(rs1);\n let rs2_val_32b = F_or_X_S(rs2);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op {\n FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b),\n FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b),\n FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b),\n FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b)\n };\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_32b;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_BIN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val_32b = F_or_X_S(rs1);\n let rs2_val_32b = F_or_X_S(rs2);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op {\n FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b),\n FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b),\n FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b),\n FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b)\n };\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_32b;\n RETIRE_SUCCESS\n }\n }" }, { "number": 80, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FSQRT_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f32Sqrt (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f32Sqrt (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 81, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_W_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_W) = riscv_f32ToI32 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_W);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_W) = riscv_f32ToI32 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_W);\n RETIRE_SUCCESS\n }\n }" }, { "number": 82, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_WU_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_WU) = riscv_f32ToUi32 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_WU);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_WU) = riscv_f32ToUi32 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_WU);\n RETIRE_SUCCESS\n }\n }" }, { "number": 83, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_W)) = {\n let rs1_val_W = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_i32ToF32 (rm_3b, rs1_val_W);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_W" } ] } ] }, "body": " let rs1_val_W = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_i32ToF32 (rm_3b, rs1_val_W);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 84, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_WU)) = {\n let rs1_val_WU = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_ui32ToF32 (rm_3b, rs1_val_WU);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_WU" } ] } ] }, "body": " let rs1_val_WU = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_ui32ToF32 (rm_3b, rs1_val_WU);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 85, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_L) = riscv_f32ToI64 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_L);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_S" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_L) = riscv_f32ToI64 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_L);\n RETIRE_SUCCESS\n }\n }" }, { "number": 86, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_LU) = riscv_f32ToUi64 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_LU);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_S" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_LU) = riscv_f32ToUi64 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_LU);\n RETIRE_SUCCESS\n }\n }" }, { "number": 87, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_L = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_i64ToF32 (rm_3b, rs1_val_L);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_L" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_L = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_i64ToF32 (rm_3b, rs1_val_L);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 88, "source": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_LU)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_LU = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_LU" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_LU)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_LU = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 89, "source": "function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FSGNJ_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n let (s1, e1, m1) = fsplit_S (rs1_val_S);\n let (s2, e2, m2) = fsplit_S (rs2_val_S);\n let rd_val_S = fmake_S (s2, e1, m1);\n\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n let (s1, e1, m1) = fsplit_S (rs1_val_S);\n let (s2, e2, m2) = fsplit_S (rs2_val_S);\n let rd_val_S = fmake_S (s2, e1, m1);\n\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS" }, { "number": 90, "source": "function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FSGNJN_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n let (s1, e1, m1) = fsplit_S (rs1_val_S);\n let (s2, e2, m2) = fsplit_S (rs2_val_S);\n let rd_val_S = fmake_S (0b1 ^ s2, e1, m1);\n\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n let (s1, e1, m1) = fsplit_S (rs1_val_S);\n let (s2, e2, m2) = fsplit_S (rs2_val_S);\n let rd_val_S = fmake_S (0b1 ^ s2, e1, m1);\n\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS" }, { "number": 91, "source": "function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FSGNJX_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n let (s1, e1, m1) = fsplit_S (rs1_val_S);\n let (s2, e2, m2) = fsplit_S (rs2_val_S);\n let rd_val_S = fmake_S (s1 ^ s2, e1, m1);\n\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n let (s1, e1, m1) = fsplit_S (rs1_val_S);\n let (s2, e2, m2) = fsplit_S (rs2_val_S);\n let rd_val_S = fmake_S (s1 ^ s2, e1, m1);\n\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS" }, { "number": 92, "source": "function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FMIN_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_S (rs1_val_S, rs2_val_S, is_quiet);\n\n let rd_val_S = if (f_is_NaN_S(rs1_val_S) & f_is_NaN_S(rs2_val_S)) then canonical_NaN_S()\n else if f_is_NaN_S(rs1_val_S) then rs2_val_S\n else if f_is_NaN_S(rs2_val_S) then rs1_val_S\n else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs1_val_S\n else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs2_val_S\n else if rs1_lt_rs2 then rs1_val_S\n else /* (not rs1_lt_rs2) */ rs2_val_S;\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_S (rs1_val_S, rs2_val_S, is_quiet);\n\n let rd_val_S = if (f_is_NaN_S(rs1_val_S) & f_is_NaN_S(rs2_val_S)) then canonical_NaN_S()\n else if f_is_NaN_S(rs1_val_S) then rs2_val_S\n else if f_is_NaN_S(rs2_val_S) then rs1_val_S\n else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs1_val_S\n else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs2_val_S\n else if rs1_lt_rs2 then rs1_val_S\n else /* (not rs1_lt_rs2) */ rs2_val_S;\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS" }, { "number": 93, "source": "function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FMAX_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_S (rs2_val_S, rs1_val_S, is_quiet);\n\n let rd_val_S = if (f_is_NaN_S(rs1_val_S) & f_is_NaN_S(rs2_val_S)) then canonical_NaN_S()\n else if f_is_NaN_S(rs1_val_S) then rs2_val_S\n else if f_is_NaN_S(rs2_val_S) then rs1_val_S\n else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs2_val_S\n else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs1_val_S\n else if rs2_lt_rs1 then rs1_val_S\n else /* (not rs2_lt_rs1) */ rs2_val_S;\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_S (rs2_val_S, rs1_val_S, is_quiet);\n\n let rd_val_S = if (f_is_NaN_S(rs1_val_S) & f_is_NaN_S(rs2_val_S)) then canonical_NaN_S()\n else if f_is_NaN_S(rs1_val_S) then rs2_val_S\n else if f_is_NaN_S(rs2_val_S) then rs1_val_S\n else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs2_val_S\n else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs1_val_S\n else if rs2_lt_rs1 then rs1_val_S\n else /* (not rs2_lt_rs1) */ rs2_val_S;\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS" }, { "number": 94, "source": "function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FEQ_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Eq (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Eq (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 95, "source": "function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FLT_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Lt (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Lt (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 96, "source": "function clause execute (F_BIN_TYPE_S(rs2, rs1, rd, FLE_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Le (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n let rs2_val_S = F_or_X_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Le (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 97, "source": "function clause execute (F_UN_TYPE_S(rs1, rd, FCLASS_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n\n let rd_val_10b : bits (10) =\n if f_is_neg_inf_S (rs1_val_S) then 0b_00_0000_0001\n else if f_is_neg_norm_S (rs1_val_S) then 0b_00_0000_0010\n else if f_is_neg_subnorm_S (rs1_val_S) then 0b_00_0000_0100\n else if f_is_neg_zero_S (rs1_val_S) then 0b_00_0000_1000\n else if f_is_pos_zero_S (rs1_val_S) then 0b_00_0001_0000\n else if f_is_pos_subnorm_S (rs1_val_S) then 0b_00_0010_0000\n else if f_is_pos_norm_S (rs1_val_S) then 0b_00_0100_0000\n else if f_is_pos_inf_S (rs1_val_S) then 0b_00_1000_0000\n else if f_is_SNaN_S (rs1_val_S) then 0b_01_0000_0000\n else if f_is_QNaN_S (rs1_val_S) then 0b_10_0000_0000\n else zeros();\n\n X(rd) = zero_extend (rd_val_10b);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n\n let rd_val_10b : bits (10) =\n if f_is_neg_inf_S (rs1_val_S) then 0b_00_0000_0001\n else if f_is_neg_norm_S (rs1_val_S) then 0b_00_0000_0010\n else if f_is_neg_subnorm_S (rs1_val_S) then 0b_00_0000_0100\n else if f_is_neg_zero_S (rs1_val_S) then 0b_00_0000_1000\n else if f_is_pos_zero_S (rs1_val_S) then 0b_00_0001_0000\n else if f_is_pos_subnorm_S (rs1_val_S) then 0b_00_0010_0000\n else if f_is_pos_norm_S (rs1_val_S) then 0b_00_0100_0000\n else if f_is_pos_inf_S (rs1_val_S) then 0b_00_1000_0000\n else if f_is_SNaN_S (rs1_val_S) then 0b_01_0000_0000\n else if f_is_QNaN_S (rs1_val_S) then 0b_10_0000_0000\n else zeros();\n\n X(rd) = zero_extend (rd_val_10b);\n RETIRE_SUCCESS" }, { "number": 98, "source": "function clause execute (F_UN_TYPE_S(rs1, rd, FMV_X_W)) = {\n let rs1_val_S = F(rs1)[31..0];\n let rd_val_X : xlenbits = sign_extend(rs1_val_S);\n X(rd) = rd_val_X;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_W" } ] } ] }, "body": " let rs1_val_S = F(rs1)[31..0];\n let rd_val_X : xlenbits = sign_extend(rs1_val_S);\n X(rd) = rd_val_X;\n RETIRE_SUCCESS" }, { "number": 99, "source": "function clause execute (F_UN_TYPE_S(rs1, rd, FMV_W_X)) = {\n let rs1_val_X = X(rs1);\n let rd_val_S = rs1_val_X [31..0];\n F(rd) = nan_box (rd_val_S);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_W_X" } ] } ] }, "body": " let rs1_val_X = X(rs1);\n let rd_val_S = rs1_val_X [31..0];\n F(rd) = nan_box (rd_val_S);\n RETIRE_SUCCESS" }, { "number": 100, "source": "function clause execute (C_FLWSP(imm, rd)) = {\n let imm : bits(12) = zero_extend(imm @ 0b00);\n execute(LOAD_FP(imm, sp, rd, WORD))\n}", "pattern": { "type": "app", "id": "C_FLWSP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let imm : bits(12) = zero_extend(imm @ 0b00);\n execute(LOAD_FP(imm, sp, rd, WORD))" }, { "number": 101, "source": "function clause execute (C_FSWSP(uimm, rs2)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b00);\n execute(STORE_FP(imm, rs2, sp, WORD))\n}", "pattern": { "type": "app", "id": "C_FSWSP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b00);\n execute(STORE_FP(imm, rs2, sp, WORD))" }, { "number": 102, "source": "function clause execute (C_FLW(uimm, rsc, rdc)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b00);\n let rd = creg2reg_idx(rdc);\n let rs = creg2reg_idx(rsc);\n execute(LOAD_FP(imm, rs, rd, WORD))\n}", "pattern": { "type": "app", "id": "C_FLW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc" }, { "type": "id", "id": "rdc" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b00);\n let rd = creg2reg_idx(rdc);\n let rs = creg2reg_idx(rsc);\n execute(LOAD_FP(imm, rs, rd, WORD))" }, { "number": 103, "source": "function clause execute (C_FSW(uimm, rsc1, rsc2)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b00);\n let rs1 = creg2reg_idx(rsc1);\n let rs2 = creg2reg_idx(rsc2);\n execute(STORE_FP(imm, rs2, rs1, WORD))\n}", "pattern": { "type": "app", "id": "C_FSW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc1" }, { "type": "id", "id": "rsc2" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b00);\n let rs1 = creg2reg_idx(rsc1);\n let rs2 = creg2reg_idx(rsc2);\n execute(STORE_FP(imm, rs2, rs1, WORD))" }, { "number": 104, "source": "function clause execute (F_MADD_TYPE_D(rs3, rs2, rs1, rm, rd, op)) = {\n let rs1_val_64b = F_or_X_D(rs1);\n let rs2_val_64b = F_or_X_D(rs2);\n let rs3_val_64b = F_or_X_D(rs3);\n\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_64b) : (bits(5), bits(64)) =\n match op {\n FMADD_D => riscv_f64MulAdd (rm_3b, rs1_val_64b, rs2_val_64b, rs3_val_64b),\n FMSUB_D => riscv_f64MulAdd (rm_3b, rs1_val_64b, rs2_val_64b, negate_D (rs3_val_64b)),\n FNMSUB_D => riscv_f64MulAdd (rm_3b, negate_D (rs1_val_64b), rs2_val_64b, rs3_val_64b),\n FNMADD_D => riscv_f64MulAdd (rm_3b, negate_D (rs1_val_64b), rs2_val_64b, negate_D (rs3_val_64b))\n };\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_64b;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_MADD_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val_64b = F_or_X_D(rs1);\n let rs2_val_64b = F_or_X_D(rs2);\n let rs3_val_64b = F_or_X_D(rs3);\n\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_64b) : (bits(5), bits(64)) =\n match op {\n FMADD_D => riscv_f64MulAdd (rm_3b, rs1_val_64b, rs2_val_64b, rs3_val_64b),\n FMSUB_D => riscv_f64MulAdd (rm_3b, rs1_val_64b, rs2_val_64b, negate_D (rs3_val_64b)),\n FNMSUB_D => riscv_f64MulAdd (rm_3b, negate_D (rs1_val_64b), rs2_val_64b, rs3_val_64b),\n FNMADD_D => riscv_f64MulAdd (rm_3b, negate_D (rs1_val_64b), rs2_val_64b, negate_D (rs3_val_64b))\n };\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_64b;\n RETIRE_SUCCESS\n }\n }" }, { "number": 105, "source": "function clause execute (F_BIN_RM_TYPE_D(rs2, rs1, rm, rd, op)) = {\n let rs1_val_64b = F_or_X_D(rs1);\n let rs2_val_64b = F_or_X_D(rs2);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_64b) : (bits(5), bits(64)) = match op {\n FADD_D => riscv_f64Add (rm_3b, rs1_val_64b, rs2_val_64b),\n FSUB_D => riscv_f64Sub (rm_3b, rs1_val_64b, rs2_val_64b),\n FMUL_D => riscv_f64Mul (rm_3b, rs1_val_64b, rs2_val_64b),\n FDIV_D => riscv_f64Div (rm_3b, rs1_val_64b, rs2_val_64b)\n };\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_64b;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_BIN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val_64b = F_or_X_D(rs1);\n let rs2_val_64b = F_or_X_D(rs2);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_64b) : (bits(5), bits(64)) = match op {\n FADD_D => riscv_f64Add (rm_3b, rs1_val_64b, rs2_val_64b),\n FSUB_D => riscv_f64Sub (rm_3b, rs1_val_64b, rs2_val_64b),\n FMUL_D => riscv_f64Mul (rm_3b, rs1_val_64b, rs2_val_64b),\n FDIV_D => riscv_f64Div (rm_3b, rs1_val_64b, rs2_val_64b)\n };\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_64b;\n RETIRE_SUCCESS\n }\n }" }, { "number": 106, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FSQRT_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f64Sqrt (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f64Sqrt (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 107, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_W_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_W) = riscv_f64ToI32 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_W);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_W) = riscv_f64ToI32 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_W);\n RETIRE_SUCCESS\n }\n }" }, { "number": 108, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_WU_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_WU) = riscv_f64ToUi32 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_WU);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_WU) = riscv_f64ToUi32 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_WU);\n RETIRE_SUCCESS\n }\n }" }, { "number": 109, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_W)) = {\n let rs1_val_W = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_i32ToF64 (rm_3b, rs1_val_W);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_W" } ] } ] }, "body": " let rs1_val_W = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_i32ToF64 (rm_3b, rs1_val_W);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 110, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_WU)) = {\n let rs1_val_WU = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_ui32ToF64 (rm_3b, rs1_val_WU);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_WU" } ] } ] }, "body": " let rs1_val_WU = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_ui32ToF64 (rm_3b, rs1_val_WU);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 111, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_S_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f64ToF32 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f64ToF32 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 112, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f32ToF64 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f32ToF64 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 113, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_L) = riscv_f64ToI64 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_L);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_D" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_L) = riscv_f64ToI64 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_L);\n RETIRE_SUCCESS\n }\n }" }, { "number": 114, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_LU) = riscv_f64ToUi64 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_LU);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_D" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_LU) = riscv_f64ToUi64 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_LU);\n RETIRE_SUCCESS\n }\n }" }, { "number": 115, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_L = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_i64ToF64 (rm_3b, rs1_val_L);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_L" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_L = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_i64ToF64 (rm_3b, rs1_val_L);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 116, "source": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_LU = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_ui64ToF64 (rm_3b, rs1_val_LU);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_LU" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_LU = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_ui64ToF64 (rm_3b, rs1_val_LU);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 117, "source": "function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FSGNJ_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let (s1, e1, m1) = fsplit_D (rs1_val_D);\n let (s2, e2, m2) = fsplit_D (rs2_val_D);\n let rd_val_D = fmake_D (s2, e1, m1);\n\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let (s1, e1, m1) = fsplit_D (rs1_val_D);\n let (s2, e2, m2) = fsplit_D (rs2_val_D);\n let rd_val_D = fmake_D (s2, e1, m1);\n\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 118, "source": "function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FSGNJN_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n let (s1, e1, m1) = fsplit_D (rs1_val_D);\n let (s2, e2, m2) = fsplit_D (rs2_val_D);\n let rd_val_D = fmake_D (0b1 ^ s2, e1, m1);\n\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n let (s1, e1, m1) = fsplit_D (rs1_val_D);\n let (s2, e2, m2) = fsplit_D (rs2_val_D);\n let rd_val_D = fmake_D (0b1 ^ s2, e1, m1);\n\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 119, "source": "function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FSGNJX_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n let (s1, e1, m1) = fsplit_D (rs1_val_D);\n let (s2, e2, m2) = fsplit_D (rs2_val_D);\n let rd_val_D = fmake_D (s1 ^ s2, e1, m1);\n\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n let (s1, e1, m1) = fsplit_D (rs1_val_D);\n let (s2, e2, m2) = fsplit_D (rs2_val_D);\n let rd_val_D = fmake_D (s1 ^ s2, e1, m1);\n\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 120, "source": "function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FMIN_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_D (rs1_val_D, rs2_val_D, is_quiet);\n\n let rd_val_D = if (f_is_NaN_D(rs1_val_D) & f_is_NaN_D(rs2_val_D)) then canonical_NaN_D()\n else if f_is_NaN_D(rs1_val_D) then rs2_val_D\n else if f_is_NaN_D(rs2_val_D) then rs1_val_D\n else if (f_is_neg_zero_D(rs1_val_D) & f_is_pos_zero_D(rs2_val_D)) then rs1_val_D\n else if (f_is_neg_zero_D(rs2_val_D) & f_is_pos_zero_D(rs1_val_D)) then rs2_val_D\n else if rs1_lt_rs2 then rs1_val_D\n else /* (not rs1_lt_rs2) */ rs2_val_D;\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_D (rs1_val_D, rs2_val_D, is_quiet);\n\n let rd_val_D = if (f_is_NaN_D(rs1_val_D) & f_is_NaN_D(rs2_val_D)) then canonical_NaN_D()\n else if f_is_NaN_D(rs1_val_D) then rs2_val_D\n else if f_is_NaN_D(rs2_val_D) then rs1_val_D\n else if (f_is_neg_zero_D(rs1_val_D) & f_is_pos_zero_D(rs2_val_D)) then rs1_val_D\n else if (f_is_neg_zero_D(rs2_val_D) & f_is_pos_zero_D(rs1_val_D)) then rs2_val_D\n else if rs1_lt_rs2 then rs1_val_D\n else /* (not rs1_lt_rs2) */ rs2_val_D;\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 121, "source": "function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FMAX_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_D (rs2_val_D, rs1_val_D, is_quiet);\n\n let rd_val_D = if (f_is_NaN_D(rs1_val_D) & f_is_NaN_D(rs2_val_D)) then canonical_NaN_D()\n else if f_is_NaN_D(rs1_val_D) then rs2_val_D\n else if f_is_NaN_D(rs2_val_D) then rs1_val_D\n else if (f_is_neg_zero_D(rs1_val_D) & f_is_pos_zero_D(rs2_val_D)) then rs2_val_D\n else if (f_is_neg_zero_D(rs2_val_D) & f_is_pos_zero_D(rs1_val_D)) then rs1_val_D\n else if rs2_lt_rs1 then rs1_val_D\n else /* (not rs2_lt_rs1) */ rs2_val_D;\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_D (rs2_val_D, rs1_val_D, is_quiet);\n\n let rd_val_D = if (f_is_NaN_D(rs1_val_D) & f_is_NaN_D(rs2_val_D)) then canonical_NaN_D()\n else if f_is_NaN_D(rs1_val_D) then rs2_val_D\n else if f_is_NaN_D(rs2_val_D) then rs1_val_D\n else if (f_is_neg_zero_D(rs1_val_D) & f_is_pos_zero_D(rs2_val_D)) then rs2_val_D\n else if (f_is_neg_zero_D(rs2_val_D) & f_is_pos_zero_D(rs1_val_D)) then rs1_val_D\n else if rs2_lt_rs1 then rs1_val_D\n else /* (not rs2_lt_rs1) */ rs2_val_D;\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 122, "source": "function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FEQ_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Eq (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Eq (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 123, "source": "function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FLT_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Lt (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Lt (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 124, "source": "function clause execute (F_BIN_TYPE_D(rs2, rs1, rd, FLE_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Le (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n let rs2_val_D = F_or_X_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Le (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 125, "source": "function clause execute (F_UN_TYPE_D(rs1, rd, FCLASS_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n\n let rd_val_10b : bits (10) =\n if f_is_neg_inf_D (rs1_val_D) then 0b_00_0000_0001\n else if f_is_neg_norm_D (rs1_val_D) then 0b_00_0000_0010\n else if f_is_neg_subnorm_D (rs1_val_D) then 0b_00_0000_0100\n else if f_is_neg_zero_D (rs1_val_D) then 0b_00_0000_1000\n else if f_is_pos_zero_D (rs1_val_D) then 0b_00_0001_0000\n else if f_is_pos_subnorm_D (rs1_val_D) then 0b_00_0010_0000\n else if f_is_pos_norm_D (rs1_val_D) then 0b_00_0100_0000\n else if f_is_pos_inf_D (rs1_val_D) then 0b_00_1000_0000\n else if f_is_SNaN_D (rs1_val_D) then 0b_01_0000_0000\n else if f_is_QNaN_D (rs1_val_D) then 0b_10_0000_0000\n else zeros();\n\n X(rd) = zero_extend (rd_val_10b);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n\n let rd_val_10b : bits (10) =\n if f_is_neg_inf_D (rs1_val_D) then 0b_00_0000_0001\n else if f_is_neg_norm_D (rs1_val_D) then 0b_00_0000_0010\n else if f_is_neg_subnorm_D (rs1_val_D) then 0b_00_0000_0100\n else if f_is_neg_zero_D (rs1_val_D) then 0b_00_0000_1000\n else if f_is_pos_zero_D (rs1_val_D) then 0b_00_0001_0000\n else if f_is_pos_subnorm_D (rs1_val_D) then 0b_00_0010_0000\n else if f_is_pos_norm_D (rs1_val_D) then 0b_00_0100_0000\n else if f_is_pos_inf_D (rs1_val_D) then 0b_00_1000_0000\n else if f_is_SNaN_D (rs1_val_D) then 0b_01_0000_0000\n else if f_is_QNaN_D (rs1_val_D) then 0b_10_0000_0000\n else zeros();\n\n X(rd) = zero_extend (rd_val_10b);\n RETIRE_SUCCESS" }, { "number": 126, "source": "function clause execute (F_UN_TYPE_D(rs1, rd, FMV_X_D)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_D = F(rs1)[63..0];\n let rd_val_X : xlenbits = sign_extend(rs1_val_D);\n X(rd) = rd_val_X;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_D" } ] } ] }, "body": "function clause execute (F_UN_TYPE_D(rs1, rd, FMV_X_D)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_D = F(rs1)[63..0];\n let rd_val_X : xlenbits = sign_extend(rs1_val_D);\n X(rd) = rd_val_X;\n RETIRE_SUCCESS" }, { "number": 127, "source": "function clause execute (F_UN_TYPE_D(rs1, rd, FMV_D_X)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_X = X(rs1);\n let rd_val_D = rs1_val_X [63..0];\n F(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_D_X" } ] } ] }, "body": "function clause execute (F_UN_TYPE_D(rs1, rd, FMV_D_X)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_X = X(rs1);\n let rd_val_D = rs1_val_X [63..0];\n F(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 128, "source": "function clause execute (C_FLDSP(uimm, rd)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b000);\n execute(LOAD_FP(imm, sp, rd, DOUBLE))\n}", "pattern": { "type": "app", "id": "C_FLDSP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b000);\n execute(LOAD_FP(imm, sp, rd, DOUBLE))" }, { "number": 129, "source": "function clause execute (C_FSDSP(uimm, rs2)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b000);\n execute(STORE_FP(imm, rs2, sp, DOUBLE))\n}", "pattern": { "type": "app", "id": "C_FSDSP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rs2" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b000);\n execute(STORE_FP(imm, rs2, sp, DOUBLE))" }, { "number": 130, "source": "function clause execute (C_FLD(uimm, rsc, rdc)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b000);\n let rd = creg2reg_idx(rdc);\n let rs = creg2reg_idx(rsc);\n execute(LOAD_FP(imm, rs, rd, DOUBLE))\n}", "pattern": { "type": "app", "id": "C_FLD", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc" }, { "type": "id", "id": "rdc" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b000);\n let rd = creg2reg_idx(rdc);\n let rs = creg2reg_idx(rsc);\n execute(LOAD_FP(imm, rs, rd, DOUBLE))" }, { "number": 131, "source": "function clause execute (C_FSD(uimm, rsc1, rsc2)) = {\n let imm : bits(12) = zero_extend(uimm @ 0b000);\n let rs1 = creg2reg_idx(rsc1);\n let rs2 = creg2reg_idx(rsc2);\n execute(STORE_FP(imm, rs2, rs1, DOUBLE))\n}", "pattern": { "type": "app", "id": "C_FSD", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc1" }, { "type": "id", "id": "rsc2" } ] } ] }, "body": " let imm : bits(12) = zero_extend(uimm @ 0b000);\n let rs1 = creg2reg_idx(rsc1);\n let rs2 = creg2reg_idx(rsc2);\n execute(STORE_FP(imm, rs2, rs1, DOUBLE))" }, { "number": 132, "source": "function clause execute (RISCV_SLLIUW(shamt, rs1, rd)) = {\n let rs1_val = X(rs1);\n let result : xlenbits = zero_extend(rs1_val[31..0]) << shamt;\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_SLLIUW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n let result : xlenbits = zero_extend(rs1_val[31..0]) << shamt;\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 133, "source": "function clause execute (ZBA_RTYPEUW(rs2, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let shamt : bits(2) = match op {\n RISCV_ADDUW => 0b00,\n RISCV_SH1ADDUW => 0b01,\n RISCV_SH2ADDUW => 0b10,\n RISCV_SH3ADDUW => 0b11\n };\n let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val;\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBA_RTYPEUW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let shamt : bits(2) = match op {\n RISCV_ADDUW => 0b00,\n RISCV_SH1ADDUW => 0b01,\n RISCV_SH2ADDUW => 0b10,\n RISCV_SH3ADDUW => 0b11\n };\n let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val;\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 134, "source": "function clause execute (ZBA_RTYPE(rs2, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let shamt : bits(2) = match op {\n RISCV_SH1ADD => 0b01,\n RISCV_SH2ADD => 0b10,\n RISCV_SH3ADD => 0b11\n };\n let result : xlenbits = (rs1_val << shamt) + rs2_val;\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBA_RTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let shamt : bits(2) = match op {\n RISCV_SH1ADD => 0b01,\n RISCV_SH2ADD => 0b10,\n RISCV_SH3ADD => 0b11\n };\n let result : xlenbits = (rs1_val << shamt) + rs2_val;\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 135, "source": "function clause execute (RISCV_RORIW(shamt, rs1, rd)) = {\n let rs1_val = (X(rs1))[31..0];\n let result : xlenbits = sign_extend(rs1_val >>> shamt);\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_RORIW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = (X(rs1))[31..0];\n let result : xlenbits = sign_extend(rs1_val >>> shamt);\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 136, "source": "function clause execute (RISCV_RORI(shamt, rs1, rd)) = {\n let rs1_val = X(rs1);\n let result : xlenbits = if sizeof(xlen) == 32\n then rs1_val >>> shamt[4..0]\n else rs1_val >>> shamt;\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_RORI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n let result : xlenbits = if sizeof(xlen) == 32\n then rs1_val >>> shamt[4..0]\n else rs1_val >>> shamt;\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 137, "source": "function clause execute (ZBB_RTYPEW(rs2, rs1, rd, op)) = {\n let rs1_val = (X(rs1))[31..0];\n let shamt = (X(rs2))[4..0];\n let result : bits(32) = match op {\n RISCV_ROLW => rs1_val <<< shamt,\n RISCV_RORW => rs1_val >>> shamt\n };\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBB_RTYPEW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = (X(rs1))[31..0];\n let shamt = (X(rs2))[4..0];\n let result : bits(32) = match op {\n RISCV_ROLW => rs1_val <<< shamt,\n RISCV_RORW => rs1_val >>> shamt\n };\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 138, "source": "function clause execute (ZBB_RTYPE(rs2, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let result : xlenbits = match op {\n RISCV_ANDN => rs1_val & ~(rs2_val),\n RISCV_ORN => rs1_val | ~(rs2_val),\n RISCV_XNOR => ~(rs1_val ^ rs2_val),\n RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))),\n RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))),\n RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))),\n RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))),\n RISCV_ROL => if sizeof(xlen) == 32\n then rs1_val <<< rs2_val[4..0]\n else rs1_val <<< rs2_val[5..0],\n RISCV_ROR => if sizeof(xlen) == 32\n then rs1_val >>> rs2_val[4..0]\n else rs1_val >>> rs2_val[5..0]\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let result : xlenbits = match op {\n RISCV_ANDN => rs1_val & ~(rs2_val),\n RISCV_ORN => rs1_val | ~(rs2_val),\n RISCV_XNOR => ~(rs1_val ^ rs2_val),\n RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))),\n RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))),\n RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))),\n RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))),\n RISCV_ROL => if sizeof(xlen) == 32\n then rs1_val <<< rs2_val[4..0]\n else rs1_val <<< rs2_val[5..0],\n RISCV_ROR => if sizeof(xlen) == 32\n then rs1_val >>> rs2_val[4..0]\n else rs1_val >>> rs2_val[5..0]\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 139, "source": "function clause execute (ZBB_EXTOP(rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let result : xlenbits = match op {\n RISCV_SEXTB => sign_extend(rs1_val[7..0]),\n RISCV_SEXTH => sign_extend(rs1_val[15..0]),\n RISCV_ZEXTH => zero_extend(rs1_val[15..0])\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBB_EXTOP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let result : xlenbits = match op {\n RISCV_SEXTB => sign_extend(rs1_val[7..0]),\n RISCV_SEXTH => sign_extend(rs1_val[15..0]),\n RISCV_ZEXTH => zero_extend(rs1_val[15..0])\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 140, "source": "function clause execute (RISCV_REV8(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 8) by 8)\n result[(i + 7) .. i] = rs1_val[(sizeof(xlen) - i - 1) .. (sizeof(xlen) - i - 8)];\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_REV8", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 8) by 8)\n result[(i + 7) .. i] = rs1_val[(sizeof(xlen) - i - 1) .. (sizeof(xlen) - i - 8)];\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 141, "source": "function clause execute (RISCV_ORCB(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 8) by 8)\n result[(i + 7) .. i] = if rs1_val[(i + 7) .. i] == zeros()\n then 0x00\n else 0xFF;\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_ORCB", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 8) by 8)\n result[(i + 7) .. i] = if rs1_val[(i + 7) .. i] == zeros()\n then 0x00\n else 0xFF;\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 142, "source": "function clause execute (RISCV_CPOP(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : nat = 0;\n foreach (i from 0 to (xlen_val - 1))\n if rs1_val[i] == bitone then result = result + 1;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CPOP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : nat = 0;\n foreach (i from 0 to (xlen_val - 1))\n if rs1_val[i] == bitone then result = result + 1;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS" }, { "number": 143, "source": "function clause execute (RISCV_CPOPW(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : nat = 0;\n foreach (i from 0 to 31)\n if rs1_val[i] == bitone then result = result + 1;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CPOPW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : nat = 0;\n foreach (i from 0 to 31)\n if rs1_val[i] == bitone then result = result + 1;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS" }, { "number": 144, "source": "function clause execute (RISCV_CLZ(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : nat = 0;\n done : bool = false;\n foreach (i from (sizeof(xlen) - 1) downto 0)\n if not(done) then if rs1_val[i] == bitzero\n then result = result + 1\n else done = true;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CLZ", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : nat = 0;\n done : bool = false;\n foreach (i from (sizeof(xlen) - 1) downto 0)\n if not(done) then if rs1_val[i] == bitzero\n then result = result + 1\n else done = true;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS" }, { "number": 145, "source": "function clause execute (RISCV_CLZW(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : nat = 0;\n done : bool = false;\n foreach (i from 31 downto 0)\n if not(done) then if rs1_val[i] == bitzero\n then result = result + 1\n else done = true;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CLZW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : nat = 0;\n done : bool = false;\n foreach (i from 31 downto 0)\n if not(done) then if rs1_val[i] == bitzero\n then result = result + 1\n else done = true;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS" }, { "number": 146, "source": "function clause execute (RISCV_CTZ(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : nat = 0;\n done : bool = false;\n foreach (i from 0 to (sizeof(xlen) - 1))\n if not(done) then if rs1_val[i] == bitzero\n then result = result + 1\n else done = true;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CTZ", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : nat = 0;\n done : bool = false;\n foreach (i from 0 to (sizeof(xlen) - 1))\n if not(done) then if rs1_val[i] == bitzero\n then result = result + 1\n else done = true;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS" }, { "number": 147, "source": "function clause execute (RISCV_CTZW(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : nat = 0;\n done : bool = false;\n foreach (i from 0 to 31)\n if not(done) then if rs1_val[i] == bitzero\n then result = result + 1\n else done = true;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CTZW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : nat = 0;\n done : bool = false;\n foreach (i from 0 to 31)\n if not(done) then if rs1_val[i] == bitzero\n then result = result + 1\n else done = true;\n X(rd) = to_bits(sizeof(xlen), result);\n RETIRE_SUCCESS" }, { "number": 148, "source": "function clause execute (RISCV_CLMUL(rs2, rs1, rd)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (xlen_val - 1))\n if rs2_val[i] == bitone then result = result ^ (rs1_val << i);\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CLMUL", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (xlen_val - 1))\n if rs2_val[i] == bitone then result = result ^ (rs1_val << i);\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 149, "source": "function clause execute (RISCV_CLMULH(rs2, rs1, rd)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (xlen_val - 1))\n if rs2_val[i] == bitone then result = result ^ (rs1_val >> (xlen_val - i));\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CLMULH", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (xlen_val - 1))\n if rs2_val[i] == bitone then result = result ^ (rs1_val >> (xlen_val - i));\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 150, "source": "function clause execute (RISCV_CLMULR(rs2, rs1, rd)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (xlen_val - 1))\n if rs2_val[i] == bitone then result = result ^ (rs1_val >> (xlen_val - i - 1));\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_CLMULR", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (xlen_val - 1))\n if rs2_val[i] == bitone then result = result ^ (rs1_val >> (xlen_val - i - 1));\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 151, "source": "function clause execute (ZBS_IOP(shamt, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let mask : xlenbits = if sizeof(xlen) == 32\n then zero_extend(0b1) << shamt[4..0]\n else zero_extend(0b1) << shamt;\n let result : xlenbits = match op {\n RISCV_BCLRI => rs1_val & ~(mask),\n RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())),\n RISCV_BINVI => rs1_val ^ mask,\n RISCV_BSETI => rs1_val | mask\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBS_IOP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let mask : xlenbits = if sizeof(xlen) == 32\n then zero_extend(0b1) << shamt[4..0]\n else zero_extend(0b1) << shamt;\n let result : xlenbits = match op {\n RISCV_BCLRI => rs1_val & ~(mask),\n RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())),\n RISCV_BINVI => rs1_val ^ mask,\n RISCV_BSETI => rs1_val | mask\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 152, "source": "function clause execute (ZBS_RTYPE(rs2, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let mask : xlenbits = if sizeof(xlen) == 32\n then zero_extend(0b1) << rs2_val[4..0]\n else zero_extend(0b1) << rs2_val[5..0];\n let result : xlenbits = match op {\n RISCV_BCLR => rs1_val & ~(mask),\n RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())),\n RISCV_BINV => rs1_val ^ mask,\n RISCV_BSET => rs1_val | mask\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBS_RTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let mask : xlenbits = if sizeof(xlen) == 32\n then zero_extend(0b1) << rs2_val[4..0]\n else zero_extend(0b1) << rs2_val[5..0];\n let result : xlenbits = match op {\n RISCV_BCLR => rs1_val & ~(mask),\n RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())),\n RISCV_BINV => rs1_val ^ mask,\n RISCV_BSET => rs1_val | mask\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 153, "source": "function clause execute (F_BIN_RM_TYPE_H(rs2, rs1, rm, rd, op)) = {\n let rs1_val_16b = F_or_X_H(rs1);\n let rs2_val_16b = F_or_X_H(rs2);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_16b) : (bits(5), bits(16)) = match op {\n FADD_H => riscv_f16Add (rm_3b, rs1_val_16b, rs2_val_16b),\n FSUB_H => riscv_f16Sub (rm_3b, rs1_val_16b, rs2_val_16b),\n FMUL_H => riscv_f16Mul (rm_3b, rs1_val_16b, rs2_val_16b),\n FDIV_H => riscv_f16Div (rm_3b, rs1_val_16b, rs2_val_16b)\n };\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_16b;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_BIN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val_16b = F_or_X_H(rs1);\n let rs2_val_16b = F_or_X_H(rs2);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_16b) : (bits(5), bits(16)) = match op {\n FADD_H => riscv_f16Add (rm_3b, rs1_val_16b, rs2_val_16b),\n FSUB_H => riscv_f16Sub (rm_3b, rs1_val_16b, rs2_val_16b),\n FMUL_H => riscv_f16Mul (rm_3b, rs1_val_16b, rs2_val_16b),\n FDIV_H => riscv_f16Div (rm_3b, rs1_val_16b, rs2_val_16b)\n };\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_16b;\n RETIRE_SUCCESS\n }\n }" }, { "number": 154, "source": "function clause execute (F_MADD_TYPE_H(rs3, rs2, rs1, rm, rd, op)) = {\n let rs1_val_16b = F_or_X_H(rs1);\n let rs2_val_16b = F_or_X_H(rs2);\n let rs3_val_16b = F_or_X_H(rs3);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_16b) : (bits(5), bits(16)) =\n match op {\n FMADD_H => riscv_f16MulAdd (rm_3b, rs1_val_16b, rs2_val_16b, rs3_val_16b),\n FMSUB_H => riscv_f16MulAdd (rm_3b, rs1_val_16b, rs2_val_16b, negate_H (rs3_val_16b)),\n FNMSUB_H => riscv_f16MulAdd (rm_3b, negate_H (rs1_val_16b), rs2_val_16b, rs3_val_16b),\n FNMADD_H => riscv_f16MulAdd (rm_3b, negate_H (rs1_val_16b), rs2_val_16b, negate_H (rs3_val_16b))\n };\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_16b;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_MADD_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val_16b = F_or_X_H(rs1);\n let rs2_val_16b = F_or_X_H(rs2);\n let rs3_val_16b = F_or_X_H(rs3);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_16b) : (bits(5), bits(16)) =\n match op {\n FMADD_H => riscv_f16MulAdd (rm_3b, rs1_val_16b, rs2_val_16b, rs3_val_16b),\n FMSUB_H => riscv_f16MulAdd (rm_3b, rs1_val_16b, rs2_val_16b, negate_H (rs3_val_16b)),\n FNMSUB_H => riscv_f16MulAdd (rm_3b, negate_H (rs1_val_16b), rs2_val_16b, rs3_val_16b),\n FNMADD_H => riscv_f16MulAdd (rm_3b, negate_H (rs1_val_16b), rs2_val_16b, negate_H (rs3_val_16b))\n };\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_16b;\n RETIRE_SUCCESS\n }\n }" }, { "number": 155, "source": "function clause execute (F_BIN_TYPE_H(rs2, rs1, rd, FSGNJ_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n let (s1, e1, m1) = fsplit_H (rs1_val_H);\n let (s2, e2, m2) = fsplit_H (rs2_val_H);\n let rd_val_H = fmake_H (s2, e1, m1);\n\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n let (s1, e1, m1) = fsplit_H (rs1_val_H);\n let (s2, e2, m2) = fsplit_H (rs2_val_H);\n let rd_val_H = fmake_H (s2, e1, m1);\n\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS" }, { "number": 156, "source": "function clause execute (F_BIN_TYPE_H(rs2, rs1, rd, FSGNJN_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n let (s1, e1, m1) = fsplit_H (rs1_val_H);\n let (s2, e2, m2) = fsplit_H (rs2_val_H);\n let rd_val_H = fmake_H (0b1 ^ s2, e1, m1);\n\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n let (s1, e1, m1) = fsplit_H (rs1_val_H);\n let (s2, e2, m2) = fsplit_H (rs2_val_H);\n let rd_val_H = fmake_H (0b1 ^ s2, e1, m1);\n\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS" }, { "number": 157, "source": "function clause execute (F_BIN_TYPE_H(rs2, rs1, rd, FSGNJX_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n let (s1, e1, m1) = fsplit_H (rs1_val_H);\n let (s2, e2, m2) = fsplit_H (rs2_val_H);\n let rd_val_H = fmake_H (s1 ^ s2, e1, m1);\n\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n let (s1, e1, m1) = fsplit_H (rs1_val_H);\n let (s2, e2, m2) = fsplit_H (rs2_val_H);\n let rd_val_H = fmake_H (s1 ^ s2, e1, m1);\n\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS" }, { "number": 158, "source": "function clause execute (F_BIN_TYPE_H(rs2, rs1, rd, FMIN_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_H (rs1_val_H, rs2_val_H, is_quiet);\n\n let rd_val_H = if (f_is_NaN_H(rs1_val_H) & f_is_NaN_H(rs2_val_H)) then canonical_NaN_H()\n else if f_is_NaN_H(rs1_val_H) then rs2_val_H\n else if f_is_NaN_H(rs2_val_H) then rs1_val_H\n else if (f_is_neg_zero_H(rs1_val_H) & f_is_pos_zero_H(rs2_val_H)) then rs1_val_H\n else if (f_is_neg_zero_H(rs2_val_H) & f_is_pos_zero_H(rs1_val_H)) then rs2_val_H\n else if rs1_lt_rs2 then rs1_val_H\n else /* (not rs1_lt_rs2) */ rs2_val_H;\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_H (rs1_val_H, rs2_val_H, is_quiet);\n\n let rd_val_H = if (f_is_NaN_H(rs1_val_H) & f_is_NaN_H(rs2_val_H)) then canonical_NaN_H()\n else if f_is_NaN_H(rs1_val_H) then rs2_val_H\n else if f_is_NaN_H(rs2_val_H) then rs1_val_H\n else if (f_is_neg_zero_H(rs1_val_H) & f_is_pos_zero_H(rs2_val_H)) then rs1_val_H\n else if (f_is_neg_zero_H(rs2_val_H) & f_is_pos_zero_H(rs1_val_H)) then rs2_val_H\n else if rs1_lt_rs2 then rs1_val_H\n else /* (not rs1_lt_rs2) */ rs2_val_H;\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS" }, { "number": 159, "source": "function clause execute (F_BIN_TYPE_H(rs2, rs1, rd, FMAX_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_H (rs2_val_H, rs1_val_H, is_quiet);\n\n let rd_val_H = if (f_is_NaN_H(rs1_val_H) & f_is_NaN_H(rs2_val_H)) then canonical_NaN_H()\n else if f_is_NaN_H(rs1_val_H) then rs2_val_H\n else if f_is_NaN_H(rs2_val_H) then rs1_val_H\n else if (f_is_neg_zero_H(rs1_val_H) & f_is_pos_zero_H(rs2_val_H)) then rs2_val_H\n else if (f_is_neg_zero_H(rs2_val_H) & f_is_pos_zero_H(rs1_val_H)) then rs1_val_H\n else if rs2_lt_rs1 then rs1_val_H\n else /* (not rs2_lt_rs1) */ rs2_val_H;\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_H (rs2_val_H, rs1_val_H, is_quiet);\n\n let rd_val_H = if (f_is_NaN_H(rs1_val_H) & f_is_NaN_H(rs2_val_H)) then canonical_NaN_H()\n else if f_is_NaN_H(rs1_val_H) then rs2_val_H\n else if f_is_NaN_H(rs2_val_H) then rs1_val_H\n else if (f_is_neg_zero_H(rs1_val_H) & f_is_pos_zero_H(rs2_val_H)) then rs2_val_H\n else if (f_is_neg_zero_H(rs2_val_H) & f_is_pos_zero_H(rs1_val_H)) then rs1_val_H\n else if rs2_lt_rs1 then rs1_val_H\n else /* (not rs2_lt_rs1) */ rs2_val_H;\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS" }, { "number": 160, "source": "function clause execute (F_BIN_TYPE_H(rs2, rs1, rd, FEQ_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Eq (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Eq (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 161, "source": "function clause execute (F_BIN_TYPE_H(rs2, rs1, rd, FLT_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Lt (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Lt (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 162, "source": "function clause execute (F_BIN_TYPE_H(rs2, rs1, rd, FLE_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Le (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n let rs2_val_H = F_or_X_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Le (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 163, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FSQRT_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f16Sqrt (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f16Sqrt (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 164, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_W_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_W) = riscv_f16ToI32 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_W);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_W) = riscv_f16ToI32 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_W);\n RETIRE_SUCCESS\n }\n }" }, { "number": 165, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_WU_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_WU) = riscv_f16ToUi32 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_WU);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_WU) = riscv_f16ToUi32 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend (rd_val_WU);\n RETIRE_SUCCESS\n }\n }" }, { "number": 166, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_W)) = {\n let rs1_val_W = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_i32ToF16 (rm_3b, rs1_val_W);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_W" } ] } ] }, "body": " let rs1_val_W = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_i32ToF16 (rm_3b, rs1_val_W);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 167, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_WU)) = {\n let rs1_val_WU = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_ui32ToF16 (rm_3b, rs1_val_WU);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_WU" } ] } ] }, "body": " let rs1_val_WU = X(rs1) [31..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_ui32ToF16 (rm_3b, rs1_val_WU);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 168, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_S)) = {\n let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f32ToF16 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_S" } ] } ] }, "body": " let rs1_val_S = F_or_X_S(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f32ToF16 (rm_3b, rs1_val_S);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 169, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_D)) = {\n let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f64ToF16 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_D" } ] } ] }, "body": " let rs1_val_D = F_or_X_D(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f64ToF16 (rm_3b, rs1_val_D);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 170, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_S_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f16ToF32 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f16ToF32 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n F_or_X_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 171, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_D_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f16ToF64 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f16ToF64 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n F_or_X_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 172, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_L_H)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_L) = riscv_f16ToI64 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_L);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_H" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_L_H)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_L) = riscv_f16ToI64 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_L);\n RETIRE_SUCCESS\n }\n }" }, { "number": 173, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_LU_H)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_LU) = riscv_f16ToUi64 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_LU);\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_H" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_LU_H)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_H = F_or_X_H(rs1);\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_LU) = riscv_f16ToUi64 (rm_3b, rs1_val_H);\n\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val_LU);\n RETIRE_SUCCESS\n }\n }" }, { "number": 174, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_L)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_L = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_i64ToF16 (rm_3b, rs1_val_L);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_L" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_L)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_L = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_i64ToF16 (rm_3b, rs1_val_L);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 175, "source": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_LU)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_LU = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_LU" } ] } ] }, "body": "function clause execute (F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_LU)) = {\n assert(sizeof(xlen) >= 64);\n let rs1_val_LU = X(rs1)[63..0];\n match (select_instr_or_fcsr_rm (rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU);\n\n accrue_fflags(fflags);\n F_or_X_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 176, "source": "function clause execute (F_UN_TYPE_H(rs1, rd, FCLASS_H)) = {\n let rs1_val_H = F_or_X_H(rs1);\n\n let rd_val_10b : bits (10) =\n if f_is_neg_inf_H (rs1_val_H) then 0b_00_0000_0001\n else if f_is_neg_norm_H (rs1_val_H) then 0b_00_0000_0010\n else if f_is_neg_subnorm_H (rs1_val_H) then 0b_00_0000_0100\n else if f_is_neg_zero_H (rs1_val_H) then 0b_00_0000_1000\n else if f_is_pos_zero_H (rs1_val_H) then 0b_00_0001_0000\n else if f_is_pos_subnorm_H (rs1_val_H) then 0b_00_0010_0000\n else if f_is_pos_norm_H (rs1_val_H) then 0b_00_0100_0000\n else if f_is_pos_inf_H (rs1_val_H) then 0b_00_1000_0000\n else if f_is_SNaN_H (rs1_val_H) then 0b_01_0000_0000\n else if f_is_QNaN_H (rs1_val_H) then 0b_10_0000_0000\n else zeros();\n\n X(rd) = zero_extend (rd_val_10b);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_H" } ] } ] }, "body": " let rs1_val_H = F_or_X_H(rs1);\n\n let rd_val_10b : bits (10) =\n if f_is_neg_inf_H (rs1_val_H) then 0b_00_0000_0001\n else if f_is_neg_norm_H (rs1_val_H) then 0b_00_0000_0010\n else if f_is_neg_subnorm_H (rs1_val_H) then 0b_00_0000_0100\n else if f_is_neg_zero_H (rs1_val_H) then 0b_00_0000_1000\n else if f_is_pos_zero_H (rs1_val_H) then 0b_00_0001_0000\n else if f_is_pos_subnorm_H (rs1_val_H) then 0b_00_0010_0000\n else if f_is_pos_norm_H (rs1_val_H) then 0b_00_0100_0000\n else if f_is_pos_inf_H (rs1_val_H) then 0b_00_1000_0000\n else if f_is_SNaN_H (rs1_val_H) then 0b_01_0000_0000\n else if f_is_QNaN_H (rs1_val_H) then 0b_10_0000_0000\n else zeros();\n\n X(rd) = zero_extend (rd_val_10b);\n RETIRE_SUCCESS" }, { "number": 177, "source": "function clause execute (F_UN_TYPE_H(rs1, rd, FMV_X_H)) = {\n let rs1_val_H = F(rs1)[15..0];\n let rd_val_X : xlenbits = sign_extend(rs1_val_H);\n X(rd) = rd_val_X;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_H" } ] } ] }, "body": " let rs1_val_H = F(rs1)[15..0];\n let rd_val_X : xlenbits = sign_extend(rs1_val_H);\n X(rd) = rd_val_X;\n RETIRE_SUCCESS" }, { "number": 178, "source": "function clause execute (F_UN_TYPE_H(rs1, rd, FMV_H_X)) = {\n let rs1_val_X = X(rs1);\n let rd_val_H = rs1_val_X [15..0];\n F(rd) = nan_box (rd_val_H);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_H_X" } ] } ] }, "body": " let rs1_val_X = X(rs1);\n let rd_val_H = rs1_val_X [15..0];\n F(rd) = nan_box (rd_val_H);\n RETIRE_SUCCESS" }, { "number": 179, "source": "function clause execute (RISCV_FLI_H(constantidx, rd)) = {\n let bits : bits(16) = match constantidx {\n 0b00000 => { 0xbc00 }, /* -1.0 */\n 0b00001 => { 0x0400 }, /* minimum positive normal */\n 0b00010 => { 0x0100 }, /* 1.0 * 2^-16 */\n 0b00011 => { 0x0200 }, /* 1.0 * 2^-15 */\n 0b00100 => { 0x1c00 }, /* 1.0 * 2^-8 */\n 0b00101 => { 0x2000 }, /* 1.0 * 2^-7 */\n 0b00110 => { 0x2c00 }, /* 1.0 * 2^-4 */\n 0b00111 => { 0x3000 }, /* 1.0 * 2^-3 */\n 0b01000 => { 0x3400 }, /* 0.25 */\n 0b01001 => { 0x3500 }, /* 0.3125 */\n 0b01010 => { 0x3600 }, /* 0.375 */\n 0b01011 => { 0x3700 }, /* 0.4375 */\n 0b01100 => { 0x3800 }, /* 0.5 */\n 0b01101 => { 0x3900 }, /* 0.625 */\n 0b01110 => { 0x3a00 }, /* 0.75 */\n 0b01111 => { 0x3b00 }, /* 0.875 */\n 0b10000 => { 0x3c00 }, /* 1.0 */\n 0b10001 => { 0x3d00 }, /* 1.25 */\n 0b10010 => { 0x3e00 }, /* 1.5 */\n 0b10011 => { 0x3f00 }, /* 1.75 */\n 0b10100 => { 0x4000 }, /* 2.0 */\n 0b10101 => { 0x4100 }, /* 2.5 */\n 0b10110 => { 0x4200 }, /* 3 */\n 0b10111 => { 0x4400 }, /* 4 */\n 0b11000 => { 0x4800 }, /* 8 */\n 0b11001 => { 0x4c00 }, /* 16 */\n 0b11010 => { 0x5800 }, /* 2^7 */\n 0b11011 => { 0x5c00 }, /* 2^8 */\n 0b11100 => { 0x7800 }, /* 2^15 */\n 0b11101 => { 0x7c00 }, /* 2^16 */\n 0b11110 => { 0x7c00 }, /* +inf */\n 0b11111 => { canonical_NaN_H() },\n };\n F_H(rd) = bits;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLI_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "constantidx" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let bits : bits(16) = match constantidx {\n 0b00000 => { 0xbc00 }, /* -1.0 */\n 0b00001 => { 0x0400 }, /* minimum positive normal */\n 0b00010 => { 0x0100 }, /* 1.0 * 2^-16 */\n 0b00011 => { 0x0200 }, /* 1.0 * 2^-15 */\n 0b00100 => { 0x1c00 }, /* 1.0 * 2^-8 */\n 0b00101 => { 0x2000 }, /* 1.0 * 2^-7 */\n 0b00110 => { 0x2c00 }, /* 1.0 * 2^-4 */\n 0b00111 => { 0x3000 }, /* 1.0 * 2^-3 */\n 0b01000 => { 0x3400 }, /* 0.25 */\n 0b01001 => { 0x3500 }, /* 0.3125 */\n 0b01010 => { 0x3600 }, /* 0.375 */\n 0b01011 => { 0x3700 }, /* 0.4375 */\n 0b01100 => { 0x3800 }, /* 0.5 */\n 0b01101 => { 0x3900 }, /* 0.625 */\n 0b01110 => { 0x3a00 }, /* 0.75 */\n 0b01111 => { 0x3b00 }, /* 0.875 */\n 0b10000 => { 0x3c00 }, /* 1.0 */\n 0b10001 => { 0x3d00 }, /* 1.25 */\n 0b10010 => { 0x3e00 }, /* 1.5 */\n 0b10011 => { 0x3f00 }, /* 1.75 */\n 0b10100 => { 0x4000 }, /* 2.0 */\n 0b10101 => { 0x4100 }, /* 2.5 */\n 0b10110 => { 0x4200 }, /* 3 */\n 0b10111 => { 0x4400 }, /* 4 */\n 0b11000 => { 0x4800 }, /* 8 */\n 0b11001 => { 0x4c00 }, /* 16 */\n 0b11010 => { 0x5800 }, /* 2^7 */\n 0b11011 => { 0x5c00 }, /* 2^8 */\n 0b11100 => { 0x7800 }, /* 2^15 */\n 0b11101 => { 0x7c00 }, /* 2^16 */\n 0b11110 => { 0x7c00 }, /* +inf */\n 0b11111 => { canonical_NaN_H() },\n };\n F_H(rd) = bits;\n RETIRE_SUCCESS" }, { "number": 180, "source": "function clause execute (RISCV_FLI_S(constantidx, rd)) = {\n let bits : bits(32) = match constantidx {\n 0b00000 => { 0xbf800000 }, /* -1.0 */\n 0b00001 => { 0x00800000 }, /* minimum positive normal */\n 0b00010 => { 0x37800000 }, /* 1.0 * 2^-16 */\n 0b00011 => { 0x38000000 }, /* 1.0 * 2^-15 */\n 0b00100 => { 0x3b800000 }, /* 1.0 * 2^-8 */\n 0b00101 => { 0x3c000000 }, /* 1.0 * 2^-7 */\n 0b00110 => { 0x3d800000 }, /* 1.0 * 2^-4 */\n 0b00111 => { 0x3e000000 }, /* 1.0 * 2^-3 */\n 0b01000 => { 0x3e800000 }, /* 0.25 */\n 0b01001 => { 0x3ea00000 }, /* 0.3125 */\n 0b01010 => { 0x3ec00000 }, /* 0.375 */\n 0b01011 => { 0x3ee00000 }, /* 0.4375 */\n 0b01100 => { 0x3f000000 }, /* 0.5 */\n 0b01101 => { 0x3f200000 }, /* 0.625 */\n 0b01110 => { 0x3f400000 }, /* 0.75 */\n 0b01111 => { 0x3f600000 }, /* 0.875 */\n 0b10000 => { 0x3f800000 }, /* 1.0 */\n 0b10001 => { 0x3fa00000 }, /* 1.25 */\n 0b10010 => { 0x3fc00000 }, /* 1.5 */\n 0b10011 => { 0x3fe00000 }, /* 1.75 */\n 0b10100 => { 0x40000000 }, /* 2.0 */\n 0b10101 => { 0x40200000 }, /* 2.5 */\n 0b10110 => { 0x40400000 }, /* 3 */\n 0b10111 => { 0x40800000 }, /* 4 */\n 0b11000 => { 0x41000000 }, /* 8 */\n 0b11001 => { 0x41800000 }, /* 16 */\n 0b11010 => { 0x43000000 }, /* 2^7 */\n 0b11011 => { 0x43800000 }, /* 2^8 */\n 0b11100 => { 0x47000000 }, /* 2^15 */\n 0b11101 => { 0x47800000 }, /* 2^16 */\n 0b11110 => { 0x7f800000 }, /* +inf */\n 0b11111 => { canonical_NaN_S() },\n };\n F_S(rd) = bits;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLI_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "constantidx" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let bits : bits(32) = match constantidx {\n 0b00000 => { 0xbf800000 }, /* -1.0 */\n 0b00001 => { 0x00800000 }, /* minimum positive normal */\n 0b00010 => { 0x37800000 }, /* 1.0 * 2^-16 */\n 0b00011 => { 0x38000000 }, /* 1.0 * 2^-15 */\n 0b00100 => { 0x3b800000 }, /* 1.0 * 2^-8 */\n 0b00101 => { 0x3c000000 }, /* 1.0 * 2^-7 */\n 0b00110 => { 0x3d800000 }, /* 1.0 * 2^-4 */\n 0b00111 => { 0x3e000000 }, /* 1.0 * 2^-3 */\n 0b01000 => { 0x3e800000 }, /* 0.25 */\n 0b01001 => { 0x3ea00000 }, /* 0.3125 */\n 0b01010 => { 0x3ec00000 }, /* 0.375 */\n 0b01011 => { 0x3ee00000 }, /* 0.4375 */\n 0b01100 => { 0x3f000000 }, /* 0.5 */\n 0b01101 => { 0x3f200000 }, /* 0.625 */\n 0b01110 => { 0x3f400000 }, /* 0.75 */\n 0b01111 => { 0x3f600000 }, /* 0.875 */\n 0b10000 => { 0x3f800000 }, /* 1.0 */\n 0b10001 => { 0x3fa00000 }, /* 1.25 */\n 0b10010 => { 0x3fc00000 }, /* 1.5 */\n 0b10011 => { 0x3fe00000 }, /* 1.75 */\n 0b10100 => { 0x40000000 }, /* 2.0 */\n 0b10101 => { 0x40200000 }, /* 2.5 */\n 0b10110 => { 0x40400000 }, /* 3 */\n 0b10111 => { 0x40800000 }, /* 4 */\n 0b11000 => { 0x41000000 }, /* 8 */\n 0b11001 => { 0x41800000 }, /* 16 */\n 0b11010 => { 0x43000000 }, /* 2^7 */\n 0b11011 => { 0x43800000 }, /* 2^8 */\n 0b11100 => { 0x47000000 }, /* 2^15 */\n 0b11101 => { 0x47800000 }, /* 2^16 */\n 0b11110 => { 0x7f800000 }, /* +inf */\n 0b11111 => { canonical_NaN_S() },\n };\n F_S(rd) = bits;\n RETIRE_SUCCESS" }, { "number": 181, "source": "function clause execute (RISCV_FLI_D(constantidx, rd)) = {\n let bits : bits(64) = match constantidx {\n 0b00000 => { 0xbff0000000000000 }, /* -1.0 */\n 0b00001 => { 0x0010000000000000 }, /* minimum positive normal */\n 0b00010 => { 0x3Ef0000000000000 }, /* 1.0 * 2^-16 */\n 0b00011 => { 0x3f00000000000000 }, /* 1.0 * 2^-15 */\n 0b00100 => { 0x3f70000000000000 }, /* 1.0 * 2^-8 */\n 0b00101 => { 0x3f80000000000000 }, /* 1.0 * 2^-7 */\n 0b00110 => { 0x3fb0000000000000 }, /* 1.0 * 2^-4 */\n 0b00111 => { 0x3fc0000000000000 }, /* 1.0 * 2^-3 */\n 0b01000 => { 0x3fd0000000000000 }, /* 0.25 */\n 0b01001 => { 0x3fd4000000000000 }, /* 0.3125 */\n 0b01010 => { 0x3fd8000000000000 }, /* 0.375 */\n 0b01011 => { 0x3fdc000000000000 }, /* 0.4375 */\n 0b01100 => { 0x3fe0000000000000 }, /* 0.5 */\n 0b01101 => { 0x3fe4000000000000 }, /* 0.625 */\n 0b01110 => { 0x3fe8000000000000 }, /* 0.75 */\n 0b01111 => { 0x3fec000000000000 }, /* 0.875 */\n 0b10000 => { 0x3ff0000000000000 }, /* 1.0 */\n 0b10001 => { 0x3ff4000000000000 }, /* 1.25 */\n 0b10010 => { 0x3ff8000000000000 }, /* 1.5 */\n 0b10011 => { 0x3ffc000000000000 }, /* 1.75 */\n 0b10100 => { 0x4000000000000000 }, /* 2.0 */\n 0b10101 => { 0x4004000000000000 }, /* 2.5 */\n 0b10110 => { 0x4008000000000000 }, /* 3 */\n 0b10111 => { 0x4010000000000000 }, /* 4 */\n 0b11000 => { 0x4020000000000000 }, /* 8 */\n 0b11001 => { 0x4030000000000000 }, /* 16 */\n 0b11010 => { 0x4060000000000000 }, /* 2^7 */\n 0b11011 => { 0x4070000000000000 }, /* 2^8 */\n 0b11100 => { 0x40e0000000000000 }, /* 2^15 */\n 0b11101 => { 0x40f0000000000000 }, /* 2^16 */\n 0b11110 => { 0x7ff0000000000000 }, /* +inf */\n 0b11111 => { canonical_NaN_D() },\n };\n F_D(rd) = bits;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLI_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "constantidx" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let bits : bits(64) = match constantidx {\n 0b00000 => { 0xbff0000000000000 }, /* -1.0 */\n 0b00001 => { 0x0010000000000000 }, /* minimum positive normal */\n 0b00010 => { 0x3Ef0000000000000 }, /* 1.0 * 2^-16 */\n 0b00011 => { 0x3f00000000000000 }, /* 1.0 * 2^-15 */\n 0b00100 => { 0x3f70000000000000 }, /* 1.0 * 2^-8 */\n 0b00101 => { 0x3f80000000000000 }, /* 1.0 * 2^-7 */\n 0b00110 => { 0x3fb0000000000000 }, /* 1.0 * 2^-4 */\n 0b00111 => { 0x3fc0000000000000 }, /* 1.0 * 2^-3 */\n 0b01000 => { 0x3fd0000000000000 }, /* 0.25 */\n 0b01001 => { 0x3fd4000000000000 }, /* 0.3125 */\n 0b01010 => { 0x3fd8000000000000 }, /* 0.375 */\n 0b01011 => { 0x3fdc000000000000 }, /* 0.4375 */\n 0b01100 => { 0x3fe0000000000000 }, /* 0.5 */\n 0b01101 => { 0x3fe4000000000000 }, /* 0.625 */\n 0b01110 => { 0x3fe8000000000000 }, /* 0.75 */\n 0b01111 => { 0x3fec000000000000 }, /* 0.875 */\n 0b10000 => { 0x3ff0000000000000 }, /* 1.0 */\n 0b10001 => { 0x3ff4000000000000 }, /* 1.25 */\n 0b10010 => { 0x3ff8000000000000 }, /* 1.5 */\n 0b10011 => { 0x3ffc000000000000 }, /* 1.75 */\n 0b10100 => { 0x4000000000000000 }, /* 2.0 */\n 0b10101 => { 0x4004000000000000 }, /* 2.5 */\n 0b10110 => { 0x4008000000000000 }, /* 3 */\n 0b10111 => { 0x4010000000000000 }, /* 4 */\n 0b11000 => { 0x4020000000000000 }, /* 8 */\n 0b11001 => { 0x4030000000000000 }, /* 16 */\n 0b11010 => { 0x4060000000000000 }, /* 2^7 */\n 0b11011 => { 0x4070000000000000 }, /* 2^8 */\n 0b11100 => { 0x40e0000000000000 }, /* 2^15 */\n 0b11101 => { 0x40f0000000000000 }, /* 2^16 */\n 0b11110 => { 0x7ff0000000000000 }, /* +inf */\n 0b11111 => { canonical_NaN_D() },\n };\n F_D(rd) = bits;\n RETIRE_SUCCESS" }, { "number": 182, "source": "function clause execute (RISCV_FMINM_H(rs2, rs1, rd)) = {\n let rs1_val_H = F_H(rs1);\n let rs2_val_H = F_H(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_H (rs1_val_H, rs2_val_H, is_quiet);\n\n let rd_val_H = if (f_is_NaN_H(rs1_val_H) | f_is_NaN_H(rs2_val_H)) then canonical_NaN_H()\n else if (f_is_neg_zero_H(rs1_val_H) & f_is_pos_zero_H(rs2_val_H)) then rs1_val_H\n else if (f_is_neg_zero_H(rs2_val_H) & f_is_pos_zero_H(rs1_val_H)) then rs2_val_H\n else if rs1_lt_rs2 then rs1_val_H\n else /* (not rs1_lt_rs2) */ rs2_val_H;\n\n accrue_fflags(fflags);\n F_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FMINM_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_H = F_H(rs1);\n let rs2_val_H = F_H(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_H (rs1_val_H, rs2_val_H, is_quiet);\n\n let rd_val_H = if (f_is_NaN_H(rs1_val_H) | f_is_NaN_H(rs2_val_H)) then canonical_NaN_H()\n else if (f_is_neg_zero_H(rs1_val_H) & f_is_pos_zero_H(rs2_val_H)) then rs1_val_H\n else if (f_is_neg_zero_H(rs2_val_H) & f_is_pos_zero_H(rs1_val_H)) then rs2_val_H\n else if rs1_lt_rs2 then rs1_val_H\n else /* (not rs1_lt_rs2) */ rs2_val_H;\n\n accrue_fflags(fflags);\n F_H(rd) = rd_val_H;\n RETIRE_SUCCESS" }, { "number": 183, "source": "function clause execute (RISCV_FMAXM_H(rs2, rs1, rd)) = {\n let rs1_val_H = F_H(rs1);\n let rs2_val_H = F_H(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_H (rs2_val_H, rs1_val_H, is_quiet);\n\n let rd_val_H = if (f_is_NaN_H(rs1_val_H) | f_is_NaN_H(rs2_val_H)) then canonical_NaN_H()\n else if (f_is_neg_zero_H(rs1_val_H) & f_is_pos_zero_H(rs2_val_H)) then rs2_val_H\n else if (f_is_neg_zero_H(rs2_val_H) & f_is_pos_zero_H(rs1_val_H)) then rs1_val_H\n else if rs2_lt_rs1 then rs1_val_H\n else /* (not rs2_lt_rs1) */ rs2_val_H;\n\n accrue_fflags(fflags);\n F_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FMAXM_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_H = F_H(rs1);\n let rs2_val_H = F_H(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_H (rs2_val_H, rs1_val_H, is_quiet);\n\n let rd_val_H = if (f_is_NaN_H(rs1_val_H) | f_is_NaN_H(rs2_val_H)) then canonical_NaN_H()\n else if (f_is_neg_zero_H(rs1_val_H) & f_is_pos_zero_H(rs2_val_H)) then rs2_val_H\n else if (f_is_neg_zero_H(rs2_val_H) & f_is_pos_zero_H(rs1_val_H)) then rs1_val_H\n else if rs2_lt_rs1 then rs1_val_H\n else /* (not rs2_lt_rs1) */ rs2_val_H;\n\n accrue_fflags(fflags);\n F_H(rd) = rd_val_H;\n RETIRE_SUCCESS" }, { "number": 184, "source": "function clause execute (RISCV_FMINM_S(rs2, rs1, rd)) = {\n let rs1_val_S = F_S(rs1);\n let rs2_val_S = F_S(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_S (rs1_val_S, rs2_val_S, is_quiet);\n\n let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S()\n else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs1_val_S\n else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs2_val_S\n else if rs1_lt_rs2 then rs1_val_S\n else /* (not rs1_lt_rs2) */ rs2_val_S;\n\n accrue_fflags(fflags);\n F_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FMINM_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_S = F_S(rs1);\n let rs2_val_S = F_S(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_S (rs1_val_S, rs2_val_S, is_quiet);\n\n let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S()\n else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs1_val_S\n else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs2_val_S\n else if rs1_lt_rs2 then rs1_val_S\n else /* (not rs1_lt_rs2) */ rs2_val_S;\n\n accrue_fflags(fflags);\n F_S(rd) = rd_val_S;\n RETIRE_SUCCESS" }, { "number": 185, "source": "function clause execute (RISCV_FMAXM_S(rs2, rs1, rd)) = {\n let rs1_val_S = F_S(rs1);\n let rs2_val_S = F_S(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_S (rs2_val_S, rs1_val_S, is_quiet);\n\n let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S()\n else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs2_val_S\n else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs1_val_S\n else if rs2_lt_rs1 then rs1_val_S\n else /* (not rs2_lt_rs1) */ rs2_val_S;\n\n accrue_fflags(fflags);\n F_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FMAXM_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_S = F_S(rs1);\n let rs2_val_S = F_S(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_S (rs2_val_S, rs1_val_S, is_quiet);\n\n let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S()\n else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs2_val_S\n else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs1_val_S\n else if rs2_lt_rs1 then rs1_val_S\n else /* (not rs2_lt_rs1) */ rs2_val_S;\n\n accrue_fflags(fflags);\n F_S(rd) = rd_val_S;\n RETIRE_SUCCESS" }, { "number": 186, "source": "function clause execute (RISCV_FMINM_D(rs2, rs1, rd)) = {\n let rs1_val_D = F(rs1);\n let rs2_val_D = F(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_D (rs1_val_D, rs2_val_D, is_quiet);\n\n let rd_val_D = if (f_is_NaN_D(rs1_val_D) | f_is_NaN_D(rs2_val_D)) then canonical_NaN_D()\n else if (f_is_neg_zero_D(rs1_val_D) & f_is_pos_zero_D(rs2_val_D)) then rs1_val_D\n else if (f_is_neg_zero_D(rs2_val_D) & f_is_pos_zero_D(rs1_val_D)) then rs2_val_D\n else if rs1_lt_rs2 then rs1_val_D\n else rs2_val_D;\n\n accrue_fflags(fflags);\n F(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FMINM_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_D = F(rs1);\n let rs2_val_D = F(rs2);\n\n let is_quiet = true;\n let (rs1_lt_rs2, fflags) = fle_D (rs1_val_D, rs2_val_D, is_quiet);\n\n let rd_val_D = if (f_is_NaN_D(rs1_val_D) | f_is_NaN_D(rs2_val_D)) then canonical_NaN_D()\n else if (f_is_neg_zero_D(rs1_val_D) & f_is_pos_zero_D(rs2_val_D)) then rs1_val_D\n else if (f_is_neg_zero_D(rs2_val_D) & f_is_pos_zero_D(rs1_val_D)) then rs2_val_D\n else if rs1_lt_rs2 then rs1_val_D\n else rs2_val_D;\n\n accrue_fflags(fflags);\n F(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 187, "source": "function clause execute (RISCV_FMAXM_D(rs2, rs1, rd)) = {\n let rs1_val_D = F(rs1);\n let rs2_val_D = F(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_D (rs2_val_D, rs1_val_D, is_quiet);\n\n let rd_val_D = if (f_is_NaN_D(rs1_val_D) | f_is_NaN_D(rs2_val_D)) then canonical_NaN_D()\n else if (f_is_neg_zero_D(rs1_val_D) & f_is_pos_zero_D(rs2_val_D)) then rs2_val_D\n else if (f_is_neg_zero_D(rs2_val_D) & f_is_pos_zero_D(rs1_val_D)) then rs1_val_D\n else if rs2_lt_rs1 then rs1_val_D\n else rs2_val_D;\n\n accrue_fflags(fflags);\n F(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FMAXM_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_D = F(rs1);\n let rs2_val_D = F(rs2);\n\n let is_quiet = true;\n let (rs2_lt_rs1, fflags) = fle_D (rs2_val_D, rs1_val_D, is_quiet);\n\n let rd_val_D = if (f_is_NaN_D(rs1_val_D) | f_is_NaN_D(rs2_val_D)) then canonical_NaN_D()\n else if (f_is_neg_zero_D(rs1_val_D) & f_is_pos_zero_D(rs2_val_D)) then rs2_val_D\n else if (f_is_neg_zero_D(rs2_val_D) & f_is_pos_zero_D(rs1_val_D)) then rs1_val_D\n else if rs2_lt_rs1 then rs1_val_D\n else rs2_val_D;\n\n accrue_fflags(fflags);\n F(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 188, "source": "function clause execute (RISCV_FROUND_H(rs1, rm, rd)) = {\n let rs1_val_H = F_H(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f16roundToInt(rm_3b, rs1_val_H, false);\n\n accrue_fflags(fflags);\n F_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "RISCV_FROUND_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_H = F_H(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f16roundToInt(rm_3b, rs1_val_H, false);\n\n accrue_fflags(fflags);\n F_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 189, "source": "function clause execute (RISCV_FROUNDNX_H(rs1, rm, rd)) = {\n let rs1_val_H = F_H(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f16roundToInt(rm_3b, rs1_val_H, true);\n\n accrue_fflags(fflags);\n F_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "RISCV_FROUNDNX_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_H = F_H(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_H) = riscv_f16roundToInt(rm_3b, rs1_val_H, true);\n\n accrue_fflags(fflags);\n F_H(rd) = rd_val_H;\n RETIRE_SUCCESS\n }\n }" }, { "number": 190, "source": "function clause execute (RISCV_FROUND_S(rs1, rm, rd)) = {\n let rs1_val_S = F_S(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, false);\n\n accrue_fflags(fflags);\n F_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "RISCV_FROUND_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_S = F_S(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, false);\n\n accrue_fflags(fflags);\n F_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 191, "source": "function clause execute (RISCV_FROUNDNX_S(rs1, rm, rd)) = {\n let rs1_val_S = F_S(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, true);\n\n accrue_fflags(fflags);\n F_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "RISCV_FROUNDNX_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_S = F_S(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, true);\n\n accrue_fflags(fflags);\n F_S(rd) = rd_val_S;\n RETIRE_SUCCESS\n }\n }" }, { "number": 192, "source": "function clause execute (RISCV_FROUND_D(rs1, rm, rd)) = {\n let rs1_val_D = F(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f64roundToInt(rm_3b, rs1_val_D, false);\n\n accrue_fflags(fflags);\n F(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "RISCV_FROUND_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_D = F(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f64roundToInt(rm_3b, rs1_val_D, false);\n\n accrue_fflags(fflags);\n F(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 193, "source": "function clause execute (RISCV_FROUNDNX_D(rs1, rm, rd)) = {\n let rs1_val_D = F_D(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f64roundToInt(rm_3b, rs1_val_D, true);\n\n accrue_fflags(fflags);\n F_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }\n}", "pattern": { "type": "app", "id": "RISCV_FROUNDNX_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_D = F_D(rs1);\n\n match (select_instr_or_fcsr_rm(rm)) {\n None() => { handle_illegal(); RETIRE_FAIL },\n Some(rm') => {\n let rm_3b = encdec_rounding_mode(rm');\n let (fflags, rd_val_D) = riscv_f64roundToInt(rm_3b, rs1_val_D, true);\n\n accrue_fflags(fflags);\n F_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n }\n }" }, { "number": 194, "source": "function clause execute (RISCV_FMVH_X_D(rs1, rd)) = {\n let rs1_val_D = F_D(rs1)[63..32];\n let rd_val_X : xlenbits = sign_extend(rs1_val_D);\n X(rd) = rd_val_X;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FMVH_X_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_D = F_D(rs1)[63..32];\n let rd_val_X : xlenbits = sign_extend(rs1_val_D);\n X(rd) = rd_val_X;\n RETIRE_SUCCESS" }, { "number": 195, "source": "function clause execute (RISCV_FMVP_D_X(rs2, rs1, rd)) = {\n let rs1_val_X = X(rs1)[31..0];\n let rs2_val_X = X(rs2)[31..0];\n\n /* Concatenate the two values using '@' operator */\n /* e.g. */\n /* rs1 = 0x01234567 */\n /* rs2 = 0x89abcdef */\n /* rd = rs1 @ rs2 => 0x89abcdef01234567 */\n let rd_val_D = rs2_val_X @ rs1_val_X;\n\n F_D(rd) = rd_val_D;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FMVP_D_X", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_X = X(rs1)[31..0];\n let rs2_val_X = X(rs2)[31..0];\n\n /* Concatenate the two values using '@' operator */\n /* e.g. */\n /* rs1 = 0x01234567 */\n /* rs2 = 0x89abcdef */\n /* rd = rs1 @ rs2 => 0x89abcdef01234567 */\n let rd_val_D = rs2_val_X @ rs1_val_X;\n\n F_D(rd) = rd_val_D;\n RETIRE_SUCCESS" }, { "number": 196, "source": "function clause execute(RISCV_FLEQ_H(rs2, rs1, rd)) = {\n let rs1_val_H = F_H(rs1);\n let rs2_val_H = F_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Le_quiet (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLEQ_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_H = F_H(rs1);\n let rs2_val_H = F_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Le_quiet (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 197, "source": "function clause execute(RISCV_FLTQ_H(rs2, rs1, rd)) = {\n let rs1_val_H = F_H(rs1);\n let rs2_val_H = F_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Lt_quiet (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLTQ_H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_H = F_H(rs1);\n let rs2_val_H = F_H(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f16Lt_quiet (rs1_val_H, rs2_val_H);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 198, "source": "function clause execute(RISCV_FLEQ_S(rs2, rs1, rd)) = {\n let rs1_val_S = F_S(rs1);\n let rs2_val_S = F_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Le_quiet (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLEQ_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_S = F_S(rs1);\n let rs2_val_S = F_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Le_quiet (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 199, "source": "function clause execute(RISCV_FLTQ_S(rs2, rs1, rd)) = {\n let rs1_val_S = F_S(rs1);\n let rs2_val_S = F_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Lt_quiet (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLTQ_S", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_S = F_S(rs1);\n let rs2_val_S = F_S(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f32Lt_quiet (rs1_val_S, rs2_val_S);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 200, "source": "function clause execute(RISCV_FLEQ_D(rs2, rs1, rd)) = {\n let rs1_val_D = F_D(rs1);\n let rs2_val_D = F_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Le_quiet (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLEQ_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_D = F_D(rs1);\n let rs2_val_D = F_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Le_quiet (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 201, "source": "function clause execute(RISCV_FLTQ_D(rs2, rs1, rd)) = {\n let rs1_val_D = F_D(rs1);\n let rs2_val_D = F_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Lt_quiet (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FLTQ_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_D = F_D(rs1);\n let rs2_val_D = F_D(rs2);\n\n let (fflags, rd_val) : (bits_fflags, bool) =\n riscv_f64Lt_quiet (rs1_val_D, rs2_val_D);\n\n accrue_fflags(fflags);\n X(rd) = zero_extend(bool_to_bits(rd_val));\n RETIRE_SUCCESS" }, { "number": 202, "source": "function clause execute(RISCV_FCVTMOD_W_D(rs1, rd)) = {\n let rs1_val_D = F_D(rs1);\n let (fflags, rd_val) = fcvtmod_helper(rs1_val_D);\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_FCVTMOD_W_D", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val_D = F_D(rs1);\n let (fflags, rd_val) = fcvtmod_helper(rs1_val_D);\n accrue_fflags(fflags);\n X(rd) = sign_extend(rd_val);\n RETIRE_SUCCESS" }, { "number": 203, "source": "function clause execute (SHA256SIG0(rs1, rd)) = {\n let inb : bits(32) = X(rs1)[31..0];\n let result : bits(32) = (inb >>> 7) ^ (inb >>> 18) ^ (inb >> 3);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA256SIG0", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let inb : bits(32) = X(rs1)[31..0];\n let result : bits(32) = (inb >>> 7) ^ (inb >>> 18) ^ (inb >> 3);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 204, "source": "function clause execute (SHA256SIG1(rs1, rd)) = {\n let inb : bits(32) = X(rs1)[31..0];\n let result : bits(32) = (inb >>> 17) ^ (inb >>> 19) ^ (inb >> 10);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA256SIG1", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let inb : bits(32) = X(rs1)[31..0];\n let result : bits(32) = (inb >>> 17) ^ (inb >>> 19) ^ (inb >> 10);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 205, "source": "function clause execute (SHA256SUM0(rs1, rd)) = {\n let inb : bits(32) = X(rs1)[31..0];\n let result : bits(32) = (inb >>> 2) ^ (inb >>> 13) ^ (inb >>> 22);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA256SUM0", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let inb : bits(32) = X(rs1)[31..0];\n let result : bits(32) = (inb >>> 2) ^ (inb >>> 13) ^ (inb >>> 22);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 206, "source": "function clause execute (SHA256SUM1(rs1, rd)) = {\n let inb : bits(32) = X(rs1)[31..0];\n let result : bits(32) = (inb >>> 6) ^ (inb >>> 11) ^ (inb >>> 25);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA256SUM1", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let inb : bits(32) = X(rs1)[31..0];\n let result : bits(32) = (inb >>> 6) ^ (inb >>> 11) ^ (inb >>> 25);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 207, "source": "function clause execute (AES32ESMI (bs, rs2, rs1, rd)) = {\n let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */\n let si : bits( 8) = (X(rs2) >> shamt)[7..0]; /* SBox Input */\n let so : bits( 8) = aes_sbox_fwd(si);\n let mixed : bits(32) = aes_mixcolumn_byte_fwd(so);\n let result : bits(32) = X(rs1)[31..0] ^ (mixed <<< shamt);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES32ESMI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */\n let si : bits( 8) = (X(rs2) >> shamt)[7..0]; /* SBox Input */\n let so : bits( 8) = aes_sbox_fwd(si);\n let mixed : bits(32) = aes_mixcolumn_byte_fwd(so);\n let result : bits(32) = X(rs1)[31..0] ^ (mixed <<< shamt);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 208, "source": "function clause execute (AES32ESI (bs, rs2, rs1, rd)) = {\n let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */\n let si : bits( 8) = (X(rs2) >> shamt)[7..0]; /* SBox Input */\n let so : bits(32) = 0x000000 @ aes_sbox_fwd(si);\n let result : bits(32) = X(rs1)[31..0] ^ (so <<< shamt);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES32ESI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */\n let si : bits( 8) = (X(rs2) >> shamt)[7..0]; /* SBox Input */\n let so : bits(32) = 0x000000 @ aes_sbox_fwd(si);\n let result : bits(32) = X(rs1)[31..0] ^ (so <<< shamt);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 209, "source": "function clause execute (AES32DSMI (bs, rs2, rs1, rd)) = {\n let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */\n let si : bits( 8) = (X(rs2) >> shamt)[7..0]; /* SBox Input */\n let so : bits( 8) = aes_sbox_inv(si);\n let mixed : bits(32) = aes_mixcolumn_byte_inv(so);\n let result : bits(32) = X(rs1)[31..0] ^ (mixed <<< shamt);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES32DSMI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */\n let si : bits( 8) = (X(rs2) >> shamt)[7..0]; /* SBox Input */\n let so : bits( 8) = aes_sbox_inv(si);\n let mixed : bits(32) = aes_mixcolumn_byte_inv(so);\n let result : bits(32) = X(rs1)[31..0] ^ (mixed <<< shamt);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 210, "source": "function clause execute (AES32DSI (bs, rs2, rs1, rd)) = {\n let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */\n let si : bits( 8) = (X(rs2) >> shamt)[7..0]; /* SBox Input */\n let so : bits(32) = 0x000000 @ aes_sbox_inv(si);\n let result : bits(32) = X(rs1)[31..0] ^ (so <<< shamt);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES32DSI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let shamt : bits( 5) = bs @ 0b000; /* shamt = bs*8 */\n let si : bits( 8) = (X(rs2) >> shamt)[7..0]; /* SBox Input */\n let so : bits(32) = 0x000000 @ aes_sbox_inv(si);\n let result : bits(32) = X(rs1)[31..0] ^ (so <<< shamt);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 211, "source": "function clause execute (SHA512SIG0H(rs2, rs1, rd)) = {\n X(rd) = sign_extend((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^\n (X(rs2) << 31) ^ (X(rs2) << 24));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SIG0H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " X(rd) = sign_extend((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^\n (X(rs2) << 31) ^ (X(rs2) << 24));\n RETIRE_SUCCESS" }, { "number": 212, "source": "function clause execute (SHA512SIG0L(rs2, rs1, rd)) = {\n X(rd) = sign_extend((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^\n (X(rs2) << 31) ^ (X(rs2) << 25) ^ (X(rs2) << 24));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SIG0L", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " X(rd) = sign_extend((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^\n (X(rs2) << 31) ^ (X(rs2) << 25) ^ (X(rs2) << 24));\n RETIRE_SUCCESS" }, { "number": 213, "source": "function clause execute (SHA512SIG1H(rs2, rs1, rd)) = {\n X(rd) = sign_extend((X(rs1) << 3) ^ (X(rs1) >> 6) ^ (X(rs1) >> 19) ^\n (X(rs2) >> 29) ^ (X(rs2) << 13));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SIG1H", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " X(rd) = sign_extend((X(rs1) << 3) ^ (X(rs1) >> 6) ^ (X(rs1) >> 19) ^\n (X(rs2) >> 29) ^ (X(rs2) << 13));\n RETIRE_SUCCESS" }, { "number": 214, "source": "function clause execute (SHA512SIG1L(rs2, rs1, rd)) = {\n X(rd) = sign_extend((X(rs1) << 3) ^ (X(rs1) >> 6) ^ (X(rs1) >> 19) ^\n (X(rs2) >> 29) ^ (X(rs2) << 26) ^ (X(rs2) << 13));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SIG1L", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " X(rd) = sign_extend((X(rs1) << 3) ^ (X(rs1) >> 6) ^ (X(rs1) >> 19) ^\n (X(rs2) >> 29) ^ (X(rs2) << 26) ^ (X(rs2) << 13));\n RETIRE_SUCCESS" }, { "number": 215, "source": "function clause execute (SHA512SUM0R(rs2, rs1, rd)) = {\n X(rd) = sign_extend((X(rs1) << 25) ^ (X(rs1) << 30) ^ (X(rs1) >> 28) ^\n (X(rs2) >> 7) ^ (X(rs2) >> 2) ^ (X(rs2) << 4));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SUM0R", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " X(rd) = sign_extend((X(rs1) << 25) ^ (X(rs1) << 30) ^ (X(rs1) >> 28) ^\n (X(rs2) >> 7) ^ (X(rs2) >> 2) ^ (X(rs2) << 4));\n RETIRE_SUCCESS" }, { "number": 216, "source": "function clause execute (SHA512SUM1R(rs2, rs1, rd)) = {\n X(rd) = sign_extend((X(rs1) << 23) ^ (X(rs1) >> 14) ^ (X(rs1) >> 18) ^\n (X(rs2) >> 9) ^ (X(rs2) << 18) ^ (X(rs2) << 14));\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SUM1R", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " X(rd) = sign_extend((X(rs1) << 23) ^ (X(rs1) >> 14) ^ (X(rs1) >> 18) ^\n (X(rs2) >> 9) ^ (X(rs2) << 18) ^ (X(rs2) << 14));\n RETIRE_SUCCESS" }, { "number": 217, "source": "function clause execute (AES64KS1I(rnum, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let prev : bits(32) = X(rs1)[63..32];\n let subwords : bits(32) = aes_subword_fwd(prev);\n let result : bits(32) = if (rnum == 0xA) then subwords\n else (subwords >>> 8) ^ aes_decode_rcon(rnum);\n X(rd) = result @ result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES64KS1I", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rnum" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (AES64KS1I(rnum, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let prev : bits(32) = X(rs1)[63..32];\n let subwords : bits(32) = aes_subword_fwd(prev);\n let result : bits(32) = if (rnum == 0xA) then subwords\n else (subwords >>> 8) ^ aes_decode_rcon(rnum);\n X(rd) = result @ result;\n RETIRE_SUCCESS" }, { "number": 218, "source": "function clause execute (AES64KS2(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let w0 : bits(32) = X(rs1)[63..32] ^ X(rs2)[31..0];\n let w1 : bits(32) = X(rs1)[63..32] ^ X(rs2)[31..0] ^ X(rs2)[63..32];\n X(rd) = w1 @ w0;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES64KS2", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (AES64KS2(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let w0 : bits(32) = X(rs1)[63..32] ^ X(rs2)[31..0];\n let w1 : bits(32) = X(rs1)[63..32] ^ X(rs2)[31..0] ^ X(rs2)[63..32];\n X(rd) = w1 @ w0;\n RETIRE_SUCCESS" }, { "number": 219, "source": "function clause execute (AES64IM(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let w0 : bits(32) = aes_mixcolumn_inv(X(rs1)[31.. 0]);\n let w1 : bits(32) = aes_mixcolumn_inv(X(rs1)[63..32]);\n X(rd) = w1 @ w0;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES64IM", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (AES64IM(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let w0 : bits(32) = aes_mixcolumn_inv(X(rs1)[31.. 0]);\n let w1 : bits(32) = aes_mixcolumn_inv(X(rs1)[63..32]);\n X(rd) = w1 @ w0;\n RETIRE_SUCCESS" }, { "number": 220, "source": "function clause execute (AES64ESM(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let sr : bits(64) = aes_rv64_shiftrows_fwd(X(rs2), X(rs1));\n let wd : bits(64) = sr[63..0];\n let sb : bits(64) = aes_apply_fwd_sbox_to_each_byte(wd);\n X(rd) = aes_mixcolumn_fwd(sb[63..32]) @ aes_mixcolumn_fwd(sb[31..0]);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES64ESM", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (AES64ESM(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let sr : bits(64) = aes_rv64_shiftrows_fwd(X(rs2), X(rs1));\n let wd : bits(64) = sr[63..0];\n let sb : bits(64) = aes_apply_fwd_sbox_to_each_byte(wd);\n X(rd) = aes_mixcolumn_fwd(sb[63..32]) @ aes_mixcolumn_fwd(sb[31..0]);\n RETIRE_SUCCESS" }, { "number": 221, "source": "function clause execute (AES64ES(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let sr : bits(64) = aes_rv64_shiftrows_fwd(X(rs2), X(rs1));\n let wd : bits(64) = sr[63..0];\n X(rd) = aes_apply_fwd_sbox_to_each_byte(wd);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES64ES", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (AES64ES(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let sr : bits(64) = aes_rv64_shiftrows_fwd(X(rs2), X(rs1));\n let wd : bits(64) = sr[63..0];\n X(rd) = aes_apply_fwd_sbox_to_each_byte(wd);\n RETIRE_SUCCESS" }, { "number": 222, "source": "function clause execute (AES64DSM(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let sr : bits(64) = aes_rv64_shiftrows_inv(X(rs2), X(rs1));\n let wd : bits(64) = sr[63..0];\n let sb : bits(64) = aes_apply_inv_sbox_to_each_byte(wd);\n X(rd) = aes_mixcolumn_inv(sb[63..32]) @ aes_mixcolumn_inv(sb[31..0]);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES64DSM", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (AES64DSM(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let sr : bits(64) = aes_rv64_shiftrows_inv(X(rs2), X(rs1));\n let wd : bits(64) = sr[63..0];\n let sb : bits(64) = aes_apply_inv_sbox_to_each_byte(wd);\n X(rd) = aes_mixcolumn_inv(sb[63..32]) @ aes_mixcolumn_inv(sb[31..0]);\n RETIRE_SUCCESS" }, { "number": 223, "source": "function clause execute (AES64DS(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let sr : bits(64) = aes_rv64_shiftrows_inv(X(rs2), X(rs1));\n let wd : bits(64) = sr[63..0];\n X(rd) = aes_apply_inv_sbox_to_each_byte(wd);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "AES64DS", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (AES64DS(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let sr : bits(64) = aes_rv64_shiftrows_inv(X(rs2), X(rs1));\n let wd : bits(64) = sr[63..0];\n X(rd) = aes_apply_inv_sbox_to_each_byte(wd);\n RETIRE_SUCCESS" }, { "number": 224, "source": "function clause execute (SHA512SIG0(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let input : bits(64) = X(rs1);\n let result : bits(64) = (input >>> 1) ^ (input >>> 8) ^ (input >> 7);\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SIG0", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (SHA512SIG0(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let input : bits(64) = X(rs1);\n let result : bits(64) = (input >>> 1) ^ (input >>> 8) ^ (input >> 7);\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 225, "source": "function clause execute (SHA512SIG1(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let input : bits(64) = X(rs1);\n let result : bits(64) = (input >>> 19) ^ (input >>> 61) ^ (input >> 6);\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SIG1", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (SHA512SIG1(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let input : bits(64) = X(rs1);\n let result : bits(64) = (input >>> 19) ^ (input >>> 61) ^ (input >> 6);\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 226, "source": "function clause execute (SHA512SUM0(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let input : bits(64) = X(rs1);\n let result : bits(64) = (input >>> 28) ^ (input >>> 34) ^ (input >>> 39);\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SUM0", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (SHA512SUM0(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let input : bits(64) = X(rs1);\n let result : bits(64) = (input >>> 28) ^ (input >>> 34) ^ (input >>> 39);\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 227, "source": "function clause execute (SHA512SUM1(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let input : bits(64) = X(rs1);\n let result : bits(64) = (input >>> 14) ^ (input >>> 18) ^ (input >>> 41);\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SHA512SUM1", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (SHA512SUM1(rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let input : bits(64) = X(rs1);\n let result : bits(64) = (input >>> 14) ^ (input >>> 18) ^ (input >>> 41);\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 228, "source": "function clause execute (SM3P0(rs1, rd)) = {\n let r1 : bits(32) = X(rs1)[31..0];\n let result : bits(32) = r1 ^ (r1 <<< 9) ^ (r1 <<< 17);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SM3P0", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let r1 : bits(32) = X(rs1)[31..0];\n let result : bits(32) = r1 ^ (r1 <<< 9) ^ (r1 <<< 17);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 229, "source": "function clause execute (SM3P1(rs1, rd)) = {\n let r1 : bits(32) = X(rs1)[31..0];\n let result : bits(32) = r1 ^ (r1 <<< 15) ^ (r1 <<< 23);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SM3P1", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let r1 : bits(32) = X(rs1)[31..0];\n let result : bits(32) = r1 ^ (r1 <<< 15) ^ (r1 <<< 23);\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 230, "source": "function clause execute (SM4ED (bs, rs2, rs1, rd)) = {\n let shamt : bits(5) = bs @ 0b000; /* shamt = bs*8 */\n let sb_in : bits(8) = (X(rs2)[31..0] >> shamt)[7..0];\n let x : bits(32) = 0x000000 @ sm4_sbox(sb_in);\n let y : bits(32) = x ^ (x << 8) ^ ( x << 2) ^\n (x << 18) ^ ((x & 0x0000003F) << 26) ^\n ((x & 0x000000C0) << 10);\n let z : bits(32) = (y <<< shamt);\n let result : bits(32) = z ^ X(rs1)[31..0];\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SM4ED", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let shamt : bits(5) = bs @ 0b000; /* shamt = bs*8 */\n let sb_in : bits(8) = (X(rs2)[31..0] >> shamt)[7..0];\n let x : bits(32) = 0x000000 @ sm4_sbox(sb_in);\n let y : bits(32) = x ^ (x << 8) ^ ( x << 2) ^\n (x << 18) ^ ((x & 0x0000003F) << 26) ^\n ((x & 0x000000C0) << 10);\n let z : bits(32) = (y <<< shamt);\n let result : bits(32) = z ^ X(rs1)[31..0];\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 231, "source": "function clause execute (SM4KS (bs, rs2, rs1, rd)) = {\n let shamt : bits(5) = (bs @ 0b000); /* shamt = bs*8 */\n let sb_in : bits(8) = (X(rs2)[31..0] >> shamt)[7..0];\n let x : bits(32) = 0x000000 @ sm4_sbox(sb_in);\n let y : bits(32) = x ^ ((x & 0x00000007) << 29) ^ ((x & 0x000000FE) << 7) ^\n ((x & 0x00000001) << 23) ^ ((x & 0x000000F8) << 13) ;\n let z : bits(32) = (y <<< shamt);\n let result : bits(32) = z ^ X(rs1)[31..0];\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "SM4KS", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let shamt : bits(5) = (bs @ 0b000); /* shamt = bs*8 */\n let sb_in : bits(8) = (X(rs2)[31..0] >> shamt)[7..0];\n let x : bits(32) = 0x000000 @ sm4_sbox(sb_in);\n let y : bits(32) = x ^ ((x & 0x00000007) << 29) ^ ((x & 0x000000FE) << 7) ^\n ((x & 0x00000001) << 23) ^ ((x & 0x000000F8) << 13) ;\n let z : bits(32) = (y <<< shamt);\n let result : bits(32) = z ^ X(rs1)[31..0];\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 232, "source": "function clause execute (ZBKB_RTYPE(rs2, rs1, rd, op)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let result : xlenbits = match op {\n RISCV_PACK => rs2_val[(sizeof(xlen_bytes)*4 - 1)..0] @ rs1_val[(sizeof(xlen_bytes)*4 - 1)..0],\n RISCV_PACKH => zero_extend(rs2_val[7..0] @ rs1_val[7..0])\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBKB_RTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let result : xlenbits = match op {\n RISCV_PACK => rs2_val[(sizeof(xlen_bytes)*4 - 1)..0] @ rs1_val[(sizeof(xlen_bytes)*4 - 1)..0],\n RISCV_PACKH => zero_extend(rs2_val[7..0] @ rs1_val[7..0])\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 233, "source": "function clause execute (ZBKB_PACKW(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let result : bits(32) = rs2_val[15..0] @ rs1_val[15..0];\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZBKB_PACKW", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (ZBKB_PACKW(rs2, rs1, rd)) = {\n assert(sizeof(xlen) == 64);\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n let result : bits(32) = rs2_val[15..0] @ rs1_val[15..0];\n X(rd) = sign_extend(result);\n RETIRE_SUCCESS" }, { "number": 234, "source": "function clause execute (RISCV_ZIP(rs1, rd)) = {\n assert(sizeof(xlen) == 32);\n let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen_bytes)*4 - 1)) {\n result[i*2] = rs1_val[i];\n result[i*2 + 1] = rs1_val[i + sizeof(xlen_bytes)*4];\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_ZIP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (RISCV_ZIP(rs1, rd)) = {\n assert(sizeof(xlen) == 32);\n let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen_bytes)*4 - 1)) {\n result[i*2] = rs1_val[i];\n result[i*2 + 1] = rs1_val[i + sizeof(xlen_bytes)*4];\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}" }, { "number": 235, "source": "function clause execute (RISCV_UNZIP(rs1, rd)) = {\n assert(sizeof(xlen) == 32);\n let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen_bytes)*4 - 1)) {\n result[i] = rs1_val[i*2];\n result[i + sizeof(xlen_bytes)*4] = rs1_val[i*2 + 1];\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_UNZIP", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": "function clause execute (RISCV_UNZIP(rs1, rd)) = {\n assert(sizeof(xlen) == 32);\n let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen_bytes)*4 - 1)) {\n result[i] = rs1_val[i*2];\n result[i + sizeof(xlen_bytes)*4] = rs1_val[i*2 + 1];\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}" }, { "number": 236, "source": "function clause execute (RISCV_BREV8(rs1, rd)) = {\n let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 8) by 8)\n result[i+7..i] = reverse(rs1_val[i+7..i]);\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_BREV8", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 8) by 8)\n result[i+7..i] = reverse(rs1_val[i+7..i]);\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 237, "source": "function clause execute (RISCV_XPERM8(rs2, rs1, rd)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 8) by 8) {\n let index = unsigned(rs2_val[i+7..i]);\n result[i+7..i] = if 8*index < sizeof(xlen)\n then rs1_val[8*index+7..8*index]\n else zeros()\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_XPERM8", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 8) by 8) {\n let index = unsigned(rs2_val[i+7..i]);\n result[i+7..i] = if 8*index < sizeof(xlen)\n then rs1_val[8*index+7..8*index]\n else zeros()\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 238, "source": "function clause execute (RISCV_XPERM4(rs2, rs1, rd)) = {\n let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 4) by 4) {\n let index = unsigned(rs2_val[i+3..i]);\n result[i+3..i] = if 4*index < sizeof(xlen)\n then rs1_val[4*index+3..4*index]\n else zeros()\n };\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RISCV_XPERM4", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rs1_val = X(rs1);\n let rs2_val = X(rs2);\n result : xlenbits = zeros();\n foreach (i from 0 to (sizeof(xlen) - 4) by 4) {\n let index = unsigned(rs2_val[i+3..i]);\n result[i+3..i] = if 4*index < sizeof(xlen)\n then rs1_val[4*index+3..4*index]\n else zeros()\n };\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 239, "source": "function clause execute (ZICOND_RTYPE(rs2, rs1, rd, RISCV_CZERO_EQZ)) = {\n let value = X(rs1);\n let condition = X(rs2);\n let result : xlenbits = if condition == zeros() then zeros()\n\t\t\t\t\t\t else value;\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZICOND_RTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_CZERO_EQZ" } ] } ] }, "body": " let value = X(rs1);\n let condition = X(rs2);\n let result : xlenbits = if condition == zeros() then zeros()\n\t\t\t\t\t\t else value;\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 240, "source": "function clause execute (ZICOND_RTYPE(rs2, rs1, rd, RISCV_CZERO_NEZ)) = {\n let value = X(rs1);\n let condition = X(rs2);\n let result : xlenbits = if (condition != zeros()) then zeros()\n\t\t\t\t\t\t else value;\n X(rd) = result;\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "ZICOND_RTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_CZERO_NEZ" } ] } ] }, "body": " let value = X(rs1);\n let condition = X(rs2);\n let result : xlenbits = if (condition != zeros()) then zeros()\n\t\t\t\t\t\t else value;\n X(rd) = result;\n RETIRE_SUCCESS" }, { "number": 241, "source": "function clause execute VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) = {\n let VLEN_pow = get_vlen_pow();\n let ELEN_pow = get_elen_pow();\n let LMUL_pow_ori = get_lmul_pow();\n let SEW_pow_ori = get_sew_pow();\n let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori;\n\n /* set vtype */\n match op {\n VSETVLI => {\n vtype.bits = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul\n },\n VSETVL => {\n let rs2 : regidx = sew[1 .. 0] @ lmul;\n vtype.bits = X(rs2)\n }\n };\n\n /* check legal SEW and LMUL and calculate VLMAX */\n let LMUL_pow_new = get_lmul_pow();\n let SEW_pow_new = get_sew_pow();\n if SEW_pow_new > LMUL_pow_new + ELEN_pow then {\n /* Note: Implementations can set vill or trap if the vtype setting is not supported.\n * TODO: configuration support for both solutions\n */\n vtype.bits = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */\n vl = zeros();\n print_reg(\"CSR vtype <- \" ^ BitStr(vtype.bits));\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n return RETIRE_SUCCESS\n };\n let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new);\n\n /* set vl according to VLMAX and AVL */\n if (rs1 != 0b00000) then { /* normal stripmining */\n let rs1_val = X(rs1);\n let AVL = unsigned(rs1_val);\n vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL)\n else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2)\n else to_bits(sizeof(xlen), VLMAX);\n /* Note: ceil(AVL / 2) ≤ vl ≤ VLMAX when VLMAX < AVL < (2 * VLMAX)\n * TODO: configuration support for either using ceil(AVL / 2) or VLMAX\n */\n X(rd) = vl;\n } else if (rd != 0b00000) then { /* set vl to VLMAX */\n let AVL = unsigned(ones(sizeof(xlen)));\n vl = to_bits(sizeof(xlen), VLMAX);\n X(rd) = vl;\n } else { /* keep existing vl */\n let AVL = unsigned(vl);\n let ratio_pow_new = SEW_pow_new - LMUL_pow_new;\n if (ratio_pow_new != ratio_pow_ori) then {\n /* Note: Implementations can set vill or trap if the vtype setting is not supported.\n * TODO: configuration support for both solutions\n */\n vtype.bits = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */\n vl = zeros();\n }\n };\n print_reg(\"CSR vtype <- \" ^ BitStr(vtype.bits));\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n\n /* reset vstart to 0 */\n vstart = zeros();\n print_reg(\"CSR vstart <- \" ^ BitStr(vstart));\n\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VSET_TYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "op" }, { "type": "id", "id": "ma" }, { "type": "id", "id": "ta" }, { "type": "id", "id": "sew" }, { "type": "id", "id": "lmul" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let VLEN_pow = get_vlen_pow();\n let ELEN_pow = get_elen_pow();\n let LMUL_pow_ori = get_lmul_pow();\n let SEW_pow_ori = get_sew_pow();\n let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori;\n\n /* set vtype */\n match op {\n VSETVLI => {\n vtype.bits = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul\n },\n VSETVL => {\n let rs2 : regidx = sew[1 .. 0] @ lmul;\n vtype.bits = X(rs2)\n }\n };\n\n /* check legal SEW and LMUL and calculate VLMAX */\n let LMUL_pow_new = get_lmul_pow();\n let SEW_pow_new = get_sew_pow();\n if SEW_pow_new > LMUL_pow_new + ELEN_pow then {\n /* Note: Implementations can set vill or trap if the vtype setting is not supported.\n * TODO: configuration support for both solutions\n */\n vtype.bits = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */\n vl = zeros();\n print_reg(\"CSR vtype <- \" ^ BitStr(vtype.bits));\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n return RETIRE_SUCCESS\n };\n let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new);\n\n /* set vl according to VLMAX and AVL */\n if (rs1 != 0b00000) then { /* normal stripmining */\n let rs1_val = X(rs1);\n let AVL = unsigned(rs1_val);\n vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL)\n else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2)\n else to_bits(sizeof(xlen), VLMAX);\n /* Note: ceil(AVL / 2) ≤ vl ≤ VLMAX when VLMAX < AVL < (2 * VLMAX)\n * TODO: configuration support for either using ceil(AVL / 2) or VLMAX\n */\n X(rd) = vl;\n } else if (rd != 0b00000) then { /* set vl to VLMAX */\n let AVL = unsigned(ones(sizeof(xlen)));\n vl = to_bits(sizeof(xlen), VLMAX);\n X(rd) = vl;\n } else { /* keep existing vl */\n let AVL = unsigned(vl);\n let ratio_pow_new = SEW_pow_new - LMUL_pow_new;\n if (ratio_pow_new != ratio_pow_ori) then {\n /* Note: Implementations can set vill or trap if the vtype setting is not supported.\n * TODO: configuration support for both solutions\n */\n vtype.bits = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */\n vl = zeros();\n }\n };\n print_reg(\"CSR vtype <- \" ^ BitStr(vtype.bits));\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n\n /* reset vstart to 0 */\n vstart = zeros();\n print_reg(\"CSR vstart <- \" ^ BitStr(vstart));\n\n RETIRE_SUCCESS" }, { "number": 242, "source": "function clause execute VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) = {\n let VLEN_pow = get_vlen_pow();\n let ELEN_pow = get_elen_pow();\n let LMUL_pow_ori = get_lmul_pow();\n let SEW_pow_ori = get_sew_pow();\n let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori;\n\n /* set vtype */\n vtype.bits = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul;\n\n /* check legal SEW and LMUL and calculate VLMAX */\n let LMUL_pow_new = get_lmul_pow();\n let SEW_pow_new = get_sew_pow();\n if SEW_pow_new > LMUL_pow_new + ELEN_pow then {\n /* Note: Implementations can set vill or trap if the vtype setting is not supported.\n * TODO: configuration support for both solutions\n */\n vtype.bits = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */\n vl = zeros();\n print_reg(\"CSR vtype <- \" ^ BitStr(vtype.bits));\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n return RETIRE_SUCCESS\n };\n let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new);\n let AVL = unsigned(uimm); /* AVL is encoded as 5-bit zero-extended imm in the rs1 field */\n\n /* set vl according to VLMAX and AVL */\n vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL)\n else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2)\n else to_bits(sizeof(xlen), VLMAX);\n /* Note: ceil(AVL / 2) ≤ vl ≤ VLMAX when VLMAX < AVL < (2 * VLMAX)\n * TODO: configuration support for either using ceil(AVL / 2) or VLMAX\n */\n X(rd) = vl;\n print_reg(\"CSR vtype <- \" ^ BitStr(vtype.bits));\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n\n /* reset vstart to 0 */\n vstart = zeros();\n print_reg(\"CSR vstart <- \" ^ BitStr(vstart));\n\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VSETI_TYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "ma" }, { "type": "id", "id": "ta" }, { "type": "id", "id": "sew" }, { "type": "id", "id": "lmul" }, { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let VLEN_pow = get_vlen_pow();\n let ELEN_pow = get_elen_pow();\n let LMUL_pow_ori = get_lmul_pow();\n let SEW_pow_ori = get_sew_pow();\n let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori;\n\n /* set vtype */\n vtype.bits = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul;\n\n /* check legal SEW and LMUL and calculate VLMAX */\n let LMUL_pow_new = get_lmul_pow();\n let SEW_pow_new = get_sew_pow();\n if SEW_pow_new > LMUL_pow_new + ELEN_pow then {\n /* Note: Implementations can set vill or trap if the vtype setting is not supported.\n * TODO: configuration support for both solutions\n */\n vtype.bits = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */\n vl = zeros();\n print_reg(\"CSR vtype <- \" ^ BitStr(vtype.bits));\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n return RETIRE_SUCCESS\n };\n let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new);\n let AVL = unsigned(uimm); /* AVL is encoded as 5-bit zero-extended imm in the rs1 field */\n\n /* set vl according to VLMAX and AVL */\n vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL)\n else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2)\n else to_bits(sizeof(xlen), VLMAX);\n /* Note: ceil(AVL / 2) ≤ vl ≤ VLMAX when VLMAX < AVL < (2 * VLMAX)\n * TODO: configuration support for either using ceil(AVL / 2) or VLMAX\n */\n X(rd) = vl;\n print_reg(\"CSR vtype <- \" ^ BitStr(vtype.bits));\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n\n /* reset vstart to 0 */\n vstart = zeros();\n print_reg(\"CSR vstart <- \" ^ BitStr(vstart));\n\n RETIRE_SUCCESS" }, { "number": 243, "source": "function clause execute(VVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW_pow = get_sew_pow();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let VLEN_pow = get_vlen_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VV_VADD => vs2_val[i] + vs1_val[i],\n VV_VSUB => vs2_val[i] - vs1_val[i],\n VV_VAND => vs2_val[i] & vs1_val[i],\n VV_VOR => vs2_val[i] | vs1_val[i],\n VV_VXOR => vs2_val[i] ^ vs1_val[i],\n VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])),\n VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])),\n VV_VSSUBU => {\n if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros()\n else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]))\n },\n VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])),\n VV_VSMUL => {\n let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i]));\n let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1);\n let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr);\n signed_saturation('m, result_wide['m..0])\n },\n VV_VSLL => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n vs2_val[i] << shift_amount\n },\n VV_VSRL => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n vs2_val[i] >> shift_amount\n },\n VV_VSRA => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW)\n },\n VV_VSSRL => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr)\n },\n VV_VSSRA => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr)\n },\n VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))),\n VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))),\n VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))),\n VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))),\n VV_VRGATHER => {\n if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n let idx = unsigned(vs1_val[i]);\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX <= 'n);\n if idx < VLMAX then vs2_val[idx] else zeros()\n },\n VV_VRGATHEREI16 => {\n if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */\n let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1);\n let idx = unsigned(vs1_new[i]);\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX <= 'n);\n if idx < VLMAX then vs2_val[idx] else zeros()\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW_pow = get_sew_pow();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let VLEN_pow = get_vlen_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VV_VADD => vs2_val[i] + vs1_val[i],\n VV_VSUB => vs2_val[i] - vs1_val[i],\n VV_VAND => vs2_val[i] & vs1_val[i],\n VV_VOR => vs2_val[i] | vs1_val[i],\n VV_VXOR => vs2_val[i] ^ vs1_val[i],\n VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])),\n VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])),\n VV_VSSUBU => {\n if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros()\n else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]))\n },\n VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])),\n VV_VSMUL => {\n let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i]));\n let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1);\n let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr);\n signed_saturation('m, result_wide['m..0])\n },\n VV_VSLL => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n vs2_val[i] << shift_amount\n },\n VV_VSRL => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n vs2_val[i] >> shift_amount\n },\n VV_VSRA => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW)\n },\n VV_VSSRL => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr)\n },\n VV_VSSRA => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr)\n },\n VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))),\n VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))),\n VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))),\n VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))),\n VV_VRGATHER => {\n if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n let idx = unsigned(vs1_val[i]);\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX <= 'n);\n if idx < VLMAX then vs2_val[idx] else zeros()\n },\n VV_VRGATHEREI16 => {\n if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */\n let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1);\n let idx = unsigned(vs1_new[i]);\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX <= 'n);\n if idx < VLMAX then vs2_val[idx] else zeros()\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 244, "source": "function clause execute(NVSTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n NVS_VNSRL => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW_widen);\n slice(vs2_val[i] >> shift_amount, 0, SEW)\n },\n NVS_VNSRA => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW_widen);\n let v_double : bits('o * 2) = sign_extend(vs2_val[i]);\n let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen);\n slice(arith_shifted, 0, SEW)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "NVSTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n NVS_VNSRL => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW_widen);\n slice(vs2_val[i] >> shift_amount, 0, SEW)\n },\n NVS_VNSRA => {\n let shift_amount = get_shift_amount(vs1_val[i], SEW_widen);\n let v_double : bits('o * 2) = sign_extend(vs2_val[i]);\n let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen);\n slice(arith_shifted, 0, SEW)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 245, "source": "function clause execute(NVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let shift_amount = get_shift_amount(vs1_val[i], SEW_widen);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n result[i] = match funct6 {\n NV_VNCLIPU => {\n let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr);\n unsigned_saturation('m, result_wide);\n },\n NV_VNCLIP => {\n let v_double : bits('m * 4) = sign_extend(vs2_val[i]);\n let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr);\n signed_saturation('m, result_wide);\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "NVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let shift_amount = get_shift_amount(vs1_val[i], SEW_widen);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n result[i] = match funct6 {\n NV_VNCLIPU => {\n let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr);\n unsigned_saturation('m, result_wide);\n },\n NV_VNCLIP => {\n let v_double : bits('m * 4) = sign_extend(vs2_val[i]);\n let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr);\n signed_saturation('m, result_wide);\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 246, "source": "function clause execute(MASKTYPEV(vs2, vs1, vd)) = {\n let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n result[i] = vd_val[i]\n } else if i > end_element | i >= real_num_elem then {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n } else {\n /* the merge operates on all body elements */\n result[i] = if vm_val[i] then vs1_val[i] else vs2_val[i]\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MASKTYPEV", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n result[i] = vd_val[i]\n } else if i > end_element | i >= real_num_elem then {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n } else {\n /* the merge operates on all body elements */\n result[i] = if vm_val[i] then vs1_val[i] else vs2_val[i]\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 247, "source": "function clause execute(MOVETYPEV(vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = vs1_val[i]\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MOVETYPEV", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = vs1_val[i]\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 248, "source": "function clause execute(VXTYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VX_VADD => vs2_val[i] + rs1_val,\n VX_VSUB => vs2_val[i] - rs1_val,\n VX_VRSUB => rs1_val - vs2_val[i],\n VX_VAND => vs2_val[i] & rs1_val,\n VX_VOR => vs2_val[i] | rs1_val,\n VX_VXOR => vs2_val[i] ^ rs1_val,\n VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ),\n VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ),\n VX_VSSUBU => {\n if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros()\n else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) )\n },\n VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ),\n VX_VSMUL => {\n let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val));\n let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1);\n let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr);\n signed_saturation('m, result_wide['m..0])\n },\n VX_VSLL => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n vs2_val[i] << shift_amount\n },\n VX_VSRL => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n vs2_val[i] >> shift_amount\n },\n VX_VSRA => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW)\n },\n VX_VSSRL => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr)\n },\n VX_VSSRA => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr)\n },\n VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))),\n VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))),\n VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))),\n VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val)))\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VXTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VX_VADD => vs2_val[i] + rs1_val,\n VX_VSUB => vs2_val[i] - rs1_val,\n VX_VRSUB => rs1_val - vs2_val[i],\n VX_VAND => vs2_val[i] & rs1_val,\n VX_VOR => vs2_val[i] | rs1_val,\n VX_VXOR => vs2_val[i] ^ rs1_val,\n VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ),\n VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ),\n VX_VSSUBU => {\n if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros()\n else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) )\n },\n VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ),\n VX_VSMUL => {\n let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val));\n let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1);\n let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr);\n signed_saturation('m, result_wide['m..0])\n },\n VX_VSLL => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n vs2_val[i] << shift_amount\n },\n VX_VSRL => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n vs2_val[i] >> shift_amount\n },\n VX_VSRA => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW)\n },\n VX_VSSRL => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr)\n },\n VX_VSSRA => {\n let shift_amount = get_shift_amount(rs1_val, SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr)\n },\n VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))),\n VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))),\n VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))),\n VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val)))\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 249, "source": "function clause execute(NXSTYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n NXS_VNSRL => {\n let shift_amount = get_shift_amount(rs1_val, SEW_widen);\n slice(vs2_val[i] >> shift_amount, 0, SEW)\n },\n NXS_VNSRA => {\n let shift_amount = get_shift_amount(rs1_val, SEW_widen);\n let v_double : bits('o * 2) = sign_extend(vs2_val[i]);\n let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen);\n slice(arith_shifted, 0, SEW)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "NXSTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n NXS_VNSRL => {\n let shift_amount = get_shift_amount(rs1_val, SEW_widen);\n slice(vs2_val[i] >> shift_amount, 0, SEW)\n },\n NXS_VNSRA => {\n let shift_amount = get_shift_amount(rs1_val, SEW_widen);\n let v_double : bits('o * 2) = sign_extend(vs2_val[i]);\n let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen);\n slice(arith_shifted, 0, SEW)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 250, "source": "function clause execute(NXTYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let shift_amount = get_shift_amount(rs1_val, SEW_widen);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n result[i] = match funct6 {\n NX_VNCLIPU => {\n let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr);\n unsigned_saturation('m, result_wide)\n },\n NX_VNCLIP => {\n let v_double : bits('m * 4) = sign_extend(vs2_val[i]);\n let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr);\n signed_saturation('m, result_wide)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "NXTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let shift_amount = get_shift_amount(rs1_val, SEW_widen);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n result[i] = match funct6 {\n NX_VNCLIPU => {\n let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr);\n unsigned_saturation('m, result_wide)\n },\n NX_VNCLIP => {\n let v_double : bits('m * 4) = sign_extend(vs2_val[i]);\n let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr);\n signed_saturation('m, result_wide)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 251, "source": "function clause execute(VXSG(funct6, vm, vs2, rs1, vd)) = {\n let SEW_pow = get_sew_pow();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let VLEN_pow = get_vlen_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : nat = unsigned(X(rs1));\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VX_VSLIDEUP => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n if i >= rs1_val then vs2_val[i - rs1_val] else vd_val[i]\n },\n VX_VSLIDEDOWN => {\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX > 0 & VLMAX <= 'n);\n if i + rs1_val < VLMAX then vs2_val[i + rs1_val] else zeros()\n },\n VX_VRGATHER => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX > 0 & VLMAX <= 'n);\n if rs1_val < VLMAX then vs2_val[rs1_val] else zeros()\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VXSG", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW_pow = get_sew_pow();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let VLEN_pow = get_vlen_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : nat = unsigned(X(rs1));\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VX_VSLIDEUP => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n if i >= rs1_val then vs2_val[i - rs1_val] else vd_val[i]\n },\n VX_VSLIDEDOWN => {\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX > 0 & VLMAX <= 'n);\n if i + rs1_val < VLMAX then vs2_val[i + rs1_val] else zeros()\n },\n VX_VRGATHER => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX > 0 & VLMAX <= 'n);\n if rs1_val < VLMAX then vs2_val[rs1_val] else zeros()\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 252, "source": "function clause execute(MASKTYPEX(vs2, rs1, vd)) = {\n let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n result[i] = vd_val[i]\n } else if i > end_element | i >= real_num_elem then {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n } else {\n /* the merge operates on all body elements */\n result[i] = if vm_val[i] then rs1_val else vs2_val[i]\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MASKTYPEX", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n result[i] = vd_val[i]\n } else if i > end_element | i >= real_num_elem then {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n } else {\n /* the merge operates on all body elements */\n result[i] = if vm_val[i] then rs1_val else vs2_val[i]\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 253, "source": "function clause execute(MOVETYPEX(rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let rs1_val : bits('m) = get_scalar(rs1, 'm);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = rs1_val\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MOVETYPEX", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let rs1_val : bits('m) = get_scalar(rs1, 'm);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = rs1_val\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 254, "source": "function clause execute(VITYPE(funct6, vm, vs2, simm, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VI_VADD => vs2_val[i] + imm_val,\n VI_VRSUB => imm_val - vs2_val[i],\n VI_VAND => vs2_val[i] & imm_val,\n VI_VOR => vs2_val[i] | imm_val,\n VI_VXOR => vs2_val[i] ^ imm_val,\n VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ),\n VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ),\n VI_VSLL => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n vs2_val[i] << shift_amount\n },\n VI_VSRL => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n vs2_val[i] >> shift_amount\n },\n VI_VSRA => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW)\n },\n VI_VSSRL => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr)\n },\n VI_VSSRA => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VITYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VI_VADD => vs2_val[i] + imm_val,\n VI_VRSUB => imm_val - vs2_val[i],\n VI_VAND => vs2_val[i] & imm_val,\n VI_VOR => vs2_val[i] | imm_val,\n VI_VXOR => vs2_val[i] ^ imm_val,\n VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ),\n VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ),\n VI_VSLL => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n vs2_val[i] << shift_amount\n },\n VI_VSRL => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n vs2_val[i] >> shift_amount\n },\n VI_VSRA => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW)\n },\n VI_VSSRL => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr)\n },\n VI_VSSRA => {\n let shift_amount = get_shift_amount(zero_extend('m, simm), SEW);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n let v_double : bits('m * 2) = sign_extend(vs2_val[i]);\n slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 255, "source": "function clause execute(NISTYPE(funct6, vm, vs2, simm, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n NIS_VNSRL => {\n let shift_amount = get_shift_amount(imm_val, SEW_widen);\n slice(vs2_val[i] >> shift_amount, 0, SEW)\n },\n NIS_VNSRA => {\n let shift_amount = get_shift_amount(imm_val, SEW_widen);\n let v_double : bits('o * 2) = sign_extend(vs2_val[i]);\n let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen);\n slice(arith_shifted, 0, SEW)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "NISTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n NIS_VNSRL => {\n let shift_amount = get_shift_amount(imm_val, SEW_widen);\n slice(vs2_val[i] >> shift_amount, 0, SEW)\n },\n NIS_VNSRA => {\n let shift_amount = get_shift_amount(imm_val, SEW_widen);\n let v_double : bits('o * 2) = sign_extend(vs2_val[i]);\n let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen);\n slice(arith_shifted, 0, SEW)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 256, "source": "function clause execute(NITYPE(funct6, vm, vs2, simm, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let shift_amount = get_shift_amount(imm_val, SEW_widen);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n result[i] = match funct6 {\n NI_VNCLIPU => {\n let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr);\n unsigned_saturation('m, result_wide)\n },\n NI_VNCLIP => {\n let v_double : bits('m * 4) = sign_extend(vs2_val[i]);\n let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr);\n signed_saturation('m, result_wide)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "NITYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW_widen <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let shift_amount = get_shift_amount(imm_val, SEW_widen);\n let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount);\n result[i] = match funct6 {\n NI_VNCLIPU => {\n let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr);\n unsigned_saturation('m, result_wide)\n },\n NI_VNCLIP => {\n let v_double : bits('m * 4) = sign_extend(vs2_val[i]);\n let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr);\n signed_saturation('m, result_wide)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 257, "source": "function clause execute(VISG(funct6, vm, vs2, simm, vd)) = {\n let SEW_pow = get_sew_pow();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let VLEN_pow = get_vlen_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm));\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VI_VSLIDEUP => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n if i >= imm_val then vs2_val[i - imm_val] else vd_val[i]\n },\n VI_VSLIDEDOWN => {\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX > 0 & VLMAX <= 'n);\n if i + imm_val < VLMAX then vs2_val[i + imm_val] else zeros()\n },\n VI_VRGATHER => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX > 0 & VLMAX <= 'n);\n if imm_val < VLMAX then vs2_val[imm_val] else zeros()\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VISG", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW_pow = get_sew_pow();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let VLEN_pow = get_vlen_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm));\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VI_VSLIDEUP => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n if i >= imm_val then vs2_val[i - imm_val] else vd_val[i]\n },\n VI_VSLIDEDOWN => {\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX > 0 & VLMAX <= 'n);\n if i + imm_val < VLMAX then vs2_val[i + imm_val] else zeros()\n },\n VI_VRGATHER => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow);\n assert(VLMAX > 0 & VLMAX <= 'n);\n if imm_val < VLMAX then vs2_val[imm_val] else zeros()\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 258, "source": "function clause execute(MASKTYPEI(vs2, simm, vd)) = {\n let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n result[i] = vd_val[i]\n } else if i > end_element | i >= real_num_elem then {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n } else {\n /* the merge operates on all body elements */\n result[i] = if vm_val[i] then imm_val else vs2_val[i]\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MASKTYPEI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n result[i] = vd_val[i]\n } else if i > end_element | i >= real_num_elem then {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n } else {\n /* the merge operates on all body elements */\n result[i] = if vm_val[i] then imm_val else vs2_val[i]\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 259, "source": "function clause execute(MOVETYPEI(vd, simm)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = imm_val\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MOVETYPEI", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "simm" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = imm_val\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 260, "source": "function clause execute(VMVRTYPE(vs2, simm, vd)) = {\n let start_element = get_start_element();\n let SEW = get_sew();\n let imm_val = unsigned(zero_extend(sizeof(xlen), simm));\n let EMUL = imm_val + 1;\n\n if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL };\n\n let EMUL_pow = log2(EMUL);\n let num_elem = get_num_elem(EMUL_pow, SEW);\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n foreach (i from 0 to (num_elem - 1)) {\n result[i] = if i < start_element then vd_val[i] else vs2_val[i]\n };\n\n write_vreg(num_elem, SEW, EMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VMVRTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let start_element = get_start_element();\n let SEW = get_sew();\n let imm_val = unsigned(zero_extend(sizeof(xlen), simm));\n let EMUL = imm_val + 1;\n\n if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL };\n\n let EMUL_pow = log2(EMUL);\n let num_elem = get_num_elem(EMUL_pow, SEW);\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n foreach (i from 0 to (num_elem - 1)) {\n result[i] = if i < start_element then vd_val[i] else vs2_val[i]\n };\n\n write_vreg(num_elem, SEW, EMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 261, "source": "function clause execute(MVVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MVV_VAADDU => {\n let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]);\n let rounding_incr = get_fixed_rounding_incr(result_add, 1);\n slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVV_VAADD => {\n let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]);\n let rounding_incr = get_fixed_rounding_incr(result_add, 1);\n slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVV_VASUBU => {\n let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]);\n let rounding_incr = get_fixed_rounding_incr(result_sub, 1);\n slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVV_VASUB => {\n let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]);\n let rounding_incr = get_fixed_rounding_incr(result_sub, 1);\n slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0),\n MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW),\n MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW),\n MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW),\n MVV_VDIVU => {\n let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i]));\n to_bits(SEW, q)\n },\n MVV_VDIV => {\n let elem_max : int = 2 ^ (SEW - 1) - 1;\n let elem_min : int = 0 - 2 ^ (SEW - 1);\n let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i]));\n /* check for signed overflow */\n let q' : int = if q > elem_max then elem_min else q;\n to_bits(SEW, q')\n },\n MVV_VREMU => {\n let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i]));\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n to_bits(SEW, r)\n },\n MVV_VREM => {\n let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i]));\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n to_bits(SEW, r)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MVVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MVV_VAADDU => {\n let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]);\n let rounding_incr = get_fixed_rounding_incr(result_add, 1);\n slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVV_VAADD => {\n let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]);\n let rounding_incr = get_fixed_rounding_incr(result_add, 1);\n slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVV_VASUBU => {\n let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]);\n let rounding_incr = get_fixed_rounding_incr(result_sub, 1);\n slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVV_VASUB => {\n let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]);\n let rounding_incr = get_fixed_rounding_incr(result_sub, 1);\n slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0),\n MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW),\n MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW),\n MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW),\n MVV_VDIVU => {\n let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i]));\n to_bits(SEW, q)\n },\n MVV_VDIV => {\n let elem_max : int = 2 ^ (SEW - 1) - 1;\n let elem_min : int = 0 - 2 ^ (SEW - 1);\n let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i]));\n /* check for signed overflow */\n let q' : int = if q > elem_max then elem_min else q;\n to_bits(SEW, q')\n },\n MVV_VREMU => {\n let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i]));\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n to_bits(SEW, r)\n },\n MVV_VREM => {\n let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i]));\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n to_bits(SEW, r)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 262, "source": "function clause execute(MVVMATYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MVV_VMACC => get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0) + vd_val[i],\n MVV_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0),\n MVV_VMADD => get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + vs2_val[i],\n MVV_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0)\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MVVMATYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MVV_VMACC => get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0) + vd_val[i],\n MVV_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0),\n MVV_VMADD => get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + vs2_val[i],\n MVV_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0)\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 263, "source": "function clause execute(WVVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])),\n WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])),\n WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])),\n WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])),\n WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])),\n WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])),\n WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i]))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "WVVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])),\n WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])),\n WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])),\n WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])),\n WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])),\n WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])),\n WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i]))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 264, "source": "function clause execute(WVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])),\n WV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])),\n WV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])),\n WV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i]))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "WVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])),\n WV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])),\n WV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])),\n WV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i]))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 265, "source": "function clause execute(WMVVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WMVV_VWMACC => to_bits(SEW_widen, signed(vs1_val[i]) * signed(vs2_val[i])) + vd_val[i],\n WMVV_VWMACCU => to_bits(SEW_widen, unsigned(vs1_val[i]) * unsigned(vs2_val[i])) + vd_val[i],\n WMVV_VWMACCSU => to_bits(SEW_widen, signed(vs1_val[i]) * unsigned(vs2_val[i]))+ vd_val[i]\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "WMVVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WMVV_VWMACC => to_bits(SEW_widen, signed(vs1_val[i]) * signed(vs2_val[i])) + vd_val[i],\n WMVV_VWMACCU => to_bits(SEW_widen, unsigned(vs1_val[i]) * unsigned(vs2_val[i])) + vd_val[i],\n WMVV_VWMACCSU => to_bits(SEW_widen, signed(vs1_val[i]) * unsigned(vs2_val[i]))+ vd_val[i]\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 266, "source": "function clause execute(VEXT2TYPE(funct6, vm, vs2, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_half = SEW / 2;\n let LMUL_pow_half = LMUL_pow - 1;\n\n if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_half;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_half, LMUL_pow_half, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW > SEW_half);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VEXT2_ZVF2 => zero_extend(vs2_val[i]),\n VEXT2_SVF2 => sign_extend(vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VEXT2TYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_half = SEW / 2;\n let LMUL_pow_half = LMUL_pow - 1;\n\n if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_half;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_half, LMUL_pow_half, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW > SEW_half);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VEXT2_ZVF2 => zero_extend(vs2_val[i]),\n VEXT2_SVF2 => sign_extend(vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 267, "source": "function clause execute(VEXT4TYPE(funct6, vm, vs2, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_quart = SEW / 4;\n let LMUL_pow_quart = LMUL_pow - 2;\n\n if illegal_variable_width(vd, vm, SEW_quart, LMUL_pow_quart) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_quart, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_quart;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_quart, LMUL_pow_quart, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW > SEW_quart);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VEXT4_ZVF4 => zero_extend(vs2_val[i]),\n VEXT4_SVF4 => sign_extend(vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VEXT4TYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_quart = SEW / 4;\n let LMUL_pow_quart = LMUL_pow - 2;\n\n if illegal_variable_width(vd, vm, SEW_quart, LMUL_pow_quart) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_quart, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_quart;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_quart, LMUL_pow_quart, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW > SEW_quart);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VEXT4_ZVF4 => zero_extend(vs2_val[i]),\n VEXT4_SVF4 => sign_extend(vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 268, "source": "function clause execute(VEXT8TYPE(funct6, vm, vs2, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_eighth = SEW / 8;\n let LMUL_pow_eighth = LMUL_pow - 3;\n\n if illegal_variable_width(vd, vm, SEW_eighth, LMUL_pow_eighth) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_eighth, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_eighth;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_eighth, LMUL_pow_eighth, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW > SEW_eighth);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VEXT8_ZVF8 => zero_extend(vs2_val[i]),\n VEXT8_SVF8 => sign_extend(vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VEXT8TYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_eighth = SEW / 8;\n let LMUL_pow_eighth = LMUL_pow - 3;\n\n if illegal_variable_width(vd, vm, SEW_eighth, LMUL_pow_eighth) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_eighth, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_eighth;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_eighth, LMUL_pow_eighth, vs2);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n assert(SEW > SEW_eighth);\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VEXT8_ZVF8 => zero_extend(vs2_val[i]),\n VEXT8_SVF8 => sign_extend(vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 269, "source": "function clause execute(VMVXS(vs2, rd)) = {\n let SEW = get_sew();\n let num_elem = get_num_elem(0, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n assert(num_elem > 0);\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2);\n X(rd) = if sizeof(xlen) < SEW then slice(vs2_val[0], 0, sizeof(xlen))\n else if sizeof(xlen) > SEW then sign_extend(vs2_val[0])\n else vs2_val[0];\n vstart = zeros();\n\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VMVXS", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let SEW = get_sew();\n let num_elem = get_num_elem(0, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n assert(num_elem > 0);\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2);\n X(rd) = if sizeof(xlen) < SEW then slice(vs2_val[0], 0, sizeof(xlen))\n else if sizeof(xlen) > SEW then sign_extend(vs2_val[0])\n else vs2_val[0];\n vstart = zeros();\n\n RETIRE_SUCCESS" }, { "number": 270, "source": "function clause execute(MVVCOMPRESS(vs2, vs1, vd)) = {\n let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n /* vcompress should always be executed with a vstart of 0 */\n if start_element != 0 | vs1 == vd | vs2 == vd | illegal_vd_unmasked()\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n /* body elements */\n vd_idx : nat = 0;\n foreach (i from 0 to (num_elem - 1)) {\n if i <= end_element then {\n if vs1_val[i] then {\n let 'p = vd_idx;\n assert('p < 'n);\n result['p] = vs2_val[i];\n vd_idx = vd_idx + 1;\n }\n }\n };\n /* tail elements */\n if vd_idx < num_elem then {\n let tail_ag : agtype = get_vtype_vta();\n let 'p = vd_idx;\n foreach (i from 'p to (num_elem - 1)) {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MVVCOMPRESS", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n /* vcompress should always be executed with a vstart of 0 */\n if start_element != 0 | vs1 == vd | vs2 == vd | illegal_vd_unmasked()\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n /* body elements */\n vd_idx : nat = 0;\n foreach (i from 0 to (num_elem - 1)) {\n if i <= end_element then {\n if vs1_val[i] then {\n let 'p = vd_idx;\n assert('p < 'n);\n result['p] = vs2_val[i];\n vd_idx = vd_idx + 1;\n }\n }\n };\n /* tail elements */\n if vd_idx < num_elem then {\n let tail_ag : agtype = get_vtype_vta();\n let 'p = vd_idx;\n foreach (i from 'p to (num_elem - 1)) {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 271, "source": "function clause execute(MVXTYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MVX_VAADDU => {\n let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val);\n let rounding_incr = get_fixed_rounding_incr(result_add, 1);\n slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVX_VAADD => {\n let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val);\n let rounding_incr = get_fixed_rounding_incr(result_add, 1);\n slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVX_VASUBU => {\n let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val);\n let rounding_incr = get_fixed_rounding_incr(result_sub, 1);\n slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVX_VASUB => {\n let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val);\n let rounding_incr = get_fixed_rounding_incr(result_sub, 1);\n slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVX_VSLIDE1UP => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n if i == 0 then rs1_val else vs2_val[i - 1]\n },\n MVX_VSLIDE1DOWN => {\n let last_elem = get_end_element();\n assert(last_elem < num_elem);\n if i < last_elem then vs2_val[i + 1] else rs1_val\n },\n MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0),\n MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW),\n MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW),\n MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW),\n MVX_VDIVU => {\n let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val));\n to_bits(SEW, q)\n },\n MVX_VDIV => {\n let elem_max : int = 2 ^ (SEW - 1) - 1;\n let elem_min : int = 0 - 2 ^ (SEW - 1);\n let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val));\n /* check for signed overflow */\n let q' : int = if q > elem_max then elem_min else q;\n to_bits(SEW, q')\n },\n MVX_VREMU => {\n let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val));\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n to_bits(SEW, r)\n },\n MVX_VREM => {\n let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val));\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n to_bits(SEW, r)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MVXTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MVX_VAADDU => {\n let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val);\n let rounding_incr = get_fixed_rounding_incr(result_add, 1);\n slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVX_VAADD => {\n let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val);\n let rounding_incr = get_fixed_rounding_incr(result_add, 1);\n slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVX_VASUBU => {\n let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val);\n let rounding_incr = get_fixed_rounding_incr(result_sub, 1);\n slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVX_VASUB => {\n let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val);\n let rounding_incr = get_fixed_rounding_incr(result_sub, 1);\n slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)\n },\n MVX_VSLIDE1UP => {\n if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL };\n if i == 0 then rs1_val else vs2_val[i - 1]\n },\n MVX_VSLIDE1DOWN => {\n let last_elem = get_end_element();\n assert(last_elem < num_elem);\n if i < last_elem then vs2_val[i + 1] else rs1_val\n },\n MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0),\n MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW),\n MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW),\n MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW),\n MVX_VDIVU => {\n let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val));\n to_bits(SEW, q)\n },\n MVX_VDIV => {\n let elem_max : int = 2 ^ (SEW - 1) - 1;\n let elem_min : int = 0 - 2 ^ (SEW - 1);\n let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val));\n /* check for signed overflow */\n let q' : int = if q > elem_max then elem_min else q;\n to_bits(SEW, q')\n },\n MVX_VREMU => {\n let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val));\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n to_bits(SEW, r)\n },\n MVX_VREM => {\n let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val));\n /* signed overflow case returns zero naturally as required due to -1 divisor */\n to_bits(SEW, r)\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 272, "source": "function clause execute(MVXMATYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MVX_VMACC => get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0) + vd_val[i],\n MVX_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0),\n MVX_VMADD => get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + vs2_val[i],\n MVX_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0)\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MVXMATYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MVX_VMACC => get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0) + vd_val[i],\n MVX_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0),\n MVX_VMADD => get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + vs2_val[i],\n MVX_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0)\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 273, "source": "function clause execute(WVXTYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)),\n WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)),\n WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)),\n WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)),\n WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)),\n WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)),\n WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "WVXTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)),\n WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)),\n WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)),\n WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)),\n WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)),\n WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)),\n WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 274, "source": "function clause execute(WXTYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)),\n WX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)),\n WX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)),\n WX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "WXTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen)\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)),\n WX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)),\n WX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)),\n WX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 275, "source": "function clause execute(WMVXTYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WMVX_VWMACCU => (to_bits(SEW_widen, unsigned(rs1_val) * unsigned(vs2_val[i]) )) + vd_val[i],\n WMVX_VWMACC => (to_bits(SEW_widen, signed(rs1_val) * signed(vs2_val[i]) )) + vd_val[i],\n WMVX_VWMACCUS => (to_bits(SEW_widen, unsigned(rs1_val) * signed(vs2_val[i]) ))+ vd_val[i],\n WMVX_VWMACCSU => (to_bits(SEW_widen, signed(rs1_val) * unsigned(vs2_val[i]) ))+ vd_val[i]\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "WMVXTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n WMVX_VWMACCU => (to_bits(SEW_widen, unsigned(rs1_val) * unsigned(vs2_val[i]) )) + vd_val[i],\n WMVX_VWMACC => (to_bits(SEW_widen, signed(rs1_val) * signed(vs2_val[i]) )) + vd_val[i],\n WMVX_VWMACCUS => (to_bits(SEW_widen, unsigned(rs1_val) * signed(vs2_val[i]) ))+ vd_val[i],\n WMVX_VWMACCSU => (to_bits(SEW_widen, signed(rs1_val) * unsigned(vs2_val[i]) ))+ vd_val[i]\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 276, "source": "function clause execute(VMVSX(rs1, vd)) = {\n let SEW = get_sew();\n let num_elem = get_num_elem(0, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n assert(num_elem > 0);\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, 'm);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val);\n\n /* one body element */\n if mask[0] then result[0] = rs1_val;\n\n /* others treated as tail elements */\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 1 to (num_elem - 1)) {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n };\n\n write_vreg(num_elem, SEW, 0, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VMVSX", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let num_elem = get_num_elem(0, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n assert(num_elem > 0);\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, 'm);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val);\n\n /* one body element */\n if mask[0] then result[0] = rs1_val;\n\n /* others treated as tail elements */\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 1 to (num_elem - 1)) {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n };\n\n write_vreg(num_elem, SEW, 0, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 277, "source": "function clause execute(FVVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]),\n FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]),\n FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]),\n FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]),\n FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]),\n FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]),\n FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0],\n FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0],\n FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0]\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FVVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]),\n FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]),\n FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]),\n FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]),\n FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]),\n FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]),\n FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0],\n FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0],\n FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0]\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 278, "source": "function clause execute(FVVMATYPE(funct6, vm, vs2, vs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]),\n FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]),\n FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]),\n FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]),\n FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]),\n FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]),\n FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]),\n FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FVVMATYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]),\n FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]),\n FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]),\n FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]),\n FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]),\n FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]),\n FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]),\n FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 279, "source": "function clause execute(FWVVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWVV_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])),\n FWVV_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])),\n FWVV_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i]))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FWVVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWVV_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])),\n FWVV_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])),\n FWVV_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i]))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 280, "source": "function clause execute(FWVVMATYPE(funct6, vm, vs1, vs2, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWVV_VMACC => fp_muladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]),\n FWVV_VNMACC => fp_nmulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]),\n FWVV_VMSAC => fp_mulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]),\n FWVV_VNMSAC => fp_nmuladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FWVVMATYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWVV_VMACC => fp_muladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]),\n FWVV_VNMACC => fp_nmulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]),\n FWVV_VMSAC => fp_mulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]),\n FWVV_VNMSAC => fp_nmuladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 281, "source": "function clause execute(FWVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWV_VADD => fp_add(rm_3b, vs2_val[i], fp_widen(vs1_val[i])),\n FWV_VSUB => fp_sub(rm_3b, vs2_val[i], fp_widen(vs1_val[i]))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FWVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWV_VADD => fp_add(rm_3b, vs2_val[i], fp_widen(vs1_val[i])),\n FWV_VSUB => fp_sub(rm_3b, vs2_val[i], fp_widen(vs1_val[i]))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 282, "source": "function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match vfunary0 {\n FV_CVT_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16ToUi16(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]),\n 64 => riscv_f64ToUi64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_X_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16ToI16(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToI32(rm_3b, vs2_val[i]),\n 64 => riscv_f64ToI64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_F_XU => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])),\n 32 => riscv_ui32ToF32(rm_3b, vs2_val[i]),\n 64 => riscv_ui64ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_F_X => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])),\n 32 => riscv_i32ToF32(rm_3b, vs2_val[i]),\n 64 => riscv_i64ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_RTZ_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16ToUi16(0b001, vs2_val[i]),\n 32 => riscv_f32ToUi32(0b001, vs2_val[i]),\n 64 => riscv_f64ToUi64(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_RTZ_X_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16ToI16(0b001, vs2_val[i]),\n 32 => riscv_f32ToI32(0b001, vs2_val[i]),\n 64 => riscv_f64ToI64(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFUNARY0", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfunary0" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match vfunary0 {\n FV_CVT_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16ToUi16(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]),\n 64 => riscv_f64ToUi64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_X_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16ToI16(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToI32(rm_3b, vs2_val[i]),\n 64 => riscv_f64ToI64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_F_XU => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])),\n 32 => riscv_ui32ToF32(rm_3b, vs2_val[i]),\n 64 => riscv_ui64ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_F_X => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])),\n 32 => riscv_i32ToF32(rm_3b, vs2_val[i]),\n 64 => riscv_i64ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_RTZ_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16ToUi16(0b001, vs2_val[i]),\n 32 => riscv_f32ToUi32(0b001, vs2_val[i]),\n 64 => riscv_f64ToUi64(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FV_CVT_RTZ_X_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16ToI16(0b001, vs2_val[i]),\n 32 => riscv_f32ToI32(0b001, vs2_val[i]),\n 64 => riscv_f64ToI64(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 283, "source": "function clause execute(VFWUNARY0(vm, vs2, vfwunary0, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 8 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match vfwunary0 {\n FWV_CVT_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToUi64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_X_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToI32(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToI64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_F_XU => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])),\n 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])),\n 32 => riscv_ui32ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_F_X => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])),\n 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])),\n 32 => riscv_i32ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_F_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToF32(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_RTZ_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToUi32(0b001, vs2_val[i]),\n 32 => riscv_f32ToUi64(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_RTZ_X_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToI32(0b001, vs2_val[i]),\n 32 => riscv_f32ToI64(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFWUNARY0", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfwunary0" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 8 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match vfwunary0 {\n FWV_CVT_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToUi64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_X_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToI32(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToI64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_F_XU => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])),\n 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])),\n 32 => riscv_ui32ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_F_X => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])),\n 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])),\n 32 => riscv_i32ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_F_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToF32(rm_3b, vs2_val[i]),\n 32 => riscv_f32ToF64(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_RTZ_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToUi32(0b001, vs2_val[i]),\n 32 => riscv_f32ToUi64(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FWV_CVT_RTZ_X_F => {\n let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f16ToI32(0b001, vs2_val[i]),\n 32 => riscv_f32ToI64(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 284, "source": "function clause execute(VFNUNARY0(vm, vs2, vfnunary0, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match vfnunary0 {\n FNV_CVT_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]),\n 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]),\n 32 => riscv_f64ToUi32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_X_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => riscv_f16ToI8(rm_3b, vs2_val[i]),\n 16 => riscv_f32ToI16(rm_3b, vs2_val[i]),\n 32 => riscv_f64ToI32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_F_XU => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]),\n 32 => riscv_ui64ToF32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_F_X => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_i32ToF16(rm_3b, vs2_val[i]),\n 32 => riscv_i64ToF32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_F_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f32ToF16(rm_3b, vs2_val[i]),\n 32 => riscv_f64ToF32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_ROD_F_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f32ToF16(0b110, vs2_val[i]),\n 32 => riscv_f64ToF32(0b110, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_RTZ_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => riscv_f16ToUi8(0b001, vs2_val[i]),\n 16 => riscv_f32ToUi16(0b001, vs2_val[i]),\n 32 => riscv_f64ToUi32(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_RTZ_X_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => riscv_f16ToI8(0b001, vs2_val[i]),\n 16 => riscv_f32ToI16(0b001, vs2_val[i]),\n 32 => riscv_f64ToI32(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFNUNARY0", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfnunary0" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match vfnunary0 {\n FNV_CVT_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]),\n 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]),\n 32 => riscv_f64ToUi32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_X_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => riscv_f16ToI8(rm_3b, vs2_val[i]),\n 16 => riscv_f32ToI16(rm_3b, vs2_val[i]),\n 32 => riscv_f64ToI32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_F_XU => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]),\n 32 => riscv_ui64ToF32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_F_X => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_i32ToF16(rm_3b, vs2_val[i]),\n 32 => riscv_i64ToF32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_F_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f32ToF16(rm_3b, vs2_val[i]),\n 32 => riscv_f64ToF32(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_ROD_F_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => { handle_illegal(); return RETIRE_FAIL },\n 16 => riscv_f32ToF16(0b110, vs2_val[i]),\n 32 => riscv_f64ToF32(0b110, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_RTZ_XU_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => riscv_f16ToUi8(0b001, vs2_val[i]),\n 16 => riscv_f32ToUi16(0b001, vs2_val[i]),\n 32 => riscv_f64ToUi32(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FNV_CVT_RTZ_X_F => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 8 => riscv_f16ToI8(0b001, vs2_val[i]),\n 16 => riscv_f32ToI16(0b001, vs2_val[i]),\n 32 => riscv_f64ToI32(0b001, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 285, "source": "function clause execute(VFUNARY1(vm, vs2, vfunary1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match vfunary1 {\n FVV_VSQRT => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Sqrt(rm_3b, vs2_val[i]),\n 32 => riscv_f32Sqrt(rm_3b, vs2_val[i]),\n 64 => riscv_f64Sqrt(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FVV_VRSQRT7 => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Rsqrte7(rm_3b, vs2_val[i]),\n 32 => riscv_f32Rsqrte7(rm_3b, vs2_val[i]),\n 64 => riscv_f64Rsqrte7(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FVV_VREC7 => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Recip7(rm_3b, vs2_val[i]),\n 32 => riscv_f32Recip7(rm_3b, vs2_val[i]),\n 64 => riscv_f64Recip7(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FVV_VCLASS => fp_class(vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFUNARY1", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfunary1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match vfunary1 {\n FVV_VSQRT => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Sqrt(rm_3b, vs2_val[i]),\n 32 => riscv_f32Sqrt(rm_3b, vs2_val[i]),\n 64 => riscv_f64Sqrt(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FVV_VRSQRT7 => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Rsqrte7(rm_3b, vs2_val[i]),\n 32 => riscv_f32Rsqrte7(rm_3b, vs2_val[i]),\n 64 => riscv_f64Rsqrte7(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FVV_VREC7 => {\n let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Recip7(rm_3b, vs2_val[i]),\n 32 => riscv_f32Recip7(rm_3b, vs2_val[i]),\n 64 => riscv_f64Recip7(rm_3b, vs2_val[i])\n };\n accrue_fflags(fflags);\n elem\n },\n FVV_VCLASS => fp_class(vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 286, "source": "function clause execute(VFMVFS(vs2, rd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let num_elem = get_num_elem(0, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) | SEW > sizeof(flen)\n then { handle_illegal(); return RETIRE_FAIL };\n assert(num_elem > 0 & SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2);\n match 'm {\n 16 => F_H(rd) = vs2_val[0],\n 32 => F_S(rd) = vs2_val[0],\n 64 => F_D(rd) = vs2_val[0]\n };\n vstart = zeros();\n\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFMVFS", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let num_elem = get_num_elem(0, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) | SEW > sizeof(flen)\n then { handle_illegal(); return RETIRE_FAIL };\n assert(num_elem > 0 & SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2);\n match 'm {\n 16 => F_H(rd) = vs2_val[0],\n 32 => F_S(rd) = vs2_val[0],\n 64 => F_D(rd) = vs2_val[0]\n };\n vstart = zeros();\n\n RETIRE_SUCCESS" }, { "number": 287, "source": "function clause execute(FVFTYPE(funct6, vm, vs2, rs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val),\n VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val),\n VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]),\n VF_VMIN => fp_min(vs2_val[i], rs1_val),\n VF_VMAX => fp_max(vs2_val[i], rs1_val),\n VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val),\n VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val),\n VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]),\n VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0],\n VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0],\n VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0],\n VF_VSLIDE1UP => {\n if vs2 == vd then { handle_illegal(); return RETIRE_FAIL };\n if i == 0 then rs1_val else vs2_val[i - 1]\n },\n VF_VSLIDE1DOWN => {\n let last_elem = get_end_element();\n assert(last_elem < num_elem);\n if i < last_elem then vs2_val[i + 1] else rs1_val\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FVFTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val),\n VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val),\n VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]),\n VF_VMIN => fp_min(vs2_val[i], rs1_val),\n VF_VMAX => fp_max(vs2_val[i], rs1_val),\n VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val),\n VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val),\n VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]),\n VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0],\n VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0],\n VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0],\n VF_VSLIDE1UP => {\n if vs2 == vd then { handle_illegal(); return RETIRE_FAIL };\n if i == 0 then rs1_val else vs2_val[i - 1]\n },\n VF_VSLIDE1DOWN => {\n let last_elem = get_end_element();\n assert(last_elem < num_elem);\n if i < last_elem then vs2_val[i + 1] else rs1_val\n }\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 288, "source": "function clause execute(FVFMATYPE(funct6, vm, vs2, rs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]),\n VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]),\n VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]),\n VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]),\n VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]),\n VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]),\n VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]),\n VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FVFMATYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]),\n VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]),\n VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]),\n VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]),\n VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]),\n VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]),\n VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]),\n VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 289, "source": "function clause execute(FWVFTYPE(funct6, vm, vs2, rs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWVF_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)),\n FWVF_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)),\n FWVF_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FWVFTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWVF_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)),\n FWVF_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)),\n FWVF_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 290, "source": "function clause execute(FWVFMATYPE(funct6, vm, rs1, vs2, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWVF_VMACC => fp_muladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]),\n FWVF_VNMACC => fp_nmulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]),\n FWVF_VMSAC => fp_mulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]),\n FWVF_VNMSAC => fp_nmuladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FWVFMATYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |\n not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWVF_VMACC => fp_muladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]),\n FWVF_VNMACC => fp_nmulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]),\n FWVF_VMSAC => fp_mulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]),\n FWVF_VNMSAC => fp_nmuladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i])\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 291, "source": "function clause execute(FWFTYPE(funct6, vm, vs2, rs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen)\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWF_VADD => fp_add(rm_3b, vs2_val[i], fp_widen(rs1_val)),\n FWF_VSUB => fp_sub(rm_3b, vs2_val[i], fp_widen(rs1_val))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FWFTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n\n if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen)\n then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n let 'n = num_elem;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);\n result : vector('n, dec, bits('o)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n FWF_VADD => fp_add(rm_3b, vs2_val[i], fp_widen(rs1_val)),\n FWF_VSUB => fp_sub(rm_3b, vs2_val[i], fp_widen(rs1_val))\n }\n }\n };\n\n write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 292, "source": "function clause execute(VFMERGE(vs2, rs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */\n\n if illegal_fp_vd_masked(vd, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n result[i] = vd_val[i]\n } else if i > end_element | i >= real_num_elem then {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n } else {\n /* the merge operates on all body elements */\n result[i] = if vm_val[i] then rs1_val else vs2_val[i]\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFMERGE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let start_element = get_start_element();\n let end_element = get_end_element();\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */\n\n if illegal_fp_vd_masked(vd, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n result[i] = vd_val[i]\n } else if i > end_element | i >= real_num_elem then {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n } else {\n /* the merge operates on all body elements */\n result[i] = if vm_val[i] then rs1_val else vs2_val[i]\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 293, "source": "function clause execute(VFMV(rs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = rs1_val\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFMV", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = rs1_val\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 294, "source": "function clause execute(VFMVSF(rs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let num_elem = get_num_elem(0, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(num_elem > 0 & SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val);\n\n /* one body element */\n if mask[0] then result[0] = rs1_val;\n\n /* others treated as tail elements */\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 1 to (num_elem - 1)) {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n };\n\n write_vreg(num_elem, SEW, 0, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFMVSF", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let num_elem = get_num_elem(0, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(num_elem > 0 & SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val);\n\n /* one body element */\n if mask[0] then result[0] = rs1_val;\n\n /* others treated as tail elements */\n let tail_ag : agtype = get_vtype_vta();\n foreach (i from 1 to (num_elem - 1)) {\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n }\n };\n\n write_vreg(num_elem, SEW, 0, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 295, "source": "function clause execute(VLSEGTYPE(nf, vm, rs1, width, vd)) = {\n let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */\n let nf_int = nfields_int(nf);\n\n if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)\n}", "pattern": { "type": "app", "id": "VLSEGTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */\n let nf_int = nfields_int(nf);\n\n if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)" }, { "number": 296, "source": "function clause execute(VLSEGFFTYPE(nf, vm, rs1, width, vd)) = {\n let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW);\n let nf_int = nfields_int(nf);\n\n if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)\n}", "pattern": { "type": "app", "id": "VLSEGFFTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW);\n let nf_int = nfields_int(nf);\n\n if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)" }, { "number": 297, "source": "function clause execute(VSSEGTYPE(nf, vm, rs1, width, vs3)) = {\n let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW);\n let nf_int = nfields_int(nf);\n\n if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem)\n}", "pattern": { "type": "app", "id": "VSSEGTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] } ] }, "body": " let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW);\n let nf_int = nfields_int(nf);\n\n if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem)" }, { "number": 298, "source": "function clause execute(VLSSEGTYPE(nf, vm, rs2, rs1, width, vd)) = {\n let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW);\n let nf_int = nfields_int(nf);\n\n if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem)\n}", "pattern": { "type": "app", "id": "VLSSEGTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW);\n let nf_int = nfields_int(nf);\n\n if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem)" }, { "number": 299, "source": "function clause execute(VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3)) = {\n let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW);\n let nf_int = nfields_int(nf);\n\n if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem)\n}", "pattern": { "type": "app", "id": "VSSSEGTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] } ] }, "body": " let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let EEW_pow = vlewidth_pow(width);\n let SEW_pow = get_sew_pow();\n let LMUL_pow = get_lmul_pow();\n let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow;\n let num_elem = get_num_elem(EMUL_pow, EEW);\n let nf_int = nfields_int(nf);\n\n if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem)" }, { "number": 300, "source": "function clause execute(VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd)) = {\n let EEW_index_pow = vlewidth_pow(width);\n let EEW_index_bytes = vlewidth_bytesnumber(width);\n let EEW_data_pow = get_sew_pow();\n let EEW_data_bytes = get_sew_bytes();\n let EMUL_data_pow = get_lmul_pow();\n let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow;\n let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8);\n let nf_int = nfields_int(nf);\n\n if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1)\n}", "pattern": { "type": "app", "id": "VLUXSEGTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let EEW_index_pow = vlewidth_pow(width);\n let EEW_index_bytes = vlewidth_bytesnumber(width);\n let EEW_data_pow = get_sew_pow();\n let EEW_data_bytes = get_sew_bytes();\n let EMUL_data_pow = get_lmul_pow();\n let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow;\n let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8);\n let nf_int = nfields_int(nf);\n\n if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1)" }, { "number": 301, "source": "function clause execute(VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd)) = {\n let EEW_index_pow = vlewidth_pow(width);\n let EEW_index_bytes = vlewidth_bytesnumber(width);\n let EEW_data_pow = get_sew_pow();\n let EEW_data_bytes = get_sew_bytes();\n let EMUL_data_pow = get_lmul_pow();\n let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow;\n let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8);\n let nf_int = nfields_int(nf);\n\n if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3)\n}", "pattern": { "type": "app", "id": "VLOXSEGTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let EEW_index_pow = vlewidth_pow(width);\n let EEW_index_bytes = vlewidth_bytesnumber(width);\n let EEW_data_pow = get_sew_pow();\n let EEW_data_bytes = get_sew_bytes();\n let EMUL_data_pow = get_lmul_pow();\n let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow;\n let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8);\n let nf_int = nfields_int(nf);\n\n if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3)" }, { "number": 302, "source": "function clause execute(VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3)) = {\n let EEW_index_pow = vlewidth_pow(width);\n let EEW_index_bytes = vlewidth_bytesnumber(width);\n let EEW_data_pow = get_sew_pow();\n let EEW_data_bytes = get_sew_bytes();\n let EMUL_data_pow = get_lmul_pow();\n let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow;\n let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */\n let nf_int = nfields_int(nf);\n\n if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1)\n}", "pattern": { "type": "app", "id": "VSUXSEGTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] } ] }, "body": " let EEW_index_pow = vlewidth_pow(width);\n let EEW_index_bytes = vlewidth_bytesnumber(width);\n let EEW_data_pow = get_sew_pow();\n let EEW_data_bytes = get_sew_bytes();\n let EMUL_data_pow = get_lmul_pow();\n let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow;\n let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */\n let nf_int = nfields_int(nf);\n\n if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1)" }, { "number": 303, "source": "function clause execute(VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3)) = {\n let EEW_index_pow = vlewidth_pow(width);\n let EEW_index_bytes = vlewidth_bytesnumber(width);\n let EEW_data_pow = get_sew_pow();\n let EEW_data_bytes = get_sew_bytes();\n let EMUL_data_pow = get_lmul_pow();\n let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow;\n let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */\n let nf_int = nfields_int(nf);\n\n if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3)\n}", "pattern": { "type": "app", "id": "VSOXSEGTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] } ] }, "body": " let EEW_index_pow = vlewidth_pow(width);\n let EEW_index_bytes = vlewidth_bytesnumber(width);\n let EEW_data_pow = get_sew_pow();\n let EEW_data_bytes = get_sew_bytes();\n let EMUL_data_pow = get_lmul_pow();\n let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow;\n let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */\n let nf_int = nfields_int(nf);\n\n if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3)" }, { "number": 304, "source": "function clause execute(VLRETYPE(nf, rs1, width, vd)) = {\n let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let VLEN = unsigned(vlenb) * 8;\n let elem_per_reg : int = VLEN / EEW;\n let nf_int = nfields_int(nf);\n\n assert(elem_per_reg >= 0);\n if not(nf_int == 1 | nf_int == 2 | nf_int == 4 | nf_int == 8) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlre(nf_int, vd, load_width_bytes, rs1, elem_per_reg)\n}", "pattern": { "type": "app", "id": "VLRETYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let load_width_bytes = vlewidth_bytesnumber(width);\n let EEW = load_width_bytes * 8;\n let VLEN = unsigned(vlenb) * 8;\n let elem_per_reg : int = VLEN / EEW;\n let nf_int = nfields_int(nf);\n\n assert(elem_per_reg >= 0);\n if not(nf_int == 1 | nf_int == 2 | nf_int == 4 | nf_int == 8) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vlre(nf_int, vd, load_width_bytes, rs1, elem_per_reg)" }, { "number": 305, "source": "function clause execute(VSRETYPE(nf, rs1, vs3)) = {\n let load_width_bytes = 1;\n let EEW = 8;\n let VLEN = unsigned(vlenb) * 8;\n let elem_per_reg : int = VLEN / EEW;\n let nf_int = nfields_int(nf);\n\n assert(elem_per_reg >= 0);\n if not(nf_int == 1 | nf_int == 2 | nf_int == 4 | nf_int == 8) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vsre(nf_int, load_width_bytes, rs1, vs3, elem_per_reg)\n}", "pattern": { "type": "app", "id": "VSRETYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs3" } ] } ] }, "body": " let load_width_bytes = 1;\n let EEW = 8;\n let VLEN = unsigned(vlenb) * 8;\n let elem_per_reg : int = VLEN / EEW;\n let nf_int = nfields_int(nf);\n\n assert(elem_per_reg >= 0);\n if not(nf_int == 1 | nf_int == 2 | nf_int == 4 | nf_int == 8) then { handle_illegal(); return RETIRE_FAIL };\n\n process_vsre(nf_int, load_width_bytes, rs1, vs3, elem_per_reg)" }, { "number": 306, "source": "function clause execute(VMTYPE(rs1, vd_or_vs3, op)) = {\n let EEW = 8;\n let EMUL_pow = 0;\n let vl_val = unsigned(vl);\n let evl : int = if vl_val % 8 == 0 then vl_val / 8 else vl_val / 8 + 1; /* the effective vector length is evl=ceil(vl/8) */\n let num_elem = get_num_elem(EMUL_pow, EEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n assert(evl >= 0);\n process_vm(vd_or_vs3, rs1, num_elem, evl, op)\n}", "pattern": { "type": "app", "id": "VMTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd_or_vs3" }, { "type": "id", "id": "op" } ] } ] }, "body": " let EEW = 8;\n let EMUL_pow = 0;\n let vl_val = unsigned(vl);\n let evl : int = if vl_val % 8 == 0 then vl_val / 8 else vl_val / 8 + 1; /* the effective vector length is evl=ceil(vl/8) */\n let num_elem = get_num_elem(EMUL_pow, EEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n assert(evl >= 0);\n process_vm(vd_or_vs3, rs1, num_elem, evl, op)" }, { "number": 307, "source": "function clause execute(MMTYPE(funct6, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MM_VMAND => vs2_val[i] & vs1_val[i],\n MM_VMNAND => not(vs2_val[i] & vs1_val[i]),\n MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]),\n MM_VMXOR => vs2_val[i] != vs1_val[i],\n MM_VMOR => vs2_val[i] | vs1_val[i],\n MM_VMNOR => not(vs2_val[i] | vs1_val[i]),\n MM_VMORNOT => vs2_val[i] | not(vs1_val[i]),\n MM_VMXNOR => vs2_val[i] == vs1_val[i]\n }\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "MMTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n MM_VMAND => vs2_val[i] & vs1_val[i],\n MM_VMNAND => not(vs2_val[i] & vs1_val[i]),\n MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]),\n MM_VMXOR => vs2_val[i] != vs1_val[i],\n MM_VMOR => vs2_val[i] | vs1_val[i],\n MM_VMNOR => not(vs2_val[i] | vs1_val[i]),\n MM_VMORNOT => vs2_val[i] | not(vs1_val[i]),\n MM_VMXNOR => vs2_val[i] == vs1_val[i]\n }\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 308, "source": "function clause execute(VCPOP_M(vm, vs2, rd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val);\n\n count : nat = 0;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] & vs2_val[i] then count = count + 1;\n };\n\n X(rd) = to_bits(sizeof(xlen), count);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VCPOP_M", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val);\n\n count : nat = 0;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] & vs2_val[i] then count = count + 1;\n };\n\n X(rd) = to_bits(sizeof(xlen), count);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 309, "source": "function clause execute(VFIRST_M(vm, vs2, rd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val);\n\n index : int = -1;\n foreach (i from 0 to (num_elem - 1)) {\n if index == -1 then {\n if mask[i] & vs2_val[i] then index = i;\n };\n };\n\n X(rd) = to_bits(sizeof(xlen), index);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VFIRST_M", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val);\n\n index : int = -1;\n foreach (i from 0 to (num_elem - 1)) {\n if index == -1 then {\n if mask[i] & vs2_val[i] then index = i;\n };\n };\n\n X(rd) = to_bits(sizeof(xlen), index);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 310, "source": "function clause execute(VMSBF_M(vm, vs2, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);\n\n found_elem : bool = false;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n if vs2_val[i] then found_elem = true;\n result[i] = if found_elem then false else true\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VMSBF_M", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);\n\n found_elem : bool = false;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n if vs2_val[i] then found_elem = true;\n result[i] = if found_elem then false else true\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 311, "source": "function clause execute(VMSIF_M(vm, vs2, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);\n\n found_elem : bool = false;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = if found_elem then false else true;\n if vs2_val[i] then found_elem = true\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VMSIF_M", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);\n\n found_elem : bool = false;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = if found_elem then false else true;\n if vs2_val[i] then found_elem = true\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 312, "source": "function clause execute(VMSOF_M(vm, vs2, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);\n\n found_elem : bool = false;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n if vs2_val[i] & not(found_elem) then {\n result[i] = true;\n found_elem = true\n } else {\n result[i] = false\n }\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VMSOF_M", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = unsigned(vlenb) * 8;\n\n if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);\n\n found_elem : bool = false;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n if vs2_val[i] & not(found_elem) then {\n result[i] = true;\n found_elem = true\n } else {\n result[i] = false\n }\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 313, "source": "function clause execute(VIOTA_M(vm, vs2, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n sum : int = 0;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = to_bits(SEW, sum);\n if vs2_val[i] then sum = sum + 1\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VIOTA_M", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2\n then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n sum : int = 0;\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = to_bits(SEW, sum);\n if vs2_val[i] then sum = sum + 1\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 314, "source": "function clause execute(VID_V(vm, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = to_bits(SEW, i)\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VID_V", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then result[i] = to_bits(SEW, i)\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 315, "source": "function clause execute(VVMTYPE(funct6, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VVM_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1,\n VVM_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i])) < 0\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VVMTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VVM_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1,\n VVM_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i])) < 0\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 316, "source": "function clause execute(VVMCTYPE(funct6, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VVMC_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) > 2 ^ SEW - 1,\n VVMC_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) < 0\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VVMCTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VVMC_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) > 2 ^ SEW - 1,\n VVMC_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) < 0\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 317, "source": "function clause execute(VVMSTYPE(funct6, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n /* for bypassing normal masking in init_masked_result */\n vec_trues : vector('n, dec, bool) = undefined;\n foreach (i from 0 to (num_elem - 1)) {\n vec_trues[i] = true\n };\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VVMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i]))),\n VVMS_VSBC => to_bits(SEW, unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i])))\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VVMSTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n /* for bypassing normal masking in init_masked_result */\n vec_trues : vector('n, dec, bool) = undefined;\n foreach (i from 0 to (num_elem - 1)) {\n vec_trues[i] = true\n };\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VVMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i]))),\n VVMS_VSBC => to_bits(SEW, unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i])))\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 318, "source": "function clause execute(VVCMPTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VVCMP_VMSEQ => vs2_val[i] == vs1_val[i],\n VVCMP_VMSNE => vs2_val[i] != vs1_val[i],\n VVCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(vs1_val[i]),\n VVCMP_VMSLT => signed(vs2_val[i]) < signed(vs1_val[i]),\n VVCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]),\n VVCMP_VMSLE => signed(vs2_val[i]) <= signed(vs1_val[i])\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VVCMPTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VVCMP_VMSEQ => vs2_val[i] == vs1_val[i],\n VVCMP_VMSNE => vs2_val[i] != vs1_val[i],\n VVCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(vs1_val[i]),\n VVCMP_VMSLT => signed(vs2_val[i]) < signed(vs1_val[i]),\n VVCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]),\n VVCMP_VMSLE => signed(vs2_val[i]) <= signed(vs1_val[i])\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 319, "source": "function clause execute(VXMTYPE(funct6, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VXM_VMADC => unsigned(vs2_val[i]) + unsigned(rs1_val) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1,\n VXM_VMSBC => unsigned(vs2_val[i]) - unsigned(rs1_val) - unsigned(bool_to_bits(vm_val[i])) < 0\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VXMTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VXM_VMADC => unsigned(vs2_val[i]) + unsigned(rs1_val) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1,\n VXM_VMSBC => unsigned(vs2_val[i]) - unsigned(rs1_val) - unsigned(bool_to_bits(vm_val[i])) < 0\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 320, "source": "function clause execute(VXMCTYPE(funct6, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VXMC_VMADC => unsigned(vs2_val[i]) + unsigned(rs1_val) > 2 ^ SEW - 1,\n VXMC_VMSBC => unsigned(vs2_val[i]) - unsigned(rs1_val) < 0\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VXMCTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VXMC_VMADC => unsigned(vs2_val[i]) + unsigned(rs1_val) > 2 ^ SEW - 1,\n VXMC_VMSBC => unsigned(vs2_val[i]) - unsigned(rs1_val) < 0\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 321, "source": "function clause execute(VXMSTYPE(funct6, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n /* for bypassing normal masking in init_masked_result */\n vec_trues : vector('n, dec, bool) = undefined;\n foreach (i from 0 to (num_elem - 1)) {\n vec_trues[i] = true\n };\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VXMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(rs1_val) + unsigned(bool_to_bits(vm_val[i]))),\n VXMS_VSBC => to_bits(SEW, unsigned(vs2_val[i]) - unsigned(rs1_val) - unsigned(bool_to_bits(vm_val[i])))\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VXMSTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n /* for bypassing normal masking in init_masked_result */\n vec_trues : vector('n, dec, bool) = undefined;\n foreach (i from 0 to (num_elem - 1)) {\n vec_trues[i] = true\n };\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VXMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(rs1_val) + unsigned(bool_to_bits(vm_val[i]))),\n VXMS_VSBC => to_bits(SEW, unsigned(vs2_val[i]) - unsigned(rs1_val) - unsigned(bool_to_bits(vm_val[i])))\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 322, "source": "function clause execute(VXCMPTYPE(funct6, vm, vs2, rs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VXCMP_VMSEQ => vs2_val[i] == rs1_val,\n VXCMP_VMSNE => vs2_val[i] != rs1_val,\n VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val),\n VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val),\n VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val),\n VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val),\n VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val),\n VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val)\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VXCMPTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar(rs1, SEW);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VXCMP_VMSEQ => vs2_val[i] == rs1_val,\n VXCMP_VMSNE => vs2_val[i] != rs1_val,\n VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val),\n VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val),\n VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val),\n VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val),\n VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val),\n VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val)\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 323, "source": "function clause execute(VIMTYPE(funct6, vs2, simm, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VIM_VMADC => unsigned(vs2_val[i]) + unsigned(imm_val) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VIMTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VIM_VMADC => unsigned(vs2_val[i]) + unsigned(imm_val) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 324, "source": "function clause execute(VIMCTYPE(funct6, vs2, simm, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VIMC_VMADC => unsigned(vs2_val[i]) + unsigned(imm_val) > 2 ^ SEW - 1\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VIMCTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VIMC_VMADC => unsigned(vs2_val[i]) + unsigned(imm_val) > 2 ^ SEW - 1\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 325, "source": "function clause execute(VIMSTYPE(funct6, vs2, simm, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n /* for bypassing normal masking in init_masked_result */\n vec_trues : vector('n, dec, bool) = undefined;\n foreach (i from 0 to (num_elem - 1)) {\n vec_trues[i] = true\n };\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VIMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(imm_val) + unsigned(bool_to_bits(vm_val[i])))\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VIMSTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n /* for bypassing normal masking in init_masked_result */\n vec_trues : vector('n, dec, bool) = undefined;\n foreach (i from 0 to (num_elem - 1)) {\n vec_trues[i] = true\n };\n\n let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);\n result : vector('n, dec, bits('m)) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n result[i] = match funct6 {\n VIMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(imm_val) + unsigned(bool_to_bits(vm_val[i])))\n }\n }\n };\n\n write_vreg(num_elem, SEW, LMUL_pow, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 326, "source": "function clause execute(VICMPTYPE(funct6, vm, vs2, simm, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VICMP_VMSEQ => vs2_val[i] == imm_val,\n VICMP_VMSNE => vs2_val[i] != imm_val,\n VICMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(imm_val),\n VICMP_VMSLE => signed(vs2_val[i]) <= signed(imm_val),\n VICMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(imm_val),\n VICMP_VMSGT => signed(vs2_val[i]) > signed(imm_val)\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "VICMPTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let imm_val : bits('m) = sign_extend(simm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VICMP_VMSEQ => vs2_val[i] == imm_val,\n VICMP_VMSNE => vs2_val[i] != imm_val,\n VICMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(imm_val),\n VICMP_VMSLE => signed(vs2_val[i]) <= signed(imm_val),\n VICMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(imm_val),\n VICMP_VMSGT => signed(vs2_val[i]) > signed(imm_val)\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 327, "source": "function clause execute(FVVMTYPE(funct6, vm, vs2, vs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n FVVM_VMFEQ => fp_eq(vs2_val[i], vs1_val[i]),\n FVVM_VMFNE => ~(fp_eq(vs2_val[i], vs1_val[i])),\n FVVM_VMFLE => fp_le(vs2_val[i], vs1_val[i]),\n FVVM_VMFLT => fp_lt(vs2_val[i], vs1_val[i])\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FVVMTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n FVVM_VMFEQ => fp_eq(vs2_val[i], vs1_val[i]),\n FVVM_VMFNE => ~(fp_eq(vs2_val[i], vs1_val[i])),\n FVVM_VMFLE => fp_le(vs2_val[i], vs1_val[i]),\n FVVM_VMFLT => fp_lt(vs2_val[i], vs1_val[i])\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 328, "source": "function clause execute(FVFMTYPE(funct6, vm, vs2, rs1, vd)) = {\n let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VFM_VMFEQ => fp_eq(vs2_val[i], rs1_val),\n VFM_VMFNE => ~(fp_eq(vs2_val[i], rs1_val)),\n VFM_VMFLE => fp_le(vs2_val[i], rs1_val),\n VFM_VMFLT => fp_lt(vs2_val[i], rs1_val),\n VFM_VMFGE => fp_ge(vs2_val[i], rs1_val),\n VFM_VMFGT => fp_gt(vs2_val[i], rs1_val)\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "FVFMTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem = get_num_elem(LMUL_pow, SEW);\n\n if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n let 'n = num_elem;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);\n let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);\n result : vector('n, dec, bool) = undefined;\n mask : vector('n, dec, bool) = undefined;\n\n (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then {\n let res : bool = match funct6 {\n VFM_VMFEQ => fp_eq(vs2_val[i], rs1_val),\n VFM_VMFNE => ~(fp_eq(vs2_val[i], rs1_val)),\n VFM_VMFLE => fp_le(vs2_val[i], rs1_val),\n VFM_VMFLT => fp_lt(vs2_val[i], rs1_val),\n VFM_VMFGE => fp_ge(vs2_val[i], rs1_val),\n VFM_VMFGT => fp_gt(vs2_val[i], rs1_val)\n };\n result[i] = res\n }\n };\n\n write_vmask(num_elem, vd, result);\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 329, "source": "function clause execute(RIVVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n let num_elem_vs = get_num_elem(LMUL_pow, SEW);\n let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */\n\n if illegal_reduction_widen(SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL };\n\n if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */\n\n let 'n = num_elem_vs;\n let 'd = num_elem_vd;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);\n let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);\n\n sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */\n foreach (i from 0 to (num_elem_vs - 1)) {\n if mask[i] then {\n let elem : bits('o) = match funct6 {\n IVV_VWREDSUMU => to_bits(SEW_widen, unsigned(vs2_val[i])),\n IVV_VWREDSUM => to_bits(SEW_widen, signed(vs2_val[i]))\n };\n sum = sum + elem\n }\n };\n\n write_single_element(SEW_widen, 0, vd, sum);\n /* other elements in vd are treated as tail elements, currently remain unchanged */\n /* TODO: configuration support for agnostic behavior */\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RIVVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n let num_elem_vs = get_num_elem(LMUL_pow, SEW);\n let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */\n\n if illegal_reduction_widen(SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL };\n\n if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */\n\n let 'n = num_elem_vs;\n let 'd = num_elem_vd;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);\n let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);\n\n sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */\n foreach (i from 0 to (num_elem_vs - 1)) {\n if mask[i] then {\n let elem : bits('o) = match funct6 {\n IVV_VWREDSUMU => to_bits(SEW_widen, unsigned(vs2_val[i])),\n IVV_VWREDSUM => to_bits(SEW_widen, signed(vs2_val[i]))\n };\n sum = sum + elem\n }\n };\n\n write_single_element(SEW_widen, 0, vd, sum);\n /* other elements in vd are treated as tail elements, currently remain unchanged */\n /* TODO: configuration support for agnostic behavior */\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 330, "source": "function clause execute(RMVVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem_vs = get_num_elem(LMUL_pow, SEW);\n let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */\n\n if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL };\n\n if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */\n\n let 'n = num_elem_vs;\n let 'd = num_elem_vd;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);\n let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);\n\n sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */\n foreach (i from 0 to (num_elem_vs - 1)) {\n if mask[i] then {\n sum = match funct6 {\n MVV_VREDSUM => sum + vs2_val[i],\n MVV_VREDAND => sum & vs2_val[i],\n MVV_VREDOR => sum | vs2_val[i],\n MVV_VREDXOR => sum ^ vs2_val[i],\n MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))),\n MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))),\n MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))),\n MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum)))\n }\n }\n };\n\n write_single_element(SEW, 0, vd, sum);\n /* other elements in vd are treated as tail elements, currently remain unchanged */\n /* TODO: configuration support for agnostic behavior */\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "app", "id": "RMVVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem_vs = get_num_elem(LMUL_pow, SEW);\n let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */\n\n if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL };\n\n if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */\n\n let 'n = num_elem_vs;\n let 'd = num_elem_vd;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);\n let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);\n\n sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */\n foreach (i from 0 to (num_elem_vs - 1)) {\n if mask[i] then {\n sum = match funct6 {\n MVV_VREDSUM => sum + vs2_val[i],\n MVV_VREDAND => sum & vs2_val[i],\n MVV_VREDOR => sum | vs2_val[i],\n MVV_VREDXOR => sum ^ vs2_val[i],\n MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))),\n MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))),\n MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))),\n MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum)))\n }\n }\n };\n\n write_single_element(SEW, 0, vd, sum);\n /* other elements in vd are treated as tail elements, currently remain unchanged */\n /* TODO: configuration support for agnostic behavior */\n vstart = zeros();\n RETIRE_SUCCESS" }, { "number": 331, "source": "function clause execute(RFVVTYPE(funct6, vm, vs2, vs1, vd)) = {\n let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem_vs = get_num_elem(LMUL_pow, SEW);\n\n if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then\n process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow)\n else\n process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow)\n}", "pattern": { "type": "app", "id": "RFVVTYPE", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] } ] }, "body": " let SEW = get_sew();\n let LMUL_pow = get_lmul_pow();\n let num_elem_vs = get_num_elem(LMUL_pow, SEW);\n\n if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then\n process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow)\n else\n process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow)" }, { "number": 332, "source": "function clause execute (RISCV_JALR(imm, rs1, rd)) = {\n/* For the sequential model, the memory-model definition doesn't work directly\n * if rs1 = rd. We would effectively have to keep a regfile for reads and another for\n * writes, and swap on instruction completion. This could perhaps be optimized in\n * some manner, but for now, we just keep a reordered definition to improve simulator\n * performance.\n */\n let t : xlenbits = X(rs1) + sign_extend(imm);\n /* Extensions get the first checks on the prospective target address. */\n match ext_control_check_addr(t) {\n Ext_ControlAddr_Error(e) => {\n ext_handle_control_check_error(e);\n RETIRE_FAIL\n },\n Ext_ControlAddr_OK(addr) => {\n let target = [addr with 0 = bitzero]; /* clear addr[0] */\n if bit_to_bool(target[1]) & not(haveRVC()) then {\n handle_mem_exception(target, E_Fetch_Addr_Align());\n RETIRE_FAIL\n } else {\n X(rd) = get_next_pc();\n set_next_pc(target);\n RETIRE_SUCCESS\n }\n }\n }\n}", "pattern": { "type": "app", "id": "RISCV_JALR", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] } ] }, "body": " let t : xlenbits = X(rs1) + sign_extend(imm);\n /* Extensions get the first checks on the prospective target address. */\n match ext_control_check_addr(t) {\n Ext_ControlAddr_Error(e) => {\n ext_handle_control_check_error(e);\n RETIRE_FAIL\n },\n Ext_ControlAddr_OK(addr) => {\n let target = [addr with 0 = bitzero]; /* clear addr[0] */\n if bit_to_bool(target[1]) & not(haveRVC()) then {\n handle_mem_exception(target, E_Fetch_Addr_Align());\n RETIRE_FAIL\n } else {\n X(rd) = get_next_pc();\n set_next_pc(target);\n RETIRE_SUCCESS\n }\n }\n }" }, { "number": 333, "source": "function clause execute (ILLEGAL(s)) = { handle_illegal(); RETIRE_FAIL }", "pattern": { "type": "app", "id": "ILLEGAL", "patterns": [ { "type": "id", "id": "s" } ] }, "body": "function clause execute (ILLEGAL(s)) = { handle_illegal(); RETIRE_FAIL" }, { "number": 334, "source": "function clause execute C_ILLEGAL(s) = { handle_illegal(); RETIRE_FAIL }", "pattern": { "type": "app", "id": "C_ILLEGAL", "patterns": [ { "type": "id", "id": "s" } ] }, "body": "function clause execute C_ILLEGAL(s) = { handle_illegal(); RETIRE_FAIL" } ], "links": [ { "type": "function", "id": "handle_illegal", "file": "model/riscv_insts_end.sail", "loc": [ 1152, 1166 ] }, { "type": "function", "id": "handle_illegal", "file": "model/riscv_insts_end.sail", "loc": [ 872, 886 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_jalr_seq.sail", "loc": [ 1133, 1144 ] }, { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] }, { "type": "function", "id": "ext_control_check_addr", "file": "model/riscv_jalr_seq.sail", "loc": [ 1234, 1256 ] }, { "type": "function", "id": "not", "file": "model/riscv_jalr_seq.sail", "loc": [ 1495, 1498 ] }, { "type": "function", "id": "haveRVC", "file": "model/riscv_jalr_seq.sail", "loc": [ 1499, 1506 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_jalr_seq.sail", "loc": [ 1470, 1481 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_jalr_seq.sail", "loc": [ 1525, 1545 ] }, { "type": "function", "id": "E_Fetch_Addr_Align", "file": "model/riscv_jalr_seq.sail", "loc": [ 1554, 1572 ] }, { "type": "function", "id": "set_next_pc", "file": "model/riscv_jalr_seq.sail", "loc": [ 1651, 1662 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] }, { "type": "function", "id": "get_next_pc", "file": "model/riscv_jalr_seq.sail", "loc": [ 1628, 1639 ] }, { "type": "function", "id": "ext_handle_control_check_error", "file": "model/riscv_jalr_seq.sail", "loc": [ 1302, 1332 ] }, { "type": "function", "id": "get_sew", "file": "model/riscv_insts_vext_red.sail", "loc": [ 10228, 10235 ] }, { "type": "function", "id": "get_lmul_pow", "file": "model/riscv_insts_vext_red.sail", "loc": [ 10256, 10268 ] }, { "type": "function", "id": "get_num_elem", "file": "model/riscv_insts_vext_red.sail", "loc": [ 10292, 10304 ] }, { "type": "function", "id": "process_rfvv_widen", "file": "model/riscv_insts_vext_red.sail", "loc": [ 10388, 10406 ] }, { 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"model/riscv_insts_base.sail", "loc": [ 4156, 4159 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_insts_base.sail", "loc": [ 4318, 4329 ] }, { "type": "register", "id": "PC", "file": "model/riscv_insts_base.sail", "loc": [ 4313, 4315 ] }, { "type": "function", "id": "ext_control_check_pc", "file": "model/riscv_insts_base.sail", "loc": [ 4441, 4461 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_base.sail", "loc": [ 4649, 4652 ] }, { "type": "function", "id": "haveRVC", "file": "model/riscv_insts_base.sail", "loc": [ 4653, 4660 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_insts_base.sail", "loc": [ 4624, 4635 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_base.sail", "loc": [ 4681, 4701 ] }, { "type": "function", "id": "E_Fetch_Addr_Align", "file": "model/riscv_insts_base.sail", "loc": [ 4710, 4728 ] }, { "type": "function", "id": "set_next_pc", "file": "model/riscv_insts_base.sail", "loc": [ 4783, 4794 ] }, { "type": "function", "id": "ext_handle_control_check_error", "file": "model/riscv_insts_base.sail", "loc": [ 4511, 4541 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_insts_base.sail", "loc": [ 2212, 2223 ] }, { "type": "register", "id": "PC", "file": "model/riscv_insts_base.sail", "loc": [ 2207, 2209 ] }, { "type": "function", "id": "ext_control_check_pc", "file": "model/riscv_insts_base.sail", "loc": [ 2313, 2333 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_base.sail", "loc": [ 2554, 2557 ] }, { "type": "function", "id": "haveRVC", "file": "model/riscv_insts_base.sail", "loc": [ 2558, 2565 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_insts_base.sail", "loc": [ 2529, 2540 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_base.sail", "loc": [ 2590, 2610 ] }, { "type": "function", "id": "E_Fetch_Addr_Align", "file": "model/riscv_insts_base.sail", "loc": [ 2619, 2637 ] }, { "type": "function", "id": "set_next_pc", "file": "model/riscv_insts_base.sail", "loc": [ 2716, 2727 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] }, { "type": "function", "id": "get_next_pc", "file": "model/riscv_insts_base.sail", "loc": [ 2693, 2704 ] }, { "type": "function", "id": "ext_handle_control_check_error", "file": "model/riscv_insts_base.sail", "loc": [ 2379, 2409 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_insts_base.sail", "loc": [ 1165, 1176 ] }, { "type": "function", "id": "get_arch_pc", "file": "model/riscv_insts_base.sail", "loc": [ 1268, 1279 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] } ] }, "extStatus_of_bits": { "function": { "number": 0, "source": "function extStatus_of_bits(e) =\n match (e) {\n 0b00 => Off,\n 0b01 => Initial,\n 0b10 => Clean,\n 0b11 => Dirty\n }", "pattern": { "type": "id", "id": "e" }, "body": "match (e) {\n 0b00 => Off,\n 0b01 => Initial,\n 0b10 => Clean,\n 0b11 => Dirty\n }" } }, "extStatus_to_bits": { "function": { "number": 0, "source": "function extStatus_to_bits(e) =\n match (e) {\n Off => 0b00,\n Initial => 0b01,\n Clean => 0b10,\n Dirty => 0b11\n }", "pattern": { "type": "id", "id": "e" }, "body": "match (e) {\n Off => 0b00,\n Initial => 0b01,\n Clean => 0b10,\n Dirty => 0b11\n }" } }, "ext_check_CSR": { "function": { "number": 0, "source": "function ext_check_CSR (csrno, p, isWrite) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "csrno" }, { "type": "id", "id": "p" }, { "type": "id", "id": "isWrite" } ] }, "body": "true" } }, "ext_check_CSR_fail": { "function": { "number": 0, "source": "function ext_check_CSR_fail () = ()", "pattern": { "type": "literal", "value": "()" }, "body": "()" } }, "ext_check_phys_mem_read": { "function": { "number": 0, "source": "function ext_check_phys_mem_read (access_type, paddr, size, aquire, release, reserved, read_meta) =\n Ext_PhysAddr_OK ()", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "access_type" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "size" }, { "type": "id", "id": "aquire" }, { "type": "id", "id": "release" }, { "type": "id", "id": "reserved" }, { "type": "id", "id": "read_meta" } ] }, "body": "Ext_PhysAddr_OK ()" }, "links": [ { "type": "function", "id": "Ext_PhysAddr_OK", "file": "model/riscv_addr_checks.sail", "loc": [ 2984, 2999 ] } ] }, "ext_check_phys_mem_write": { "function": { "number": 0, "source": "function ext_check_phys_mem_write(write_kind, paddr, size, data, metadata) =\n Ext_PhysAddr_OK ()", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "write_kind" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "size" }, { "type": "id", "id": "data" }, { "type": "id", "id": "metadata" } ] }, "body": "Ext_PhysAddr_OK ()" }, "links": [ { "type": "function", "id": "Ext_PhysAddr_OK", "file": "model/riscv_addr_checks.sail", "loc": [ 3083, 3098 ] } ] }, "ext_check_xret_priv": { "function": { "number": 0, "source": "function ext_check_xret_priv (p : Privilege) : Privilege -> bool = true", "pattern": { "type": "id", "id": "p" }, "body": "true" } }, "ext_control_check_addr": { "function": { "number": 0, "source": "function ext_control_check_addr(pc : xlenbits) -> Ext_ControlAddr_Check(ext_control_addr_error) =\n Ext_ControlAddr_OK(pc)", "pattern": { "type": "id", "id": "pc" }, "body": "Ext_ControlAddr_OK(pc)" }, "links": [ { "type": "function", "id": "Ext_ControlAddr_OK", "file": "model/riscv_addr_checks.sail", "loc": [ 1929, 1947 ] } ] }, "ext_control_check_pc": { "function": { "number": 0, "source": "function ext_control_check_pc(pc : xlenbits) -> Ext_ControlAddr_Check(ext_control_addr_error) =\n Ext_ControlAddr_OK(pc)", "pattern": { "type": "id", "id": "pc" }, "body": "Ext_ControlAddr_OK(pc)" }, "links": [ { "type": "function", "id": "Ext_ControlAddr_OK", "file": "model/riscv_addr_checks.sail", "loc": [ 2122, 2140 ] } ] }, "ext_data_get_addr": { "function": { "number": 0, "source": "function ext_data_get_addr(base : regidx, offset : xlenbits, acc : AccessType(ext_access_type), width : word_width)\n -> Ext_DataAddr_Check(ext_data_addr_error) =\n let addr = X(base) + offset in\n Ext_DataAddr_OK(addr)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "base" }, { "type": "id", "id": "offset" }, { "type": "id", "id": "acc" }, { "type": "id", "id": "width" } ] }, "body": "let addr = X(base) + offset in\n Ext_DataAddr_OK(addr)" }, "links": [ { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] }, { "type": "function", "id": "Ext_DataAddr_OK", "file": "model/riscv_addr_checks.sail", "loc": [ 2712, 2727 ] } ] }, "ext_decode": { "function": { "number": 0, "source": "function ext_decode(bv) = encdec(bv)", "pattern": { "type": "id", "id": "bv" }, "body": "encdec(bv)" } }, "ext_decode_compressed": { "function": { "number": 0, "source": "function ext_decode_compressed(bv) = encdec_compressed(bv)", "pattern": { "type": "id", "id": "bv" }, "body": "encdec_compressed(bv)" } }, "ext_exc_type_to_bits": { "function": { "number": 0, "source": "function ext_exc_type_to_bits(e) = 0x18", "pattern": { "type": "id", "id": "e" }, "body": "0x18" } }, "ext_exc_type_to_str": { "function": { "number": 0, "source": "function ext_exc_type_to_str(e) = \"extension-exception\"", "pattern": { "type": "id", "id": "e" }, "body": "\"extension-exception\"" } }, "ext_fail_xret_priv": { "function": { "number": 0, "source": "function ext_fail_xret_priv () : unit -> unit = ()", "pattern": { "type": "literal", "value": "()" }, "body": "()" } }, "ext_fetch_check_pc": { "function": { "number": 0, "source": "function ext_fetch_check_pc(start_pc : xlenbits, pc : xlenbits) -> Ext_FetchAddr_Check(ext_fetch_addr_error) =\n Ext_FetchAddr_OK(pc)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "start_pc" }, { "type": "id", "id": "pc" } ] }, "body": "Ext_FetchAddr_OK(pc)" }, "links": [ { "type": "function", "id": "Ext_FetchAddr_OK", "file": "model/riscv_addr_checks.sail", "loc": [ 1170, 1186 ] } ] }, "ext_fetch_hook": { "function": { "number": 0, "source": "function ext_fetch_hook(f : FetchResult) -> FetchResult = f", "pattern": { "type": "id", "id": "f" }, "body": "f" } }, "ext_get_ptw_error": { "function": { "number": 0, "source": "function ext_get_ptw_error(eptwf : ext_ptw_fail) -> PTW_Error =\n PTW_No_Permission()", "pattern": { "type": "id", "id": "eptwf" }, "body": "PTW_No_Permission()" }, "links": [ { "type": "function", "id": "PTW_No_Permission", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2157, 2174 ] } ] }, "ext_handle_control_check_error": { "function": { "number": 0, "source": "function ext_handle_control_check_error(err : ext_control_addr_error) -> unit =\n ()", "pattern": { "type": "id", "id": "err" }, "body": "()" } }, "ext_handle_data_check_error": { "function": { "number": 0, "source": "function ext_handle_data_check_error(err : ext_data_addr_error) -> unit =\n ()", "pattern": { "type": "id", "id": "err" }, "body": "()" } }, "ext_handle_fetch_check_error": { "function": { "number": 0, "source": "function ext_handle_fetch_check_error(err : ext_fetch_addr_error) -> unit =\n ()", "pattern": { "type": "id", "id": "err" }, "body": "()" } }, "ext_init": { "function": { "number": 0, "source": "function ext_init() -> unit = ()", "pattern": { "type": "literal", "value": "()" }, "body": "()" } }, "ext_init_regs": { "function": { "number": 0, "source": "function ext_init_regs () = ()", "pattern": { "type": "literal", "value": "()" }, "body": "()" } }, "ext_is_CSR_defined": { "function": [ { "number": 0, "source": "function clause ext_is_CSR_defined (0x008, _) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x008" }, { "type": "wildcard" } ] }, "body": "true" }, { "number": 1, "source": "function clause ext_is_CSR_defined (0xC20, _) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0xC20" }, { "type": "wildcard" } ] }, "body": "true" }, { "number": 2, "source": "function clause ext_is_CSR_defined (0xC21, _) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0xC21" }, { "type": "wildcard" } ] }, "body": "true" }, { "number": 3, "source": "function clause ext_is_CSR_defined (0xC22, _) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0xC22" }, { "type": "wildcard" } ] }, "body": "true" }, { "number": 4, "source": "function clause ext_is_CSR_defined (0x009, _) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x009" }, { "type": "wildcard" } ] }, "body": "true" }, { "number": 5, "source": "function clause ext_is_CSR_defined (0x00A, _) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x00A" }, { "type": "wildcard" } ] }, "body": "true" }, { "number": 6, "source": "function clause ext_is_CSR_defined (0x00F, _) = true", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x00F" }, { "type": "wildcard" } ] }, "body": "true" }, { "number": 7, "source": "function clause ext_is_CSR_defined(0x000, _) = haveUsrMode() & haveNExt()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x000" }, { "type": "wildcard" } ] }, "body": "haveUsrMode() & haveNExt()" }, { "number": 8, "source": "function clause ext_is_CSR_defined(0x004, _) = haveUsrMode() & haveNExt()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x004" }, { "type": "wildcard" } ] }, "body": "haveUsrMode() & haveNExt()" }, { "number": 9, "source": "function clause ext_is_CSR_defined(0x005, _) = haveUsrMode() & haveNExt()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x005" }, { "type": "wildcard" } ] }, "body": "haveUsrMode() & haveNExt()" }, { "number": 10, "source": "function clause ext_is_CSR_defined(0x040, _) = haveUsrMode() & haveNExt()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x040" }, { "type": "wildcard" } ] }, "body": "haveUsrMode() & haveNExt()" }, { "number": 11, "source": "function clause ext_is_CSR_defined(0x041, _) = haveUsrMode() & haveNExt()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x041" }, { "type": "wildcard" } ] }, "body": "haveUsrMode() & haveNExt()" }, { "number": 12, "source": "function clause ext_is_CSR_defined(0x042, _) = haveUsrMode() & haveNExt()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x042" }, { "type": "wildcard" } ] }, "body": "haveUsrMode() & haveNExt()" }, { "number": 13, "source": "function clause ext_is_CSR_defined(0x043, _) = haveUsrMode() & haveNExt()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x043" }, { "type": "wildcard" } ] }, "body": "haveUsrMode() & haveNExt()" }, { "number": 14, "source": "function clause ext_is_CSR_defined(0x044, _) = haveUsrMode() & haveNExt()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x044" }, { "type": "wildcard" } ] }, "body": "haveUsrMode() & haveNExt()" }, { "number": 15, "source": "function clause ext_is_CSR_defined (0x001, _) = haveFExt() | haveZfinx()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x001" }, { "type": "wildcard" } ] }, "body": "haveFExt() | haveZfinx()" }, { "number": 16, "source": "function clause ext_is_CSR_defined (0x002, _) = haveFExt() | haveZfinx()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x002" }, { "type": "wildcard" } ] }, "body": "haveFExt() | haveZfinx()" }, { "number": 17, "source": "function clause ext_is_CSR_defined (0x003, _) = haveFExt() | haveZfinx()", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x003" }, { "type": "wildcard" } ] }, "body": "haveFExt() | haveZfinx()" }, { "number": 18, "source": "function clause ext_is_CSR_defined(_, _) = false", "pattern": { "type": "tuple", "patterns": [ { "type": "wildcard" }, { "type": "wildcard" } ] }, "body": "false" } ], "links": [ { "type": "function", "id": "haveZfinx", "file": "model/riscv_fdext_control.sail", "loc": [ 1347, 1356 ] }, { "type": "function", "id": "haveFExt", "file": "model/riscv_fdext_control.sail", "loc": [ 1334, 1342 ] }, { "type": "function", "id": "haveZfinx", "file": "model/riscv_fdext_control.sail", "loc": [ 1274, 1283 ] }, { "type": "function", "id": "haveFExt", "file": "model/riscv_fdext_control.sail", "loc": [ 1261, 1269 ] }, { "type": "function", "id": "haveZfinx", "file": "model/riscv_fdext_control.sail", "loc": [ 1201, 1210 ] }, { "type": "function", "id": "haveFExt", "file": "model/riscv_fdext_control.sail", "loc": [ 1188, 1196 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_next_control.sail", "loc": [ 1378, 1386 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_next_control.sail", "loc": [ 1362, 1373 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_next_control.sail", "loc": [ 1295, 1303 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_next_control.sail", "loc": [ 1279, 1290 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_next_control.sail", "loc": [ 1211, 1219 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_next_control.sail", "loc": [ 1195, 1206 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_next_control.sail", "loc": [ 1129, 1137 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_next_control.sail", "loc": [ 1113, 1124 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_next_control.sail", "loc": [ 1043, 1051 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_next_control.sail", "loc": [ 1027, 1038 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_next_control.sail", "loc": [ 960, 968 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_next_control.sail", "loc": [ 944, 955 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_next_control.sail", "loc": [ 879, 887 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_next_control.sail", "loc": [ 863, 874 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_next_control.sail", "loc": [ 794, 802 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_next_control.sail", "loc": [ 778, 789 ] } ] }, "ext_post_step_hook": { "function": { "number": 0, "source": "function ext_post_step_hook() -> unit = ()", "pattern": { "type": "literal", "value": "()" }, "body": "()" } }, "ext_pre_step_hook": { "function": { "number": 0, "source": "function ext_pre_step_hook() -> unit = ()", "pattern": { "type": "literal", "value": "()" }, "body": "()" } }, "ext_read_CSR": { "function": [ { "number": 0, "source": "function clause ext_read_CSR (0x009) = Some (zero_extend(vcsr[vxsat]))", "pattern": { "type": "literal", "value": "0x009" }, "body": "Some (zero_extend(vcsr[vxsat]))" }, { "number": 1, "source": "function clause ext_read_CSR (0x00A) = Some (zero_extend(vcsr[vxrm]))", "pattern": { "type": "literal", "value": "0x00A" }, "body": "Some (zero_extend(vcsr[vxrm]))" }, { "number": 2, "source": "function clause ext_read_CSR (0x00F) = Some (zero_extend(vcsr.bits))", "pattern": { "type": "literal", "value": "0x00F" }, "body": "Some (zero_extend(vcsr.bits))" }, { "number": 3, "source": "function clause ext_read_CSR (0x009) = Some (zero_extend(vcsr[vxsat]))", "pattern": { "type": "literal", "value": "0x009" }, "body": "Some (zero_extend(vcsr[vxsat]))" }, { "number": 4, "source": "function clause ext_read_CSR (0x00A) = Some (zero_extend(vcsr[vxrm]))", "pattern": { "type": "literal", "value": "0x00A" }, "body": "Some (zero_extend(vcsr[vxrm]))" }, { "number": 5, "source": "function clause ext_read_CSR (0x00F) = Some (zero_extend(vcsr.bits))", "pattern": { "type": "literal", "value": "0x00F" }, "body": "Some (zero_extend(vcsr.bits))" }, { "number": 6, "source": "function clause ext_read_CSR(0x000) = Some(lower_sstatus(lower_mstatus(mstatus)).bits)", "pattern": { "type": "literal", "value": "0x000" }, "body": "Some(lower_sstatus(lower_mstatus(mstatus)).bits)" }, { "number": 7, "source": "function clause ext_read_CSR(0x004) = Some(lower_sie(lower_mie(mie, mideleg), sideleg).bits)", "pattern": { "type": "literal", "value": "0x004" }, "body": "Some(lower_sie(lower_mie(mie, mideleg), sideleg).bits)" }, { "number": 8, "source": "function clause ext_read_CSR(0x005) = Some(get_utvec())", "pattern": { "type": "literal", "value": "0x005" }, "body": "Some(get_utvec())" }, { "number": 9, "source": "function clause ext_read_CSR(0x040) = Some(uscratch)", "pattern": { "type": "literal", "value": "0x040" }, "body": "Some(uscratch)" }, { "number": 10, "source": "function clause ext_read_CSR(0x041) = Some(get_xret_target(User) & pc_alignment_mask())", "pattern": { "type": "literal", "value": "0x041" }, "body": "Some(get_xret_target(User) & pc_alignment_mask())" }, { "number": 11, "source": "function clause ext_read_CSR(0x042) = Some(ucause.bits)", "pattern": { "type": "literal", "value": "0x042" }, "body": "Some(ucause.bits)" }, { "number": 12, "source": "function clause ext_read_CSR(0x043) = Some(utval)", "pattern": { "type": "literal", "value": "0x043" }, "body": "Some(utval)" }, { "number": 13, "source": "function clause ext_read_CSR(0x044) = Some(lower_sip(lower_mip(mip, mideleg), sideleg).bits)", "pattern": { "type": "literal", "value": "0x044" }, "body": "Some(lower_sip(lower_mip(mip, mideleg), sideleg).bits)" }, { "number": 14, "source": "function clause ext_read_CSR (0x001) = Some(zero_extend(fcsr[FFLAGS]))", "pattern": { "type": "literal", "value": "0x001" }, "body": "Some(zero_extend(fcsr[FFLAGS]))" }, { "number": 15, "source": "function clause ext_read_CSR (0x002) = Some(zero_extend(fcsr[FRM]))", "pattern": { "type": "literal", "value": "0x002" }, "body": "Some(zero_extend(fcsr[FRM]))" }, { "number": 16, "source": "function clause ext_read_CSR (0x003) = Some(zero_extend(fcsr.bits))", "pattern": { "type": "literal", "value": "0x003" }, "body": "Some(zero_extend(fcsr.bits))" }, { "number": 17, "source": "function clause ext_read_CSR _ = None()", "pattern": { "type": "wildcard" }, "body": "None()" } ], "links": [ { "type": "function", "id": "None", "file": "model/riscv_csr_ext.sail", "loc": [ 1037, 1041 ] }, { "type": "function", "id": "Some", "file": "model/riscv_fdext_control.sail", "loc": [ 1538, 1542 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_fdext_control.sail", "loc": [ 1543, 1554 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1555, 1559 ] }, { "type": "function", "id": "Some", "file": "model/riscv_fdext_control.sail", "loc": [ 1470, 1474 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_fdext_control.sail", "loc": [ 1475, 1486 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1487, 1491 ] }, { "type": "function", "id": "Some", "file": "model/riscv_fdext_control.sail", "loc": [ 1399, 1403 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_fdext_control.sail", "loc": [ 1404, 1415 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1416, 1420 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 1918, 1922 ] }, { "type": "function", "id": "lower_sip", "file": "model/riscv_next_control.sail", "loc": [ 1923, 1932 ] }, { "type": "register", "id": "sideleg", "file": "model/riscv_next_control.sail", "loc": [ 1958, 1965 ] }, { "type": "function", "id": "lower_mip", "file": "model/riscv_next_control.sail", "loc": [ 1933, 1942 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_next_control.sail", "loc": [ 1948, 1955 ] }, { "type": "register", "id": "mip", "file": "model/riscv_next_control.sail", "loc": [ 1943, 1946 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 1868, 1872 ] }, { "type": "register", "id": "utval", "file": "model/riscv_next_control.sail", "loc": [ 1873, 1878 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 1812, 1816 ] }, { "type": "register", "id": "ucause", "file": "model/riscv_next_control.sail", "loc": [ 1817, 1823 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 1724, 1728 ] }, { "type": "function", "id": "pc_alignment_mask", "file": "model/riscv_next_control.sail", "loc": [ 1753, 1770 ] }, { "type": "function", "id": "get_xret_target", "file": "model/riscv_next_control.sail", "loc": [ 1729, 1744 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 1671, 1675 ] }, { "type": "register", "id": "uscratch", "file": "model/riscv_next_control.sail", "loc": [ 1676, 1684 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 1615, 1619 ] }, { "type": "function", "id": "get_utvec", "file": "model/riscv_next_control.sail", "loc": [ 1620, 1629 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 1522, 1526 ] }, { "type": "function", "id": "lower_sie", "file": "model/riscv_next_control.sail", "loc": [ 1527, 1536 ] }, { "type": "register", "id": "sideleg", "file": "model/riscv_next_control.sail", "loc": [ 1562, 1569 ] }, { "type": "function", "id": "lower_mie", "file": "model/riscv_next_control.sail", "loc": [ 1537, 1546 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_next_control.sail", "loc": [ 1552, 1559 ] }, { "type": "register", "id": "mie", "file": "model/riscv_next_control.sail", "loc": [ 1547, 1550 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 1435, 1439 ] }, { "type": "function", "id": "lower_sstatus", "file": "model/riscv_next_control.sail", "loc": [ 1440, 1453 ] }, { "type": "function", "id": "lower_mstatus", "file": "model/riscv_next_control.sail", "loc": [ 1454, 1467 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_next_control.sail", "loc": [ 1468, 1475 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1409, 1413 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1415, 1426 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1427, 1431 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1339, 1343 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1345, 1356 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1357, 1361 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1268, 1272 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1274, 1285 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1286, 1290 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1198, 1202 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1204, 1215 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1216, 1220 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1128, 1132 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1134, 1145 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1146, 1150 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1057, 1061 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1063, 1074 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1075, 1079 ] } ] }, "ext_rvfi_init": { "function": { "number": 0, "source": "function ext_rvfi_init () = {\n x1 = x1 // to avoid hook being optimized out\n}", "pattern": { "type": "literal", "value": "()" }, "body": " x1 = x1" }, "links": [ { "type": "register", "id": "x1", "file": "model/riscv_ext_regs.sail", "loc": [ 1053, 1055 ] }, { "type": "register", "id": "x1", "file": "model/riscv_ext_regs.sail", "loc": [ 1058, 1060 ] } ] }, "ext_translate_exception": { "function": { "number": 0, "source": "function ext_translate_exception(e : ext_ptw_error) -> ext_exc_type =\n e", "pattern": { "type": "id", "id": "e" }, "body": "e" } }, "ext_veto_disable_C": { "function": { "number": 0, "source": "function ext_veto_disable_C () = false", "pattern": { "type": "literal", "value": "()" }, "body": "false" } }, "ext_write_CSR": { "function": [ { "number": 0, "source": "function clause ext_write_CSR (0x009, value) = { ext_write_vcsr (vcsr[vxrm], value[0 .. 0]); Some(zero_extend(vcsr[vxsat])) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x009" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR (0x009, value) = { ext_write_vcsr (vcsr[vxrm], value[0 .. 0]); Some(zero_extend(vcsr[vxsat]))" }, { "number": 1, "source": "function clause ext_write_CSR (0x00A, value) = { ext_write_vcsr (value[1 .. 0], vcsr[vxsat]); Some(zero_extend(vcsr[vxrm])) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x00A" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR (0x00A, value) = { ext_write_vcsr (value[1 .. 0], vcsr[vxsat]); Some(zero_extend(vcsr[vxrm]))" }, { "number": 2, "source": "function clause ext_write_CSR (0x00F, value) = { ext_write_vcsr (value [2 .. 1], value [0 .. 0]); Some(zero_extend(vcsr.bits)) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x00F" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR (0x00F, value) = { ext_write_vcsr (value [2 .. 1], value [0 .. 0]); Some(zero_extend(vcsr.bits))" }, { "number": 3, "source": "function clause ext_write_CSR(0x000, value) = { mstatus = legalize_ustatus(mstatus, value); Some(mstatus.bits) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x000" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR(0x000, value) = { mstatus = legalize_ustatus(mstatus, value); Some(mstatus.bits)" }, { "number": 4, "source": "function clause ext_write_CSR(0x004, value) = { let sie = legalize_uie(lower_mie(mie, mideleg), sideleg, value);\n mie = lift_sie(mie, mideleg, sie);\n Some(mie.bits) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x004" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR(0x004, value) = { let sie = legalize_uie(lower_mie(mie, mideleg), sideleg, value);\n mie = lift_sie(mie, mideleg, sie);\n Some(mie.bits)" }, { "number": 5, "source": "function clause ext_write_CSR(0x005, value) = { Some(set_utvec(value)) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x005" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR(0x005, value) = { Some(set_utvec(value))" }, { "number": 6, "source": "function clause ext_write_CSR(0x040, value) = { uscratch = value; Some(uscratch) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x040" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR(0x040, value) = { uscratch = value; Some(uscratch)" }, { "number": 7, "source": "function clause ext_write_CSR(0x041, value) = { Some(set_xret_target(User, value)) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x041" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR(0x041, value) = { Some(set_xret_target(User, value))" }, { "number": 8, "source": "function clause ext_write_CSR(0x042, value) = { ucause.bits = value; Some(ucause.bits) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x042" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR(0x042, value) = { ucause.bits = value; Some(ucause.bits)" }, { "number": 9, "source": "function clause ext_write_CSR(0x043, value) = { utval = value; Some(utval) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x043" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR(0x043, value) = { utval = value; Some(utval)" }, { "number": 10, "source": "function clause ext_write_CSR(0x044, value) = { let sip = legalize_uip(lower_mip(mip, mideleg), sideleg, value);\n mip = lift_sip(mip, mideleg, sip);\n Some(mip.bits) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x044" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR(0x044, value) = { let sip = legalize_uip(lower_mip(mip, mideleg), sideleg, value);\n mip = lift_sip(mip, mideleg, sip);\n Some(mip.bits)" }, { "number": 11, "source": "function clause ext_write_CSR (0x001, value) = { ext_write_fcsr(fcsr[FRM], value[4..0]); Some(zero_extend(fcsr[FFLAGS])) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x001" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR (0x001, value) = { ext_write_fcsr(fcsr[FRM], value[4..0]); Some(zero_extend(fcsr[FFLAGS]))" }, { "number": 12, "source": "function clause ext_write_CSR (0x002, value) = { ext_write_fcsr(value[2..0], fcsr[FFLAGS]); Some(zero_extend(fcsr[FRM])) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x002" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR (0x002, value) = { ext_write_fcsr(value[2..0], fcsr[FFLAGS]); Some(zero_extend(fcsr[FRM]))" }, { "number": 13, "source": "function clause ext_write_CSR (0x003, value) = { ext_write_fcsr(value[7..5], value[4..0]); Some(zero_extend(fcsr.bits)) }", "pattern": { "type": "tuple", "patterns": [ { "type": "literal", "value": "0x003" }, { "type": "id", "id": "value" } ] }, "body": "function clause ext_write_CSR (0x003, value) = { ext_write_fcsr(value[7..5], value[4..0]); Some(zero_extend(fcsr.bits))" }, { "number": 14, "source": "function clause ext_write_CSR (_, _) = None()", "pattern": { "type": "tuple", "patterns": [ { "type": "wildcard" }, { "type": "wildcard" } ] }, "body": "None()" } ], "links": [ { "type": "function", "id": "None", "file": "model/riscv_csr_ext.sail", "loc": [ 1101, 1105 ] }, { "type": "function", "id": "Some", "file": "model/riscv_fdext_control.sail", "loc": [ 1905, 1909 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_fdext_control.sail", "loc": [ 1910, 1921 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1922, 1926 ] }, { "type": "function", "id": "ext_write_fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1863, 1877 ] }, { "type": "function", "id": "Some", "file": "model/riscv_fdext_control.sail", "loc": [ 1783, 1787 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_fdext_control.sail", "loc": [ 1788, 1799 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1800, 1804 ] }, { "type": "function", "id": "ext_write_fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1740, 1754 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1768, 1772 ] }, { "type": "function", "id": "Some", "file": "model/riscv_fdext_control.sail", "loc": [ 1657, 1661 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_fdext_control.sail", "loc": [ 1662, 1673 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1674, 1678 ] }, { "type": "function", "id": "ext_write_fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1617, 1631 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_control.sail", "loc": [ 1632, 1636 ] }, { "type": "function", "id": "legalize_uip", "file": "model/riscv_next_control.sail", "loc": [ 2815, 2827 ] }, { "type": "register", "id": "sideleg", "file": "model/riscv_next_control.sail", "loc": [ 2853, 2860 ] }, { "type": "function", "id": "lower_mip", "file": "model/riscv_next_control.sail", "loc": [ 2828, 2837 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_next_control.sail", "loc": [ 2843, 2850 ] }, { "type": "register", "id": "mip", "file": "model/riscv_next_control.sail", "loc": [ 2838, 2841 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 3003, 3007 ] }, { "type": "register", "id": "mip", "file": "model/riscv_next_control.sail", "loc": [ 3008, 3011 ] }, { "type": "register", "id": "mip", "file": "model/riscv_next_control.sail", "loc": [ 2919, 2922 ] }, { "type": "function", "id": "lift_sip", "file": "model/riscv_next_control.sail", "loc": [ 2925, 2933 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_next_control.sail", "loc": [ 2939, 2946 ] }, { "type": "register", "id": "mip", "file": "model/riscv_next_control.sail", "loc": [ 2934, 2937 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 2743, 2747 ] }, { "type": "register", "id": "utval", "file": "model/riscv_next_control.sail", "loc": [ 2748, 2753 ] }, { "type": "register", "id": "utval", "file": "model/riscv_next_control.sail", "loc": [ 2728, 2733 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 2660, 2664 ] }, { "type": "register", "id": "ucause", "file": "model/riscv_next_control.sail", "loc": [ 2665, 2671 ] }, { "type": "register", "id": "ucause", "file": "model/riscv_next_control.sail", "loc": [ 2639, 2645 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 2554, 2558 ] }, { "type": "function", "id": "set_xret_target", "file": "model/riscv_next_control.sail", "loc": [ 2559, 2574 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 2489, 2493 ] }, { "type": "register", "id": "uscratch", "file": "model/riscv_next_control.sail", "loc": [ 2494, 2502 ] }, { "type": "register", "id": "uscratch", "file": "model/riscv_next_control.sail", "loc": [ 2471, 2479 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 2398, 2402 ] }, { "type": "function", "id": "set_utvec", "file": "model/riscv_next_control.sail", "loc": [ 2403, 2412 ] }, { "type": "function", "id": "legalize_uie", "file": "model/riscv_next_control.sail", "loc": [ 2145, 2157 ] }, { "type": "register", "id": "sideleg", "file": "model/riscv_next_control.sail", "loc": [ 2183, 2190 ] }, { "type": "function", "id": "lower_mie", "file": "model/riscv_next_control.sail", "loc": [ 2158, 2167 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_next_control.sail", "loc": [ 2173, 2180 ] }, { "type": "register", "id": "mie", "file": "model/riscv_next_control.sail", "loc": [ 2168, 2171 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 2333, 2337 ] }, { "type": "register", "id": "mie", "file": "model/riscv_next_control.sail", "loc": [ 2338, 2341 ] }, { "type": "register", "id": "mie", "file": "model/riscv_next_control.sail", "loc": [ 2249, 2252 ] }, { "type": "function", "id": "lift_sie", "file": "model/riscv_next_control.sail", "loc": [ 2255, 2263 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_next_control.sail", "loc": [ 2269, 2276 ] }, { "type": "register", "id": "mie", "file": "model/riscv_next_control.sail", "loc": [ 2264, 2267 ] }, { "type": "function", "id": "Some", "file": "model/riscv_next_control.sail", "loc": [ 2066, 2070 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_next_control.sail", "loc": [ 2071, 2078 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_next_control.sail", "loc": [ 2022, 2029 ] }, { "type": "function", "id": "legalize_ustatus", "file": "model/riscv_next_control.sail", "loc": [ 2032, 2048 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_next_control.sail", "loc": [ 2049, 2056 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1790, 1794 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1795, 1806 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1807, 1811 ] }, { "type": "function", "id": "ext_write_vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1741, 1755 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1660, 1664 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1665, 1676 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1677, 1681 ] }, { "type": "function", "id": "ext_write_vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1615, 1629 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1646, 1650 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vext_control.sail", "loc": [ 1533, 1537 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_control.sail", "loc": [ 1538, 1549 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1550, 1554 ] }, { "type": "function", "id": "ext_write_vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1489, 1503 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_control.sail", "loc": [ 1505, 1509 ] } ] }, "ext_write_fcsr": { "function": { "number": 0, "source": "function ext_write_fcsr (frm, fflags) = {\n fcsr[FRM] = frm; /* Note: frm can be an illegal value, 101, 110, 111 */\n fcsr[FFLAGS] = fflags;\n dirty_fd_context_if_present();\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "frm" }, { "type": "id", "id": "fflags" } ] }, "body": " fcsr[FRM] = frm; /* Note: frm can be an illegal value, 101, 110, 111 */\n fcsr[FFLAGS] = fflags;\n dirty_fd_context_if_present()" }, "links": [ { "type": "function", "id": "dirty_fd_context_if_present", "file": "model/riscv_fdext_regs.sail", "loc": [ 12137, 12164 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_regs.sail", "loc": [ 12112, 12116 ] }, { "type": "register", "id": "fcsr", "file": "model/riscv_fdext_regs.sail", "loc": [ 12030, 12034 ] } ] }, "ext_write_vcsr": { "function": { "number": 0, "source": "function ext_write_vcsr (vxrm_val, vxsat_val) = {\n vcsr[vxrm] = vxrm_val; /* Note: frm can be an illegal value, 101, 110, 111 */\n vcsr[vxsat] = vxsat_val;\n dirty_v_context_if_present()\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vxrm_val" }, { "type": "id", "id": "vxsat_val" } ] }, "body": " vcsr[vxrm] = vxrm_val; /* Note: frm can be an illegal value, 101, 110, 111 */\n vcsr[vxsat] = vxsat_val;\n dirty_v_context_if_present()" }, "links": [ { "type": "function", "id": "dirty_v_context_if_present", "file": "model/riscv_vext_regs.sail", "loc": [ 5506, 5532 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_regs.sail", "loc": [ 5479, 5483 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_vext_regs.sail", "loc": [ 5398, 5402 ] } ] }, "extend_value": { "function": { "number": 0, "source": "function extend_value(is_unsigned, value) = match (value) {\n MemValue(v) => MemValue(if is_unsigned then zero_extend(v) else sign_extend(v) : xlenbits),\n MemException(e) => MemException(e)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "is_unsigned" }, { "type": "id", "id": "value" } ] }, "body": "match (value) {\n MemValue(v) => MemValue(if is_unsigned then zero_extend(v) else sign_extend(v) : xlenbits),\n MemException(e) => MemException(e)\n}" }, "links": [ { "type": "function", "id": "MemException", "file": "model/riscv_insts_base.sail", "loc": [ 11706, 11718 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_insts_base.sail", "loc": [ 11608, 11616 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_base.sail", "loc": [ 11637, 11648 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_insts_base.sail", "loc": [ 11657, 11668 ] } ] }, "extop_zbb_of_num": { "function": { "number": 0, "source": "extop_zbb_of_num arg# = $[complete] match arg# {\n 0 => RISCV_SEXTB,\n 1 => RISCV_SEXTH,\n _ => RISCV_ZEXTH\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_SEXTB,\n 1 => RISCV_SEXTH,\n _ => RISCV_ZEXTH\n}" } }, "f_bin_op_D_of_num": { "function": { "number": 0, "source": "f_bin_op_D_of_num arg# = $[complete] match arg# {\n 0 => FSGNJ_D,\n 1 => FSGNJN_D,\n 2 => FSGNJX_D,\n 3 => FMIN_D,\n 4 => FMAX_D,\n 5 => FEQ_D,\n 6 => FLT_D,\n _ => FLE_D\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FSGNJ_D,\n 1 => FSGNJN_D,\n 2 => FSGNJX_D,\n 3 => FMIN_D,\n 4 => FMAX_D,\n 5 => FEQ_D,\n 6 => FLT_D,\n _ => FLE_D\n}" } }, "f_bin_op_H_of_num": { "function": { "number": 0, "source": "f_bin_op_H_of_num arg# = $[complete] match arg# {\n 0 => FSGNJ_H,\n 1 => FSGNJN_H,\n 2 => FSGNJX_H,\n 3 => FMIN_H,\n 4 => FMAX_H,\n 5 => FEQ_H,\n 6 => FLT_H,\n _ => FLE_H\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FSGNJ_H,\n 1 => FSGNJN_H,\n 2 => FSGNJX_H,\n 3 => FMIN_H,\n 4 => FMAX_H,\n 5 => FEQ_H,\n 6 => FLT_H,\n _ => FLE_H\n}" } }, "f_bin_op_S_of_num": { "function": { "number": 0, "source": "f_bin_op_S_of_num arg# = $[complete] match arg# {\n 0 => FSGNJ_S,\n 1 => FSGNJN_S,\n 2 => FSGNJX_S,\n 3 => FMIN_S,\n 4 => FMAX_S,\n 5 => FEQ_S,\n 6 => FLT_S,\n _ => FLE_S\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FSGNJ_S,\n 1 => FSGNJN_S,\n 2 => FSGNJX_S,\n 3 => FMIN_S,\n 4 => FMAX_S,\n 5 => FEQ_S,\n 6 => FLT_S,\n _ => FLE_S\n}" } }, "f_bin_rm_op_D_of_num": { "function": { "number": 0, "source": "f_bin_rm_op_D_of_num arg# = $[complete] match arg# {\n 0 => FADD_D,\n 1 => FSUB_D,\n 2 => FMUL_D,\n _ => FDIV_D\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FADD_D,\n 1 => FSUB_D,\n 2 => FMUL_D,\n _ => FDIV_D\n}" } }, "f_bin_rm_op_H_of_num": { "function": { "number": 0, "source": "f_bin_rm_op_H_of_num arg# = $[complete] match arg# {\n 0 => FADD_H,\n 1 => FSUB_H,\n 2 => FMUL_H,\n _ => FDIV_H\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FADD_H,\n 1 => FSUB_H,\n 2 => FMUL_H,\n _ => FDIV_H\n}" } }, "f_bin_rm_op_S_of_num": { "function": { "number": 0, "source": "f_bin_rm_op_S_of_num arg# = $[complete] match arg# {\n 0 => FADD_S,\n 1 => FSUB_S,\n 2 => FMUL_S,\n _ => FDIV_S\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FADD_S,\n 1 => FSUB_S,\n 2 => FMUL_S,\n _ => FDIV_S\n}" } }, "f_is_NaN": { "function": { "number": 0, "source": "function f_is_NaN(xf) = {\n match 'm {\n 16 => f_is_NaN_H(xf),\n 32 => f_is_NaN_S(xf),\n 64 => f_is_NaN_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_NaN_H(xf),\n 32 => f_is_NaN_S(xf),\n 64 => f_is_NaN_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_NaN_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20459, 20469 ] }, { "type": "function", "id": "f_is_NaN_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20433, 20443 ] }, { "type": "function", "id": "f_is_NaN_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20407, 20417 ] } ] }, "f_is_NaN_D": { "function": { "number": 0, "source": "function f_is_NaN_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (exp == ones())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (exp == ones())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 4402, 4410 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_dext.sail", "loc": [ 4431, 4435 ] } ] }, "f_is_NaN_H": { "function": { "number": 0, "source": "function f_is_NaN_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (exp == ones())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (exp == ones())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 4131, 4139 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfh.sail", "loc": [ 4161, 4165 ] } ] }, "f_is_NaN_S": { "function": { "number": 0, "source": "function f_is_NaN_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (exp == ones())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (exp == ones())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5275, 5283 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_fext.sail", "loc": [ 5304, 5308 ] } ] }, "f_is_QNaN": { "function": { "number": 0, "source": "function f_is_QNaN(xf) = {\n match 'm {\n 16 => f_is_QNaN_H(xf),\n 32 => f_is_QNaN_S(xf),\n 64 => f_is_QNaN_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_QNaN_H(xf),\n 32 => f_is_QNaN_S(xf),\n 64 => f_is_QNaN_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_QNaN_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20272, 20283 ] }, { "type": "function", "id": "f_is_QNaN_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20245, 20256 ] }, { "type": "function", "id": "f_is_QNaN_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20218, 20229 ] } ] }, "f_is_QNaN_D": { "function": { "number": 0, "source": "function f_is_QNaN_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (exp == ones())\n & (mant [51] == bitone))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (exp == ones())\n & (mant [51] == bitone))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 4213, 4221 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_dext.sail", "loc": [ 4242, 4246 ] } ] }, "f_is_QNaN_H": { "function": { "number": 0, "source": "function f_is_QNaN_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (exp == ones())\n & (mant [9] == bitone))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (exp == ones())\n & (mant [9] == bitone))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 3941, 3949 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfh.sail", "loc": [ 3971, 3975 ] } ] }, "f_is_QNaN_S": { "function": { "number": 0, "source": "function f_is_QNaN_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (exp == ones())\n & (mant [22] == bitone))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (exp == ones())\n & (mant [22] == bitone))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5086, 5094 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_fext.sail", "loc": [ 5115, 5119 ] } ] }, "f_is_SNaN": { "function": { "number": 0, "source": "function f_is_SNaN(xf) = {\n match 'm {\n 16 => f_is_SNaN_H(xf),\n 32 => f_is_SNaN_S(xf),\n 64 => f_is_SNaN_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_SNaN_H(xf),\n 32 => f_is_SNaN_S(xf),\n 64 => f_is_SNaN_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_SNaN_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20081, 20092 ] }, { "type": "function", "id": "f_is_SNaN_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20054, 20065 ] }, { "type": "function", "id": "f_is_SNaN_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 20027, 20038 ] } ] }, "f_is_SNaN_D": { "function": { "number": 0, "source": "function f_is_SNaN_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (exp == ones())\n & (mant [51] == bitzero)\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (exp == ones())\n & (mant [51] == bitzero)\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 4024, 4032 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_dext.sail", "loc": [ 4053, 4057 ] } ] }, "f_is_SNaN_H": { "function": { "number": 0, "source": "function f_is_SNaN_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (exp == ones())\n & (mant [9] == bitzero)\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (exp == ones())\n & (mant [9] == bitzero)\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 3751, 3759 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfh.sail", "loc": [ 3781, 3785 ] } ] }, "f_is_SNaN_S": { "function": { "number": 0, "source": "function f_is_SNaN_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (exp == ones())\n & (mant [22] == bitzero)\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (exp == ones())\n & (mant [22] == bitzero)\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 4897, 4905 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_fext.sail", "loc": [ 4926, 4930 ] } ] }, "f_is_neg_inf": { "function": { "number": 0, "source": "function f_is_neg_inf(xf) = {\n match 'm {\n 16 => f_is_neg_inf_H(xf),\n 32 => f_is_neg_inf_S(xf),\n 64 => f_is_neg_inf_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_neg_inf_H(xf),\n 32 => f_is_neg_inf_S(xf),\n 64 => f_is_neg_inf_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_neg_inf_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18385, 18399 ] }, { "type": "function", "id": "f_is_neg_inf_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18355, 18369 ] }, { "type": "function", "id": "f_is_neg_inf_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18325, 18339 ] } ] }, "f_is_neg_inf_D": { "function": { "number": 0, "source": "function f_is_neg_inf_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == 0b1)\n & (exp == ones())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == 0b1)\n & (exp == ones())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 2487, 2495 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_dext.sail", "loc": [ 2536, 2540 ] } ] }, "f_is_neg_inf_H": { "function": { "number": 0, "source": "function f_is_neg_inf_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == 0b1)\n & (exp == ones())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == 0b1)\n & (exp == ones())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 2198, 2206 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfh.sail", "loc": [ 2248, 2252 ] } ] }, "f_is_neg_inf_S": { "function": { "number": 0, "source": "function f_is_neg_inf_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == 0b1)\n & (exp == ones())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == 0b1)\n & (exp == ones())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 3360, 3368 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_fext.sail", "loc": [ 3409, 3413 ] } ] }, "f_is_neg_norm": { "function": { "number": 0, "source": "function f_is_neg_norm(xf) = {\n match 'm {\n 16 => f_is_neg_norm_H(xf),\n 32 => f_is_neg_norm_S(xf),\n 64 => f_is_neg_norm_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_neg_norm_H(xf),\n 32 => f_is_neg_norm_S(xf),\n 64 => f_is_neg_norm_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_neg_norm_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18595, 18610 ] }, { "type": "function", "id": "f_is_neg_norm_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18564, 18579 ] }, { "type": "function", "id": "f_is_neg_norm_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18533, 18548 ] } ] }, "f_is_neg_norm_D": { "function": { "number": 0, "source": "function f_is_neg_norm_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == 0b1)\n & (exp != zeros())\n & (exp != ones()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == 0b1)\n & (exp != zeros())\n & (exp != ones()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 2676, 2684 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_dext.sail", "loc": [ 2748, 2752 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_neg_norm_H": { "function": { "number": 0, "source": "function f_is_neg_norm_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == 0b1)\n & (exp != zeros())\n & (exp != ones()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == 0b1)\n & (exp != zeros())\n & (exp != ones()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 2389, 2397 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfh.sail", "loc": [ 2462, 2466 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_neg_norm_S": { "function": { "number": 0, "source": "function f_is_neg_norm_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == 0b1)\n & (exp != zeros())\n & (exp != ones()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == 0b1)\n & (exp != zeros())\n & (exp != ones()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 3549, 3557 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_fext.sail", "loc": [ 3621, 3625 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_neg_subnorm": { "function": { "number": 0, "source": "function f_is_neg_subnorm(xf) = {\n match 'm {\n 16 => f_is_neg_subnorm_H(xf),\n 32 => f_is_neg_subnorm_S(xf),\n 64 => f_is_neg_subnorm_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_neg_subnorm_H(xf),\n 32 => f_is_neg_subnorm_S(xf),\n 64 => f_is_neg_subnorm_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_neg_subnorm_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18818, 18836 ] }, { "type": "function", "id": "f_is_neg_subnorm_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18784, 18802 ] }, { "type": "function", "id": "f_is_neg_subnorm_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18750, 18768 ] } ] }, "f_is_neg_subnorm_D": { "function": { "number": 0, "source": "function f_is_neg_subnorm_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == 0b1)\n & (exp == zeros())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == 0b1)\n & (exp == zeros())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 2871, 2879 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_neg_subnorm_H": { "function": { "number": 0, "source": "function f_is_neg_subnorm_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == 0b1)\n & (exp == zeros())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == 0b1)\n & (exp == zeros())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 2586, 2594 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_neg_subnorm_S": { "function": { "number": 0, "source": "function f_is_neg_subnorm_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == 0b1)\n & (exp == zeros())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == 0b1)\n & (exp == zeros())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 3744, 3752 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_neg_zero": { "function": { "number": 0, "source": "function f_is_neg_zero(xf) = {\n match 'm {\n 16 => f_is_neg_zero_H(xf),\n 32 => f_is_neg_zero_S(xf),\n 64 => f_is_neg_zero_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_neg_zero_H(xf),\n 32 => f_is_neg_zero_S(xf),\n 64 => f_is_neg_zero_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_neg_zero_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19032, 19047 ] }, { "type": "function", "id": "f_is_neg_zero_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19001, 19016 ] }, { "type": "function", "id": "f_is_neg_zero_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 18970, 18985 ] } ] }, "f_is_neg_zero_D": { "function": { "number": 0, "source": "function f_is_neg_zero_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == ones())\n & (exp == zeros())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == ones())\n & (exp == zeros())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 3061, 3069 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_dext.sail", "loc": [ 3091, 3095 ] } ] }, "f_is_neg_zero_H": { "function": { "number": 0, "source": "function f_is_neg_zero_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == ones())\n & (exp == zeros())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == ones())\n & (exp == zeros())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 3368, 3376 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfh.sail", "loc": [ 3399, 3403 ] } ] }, "f_is_neg_zero_S": { "function": { "number": 0, "source": "function f_is_neg_zero_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == ones())\n & (exp == zeros())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == ones())\n & (exp == zeros())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 3934, 3942 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_fext.sail", "loc": [ 3964, 3968 ] } ] }, "f_is_pos_inf": { "function": { "number": 0, "source": "function f_is_pos_inf(xf) = {\n match 'm {\n 16 => f_is_pos_inf_H(xf),\n 32 => f_is_pos_inf_S(xf),\n 64 => f_is_pos_inf_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_pos_inf_H(xf),\n 32 => f_is_pos_inf_S(xf),\n 64 => f_is_pos_inf_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_pos_inf_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19887, 19901 ] }, { "type": "function", "id": "f_is_pos_inf_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19857, 19871 ] }, { "type": "function", "id": "f_is_pos_inf_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19827, 19841 ] } ] }, "f_is_pos_inf_D": { "function": { "number": 0, "source": "function f_is_pos_inf_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == zeros())\n & (exp == ones())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == zeros())\n & (exp == ones())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 3839, 3847 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_dext.sail", "loc": [ 3892, 3896 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_inf_H": { "function": { "number": 0, "source": "function f_is_pos_inf_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == zeros())\n & (exp == ones())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == zeros())\n & (exp == ones())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 3173, 3181 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfh.sail", "loc": [ 3227, 3231 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_inf_S": { "function": { "number": 0, "source": "function f_is_pos_inf_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == zeros())\n & (exp == ones())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == zeros())\n & (exp == ones())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 4712, 4720 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_fext.sail", "loc": [ 4765, 4769 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_norm": { "function": { "number": 0, "source": "function f_is_pos_norm(xf) = {\n match 'm {\n 16 => f_is_pos_norm_H(xf),\n 32 => f_is_pos_norm_S(xf),\n 64 => f_is_pos_norm_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_pos_norm_H(xf),\n 32 => f_is_pos_norm_S(xf),\n 64 => f_is_pos_norm_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_pos_norm_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19680, 19695 ] }, { "type": "function", "id": "f_is_pos_norm_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19649, 19664 ] }, { "type": "function", "id": "f_is_pos_norm_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19618, 19633 ] } ] }, "f_is_pos_norm_D": { "function": { "number": 0, "source": "function f_is_pos_norm_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == zeros())\n & (exp != zeros())\n & (exp != ones()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == zeros())\n & (exp != zeros())\n & (exp != ones()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 3648, 3656 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_dext.sail", "loc": [ 3724, 3728 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_norm_H": { "function": { "number": 0, "source": "function f_is_pos_norm_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == zeros())\n & (exp != zeros())\n & (exp != ones()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == zeros())\n & (exp != zeros())\n & (exp != ones()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 2980, 2988 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfh.sail", "loc": [ 3057, 3061 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_norm_S": { "function": { "number": 0, "source": "function f_is_pos_norm_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == zeros())\n & (exp != zeros())\n & (exp != ones()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == zeros())\n & (exp != zeros())\n & (exp != ones()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 4521, 4529 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_fext.sail", "loc": [ 4597, 4601 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_subnorm": { "function": { "number": 0, "source": "function f_is_pos_subnorm(xf) = {\n match 'm {\n 16 => f_is_pos_subnorm_H(xf),\n 32 => f_is_pos_subnorm_S(xf),\n 64 => f_is_pos_subnorm_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_pos_subnorm_H(xf),\n 32 => f_is_pos_subnorm_S(xf),\n 64 => f_is_pos_subnorm_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_pos_subnorm_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19466, 19484 ] }, { "type": "function", "id": "f_is_pos_subnorm_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19432, 19450 ] }, { "type": "function", "id": "f_is_pos_subnorm_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19398, 19416 ] } ] }, "f_is_pos_subnorm_D": { "function": { "number": 0, "source": "function f_is_pos_subnorm_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 3454, 3462 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_subnorm_H": { "function": { "number": 0, "source": "function f_is_pos_subnorm_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 2784, 2792 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_subnorm_S": { "function": { "number": 0, "source": "function f_is_pos_subnorm_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant != zeros()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant != zeros()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 4327, 4335 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_zero": { "function": { "number": 0, "source": "function f_is_pos_zero(xf) = {\n match 'm {\n 16 => f_is_pos_zero_H(xf),\n 32 => f_is_pos_zero_S(xf),\n 64 => f_is_pos_zero_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => f_is_pos_zero_H(xf),\n 32 => f_is_pos_zero_S(xf),\n 64 => f_is_pos_zero_D(xf)\n }" }, "links": [ { "type": "function", "id": "f_is_pos_zero_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19243, 19258 ] }, { "type": "function", "id": "f_is_pos_zero_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19212, 19227 ] }, { "type": "function", "id": "f_is_pos_zero_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 19181, 19196 ] } ] }, "f_is_pos_zero_D": { "function": { "number": 0, "source": "function f_is_pos_zero_D x64 = {\n let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 3254, 3262 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_zero_H": { "function": { "number": 0, "source": "function f_is_pos_zero_H xf16 = {\n let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 3563, 3571 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_is_pos_zero_S": { "function": { "number": 0, "source": "function f_is_pos_zero_S x32 = {\n let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant == zeros()))\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n ( (sign == zeros())\n & (exp == zeros())\n & (mant == zeros()))" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 4127, 4135 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "f_madd_op_D_of_num": { "function": { "number": 0, "source": "f_madd_op_D_of_num arg# = $[complete] match arg# {\n 0 => FMADD_D,\n 1 => FMSUB_D,\n 2 => FNMSUB_D,\n _ => FNMADD_D\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FMADD_D,\n 1 => FMSUB_D,\n 2 => FNMSUB_D,\n _ => FNMADD_D\n}" } }, "f_madd_op_H_of_num": { "function": { "number": 0, "source": "f_madd_op_H_of_num arg# = $[complete] match arg# {\n 0 => FMADD_H,\n 1 => FMSUB_H,\n 2 => FNMSUB_H,\n _ => FNMADD_H\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FMADD_H,\n 1 => FMSUB_H,\n 2 => FNMSUB_H,\n _ => FNMADD_H\n}" } }, "f_madd_op_S_of_num": { "function": { "number": 0, "source": "f_madd_op_S_of_num arg# = $[complete] match arg# {\n 0 => FMADD_S,\n 1 => FMSUB_S,\n 2 => FNMSUB_S,\n _ => FNMADD_S\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FMADD_S,\n 1 => FMSUB_S,\n 2 => FNMSUB_S,\n _ => FNMADD_S\n}" } }, "f_un_op_D_of_num": { "function": { "number": 0, "source": "f_un_op_D_of_num arg# = $[complete] match arg# {\n 0 => FCLASS_D,\n 1 => FMV_X_D,\n _ => FMV_D_X\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FCLASS_D,\n 1 => FMV_X_D,\n _ => FMV_D_X\n}" } }, "f_un_op_H_of_num": { "function": { "number": 0, "source": "f_un_op_H_of_num arg# = $[complete] match arg# {\n 0 => FCLASS_H,\n 1 => FMV_X_H,\n _ => FMV_H_X\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FCLASS_H,\n 1 => FMV_X_H,\n _ => FMV_H_X\n}" } }, "f_un_op_S_of_num": { "function": { "number": 0, "source": "f_un_op_S_of_num arg# = $[complete] match arg# {\n 0 => FCLASS_S,\n 1 => FMV_X_W,\n _ => FMV_W_X\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FCLASS_S,\n 1 => FMV_X_W,\n _ => FMV_W_X\n}" } }, "f_un_rm_op_D_of_num": { "function": { "number": 0, "source": "f_un_rm_op_D_of_num arg# = $[complete] match arg# {\n 0 => FSQRT_D,\n 1 => FCVT_W_D,\n 2 => FCVT_WU_D,\n 3 => FCVT_D_W,\n 4 => FCVT_D_WU,\n 5 => FCVT_S_D,\n 6 => FCVT_D_S,\n 7 => FCVT_L_D,\n 8 => FCVT_LU_D,\n 9 => FCVT_D_L,\n _ => FCVT_D_LU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FSQRT_D,\n 1 => FCVT_W_D,\n 2 => FCVT_WU_D,\n 3 => FCVT_D_W,\n 4 => FCVT_D_WU,\n 5 => FCVT_S_D,\n 6 => FCVT_D_S,\n 7 => FCVT_L_D,\n 8 => FCVT_LU_D,\n 9 => FCVT_D_L,\n _ => FCVT_D_LU\n}" } }, "f_un_rm_op_H_of_num": { "function": { "number": 0, "source": "f_un_rm_op_H_of_num arg# = $[complete] match arg# {\n 0 => FSQRT_H,\n 1 => FCVT_W_H,\n 2 => FCVT_WU_H,\n 3 => FCVT_H_W,\n 4 => FCVT_H_WU,\n 5 => FCVT_H_S,\n 6 => FCVT_H_D,\n 7 => FCVT_S_H,\n 8 => FCVT_D_H,\n 9 => FCVT_L_H,\n 10 => FCVT_LU_H,\n 11 => FCVT_H_L,\n _ => FCVT_H_LU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FSQRT_H,\n 1 => FCVT_W_H,\n 2 => FCVT_WU_H,\n 3 => FCVT_H_W,\n 4 => FCVT_H_WU,\n 5 => FCVT_H_S,\n 6 => FCVT_H_D,\n 7 => FCVT_S_H,\n 8 => FCVT_D_H,\n 9 => FCVT_L_H,\n 10 => FCVT_LU_H,\n 11 => FCVT_H_L,\n _ => FCVT_H_LU\n}" } }, "f_un_rm_op_S_of_num": { "function": { "number": 0, "source": "f_un_rm_op_S_of_num arg# = $[complete] match arg# {\n 0 => FSQRT_S,\n 1 => FCVT_W_S,\n 2 => FCVT_WU_S,\n 3 => FCVT_S_W,\n 4 => FCVT_S_WU,\n 5 => FCVT_L_S,\n 6 => FCVT_LU_S,\n 7 => FCVT_S_L,\n _ => FCVT_S_LU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FSQRT_S,\n 1 => FCVT_W_S,\n 2 => FCVT_WU_S,\n 3 => FCVT_S_W,\n 4 => FCVT_S_WU,\n 5 => FCVT_L_S,\n 6 => FCVT_LU_S,\n 7 => FCVT_S_L,\n _ => FCVT_S_LU\n}" } }, "fcvtmod_helper": { "function": { "number": 0, "source": "function fcvtmod_helper(x64) = {\n let (sign, exp, mant) = fsplit_D(x64);\n\n /* Detect the non-normal cases */\n let is_subnorm = exp == zeros() & mant != zeros();\n let is_zero = exp == zeros() & mant == zeros();\n let is_nan_or_inf = exp == ones();\n\n /* For normal numbers, the mantissa and exponent use special encoding */\n let true_mant = 0b1 @ mant; /* concatenate with the implicit bit */\n let true_exp = unsigned(exp) - 1023; /* undo the offset-binary */\n\n /*\n * Detect the trivial cases for normal numbers.\n *\n * While is_too_large could subsume is_nan_or_inf, and is_too_small\n * cound subsume is_subnorm, we deliberately enumerate these\n * separately as is_too_large/is_too_small operate on normal\n * numbers.\n */\n let is_too_large = true_exp >= 84; /* bits will be 'multiplied' out */\n let is_too_small = true_exp < 0; /* bits will be 'divided' out */\n\n if is_zero then (zeros(), zeros())\n else if is_subnorm then (nxFlag(), zeros())\n else if is_nan_or_inf then (nvFlag(), zeros())\n else if is_too_large then (nvFlag(), zeros())\n else if is_too_small then (nxFlag(), zeros())\n else {\n /*\n * Calculate the low 32 bits of the integer value from the\n * binary64 floating-point number and return them together with an\n * indicator whether a NV (overflow) or NX (inexact) exceptions is\n * to be raised.\n */\n\n /* Perform the exponentation on the fixed-point mantissa and\n extract the integer part */\n let fixedpoint : bits(84) = zero_extend(true_mant) << true_exp;\n let integer = fixedpoint[83..52];\n let fractional = fixedpoint[51..0];\n\n /* Apply the sign bit */\n let result = if sign == 0b1 then ~(integer) + 1\n else integer;\n\n /* Raise FP exception flags, honoring the precedence of nV > nX */\n let flags : bits(5) = if (true_exp > 31) then nvFlag()\n else if (fractional != zeros()) then nxFlag()\n else zeros();\n\n (flags, result)\n }\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D(x64);\n\n /* Detect the non-normal cases */\n let is_subnorm = exp == zeros() & mant != zeros();\n let is_zero = exp == zeros() & mant == zeros();\n let is_nan_or_inf = exp == ones();\n\n /* For normal numbers, the mantissa and exponent use special encoding */\n let true_mant = 0b1 @ mant; /* concatenate with the implicit bit */\n let true_exp = unsigned(exp) - 1023; /* undo the offset-binary */\n\n /*\n * Detect the trivial cases for normal numbers.\n *\n * While is_too_large could subsume is_nan_or_inf, and is_too_small\n * cound subsume is_subnorm, we deliberately enumerate these\n * separately as is_too_large/is_too_small operate on normal\n * numbers.\n */\n let is_too_large = true_exp >= 84; /* bits will be 'multiplied' out */\n let is_too_small = true_exp < 0; /* bits will be 'divided' out */\n\n if is_zero then (zeros(), zeros())\n else if is_subnorm then (nxFlag(), zeros())\n else if is_nan_or_inf then (nvFlag(), zeros())\n else if is_too_large then (nvFlag(), zeros())\n else if is_too_small then (nxFlag(), zeros())\n else {\n /*\n * Calculate the low 32 bits of the integer value from the\n * binary64 floating-point number and return them together with an\n * indicator whether a NV (overflow) or NX (inexact) exceptions is\n * to be raised.\n */\n\n /* Perform the exponentation on the fixed-point mantissa and\n extract the integer part */\n let fixedpoint : bits(84) = zero_extend(true_mant) << true_exp;\n let integer = fixedpoint[83..52];\n let fractional = fixedpoint[51..0];\n\n /* Apply the sign bit */\n let result = if sign == 0b1 then ~(integer) + 1\n else integer;\n\n /* Raise FP exception flags, honoring the precedence of nV > nX */\n let flags : bits(5) = if (true_exp > 31) then nvFlag()\n else if (fractional != zeros()) then nxFlag()\n else zeros();\n\n (flags, result)\n }" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_zfa.sail", "loc": [ 24998, 25006 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_zfa.sail", "loc": [ 25191, 25195 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfa.sail", "loc": [ 25372, 25380 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_zfa.sail", "loc": [ 25932, 25938 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_zfa.sail", "loc": [ 25981, 25987 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_zfa.sail", "loc": [ 26030, 26036 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_zfa.sail", "loc": [ 26079, 26085 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zfa.sail", "loc": [ 26481, 26492 ] }, { "type": "function", "id": "not_vec", "file": "model/prelude.sail", "loc": [ 997, 1004 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_zfa.sail", "loc": [ 26856, 26862 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_zfa.sail", "loc": [ 26923, 26929 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "fdiv_int": { "function": { "number": 0, "source": "fdiv_int (n : int, m : int) = {\n if and_bool(lt_int(n, 0), gt_int(m, 0)) then {\n sub_atom(tdiv_int(add_atom(n, 1), m), 1)\n } else if and_bool(gt_int(n, 0), lt_int(m, 0)) then {\n sub_atom(tdiv_int(sub_atom(n, 1), m), 1)\n } else {\n tdiv_int(n, m)\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "m" } ] }, "body": "if and_bool(lt_int(n, 0), gt_int(m, 0)) then {\n sub_atom(tdiv_int(add_atom(n, 1), m), 1)\n} else if and_bool(gt_int(n, 0), lt_int(m, 0)) then {\n sub_atom(tdiv_int(sub_atom(n, 1), m), 1)\n} else {\n tdiv_int(n, m)\n}" } }, "feq_quiet_D": { "function": { "number": 0, "source": "function feq_quiet_D (v1, v2) = {\n let (s1, e1, m1) = fsplit_D (v1);\n let (s2, e2, m2) = fsplit_D (v2);\n\n let v1Is0 = f_is_neg_zero_D(v1) | f_is_pos_zero_D(v1);\n let v2Is0 = f_is_neg_zero_D(v2) | f_is_pos_zero_D(v2);\n\n let result = ((v1 == v2) | (v1Is0 & v2Is0));\n\n let fflags = if (f_is_SNaN_D(v1) | f_is_SNaN_D(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " let (s1, e1, m1) = fsplit_D (v1);\n let (s2, e2, m2) = fsplit_D (v2);\n\n let v1Is0 = f_is_neg_zero_D(v1) | f_is_pos_zero_D(v1);\n let v2Is0 = f_is_neg_zero_D(v2) | f_is_pos_zero_D(v2);\n\n let result = ((v1 == v2) | (v1Is0 & v2Is0));\n\n let fflags = if (f_is_SNaN_D(v1) | f_is_SNaN_D(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 4936, 4944 ] }, { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 4972, 4980 ] }, { "type": "function", "id": "f_is_pos_zero_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5027, 5042 ] }, { "type": "function", "id": "f_is_neg_zero_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5005, 5020 ] }, { "type": "function", "id": "f_is_pos_zero_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5087, 5102 ] }, { "type": "function", "id": "f_is_neg_zero_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5065, 5080 ] }, { "type": "function", "id": "f_is_SNaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5196, 5207 ] }, { "type": "function", "id": "f_is_SNaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5178, 5189 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_dext.sail", "loc": [ 5233, 5239 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "feq_quiet_S": { "function": { "number": 0, "source": "function feq_quiet_S (v1, v2) = {\n let (s1, e1, m1) = fsplit_S (v1);\n let (s2, e2, m2) = fsplit_S (v2);\n\n let v1Is0 = f_is_neg_zero_S(v1) | f_is_pos_zero_S(v1);\n let v2Is0 = f_is_neg_zero_S(v2) | f_is_pos_zero_S(v2);\n\n let result = ((v1 == v2) | (v1Is0 & v2Is0));\n\n let fflags = if (f_is_SNaN_S(v1) | f_is_SNaN_S(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " let (s1, e1, m1) = fsplit_S (v1);\n let (s2, e2, m2) = fsplit_S (v2);\n\n let v1Is0 = f_is_neg_zero_S(v1) | f_is_pos_zero_S(v1);\n let v2Is0 = f_is_neg_zero_S(v2) | f_is_pos_zero_S(v2);\n\n let result = ((v1 == v2) | (v1Is0 & v2Is0));\n\n let fflags = if (f_is_SNaN_S(v1) | f_is_SNaN_S(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5808, 5816 ] }, { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5844, 5852 ] }, { "type": "function", "id": "f_is_pos_zero_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5899, 5914 ] }, { "type": "function", "id": "f_is_neg_zero_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5877, 5892 ] }, { "type": "function", "id": "f_is_pos_zero_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5959, 5974 ] }, { "type": "function", "id": "f_is_neg_zero_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5937, 5952 ] }, { "type": "function", "id": "f_is_SNaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 6068, 6079 ] }, { "type": "function", "id": "f_is_SNaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 6050, 6061 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_fext.sail", "loc": [ 6105, 6111 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "fetch": { "function": { "number": 0, "source": "function fetch() -> FetchResult =\n /* fetch PC check for extensions: extensions return a transformed PC to fetch,\n * but any exceptions use the untransformed PC.\n */\n match ext_fetch_check_pc(PC, PC) {\n Ext_FetchAddr_Error(e) => F_Ext_Error(e),\n Ext_FetchAddr_OK(use_pc) => {\n if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(haveRVC())))\n then F_Error(E_Fetch_Addr_Align(), PC)\n else match translateAddr(use_pc, Execute()) {\n TR_Failure(e, _) => F_Error(e, PC),\n TR_Address(ppclo, _) => {\n /* split instruction fetch into 16-bit granules to handle RVC, as\n * well as to generate precise fault addresses in any fetch\n * exceptions.\n */\n match mem_read(Execute(), ppclo, 2, false, false, false) {\n MemException(e) => F_Error(e, PC),\n MemValue(ilo) => {\n if isRVC(ilo)\n then F_RVC(ilo)\n else {\n /* fetch PC check for the next instruction granule */\n PC_hi : xlenbits = PC + 2;\n match ext_fetch_check_pc(PC, PC_hi) {\n Ext_FetchAddr_Error(e) => F_Ext_Error(e),\n Ext_FetchAddr_OK(use_pc_hi) => {\n match translateAddr(use_pc_hi, Execute()) {\n TR_Failure(e, _) => F_Error(e, PC_hi),\n TR_Address(ppchi, _) => {\n match mem_read(Execute(), ppchi, 2, false, false, false) {\n MemException(e) => F_Error(e, PC_hi),\n MemValue(ihi) => F_Base(append(ihi, ilo))\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }", "pattern": { "type": "literal", "value": "()" }, "body": "match ext_fetch_check_pc(PC, PC) {\n Ext_FetchAddr_Error(e) => F_Ext_Error(e),\n Ext_FetchAddr_OK(use_pc) => {\n if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(haveRVC())))\n then F_Error(E_Fetch_Addr_Align(), PC)\n else match translateAddr(use_pc, Execute()) {\n TR_Failure(e, _) => F_Error(e, PC),\n TR_Address(ppclo, _) => {\n /* split instruction fetch into 16-bit granules to handle RVC, as\n * well as to generate precise fault addresses in any fetch\n * exceptions.\n */\n match mem_read(Execute(), ppclo, 2, false, false, false) {\n MemException(e) => F_Error(e, PC),\n MemValue(ilo) => {\n if isRVC(ilo)\n then F_RVC(ilo)\n else {\n /* fetch PC check for the next instruction granule */\n PC_hi : xlenbits = PC + 2;\n match ext_fetch_check_pc(PC, PC_hi) {\n Ext_FetchAddr_Error(e) => F_Ext_Error(e),\n Ext_FetchAddr_OK(use_pc_hi) => {\n match translateAddr(use_pc_hi, Execute()) {\n TR_Failure(e, _) => F_Error(e, PC_hi),\n TR_Address(ppchi, _) => {\n match mem_read(Execute(), ppchi, 2, false, false, false) {\n MemException(e) => F_Error(e, PC_hi),\n MemValue(ihi) => F_Base(append(ihi, ilo))\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }\n }" }, "links": [ { "type": "function", "id": "ext_fetch_check_pc", "file": "model/riscv_fetch.sail", "loc": [ 1048, 1066 ] }, { "type": "register", "id": "PC", "file": "model/riscv_fetch.sail", "loc": [ 1071, 1073 ] }, { "type": "register", "id": "PC", "file": "model/riscv_fetch.sail", "loc": [ 1067, 1069 ] }, { "type": "function", "id": "not", "file": "model/riscv_fetch.sail", "loc": [ 1218, 1221 ] }, { "type": "function", "id": "haveRVC", "file": "model/riscv_fetch.sail", "loc": [ 1222, 1229 ] }, { "type": "function", "id": "F_Error", "file": "model/riscv_fetch.sail", "loc": [ 1246, 1253 ] }, { "type": "register", "id": "PC", "file": "model/riscv_fetch.sail", "loc": [ 1276, 1278 ] }, { "type": "function", "id": "E_Fetch_Addr_Align", "file": "model/riscv_fetch.sail", "loc": [ 1254, 1272 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_fetch.sail", "loc": [ 1297, 1310 ] }, { "type": "function", "id": "Execute", "file": "model/riscv_fetch.sail", "loc": [ 1319, 1326 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_fetch.sail", "loc": [ 1615, 1623 ] }, { "type": "function", "id": "Execute", "file": "model/riscv_fetch.sail", "loc": [ 1624, 1631 ] }, { "type": "function", "id": "isRVC", "file": "model/riscv_fetch.sail", "loc": [ 1767, 1772 ] }, { "type": "function", "id": "F_RVC", "file": "model/riscv_fetch.sail", "loc": [ 1797, 1802 ] }, { "type": "register", "id": "PC", "file": "model/riscv_fetch.sail", "loc": [ 1934, 1936 ] }, { "type": "function", "id": "ext_fetch_check_pc", "file": "model/riscv_fetch.sail", "loc": [ 1964, 1982 ] }, { "type": "register", "id": "PC", "file": "model/riscv_fetch.sail", "loc": [ 1983, 1985 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_fetch.sail", "loc": [ 2138, 2151 ] }, { "type": "function", "id": "Execute", "file": "model/riscv_fetch.sail", "loc": [ 2163, 2170 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_fetch.sail", "loc": [ 2319, 2327 ] }, { "type": "function", "id": "Execute", "file": "model/riscv_fetch.sail", "loc": [ 2328, 2335 ] }, { "type": "function", "id": "F_Base", "file": "model/riscv_fetch.sail", "loc": [ 2481, 2487 ] }, { "type": "function", "id": "F_Error", "file": "model/riscv_fetch.sail", "loc": [ 2417, 2424 ] }, { "type": "function", "id": "F_Error", "file": "model/riscv_fetch.sail", "loc": [ 2222, 2229 ] }, { "type": "function", "id": "F_Ext_Error", "file": "model/riscv_fetch.sail", "loc": [ 2045, 2056 ] }, { "type": "function", "id": "F_Error", "file": "model/riscv_fetch.sail", "loc": [ 1699, 1706 ] }, { "type": "register", "id": "PC", "file": "model/riscv_fetch.sail", "loc": [ 1710, 1712 ] }, { "type": "function", "id": "F_Error", "file": "model/riscv_fetch.sail", "loc": [ 1364, 1371 ] }, { "type": "register", "id": "PC", "file": "model/riscv_fetch.sail", "loc": [ 1375, 1377 ] }, { "type": "function", "id": "F_Ext_Error", "file": "model/riscv_fetch.sail", "loc": [ 1109, 1120 ] } ] }, "findPendingInterrupt": { "function": { "number": 0, "source": "function findPendingInterrupt(ip : xlenbits) -> option(InterruptType) = {\n let ip = Mk_Minterrupts(ip);\n if ip[MEI] == 0b1 then Some(I_M_External)\n else if ip[MSI] == 0b1 then Some(I_M_Software)\n else if ip[MTI] == 0b1 then Some(I_M_Timer)\n else if ip[SEI] == 0b1 then Some(I_S_External)\n else if ip[SSI] == 0b1 then Some(I_S_Software)\n else if ip[STI] == 0b1 then Some(I_S_Timer)\n else if ip[UEI] == 0b1 then Some(I_U_External)\n else if ip[USI] == 0b1 then Some(I_U_Software)\n else if ip[UTI] == 0b1 then Some(I_U_Timer)\n else None()\n}", "pattern": { "type": "id", "id": "ip" }, "body": " let ip = Mk_Minterrupts(ip);\n if ip[MEI] == 0b1 then Some(I_M_External)\n else if ip[MSI] == 0b1 then Some(I_M_Software)\n else if ip[MTI] == 0b1 then Some(I_M_Timer)\n else if ip[SEI] == 0b1 then Some(I_S_External)\n else if ip[SSI] == 0b1 then Some(I_S_Software)\n else if ip[STI] == 0b1 then Some(I_S_Timer)\n else if ip[UEI] == 0b1 then Some(I_U_External)\n else if ip[USI] == 0b1 then Some(I_U_Software)\n else if ip[UTI] == 0b1 then Some(I_U_Timer)\n else None()" }, "links": [ { "type": "function", "id": "Mk_Minterrupts", "file": "model/riscv_sys_control.sail", "loc": [ 8375, 8389 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8425, 8429 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8474, 8478 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8523, 8527 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8569, 8573 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8618, 8622 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8667, 8671 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8713, 8717 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8762, 8766 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 8811, 8815 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 8858, 8862 ] } ] }, "fle_D": { "function": { "number": 0, "source": "function fle_D (v1, v2, is_quiet) = {\n let (s1, e1, m1) = fsplit_D (v1);\n let (s2, e2, m2) = fsplit_D (v2);\n\n let v1Is0 = f_is_neg_zero_D(v1) | f_is_pos_zero_D(v1);\n let v2Is0 = f_is_neg_zero_D(v2) | f_is_pos_zero_D(v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) <= unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1) then\n (v1Is0 & v2Is0) /* Equal in this case (+0=-0) */\n else if (s1 == 0b1) & (s2 == 0b0) then\n true\n else\n if (e1 == e2)\n then unsigned (m1) >= unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_D(v1) | f_is_SNaN_D(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_D(v1) | f_is_NaN_D(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" }, { "type": "id", "id": "is_quiet" } ] }, "body": " let (s1, e1, m1) = fsplit_D (v1);\n let (s2, e2, m2) = fsplit_D (v2);\n\n let v1Is0 = f_is_neg_zero_D(v1) | f_is_pos_zero_D(v1);\n let v2Is0 = f_is_neg_zero_D(v2) | f_is_pos_zero_D(v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) <= unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1) then\n (v1Is0 & v2Is0) /* Equal in this case (+0=-0) */\n else if (s1 == 0b1) & (s2 == 0b0) then\n true\n else\n if (e1 == e2)\n then unsigned (m1) >= unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_D(v1) | f_is_SNaN_D(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_D(v1) | f_is_NaN_D(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 6322, 6330 ] }, { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 6358, 6366 ] }, { "type": "function", "id": "f_is_pos_zero_D", "file": "model/riscv_insts_dext.sail", "loc": [ 6413, 6428 ] }, { "type": "function", "id": "f_is_neg_zero_D", "file": "model/riscv_insts_dext.sail", "loc": [ 6391, 6406 ] }, { "type": "function", "id": "f_is_pos_zero_D", "file": "model/riscv_insts_dext.sail", "loc": [ 6473, 6488 ] }, { "type": "function", "id": "f_is_neg_zero_D", "file": "model/riscv_insts_dext.sail", "loc": [ 6451, 6466 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 6606, 6614 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 6588, 6596 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 6649, 6657 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 6631, 6639 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 6899, 6907 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 6881, 6889 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 6942, 6950 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 6924, 6932 ] }, { "type": "function", "id": "f_is_SNaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 7031, 7042 ] }, { "type": "function", "id": "f_is_SNaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 7013, 7024 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_dext.sail", "loc": [ 7070, 7076 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "f_is_NaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 7169, 7179 ] }, { "type": "function", "id": "f_is_NaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 7152, 7162 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_dext.sail", "loc": [ 7207, 7213 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "fle_H": { "function": { "number": 0, "source": "function fle_H (v1, v2, is_quiet) = {\n let (s1, e1, m1) = fsplit_H (v1);\n let (s2, e2, m2) = fsplit_H (v2);\n\n let v1Is0 = f_is_neg_zero_H(v1) | f_is_pos_zero_H(v1);\n let v2Is0 = f_is_neg_zero_H(v2) | f_is_pos_zero_H(v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) <= unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1)\n then (v1Is0 & v2Is0) /* Equal in this case (+0=-0) */\n else if (s1 == 0b1) & (s2 == 0b0)\n then true\n else\n if (e1 == e2)\n then unsigned (m1) >= unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_H(v1) | f_is_SNaN_H(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_H(v1) | f_is_NaN_H(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" }, { "type": "id", "id": "is_quiet" } ] }, "body": " let (s1, e1, m1) = fsplit_H (v1);\n let (s2, e2, m2) = fsplit_H (v2);\n\n let v1Is0 = f_is_neg_zero_H(v1) | f_is_pos_zero_H(v1);\n let v2Is0 = f_is_neg_zero_H(v2) | f_is_pos_zero_H(v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) <= unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1)\n then (v1Is0 & v2Is0) /* Equal in this case (+0=-0) */\n else if (s1 == 0b1) & (s2 == 0b0)\n then true\n else\n if (e1 == e2)\n then unsigned (m1) >= unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_H(v1) | f_is_SNaN_H(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_H(v1) | f_is_NaN_H(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 4334, 4342 ] }, { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 4370, 4378 ] }, { "type": "function", "id": "f_is_pos_zero_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 4425, 4440 ] }, { "type": "function", "id": "f_is_neg_zero_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 4403, 4418 ] }, { "type": "function", "id": "f_is_pos_zero_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 4485, 4500 ] }, { "type": "function", "id": "f_is_neg_zero_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 4463, 4478 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfh.sail", "loc": [ 4618, 4626 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfh.sail", "loc": [ 4600, 4608 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfh.sail", "loc": [ 4661, 4669 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfh.sail", "loc": [ 4643, 4651 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfh.sail", "loc": [ 4907, 4915 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfh.sail", "loc": [ 4889, 4897 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfh.sail", "loc": [ 4950, 4958 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zfh.sail", "loc": [ 4932, 4940 ] }, { "type": "function", "id": "f_is_SNaN_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 5039, 5050 ] }, { "type": "function", "id": "f_is_SNaN_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 5021, 5032 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_zfh.sail", "loc": [ 5078, 5084 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "f_is_NaN_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 5177, 5187 ] }, { "type": "function", "id": "f_is_NaN_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 5160, 5170 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_zfh.sail", "loc": [ 5215, 5221 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "fle_S": { "function": { "number": 0, "source": "function fle_S (v1, v2, is_quiet) = {\n let (s1, e1, m1) = fsplit_S (v1);\n let (s2, e2, m2) = fsplit_S (v2);\n\n let v1Is0 = f_is_neg_zero_S(v1) | f_is_pos_zero_S(v1);\n let v2Is0 = f_is_neg_zero_S(v2) | f_is_pos_zero_S(v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) <= unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1)\n then (v1Is0 & v2Is0) /* Equal in this case (+0=-0) */\n else if (s1 == 0b1) & (s2 == 0b0)\n then true\n else\n if (e1 == e2)\n then unsigned (m1) >= unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_S(v1) | f_is_SNaN_S(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_S(v1) | f_is_NaN_S(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" }, { "type": "id", "id": "is_quiet" } ] }, "body": " let (s1, e1, m1) = fsplit_S (v1);\n let (s2, e2, m2) = fsplit_S (v2);\n\n let v1Is0 = f_is_neg_zero_S(v1) | f_is_pos_zero_S(v1);\n let v2Is0 = f_is_neg_zero_S(v2) | f_is_pos_zero_S(v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) <= unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1)\n then (v1Is0 & v2Is0) /* Equal in this case (+0=-0) */\n else if (s1 == 0b1) & (s2 == 0b0)\n then true\n else\n if (e1 == e2)\n then unsigned (m1) >= unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_S(v1) | f_is_SNaN_S(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_S(v1) | f_is_NaN_S(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 7196, 7204 ] }, { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 7232, 7240 ] }, { "type": "function", "id": "f_is_pos_zero_S", "file": "model/riscv_insts_fext.sail", "loc": [ 7287, 7302 ] }, { "type": "function", "id": "f_is_neg_zero_S", "file": "model/riscv_insts_fext.sail", "loc": [ 7265, 7280 ] }, { "type": "function", "id": "f_is_pos_zero_S", "file": "model/riscv_insts_fext.sail", "loc": [ 7347, 7362 ] }, { "type": "function", "id": "f_is_neg_zero_S", "file": "model/riscv_insts_fext.sail", "loc": [ 7325, 7340 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 7480, 7488 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 7462, 7470 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 7523, 7531 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 7505, 7513 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 7769, 7777 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 7751, 7759 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 7812, 7820 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 7794, 7802 ] }, { "type": "function", "id": "f_is_SNaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 7901, 7912 ] }, { "type": "function", "id": "f_is_SNaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 7883, 7894 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_fext.sail", "loc": [ 7940, 7946 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "f_is_NaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 8039, 8049 ] }, { "type": "function", "id": "f_is_NaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 8022, 8032 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_fext.sail", "loc": [ 8077, 8083 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "flt_D": { "function": { "number": 0, "source": "function flt_D (v1, v2, is_quiet) = {\n let (s1, e1, m1) = fsplit_D (v1);\n let (s2, e2, m2) = fsplit_D (v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) < unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1) then\n false\n else if (s1 == 0b1) & (s2 == 0b0) then\n true\n else\n if (e1 == e2)\n then unsigned (m1) > unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_D(v1) | f_is_SNaN_D(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_D(v1) | f_is_NaN_D(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" }, { "type": "id", "id": "is_quiet" } ] }, "body": " let (s1, e1, m1) = fsplit_D (v1);\n let (s2, e2, m2) = fsplit_D (v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) < unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1) then\n false\n else if (s1 == 0b1) & (s2 == 0b0) then\n true\n else\n if (e1 == e2)\n then unsigned (m1) > unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_D(v1) | f_is_SNaN_D(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_D(v1) | f_is_NaN_D(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5432, 5440 ] }, { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5468, 5476 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 5593, 5601 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 5577, 5585 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 5634, 5642 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 5618, 5626 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 5815, 5823 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 5799, 5807 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 5856, 5864 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_dext.sail", "loc": [ 5840, 5848 ] }, { "type": "function", "id": "f_is_SNaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5945, 5956 ] }, { "type": "function", "id": "f_is_SNaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 5927, 5938 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_dext.sail", "loc": [ 5984, 5990 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "f_is_NaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 6083, 6093 ] }, { "type": "function", "id": "f_is_NaN_D", "file": "model/riscv_insts_dext.sail", "loc": [ 6066, 6076 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_dext.sail", "loc": [ 6121, 6127 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "flt_S": { "function": { "number": 0, "source": "function flt_S (v1, v2, is_quiet) = {\n let (s1, e1, m1) = fsplit_S (v1);\n let (s2, e2, m2) = fsplit_S (v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) < unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1)\n then false\n else if (s1 == 0b1) & (s2 == 0b0)\n then true\n else\n if (e1 == e2)\n then unsigned (m1) > unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_S(v1) | f_is_SNaN_S(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_S(v1) | f_is_NaN_S(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" }, { "type": "id", "id": "is_quiet" } ] }, "body": " let (s1, e1, m1) = fsplit_S (v1);\n let (s2, e2, m2) = fsplit_S (v2);\n\n let result : bool =\n if (s1 == 0b0) & (s2 == 0b0) then\n if (e1 == e2)\n then unsigned (m1) < unsigned (m2)\n else unsigned (e1) < unsigned (e2)\n else if (s1 == 0b0) & (s2 == 0b1)\n then false\n else if (s1 == 0b1) & (s2 == 0b0)\n then true\n else\n if (e1 == e2)\n then unsigned (m1) > unsigned (m2)\n else unsigned (e1) > unsigned (e2);\n\n let fflags = if is_quiet then\n if (f_is_SNaN_S(v1) | f_is_SNaN_S(v2))\n then nvFlag()\n else zeros()\n else\n if (f_is_NaN_S(v1) | f_is_NaN_S(v2))\n then nvFlag()\n else zeros();\n\n (result, fflags)" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 6304, 6312 ] }, { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 6340, 6348 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 6465, 6473 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 6449, 6457 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 6506, 6514 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 6490, 6498 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 6687, 6695 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 6671, 6679 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 6730, 6738 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_fext.sail", "loc": [ 6714, 6722 ] }, { "type": "function", "id": "f_is_SNaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 6819, 6830 ] }, { "type": "function", "id": "f_is_SNaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 6801, 6812 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_fext.sail", "loc": [ 6858, 6864 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "f_is_NaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 6957, 6967 ] }, { "type": "function", "id": "f_is_NaN_S", "file": "model/riscv_insts_fext.sail", "loc": [ 6940, 6950 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_fext.sail", "loc": [ 6995, 7001 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "flush_TLB": { "function": { "number": 0, "source": "function flush_TLB(asid_xlen : option(xlenbits),\n addr_xlen : option(xlenbits)) -> unit = {\n let asid : option(asidbits) =\n match asid_xlen {\n None() => None(),\n Some(a) => Some(a[15 .. 0])\n };\n let addr_64b : option(bits(64)) =\n match addr_xlen {\n None() => None(),\n Some(a) => Some(zero_extend(a))\n };\n match tlb {\n None() => (),\n Some(e) => if flush_TLB_Entry(e, asid, addr_64b)\n then tlb = None()\n else ()\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "asid_xlen" }, { "type": "id", "id": "addr_xlen" } ] }, "body": " let asid : option(asidbits) =\n match asid_xlen {\n None() => None(),\n Some(a) => Some(a[15 .. 0])\n };\n let addr_64b : option(bits(64)) =\n match addr_xlen {\n None() => None(),\n Some(a) => Some(zero_extend(a))\n };\n match tlb {\n None() => (),\n Some(e) => if flush_TLB_Entry(e, asid, addr_64b)\n then tlb = None()\n else ()\n }" }, "links": [ { "type": "function", "id": "Some", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4238, 4242 ] }, { "type": "function", "id": "None", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4213, 4217 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4362, 4366 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4367, 4378 ] }, { "type": "function", "id": "None", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4337, 4341 ] }, { "type": "register", "id": "tlb", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4398, 4401 ] }, { "type": "function", "id": "flush_TLB_Entry", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4441, 4456 ] }, { "type": "register", "id": "tlb", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4496, 4499 ] }, { "type": "function", "id": "None", "file": "model/riscv_vmem_tlb.sail", "loc": [ 4502, 4506 ] } ] }, "flush_TLB_Entry": { "function": { "number": 0, "source": "function flush_TLB_Entry(e : TLB_Entry,\n asid : option(asidbits),\n addr : option(bits(64))) -> bool = {\n match (asid, addr) {\n ( None(), None()) => true,\n ( None(), Some(a)) => e.vAddr == (e.vMatchMask & a),\n (Some(i), None()) => (e.asid == i) & not(e.global),\n (Some(i), Some(a)) => ( (e.asid == i) & (e.vAddr == (a & e.vMatchMask))\n & not(e.global))\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "e" }, { "type": "id", "id": "asid" }, { "type": "id", "id": "addr" } ] }, "body": " match (asid, addr) {\n ( None(), None()) => true,\n ( None(), Some(a)) => e.vAddr == (e.vMatchMask & a),\n (Some(i), None()) => (e.asid == i) & not(e.global),\n (Some(i), Some(a)) => ( (e.asid == i) & (e.vAddr == (a & e.vMatchMask))\n & not(e.global))\n }" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_vmem_tlb.sail", "loc": [ 2477, 2480 ] }, { "type": "function", "id": "not", "file": "model/riscv_vmem_tlb.sail", "loc": [ 2356, 2359 ] } ] }, "fmake_D": { "function": { "number": 0, "source": "function fmake_D (sign, exp, mant) = sign @ exp @ mant", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sign" }, { "type": "id", "id": "exp" }, { "type": "id", "id": "mant" } ] }, "body": "sign @ exp @ mant" } }, "fmake_H": { "function": { "number": 0, "source": "function fmake_H (sign, exp, mant) = sign @ exp @ mant", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sign" }, { "type": "id", "id": "exp" }, { "type": "id", "id": "mant" } ] }, "body": "sign @ exp @ mant" } }, "fmake_S": { "function": { "number": 0, "source": "function fmake_S (sign, exp, mant) = sign @ exp @ mant", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sign" }, { "type": "id", "id": "exp" }, { "type": "id", "id": "mant" } ] }, "body": "sign @ exp @ mant" } }, "fmod_int": { "function": { "number": 0, "source": "fmod_int (n : int, m : int) = {\n sub_atom(n, mult_atom(m, fdiv_int(n, m)))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "m" } ] }, "body": "sub_atom(n, mult_atom(m, fdiv_int(n, m)))" } }, "fp_add": { "function": { "number": 0, "source": "function fp_add(rm_3b, op1, op2) = {\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Add(rm_3b, op1, op2),\n 32 => riscv_f32Add(rm_3b, op1, op2),\n 64 => riscv_f64Add(rm_3b, op1, op2)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Add(rm_3b, op1, op2),\n 32 => riscv_f32Add(rm_3b, op1, op2),\n 64 => riscv_f64Add(rm_3b, op1, op2)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Add", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23282, 23294 ] }, { "type": "function", "id": "riscv_f32Add", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23240, 23252 ] }, { "type": "function", "id": "riscv_f16Add", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23198, 23210 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23319, 23332 ] } ] }, "fp_class": { "function": { "number": 0, "source": "function fp_class(xf) = {\n let result_val_10b : bits(10) =\n if f_is_neg_inf(xf) then 0b_00_0000_0001\n else if f_is_neg_norm(xf) then 0b_00_0000_0010\n else if f_is_neg_subnorm(xf) then 0b_00_0000_0100\n else if f_is_neg_zero(xf) then 0b_00_0000_1000\n else if f_is_pos_zero(xf) then 0b_00_0001_0000\n else if f_is_pos_subnorm(xf) then 0b_00_0010_0000\n else if f_is_pos_norm(xf) then 0b_00_0100_0000\n else if f_is_pos_inf(xf) then 0b_00_1000_0000\n else if f_is_SNaN(xf) then 0b_01_0000_0000\n else if f_is_QNaN(xf) then 0b_10_0000_0000\n else zeros();\n\n zero_extend(result_val_10b)\n}", "pattern": { "type": "id", "id": "xf" }, "body": " let result_val_10b : bits(10) =\n if f_is_neg_inf(xf) then 0b_00_0000_0001\n else if f_is_neg_norm(xf) then 0b_00_0000_0010\n else if f_is_neg_subnorm(xf) then 0b_00_0000_0100\n else if f_is_neg_zero(xf) then 0b_00_0000_1000\n else if f_is_pos_zero(xf) then 0b_00_0001_0000\n else if f_is_pos_subnorm(xf) then 0b_00_0010_0000\n else if f_is_pos_norm(xf) then 0b_00_0100_0000\n else if f_is_pos_inf(xf) then 0b_00_1000_0000\n else if f_is_SNaN(xf) then 0b_01_0000_0000\n else if f_is_QNaN(xf) then 0b_10_0000_0000\n else zeros();\n\n zero_extend(result_val_10b)" }, "links": [ { "type": "function", "id": "f_is_neg_inf", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29496, 29508 ] }, { "type": "function", "id": "f_is_neg_norm", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29550, 29563 ] }, { "type": "function", "id": "f_is_neg_subnorm", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29604, 29620 ] }, { "type": "function", "id": "f_is_neg_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29658, 29671 ] }, { "type": "function", "id": "f_is_pos_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29712, 29725 ] }, { "type": "function", "id": "f_is_pos_subnorm", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29766, 29782 ] }, { "type": "function", "id": "f_is_pos_norm", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29820, 29833 ] }, { "type": "function", "id": "f_is_pos_inf", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29874, 29886 ] }, { "type": "function", "id": "f_is_SNaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29928, 29937 ] }, { "type": "function", "id": "f_is_QNaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29982, 29991 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30045, 30056 ] } ] }, "fp_div": { "function": { "number": 0, "source": "function fp_div(rm_3b, op1, op2) = {\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Div(rm_3b, op1, op2),\n 32 => riscv_f32Div(rm_3b, op1, op2),\n 64 => riscv_f64Div(rm_3b, op1, op2)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Div(rm_3b, op1, op2),\n 32 => riscv_f32Div(rm_3b, op1, op2),\n 64 => riscv_f64Div(rm_3b, op1, op2)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Div", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27505, 27517 ] }, { "type": "function", "id": "riscv_f32Div", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27463, 27475 ] }, { "type": "function", "id": "riscv_f16Div", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27421, 27433 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27542, 27555 ] } ] }, "fp_eq": { "function": { "number": 0, "source": "function fp_eq(op1, op2) = {\n let (fflags, result_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Eq(op1, op2),\n 32 => riscv_f32Eq(op1, op2),\n 64 => riscv_f64Eq(op1, op2)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, result_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Eq(op1, op2),\n 32 => riscv_f32Eq(op1, op2),\n 64 => riscv_f64Eq(op1, op2)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Eq", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25411, 25422 ] }, { "type": "function", "id": "riscv_f32Eq", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25377, 25388 ] }, { "type": "function", "id": "riscv_f16Eq", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25343, 25354 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25440, 25453 ] } ] }, "fp_ge": { "function": { "number": 0, "source": "function fp_ge(op1, op2) = {\n let (fflags, temp_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Lt(op1, op2),\n 32 => riscv_f32Lt(op1, op2),\n 64 => riscv_f64Lt(op1, op2)\n };\n let result_val = (if fflags == 0b10000 then false else not(temp_val));\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, temp_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Lt(op1, op2),\n 32 => riscv_f32Lt(op1, op2),\n 64 => riscv_f64Lt(op1, op2)\n };\n let result_val = (if fflags == 0b10000 then false else not(temp_val));\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Lt", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26100, 26111 ] }, { "type": "function", "id": "riscv_f32Lt", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26066, 26077 ] }, { "type": "function", "id": "riscv_f16Lt", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26032, 26043 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26184, 26187 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26202, 26215 ] } ] }, "fp_gt": { "function": { "number": 0, "source": "function fp_gt(op1, op2) = {\n let (fflags, temp_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Le(op1, op2),\n 32 => riscv_f32Le(op1, op2),\n 64 => riscv_f64Le(op1, op2)\n };\n let result_val = (if fflags == 0b10000 then false else not(temp_val));\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, temp_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Le(op1, op2),\n 32 => riscv_f32Le(op1, op2),\n 64 => riscv_f64Le(op1, op2)\n };\n let result_val = (if fflags == 0b10000 then false else not(temp_val));\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Le", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25719, 25730 ] }, { "type": "function", "id": "riscv_f32Le", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25685, 25696 ] }, { "type": "function", "id": "riscv_f16Le", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25651, 25662 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25803, 25806 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25821, 25834 ] } ] }, "fp_le": { "function": { "number": 0, "source": "function fp_le(op1, op2) = {\n let (fflags, result_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Le(op1, op2),\n 32 => riscv_f32Le(op1, op2),\n 64 => riscv_f64Le(op1, op2)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, result_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Le(op1, op2),\n 32 => riscv_f32Le(op1, op2),\n 64 => riscv_f64Le(op1, op2)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Le", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26793, 26804 ] }, { "type": "function", "id": "riscv_f32Le", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26759, 26770 ] }, { "type": "function", "id": "riscv_f16Le", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26725, 26736 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26822, 26835 ] } ] }, "fp_lt": { "function": { "number": 0, "source": "function fp_lt(op1, op2) = {\n let (fflags, result_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Lt(op1, op2),\n 32 => riscv_f32Lt(op1, op2),\n 64 => riscv_f64Lt(op1, op2)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, result_val) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Lt(op1, op2),\n 32 => riscv_f32Lt(op1, op2),\n 64 => riscv_f64Lt(op1, op2)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Lt", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26483, 26494 ] }, { "type": "function", "id": "riscv_f32Lt", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26449, 26460 ] }, { "type": "function", "id": "riscv_f16Lt", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26415, 26426 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 26512, 26525 ] } ] }, "fp_max": { "function": { "number": 0, "source": "function fp_max(op1, op2) = {\n let (fflags, op1_lt_op2) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Lt_quiet(op1, op2),\n 32 => riscv_f32Lt_quiet(op1, op2),\n 64 => riscv_f64Lt_quiet(op1, op2)\n };\n\n let result_val = if (f_is_NaN(op1) & f_is_NaN(op2)) then canonical_NaN('m)\n else if f_is_NaN(op1) then op2\n else if f_is_NaN(op2) then op1\n else if (f_is_neg_zero(op1) & f_is_pos_zero(op2)) then op2\n else if (f_is_neg_zero(op2) & f_is_pos_zero(op1)) then op1\n else if op1_lt_op2 then op2\n else op1;\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, op1_lt_op2) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Lt_quiet(op1, op2),\n 32 => riscv_f32Lt_quiet(op1, op2),\n 64 => riscv_f64Lt_quiet(op1, op2)\n };\n\n let result_val = if (f_is_NaN(op1) & f_is_NaN(op2)) then canonical_NaN('m)\n else if f_is_NaN(op1) then op2\n else if f_is_NaN(op2) then op1\n else if (f_is_neg_zero(op1) & f_is_pos_zero(op2)) then op2\n else if (f_is_neg_zero(op2) & f_is_pos_zero(op1)) then op1\n else if op1_lt_op2 then op2\n else op1;\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Lt_quiet", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24703, 24720 ] }, { "type": "function", "id": "riscv_f32Lt_quiet", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24663, 24680 ] }, { "type": "function", "id": "riscv_f16Lt_quiet", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24623, 24640 ] }, { "type": "function", "id": "f_is_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24776, 24784 ] }, { "type": "function", "id": "f_is_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24760, 24768 ] }, { "type": "function", "id": "canonical_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24796, 24809 ] }, { "type": "function", "id": "f_is_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24838, 24846 ] }, { "type": "function", "id": "f_is_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24885, 24893 ] }, { "type": "function", "id": "f_is_pos_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24954, 24967 ] }, { "type": "function", "id": "f_is_neg_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24933, 24946 ] }, { "type": "function", "id": "f_is_pos_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25029, 25042 ] }, { "type": "function", "id": "f_is_neg_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25008, 25021 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 25130, 25143 ] } ] }, "fp_min": { "function": { "number": 0, "source": "function fp_min(op1, op2) = {\n let (fflags, op1_lt_op2) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Lt_quiet(op1, op2),\n 32 => riscv_f32Lt_quiet(op1, op2),\n 64 => riscv_f64Lt_quiet(op1, op2)\n };\n\n let result_val = if (f_is_NaN(op1) & f_is_NaN(op2)) then canonical_NaN('m)\n else if f_is_NaN(op1) then op2\n else if f_is_NaN(op2) then op1\n else if (f_is_neg_zero(op1) & f_is_pos_zero(op2)) then op1\n else if (f_is_neg_zero(op2) & f_is_pos_zero(op1)) then op2\n else if op1_lt_op2 then op1\n else op2;\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, op1_lt_op2) : (bits_fflags, bool) = match 'm {\n 16 => riscv_f16Lt_quiet(op1, op2),\n 32 => riscv_f32Lt_quiet(op1, op2),\n 64 => riscv_f64Lt_quiet(op1, op2)\n };\n\n let result_val = if (f_is_NaN(op1) & f_is_NaN(op2)) then canonical_NaN('m)\n else if f_is_NaN(op1) then op2\n else if f_is_NaN(op2) then op1\n else if (f_is_neg_zero(op1) & f_is_pos_zero(op2)) then op1\n else if (f_is_neg_zero(op2) & f_is_pos_zero(op1)) then op2\n else if op1_lt_op2 then op1\n else op2;\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Lt_quiet", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23977, 23994 ] }, { "type": "function", "id": "riscv_f32Lt_quiet", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23937, 23954 ] }, { "type": "function", "id": "riscv_f16Lt_quiet", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23897, 23914 ] }, { "type": "function", "id": "f_is_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24050, 24058 ] }, { "type": "function", "id": "f_is_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24034, 24042 ] }, { "type": "function", "id": "canonical_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24070, 24083 ] }, { "type": "function", "id": "f_is_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24112, 24120 ] }, { "type": "function", "id": "f_is_NaN", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24159, 24167 ] }, { "type": "function", "id": "f_is_pos_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24228, 24241 ] }, { "type": "function", "id": "f_is_neg_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24207, 24220 ] }, { "type": "function", "id": "f_is_pos_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24303, 24316 ] }, { "type": "function", "id": "f_is_neg_zero", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24282, 24295 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 24404, 24417 ] } ] }, "fp_mul": { "function": { "number": 0, "source": "function fp_mul(rm_3b, op1, op2) = {\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Mul(rm_3b, op1, op2),\n 32 => riscv_f32Mul(rm_3b, op1, op2),\n 64 => riscv_f64Mul(rm_3b, op1, op2)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Mul(rm_3b, op1, op2),\n 32 => riscv_f32Mul(rm_3b, op1, op2),\n 64 => riscv_f64Mul(rm_3b, op1, op2)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Mul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27145, 27157 ] }, { "type": "function", "id": "riscv_f32Mul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27103, 27115 ] }, { "type": "function", "id": "riscv_f16Mul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27061, 27073 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27182, 27195 ] } ] }, "fp_muladd": { "function": { "number": 0, "source": "function fp_muladd(rm_3b, op1, op2, opadd) = {\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16MulAdd(rm_3b, op1, op2, opadd),\n 32 => riscv_f32MulAdd(rm_3b, op1, op2, opadd),\n 64 => riscv_f64MulAdd(rm_3b, op1, op2, opadd)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" }, { "type": "id", "id": "opadd" } ] }, "body": " let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16MulAdd(rm_3b, op1, op2, opadd),\n 32 => riscv_f32MulAdd(rm_3b, op1, op2, opadd),\n 64 => riscv_f64MulAdd(rm_3b, op1, op2, opadd)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27908, 27923 ] }, { "type": "function", "id": "riscv_f32MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27856, 27871 ] }, { "type": "function", "id": "riscv_f16MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27804, 27819 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 27955, 27968 ] } ] }, "fp_mulsub": { "function": { "number": 0, "source": "function fp_mulsub(rm_3b, op1, op2, opsub) = {\n let opsub = negate_fp(opsub);\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16MulAdd(rm_3b, op1, op2, opsub),\n 32 => riscv_f32MulAdd(rm_3b, op1, op2, opsub),\n 64 => riscv_f64MulAdd(rm_3b, op1, op2, opsub)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" }, { "type": "id", "id": "opsub" } ] }, "body": " let opsub = negate_fp(opsub);\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16MulAdd(rm_3b, op1, op2, opsub),\n 32 => riscv_f32MulAdd(rm_3b, op1, op2, opsub),\n 64 => riscv_f64MulAdd(rm_3b, op1, op2, opsub)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "negate_fp", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28597, 28606 ] }, { "type": "function", "id": "riscv_f64MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28796, 28811 ] }, { "type": "function", "id": "riscv_f32MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28744, 28759 ] }, { "type": "function", "id": "riscv_f16MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28692, 28707 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28843, 28856 ] } ] }, "fp_nmuladd": { "function": { "number": 0, "source": "function fp_nmuladd(rm_3b, op1, op2, opadd) = {\n let op1 = negate_fp(op1);\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16MulAdd(rm_3b, op1, op2, opadd),\n 32 => riscv_f32MulAdd(rm_3b, op1, op2, opadd),\n 64 => riscv_f64MulAdd(rm_3b, op1, op2, opadd)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" }, { "type": "id", "id": "opadd" } ] }, "body": " let op1 = negate_fp(op1);\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16MulAdd(rm_3b, op1, op2, opadd),\n 32 => riscv_f32MulAdd(rm_3b, op1, op2, opadd),\n 64 => riscv_f64MulAdd(rm_3b, op1, op2, opadd)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "negate_fp", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28154, 28163 ] }, { "type": "function", "id": "riscv_f64MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28351, 28366 ] }, { "type": "function", "id": "riscv_f32MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28299, 28314 ] }, { "type": "function", "id": "riscv_f16MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28247, 28262 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 28398, 28411 ] } ] }, "fp_nmulsub": { "function": { "number": 0, "source": "function fp_nmulsub(rm_3b, op1, op2, opsub) = {\n let opsub = negate_fp(opsub);\n let op1 = negate_fp(op1);\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16MulAdd(rm_3b, op1, op2, opsub),\n 32 => riscv_f32MulAdd(rm_3b, op1, op2, opsub),\n 64 => riscv_f64MulAdd(rm_3b, op1, op2, opsub)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" }, { "type": "id", "id": "opsub" } ] }, "body": " let opsub = negate_fp(opsub);\n let op1 = negate_fp(op1);\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16MulAdd(rm_3b, op1, op2, opsub),\n 32 => riscv_f32MulAdd(rm_3b, op1, op2, opsub),\n 64 => riscv_f64MulAdd(rm_3b, op1, op2, opsub)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "negate_fp", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29044, 29053 ] }, { "type": "function", "id": "negate_fp", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29074, 29083 ] }, { "type": "function", "id": "riscv_f64MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29271, 29286 ] }, { "type": "function", "id": "riscv_f32MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29219, 29234 ] }, { "type": "function", "id": "riscv_f16MulAdd", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29167, 29182 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 29318, 29331 ] } ] }, "fp_sub": { "function": { "number": 0, "source": "function fp_sub(rm_3b, op1, op2) = {\n let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Sub(rm_3b, op1, op2),\n 32 => riscv_f32Sub(rm_3b, op1, op2),\n 64 => riscv_f64Sub(rm_3b, op1, op2)\n };\n accrue_fflags(fflags);\n result_val\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "op1" }, { "type": "id", "id": "op2" } ] }, "body": " let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm {\n 16 => riscv_f16Sub(rm_3b, op1, op2),\n 32 => riscv_f32Sub(rm_3b, op1, op2),\n 64 => riscv_f64Sub(rm_3b, op1, op2)\n };\n accrue_fflags(fflags);\n result_val" }, "links": [ { "type": "function", "id": "riscv_f64Sub", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23641, 23653 ] }, { "type": "function", "id": "riscv_f32Sub", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23599, 23611 ] }, { "type": "function", "id": "riscv_f16Sub", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23557, 23569 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 23678, 23691 ] } ] }, "fp_widen": { "function": { "number": 0, "source": "function fp_widen(nval) = {\n let rm_3b = fcsr[FRM];\n let (fflags, wval) : (bits_fflags, bits('m * 2)) = match 'm {\n 16 => riscv_f16ToF32(rm_3b, nval),\n 32 => riscv_f32ToF64(rm_3b, nval)\n };\n accrue_fflags(fflags);\n wval\n}", "pattern": { "type": "id", "id": "nval" }, "body": " let rm_3b = fcsr[FRM];\n let (fflags, wval) : (bits_fflags, bits('m * 2)) = match 'm {\n 16 => riscv_f16ToF32(rm_3b, nval),\n 32 => riscv_f32ToF64(rm_3b, nval)\n };\n accrue_fflags(fflags);\n wval" }, "links": [ { "type": "register", "id": "fcsr", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30185, 30189 ] }, { "type": "function", "id": "riscv_f32ToF64", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30309, 30323 ] }, { "type": "function", "id": "riscv_f16ToF32", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30270, 30284 ] }, { "type": "function", "id": "accrue_fflags", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30344, 30357 ] } ] }, "fregval_from_freg": { "function": { "number": 0, "source": "function fregval_from_freg(r) = r", "pattern": { "type": "id", "id": "r" }, "body": "r" } }, "fregval_into_freg": { "function": { "number": 0, "source": "function fregval_into_freg(v) = v", "pattern": { "type": "id", "id": "v" }, "body": "v" } }, "fsplit_D": { "function": { "number": 0, "source": "function fsplit_D x64 = (x64[63..63], x64[62..52], x64[51..0])", "pattern": { "type": "id", "id": "x64" }, "body": "(x64[63..63], x64[62..52], x64[51..0])" } }, "fsplit_H": { "function": { "number": 0, "source": "function fsplit_H (xf16) = (xf16[15..15], xf16[14..10], xf16[9..0])", "pattern": { "type": "id", "id": "xf16" }, "body": "(xf16[15..15], xf16[14..10], xf16[9..0])" } }, "fsplit_S": { "function": { "number": 0, "source": "function fsplit_S x32 = (x32[31..31], x32[30..23], x32[22..0])", "pattern": { "type": "id", "id": "x32" }, "body": "(x32[31..31], x32[30..23], x32[22..0])" } }, "fvffunct6_of_num": { "function": { "number": 0, "source": "fvffunct6_of_num arg# = $[complete] match arg# {\n 0 => VF_VADD,\n 1 => VF_VSUB,\n 2 => VF_VMIN,\n 3 => VF_VMAX,\n 4 => VF_VSGNJ,\n 5 => VF_VSGNJN,\n 6 => VF_VSGNJX,\n 7 => VF_VDIV,\n 8 => VF_VRDIV,\n 9 => VF_VMUL,\n 10 => VF_VRSUB,\n 11 => VF_VSLIDE1UP,\n _ => VF_VSLIDE1DOWN\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VF_VADD,\n 1 => VF_VSUB,\n 2 => VF_VMIN,\n 3 => VF_VMAX,\n 4 => VF_VSGNJ,\n 5 => VF_VSGNJN,\n 6 => VF_VSGNJX,\n 7 => VF_VDIV,\n 8 => VF_VRDIV,\n 9 => VF_VMUL,\n 10 => VF_VRSUB,\n 11 => VF_VSLIDE1UP,\n _ => VF_VSLIDE1DOWN\n}" } }, "fvfmafunct6_of_num": { "function": { "number": 0, "source": "fvfmafunct6_of_num arg# = $[complete] match arg# {\n 0 => VF_VMADD,\n 1 => VF_VNMADD,\n 2 => VF_VMSUB,\n 3 => VF_VNMSUB,\n 4 => VF_VMACC,\n 5 => VF_VNMACC,\n 6 => VF_VMSAC,\n _ => VF_VNMSAC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VF_VMADD,\n 1 => VF_VNMADD,\n 2 => VF_VMSUB,\n 3 => VF_VNMSUB,\n 4 => VF_VMACC,\n 5 => VF_VNMACC,\n 6 => VF_VMSAC,\n _ => VF_VNMSAC\n}" } }, "fvfmfunct6_of_num": { "function": { "number": 0, "source": "fvfmfunct6_of_num arg# = $[complete] match arg# {\n 0 => VFM_VMFEQ,\n 1 => VFM_VMFLE,\n 2 => VFM_VMFLT,\n 3 => VFM_VMFNE,\n 4 => VFM_VMFGT,\n _ => VFM_VMFGE\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VFM_VMFEQ,\n 1 => VFM_VMFLE,\n 2 => VFM_VMFLT,\n 3 => VFM_VMFNE,\n 4 => VFM_VMFGT,\n _ => VFM_VMFGE\n}" } }, "fvvfunct6_of_num": { "function": { "number": 0, "source": "fvvfunct6_of_num arg# = $[complete] match arg# {\n 0 => FVV_VADD,\n 1 => FVV_VSUB,\n 2 => FVV_VMIN,\n 3 => FVV_VMAX,\n 4 => FVV_VSGNJ,\n 5 => FVV_VSGNJN,\n 6 => FVV_VSGNJX,\n 7 => FVV_VDIV,\n _ => FVV_VMUL\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FVV_VADD,\n 1 => FVV_VSUB,\n 2 => FVV_VMIN,\n 3 => FVV_VMAX,\n 4 => FVV_VSGNJ,\n 5 => FVV_VSGNJN,\n 6 => FVV_VSGNJX,\n 7 => FVV_VDIV,\n _ => FVV_VMUL\n}" } }, "fvvmafunct6_of_num": { "function": { "number": 0, "source": "fvvmafunct6_of_num arg# = $[complete] match arg# {\n 0 => FVV_VMADD,\n 1 => FVV_VNMADD,\n 2 => FVV_VMSUB,\n 3 => FVV_VNMSUB,\n 4 => FVV_VMACC,\n 5 => FVV_VNMACC,\n 6 => FVV_VMSAC,\n _ => FVV_VNMSAC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FVV_VMADD,\n 1 => FVV_VNMADD,\n 2 => FVV_VMSUB,\n 3 => FVV_VNMSUB,\n 4 => FVV_VMACC,\n 5 => FVV_VNMACC,\n 6 => FVV_VMSAC,\n _ => FVV_VNMSAC\n}" } }, "fvvmfunct6_of_num": { "function": { "number": 0, "source": "fvvmfunct6_of_num arg# = $[complete] match arg# {\n 0 => FVVM_VMFEQ,\n 1 => FVVM_VMFLE,\n 2 => FVVM_VMFLT,\n _ => FVVM_VMFNE\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FVVM_VMFEQ,\n 1 => FVVM_VMFLE,\n 2 => FVVM_VMFLT,\n _ => FVVM_VMFNE\n}" } }, "fwffunct6_of_num": { "function": { "number": 0, "source": "fwffunct6_of_num arg# = $[complete] match arg# {\n 0 => FWF_VADD,\n _ => FWF_VSUB\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FWF_VADD,\n _ => FWF_VSUB\n}" } }, "fwvffunct6_of_num": { "function": { "number": 0, "source": "fwvffunct6_of_num arg# = $[complete] match arg# {\n 0 => FWVF_VADD,\n 1 => FWVF_VSUB,\n _ => FWVF_VMUL\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FWVF_VADD,\n 1 => FWVF_VSUB,\n _ => FWVF_VMUL\n}" } }, "fwvfmafunct6_of_num": { "function": { "number": 0, "source": "fwvfmafunct6_of_num arg# = $[complete] match arg# {\n 0 => FWVF_VMACC,\n 1 => FWVF_VNMACC,\n 2 => FWVF_VMSAC,\n _ => FWVF_VNMSAC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FWVF_VMACC,\n 1 => FWVF_VNMACC,\n 2 => FWVF_VMSAC,\n _ => FWVF_VNMSAC\n}" } }, "fwvfunct6_of_num": { "function": { "number": 0, "source": "fwvfunct6_of_num arg# = $[complete] match arg# {\n 0 => FWV_VADD,\n _ => FWV_VSUB\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FWV_VADD,\n _ => FWV_VSUB\n}" } }, "fwvvfunct6_of_num": { "function": { "number": 0, "source": "fwvvfunct6_of_num arg# = $[complete] match arg# {\n 0 => FWVV_VADD,\n 1 => FWVV_VSUB,\n _ => FWVV_VMUL\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FWVV_VADD,\n 1 => FWVV_VSUB,\n _ => FWVV_VMUL\n}" } }, "fwvvmafunct6_of_num": { "function": { "number": 0, "source": "fwvvmafunct6_of_num arg# = $[complete] match arg# {\n 0 => FWVV_VMACC,\n 1 => FWVV_VNMACC,\n 2 => FWVV_VMSAC,\n _ => FWVV_VNMSAC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FWVV_VMACC,\n 1 => FWVV_VNMACC,\n 2 => FWVV_VMSAC,\n _ => FWVV_VNMSAC\n}" } }, "getPendingSet": { "function": { "number": 0, "source": "function getPendingSet(priv : Privilege) -> option((xlenbits, Privilege)) = {\n assert(haveUsrMode(), \"no user mode: M/U or M/S/U system required\");\n let effective_pending = mip.bits & mie.bits;\n if effective_pending == zero_extend(0b0) then None() /* fast path */\n else {\n /* Higher privileges than the current one are implicitly enabled,\n * while lower privileges are blocked. An unsupported privilege is\n * considered blocked.\n */\n let mIE = priv != Machine | (priv == Machine & mstatus[MIE] == 0b1);\n let sIE = haveSupMode() & (priv == User | (priv == Supervisor & mstatus[SIE] == 0b1));\n let uIE = haveNExt() & (priv == User & mstatus[UIE] == 0b1);\n match processPending(mip, mie, mideleg.bits, mIE) {\n Ints_Empty() => None(),\n Ints_Pending(p) => let r = (p, Machine) in Some(r),\n Ints_Delegated(d) =>\n if not(haveSupMode()) then {\n if uIE then let r = (d, User) in Some(r)\n else None()\n } else {\n /* the delegated bits are pending for S-mode */\n match processPending(Mk_Minterrupts(d), mie, sideleg.bits, sIE) {\n Ints_Empty() => None(),\n Ints_Pending(p) => let r = (p, Supervisor) in Some(r),\n Ints_Delegated(d) => if uIE\n then let r = (d, User) in Some(r)\n else None()\n }\n }\n }\n }\n}", "pattern": { "type": "id", "id": "priv" }, "body": "function getPendingSet(priv : Privilege) -> option((xlenbits, Privilege)) = {\n assert(haveUsrMode(), \"no user mode: M/U or M/S/U system required\");\n let effective_pending = mip.bits & mie.bits;\n if effective_pending == zero_extend(0b0) then None() /* fast path */\n else {\n /* Higher privileges than the current one are implicitly enabled,\n * while lower privileges are blocked. An unsupported privilege is\n * considered blocked.\n */\n let mIE = priv != Machine | (priv == Machine & mstatus[MIE] == 0b1);\n let sIE = haveSupMode() & (priv == User | (priv == Supervisor & mstatus[SIE] == 0b1));\n let uIE = haveNExt() & (priv == User & mstatus[UIE] == 0b1);\n match processPending(mip, mie, mideleg.bits, mIE) {\n Ints_Empty() => None(),\n Ints_Pending(p) => let r = (p, Machine) in Some(r),\n Ints_Delegated(d) =>\n if not(haveSupMode()) then {\n if uIE then let r = (d, User) in Some(r)\n else None()\n } else {\n /* the delegated bits are pending for S-mode */\n match processPending(Mk_Minterrupts(d), mie, sideleg.bits, sIE) {\n Ints_Empty() => None(),\n Ints_Pending(p) => let r = (p, Supervisor) in Some(r),\n Ints_Delegated(d) => if uIE\n then let r = (d, User) in Some(r)\n else None()\n }\n }\n }\n }" }, "links": [ { "type": "register", "id": "mie", "file": "model/riscv_sys_control.sail", "loc": [ 10333, 10336 ] }, { "type": "register", "id": "mip", "file": "model/riscv_sys_control.sail", "loc": [ 10322, 10325 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 10370, 10381 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 10392, 10396 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 10652, 10659 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 10742, 10749 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 10688, 10699 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 10808, 10815 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_control.sail", "loc": [ 10779, 10787 ] }, { "type": "function", "id": "processPending", "file": "model/riscv_sys_control.sail", "loc": [ 10840, 10854 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_sys_control.sail", "loc": [ 10865, 10872 ] }, { "type": "register", "id": "mie", "file": "model/riscv_sys_control.sail", "loc": [ 10860, 10863 ] }, { "type": "register", "id": "mip", "file": "model/riscv_sys_control.sail", "loc": [ 10855, 10858 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_control.sail", "loc": [ 11019, 11022 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 11023, 11034 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 11088, 11092 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 11139, 11143 ] }, { "type": "function", "id": "processPending", "file": "model/riscv_sys_control.sail", "loc": [ 11237, 11251 ] }, { "type": "register", "id": "sideleg", "file": "model/riscv_sys_control.sail", "loc": [ 11276, 11283 ] }, { "type": "register", "id": "mie", "file": "model/riscv_sys_control.sail", "loc": [ 11271, 11274 ] }, { "type": "function", "id": "Mk_Minterrupts", "file": "model/riscv_sys_control.sail", "loc": [ 11252, 11266 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 11508, 11512 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 11554, 11558 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 11398, 11402 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 11330, 11334 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 10972, 10976 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 10913, 10917 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 10234, 10245 ] } ] }, "get_arch_pc": { "function": { "number": 0, "source": "function get_arch_pc() = PC", "pattern": { "type": "literal", "value": "()" }, "body": "PC" }, "links": [ { "type": "register", "id": "PC", "file": "model/riscv_pc_access.sail", "loc": [ 1047, 1049 ] } ] }, "get_config_print_instr": { "function": { "number": 0, "source": "function get_config_print_instr () = false", "pattern": { "type": "literal", "value": "()" }, "body": "false" } }, "get_config_print_mem": { "function": { "number": 0, "source": "function get_config_print_mem () = false", "pattern": { "type": "literal", "value": "()" }, "body": "false" } }, "get_config_print_platform": { "function": { "number": 0, "source": "function get_config_print_platform () = false", "pattern": { "type": "literal", "value": "()" }, "body": "false" } }, "get_config_print_reg": { "function": { "number": 0, "source": "function get_config_print_reg () = false", "pattern": { "type": "literal", "value": "()" }, "body": "false" } }, "get_elen_pow": { "function": { "number": 0, "source": "function get_elen_pow() = match elen {\n 0b0 => 5,\n 0b1 => 6\n}", "pattern": { "type": "literal", "value": "()" }, "body": "match elen {\n 0b0 => 5,\n 0b1 => 6\n}" }, "links": [ { "type": "register", "id": "elen", "file": "model/riscv_vlen.sail", "loc": [ 739, 743 ] } ] }, "get_end_element": { "function": { "number": 0, "source": "function get_end_element() = unsigned(vl) - 1", "pattern": { "type": "literal", "value": "()" }, "body": "unsigned(vl) - 1" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 10187, 10195 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 10196, 10198 ] } ] }, "get_fixed_rounding_incr": { "function": { "number": 0, "source": "function get_fixed_rounding_incr(vec_elem, shift_amount) = {\n if shift_amount == 0 then 0b0\n else {\n let rounding_mode = vxrm[1 .. 0];\n match rounding_mode {\n 0b00 => slice(vec_elem, shift_amount - 1, 1),\n 0b01 => bool_to_bits(\n (slice(vec_elem, shift_amount - 1, 1) == 0b1) & (slice(vec_elem, 0, shift_amount - 1) != zeros() | slice(vec_elem, shift_amount, 1) == 0b1)),\n 0b10 => 0b0,\n 0b11 => bool_to_bits(\n not(slice(vec_elem, shift_amount, 1) == 0b1) & (slice(vec_elem, 0, shift_amount) != zeros()))\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vec_elem" }, { "type": "id", "id": "shift_amount" } ] }, "body": " if shift_amount == 0 then 0b0\n else {\n let rounding_mode = vxrm[1 .. 0];\n match rounding_mode {\n 0b00 => slice(vec_elem, shift_amount - 1, 1),\n 0b01 => bool_to_bits(\n (slice(vec_elem, shift_amount - 1, 1) == 0b1) & (slice(vec_elem, 0, shift_amount - 1) != zeros() | slice(vec_elem, shift_amount, 1) == 0b1)),\n 0b10 => 0b0,\n 0b11 => bool_to_bits(\n not(slice(vec_elem, shift_amount, 1) == 0b1) & (slice(vec_elem, 0, shift_amount) != zeros()))\n }\n }" }, "links": [ { "type": "register", "id": "vxrm", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21376, 21380 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21679, 21691 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "slice", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21749, 21754 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21701, 21704 ] }, { "type": "function", "id": "slice", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21705, 21710 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21482, 21494 ] }, { "type": "function", "id": "slice", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21603, 21608 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "slice", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21553, 21558 ] }, { "type": "function", "id": "slice", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21505, 21510 ] }, { "type": "function", "id": "slice", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21430, 21435 ] } ] }, "get_fp_rounding_mode": { "function": { "number": 0, "source": "function get_fp_rounding_mode() = encdec_rounding_mode(fcsr[FRM])", "pattern": { "type": "literal", "value": "()" }, "body": "encdec_rounding_mode(fcsr[FRM])" }, "links": [ { "type": "register", "id": "fcsr", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22707, 22711 ] } ] }, "get_lmul_pow": { "function": { "number": 0, "source": "function get_lmul_pow() = {\n match vtype[vlmul] {\n 0b101 => -3,\n 0b110 => -2,\n 0b111 => -1,\n 0b000 => 0,\n 0b001 => 1,\n 0b010 => 2,\n 0b011 => 3,\n _ => {assert(false, \"invalid vlmul field in vtype\"); 0}\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " match vtype[vlmul] {\n 0b101 => -3,\n 0b110 => -2,\n 0b111 => -1,\n 0b000 => 0,\n 0b001 => 1,\n 0b010 => 2,\n 0b011 => 3,\n _ => {assert(false, \"invalid vlmul field in vtype\"); 0}\n }" }, "links": [ { "type": "register", "id": "vtype", "file": "model/riscv_sys_regs.sail", "loc": [ 27179, 27184 ] } ] }, "get_mstatus_SXL": { "function": { "number": 0, "source": "function get_mstatus_SXL(m : Mstatus) -> arch_xlen = {\n if sizeof(xlen) == 32\n then arch_to_bits(RV32)\n else m.bits[35 .. 34]\n}", "pattern": { "type": "id", "id": "m" }, "body": " if sizeof(xlen) == 32\n then arch_to_bits(RV32)\n else m.bits[35 .. 34]" }, "links": [ { "type": "function", "id": "arch_to_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 7575, 7587 ] } ] }, "get_mstatus_UXL": { "function": { "number": 0, "source": "function get_mstatus_UXL(m : Mstatus) -> arch_xlen = {\n if sizeof(xlen) == 32\n then arch_to_bits(RV32)\n else m.bits[33 .. 32]\n}", "pattern": { "type": "id", "id": "m" }, "body": " if sizeof(xlen) == 32\n then arch_to_bits(RV32)\n else m.bits[33 .. 32]" }, "links": [ { "type": "function", "id": "arch_to_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 7902, 7914 ] } ] }, "get_mtvec": { "function": { "number": 0, "source": "function get_mtvec() -> xlenbits =\n mtvec.bits", "pattern": { "type": "literal", "value": "()" }, "body": "mtvec.bits" }, "links": [ { "type": "register", "id": "mtvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2356, 2361 ] } ] }, "get_next_pc": { "function": { "number": 0, "source": "function get_next_pc() = nextPC", "pattern": { "type": "literal", "value": "()" }, "body": "nextPC" }, "links": [ { "type": "register", "id": "nextPC", "file": "model/riscv_pc_access.sail", "loc": [ 1111, 1117 ] } ] }, "get_num_elem": { "function": { "number": 0, "source": "function get_num_elem(LMUL_pow, SEW) = {\n let VLEN = unsigned(vlenb) * 8;\n let LMUL_pow_reg = if LMUL_pow < 0 then 0 else LMUL_pow;\n /* Ignore lmul < 1 so that the entire vreg is read, allowing all masking to\n * be handled in init_masked_result */\n let num_elem = int_power(2, LMUL_pow_reg) * VLEN / SEW;\n assert(num_elem > 0);\n num_elem\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "LMUL_pow" }, { "type": "id", "id": "SEW" } ] }, "body": " let VLEN = unsigned(vlenb) * 8;\n let LMUL_pow_reg = if LMUL_pow < 0 then 0 else LMUL_pow;\n /* Ignore lmul < 1 so that the entire vreg is read, allowing all masking to\n * be handled in init_masked_result */\n let num_elem = int_power(2, LMUL_pow_reg) * VLEN / SEW;\n assert(num_elem > 0);\n num_elem" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 5708, 5716 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 5717, 5722 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "int_power", "file": "model/riscv_vext_regs.sail", "loc": [ 5924, 5933 ] } ] }, "get_scalar": { "function": { "number": 0, "source": "function get_scalar(rs1, SEW) = {\n if SEW <= sizeof(xlen) then {\n /* Least significant SEW bits */\n X(rs1)[SEW - 1 .. 0]\n } else {\n /* Sign extend to SEW */\n sign_extend(SEW, X(rs1))\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "SEW" } ] }, "body": " if SEW <= sizeof(xlen) then {\n /* Least significant SEW bits */\n X(rs1)[SEW - 1 .. 0]\n } else {\n /* Sign extend to SEW */\n sign_extend(SEW, X(rs1))\n }" }, "links": [ { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9407, 9418 ] }, { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] } ] }, "get_scalar_fp": { "function": { "number": 0, "source": "function get_scalar_fp(rs1, SEW) = {\n assert(sizeof(flen) >= SEW, \"invalid vector floating-point type width: FLEN < SEW\");\n match SEW {\n 16 => F_H(rs1),\n 32 => F_S(rs1),\n 64 => F_D(rs1)\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "SEW" } ] }, "body": "function get_scalar_fp(rs1, SEW) = {\n assert(sizeof(flen) >= SEW, \"invalid vector floating-point type width: FLEN < SEW\");\n match SEW {\n 16 => F_H(rs1),\n 32 => F_S(rs1),\n 64 => F_D(rs1)\n }" }, "links": [ { "type": "function", "id": "rF_D", "file": "model/riscv_fdext_regs.sail", "loc": [ 7127, 7131 ] }, { "type": "function", "id": "rF_S", "file": "model/riscv_fdext_regs.sail", "loc": [ 7097, 7101 ] }, { "type": "function", "id": "rF_H", "file": "model/riscv_fdext_regs.sail", "loc": [ 7067, 7071 ] } ] }, "get_sew": { "function": { "number": 0, "source": "function get_sew() = {\n match get_sew_pow() {\n 3 => 8,\n 4 => 16,\n 5 => 32,\n 6 => 64\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " match get_sew_pow() {\n 3 => 8,\n 4 => 16,\n 5 => 32,\n 6 => 64\n }" }, "links": [ { "type": "function", "id": "get_sew_pow", "file": "model/riscv_sys_regs.sail", "loc": [ 26729, 26740 ] } ] }, "get_sew_bytes": { "function": { "number": 0, "source": "function get_sew_bytes() = {\n match get_sew_pow() {\n 3 => 1,\n 4 => 2,\n 5 => 4,\n 6 => 8\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " match get_sew_pow() {\n 3 => 1,\n 4 => 2,\n 5 => 4,\n 6 => 8\n }" }, "links": [ { "type": "function", "id": "get_sew_pow", "file": "model/riscv_sys_regs.sail", "loc": [ 26926, 26937 ] } ] }, "get_sew_pow": { "function": { "number": 0, "source": "function get_sew_pow() = {\n let SEW_pow : {|3, 4, 5, 6|} = match vtype[vsew] {\n 0b000 => 3,\n 0b001 => 4,\n 0b010 => 5,\n 0b011 => 6,\n _ => {assert(false, \"invalid vsew field in vtype\"); 0}\n };\n SEW_pow\n}", "pattern": { "type": "literal", "value": "()" }, "body": " let SEW_pow : {|3, 4, 5, 6|} = match vtype[vsew] {\n 0b000 => 3,\n 0b001 => 4,\n 0b010 => 5,\n 0b011 => 6,\n _ => {assert(false, \"invalid vsew field in vtype\"); 0}\n };\n SEW_pow" }, "links": [ { "type": "register", "id": "vtype", "file": "model/riscv_sys_regs.sail", "loc": [ 26457, 26462 ] } ] }, "get_shift_amount": { "function": { "number": 0, "source": "function get_shift_amount(bit_val, SEW) = {\n let lowlog2bits = log2(SEW);\n assert(0 < lowlog2bits & lowlog2bits < 'n);\n unsigned(bit_val[lowlog2bits - 1 .. 0]);\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "bit_val" }, { "type": "id", "id": "SEW" } ] }, "body": " let lowlog2bits = log2(SEW);\n assert(0 < lowlog2bits & lowlog2bits < 'n);\n unsigned(bit_val[lowlog2bits - 1 .. 0]);" }, "links": [ { "type": "function", "id": "log2", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21007, 21011 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21066, 21074 ] } ] }, "get_sstatus_UXL": { "function": { "number": 0, "source": "function get_sstatus_UXL(s : Sstatus) -> arch_xlen = {\n let m = Mk_Mstatus(s.bits);\n get_mstatus_UXL(m)\n}", "pattern": { "type": "id", "id": "s" }, "body": " let m = Mk_Mstatus(s.bits);\n get_mstatus_UXL(m)" }, "links": [ { "type": "function", "id": "Mk_Mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 16947, 16957 ] }, { "type": "function", "id": "get_mstatus_UXL", "file": "model/riscv_sys_regs.sail", "loc": [ 16969, 16984 ] } ] }, "get_start_element": { "function": { "number": 0, "source": "function get_start_element() = {\n let start_element = unsigned(vstart);\n let VLEN_pow = get_vlen_pow();\n let SEW_pow = get_sew_pow();\n /* The use of vstart values greater than the largest element\n index for the current SEW setting is reserved.\n It is recommended that implementations trap if vstart is out of bounds.\n It is not required to trap, as a possible future use of upper vstart bits\n is to store imprecise trap information. */\n if start_element > (2 ^ (3 + VLEN_pow - SEW_pow) - 1) then handle_illegal();\n start_element\n}", "pattern": { "type": "literal", "value": "()" }, "body": " let start_element = unsigned(vstart);\n let VLEN_pow = get_vlen_pow();\n let SEW_pow = get_sew_pow();\n /* The use of vstart values greater than the largest element\n index for the current SEW setting is reserved.\n It is recommended that implementations trap if vstart is out of bounds.\n It is not required to trap, as a possible future use of upper vstart bits\n is to store imprecise trap information. */\n if start_element > (2 ^ (3 + VLEN_pow - SEW_pow) - 1) then handle_illegal();\n start_element" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9582, 9590 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9591, 9597 ] }, { "type": "function", "id": "get_vlen_pow", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9617, 9629 ] }, { "type": "function", "id": "get_sew_pow", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9649, 9660 ] }, { "type": "function", "id": "pow2", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 10001, 10004 ] }, { "type": "function", "id": "handle_illegal", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 10040, 10054 ] } ] }, "get_stvec": { "function": { "number": 0, "source": "function get_stvec() -> xlenbits =\n stvec.bits", "pattern": { "type": "literal", "value": "()" }, "body": "stvec.bits" }, "links": [ { "type": "register", "id": "stvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2405, 2410 ] } ] }, "get_utvec": { "function": { "number": 0, "source": "function get_utvec() -> xlenbits =\n utvec.bits", "pattern": { "type": "literal", "value": "()" }, "body": "utvec.bits" }, "links": [ { "type": "register", "id": "utvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2454, 2459 ] } ] }, "get_vlen_pow": { "function": { "number": 0, "source": "function get_vlen_pow() = match vlen {\n 0b0000 => 5,\n 0b0001 => 6,\n 0b0010 => 7,\n 0b0011 => 8,\n 0b0100 => 9,\n 0b0101 => 10,\n 0b0110 => 11,\n 0b0111 => 12,\n 0b1000 => 13,\n 0b1001 => 14,\n 0b1010 => 15,\n _ => 16\n}", "pattern": { "type": "literal", "value": "()" }, "body": "match vlen {\n 0b0000 => 5,\n 0b0001 => 6,\n 0b0010 => 7,\n 0b0011 => 8,\n 0b0100 => 9,\n 0b0101 => 10,\n 0b0110 => 11,\n 0b0111 => 12,\n 0b1000 => 13,\n 0b1001 => 14,\n 0b1010 => 15,\n _ => 16\n}" }, "links": [ { "type": "register", "id": "vlen", "file": "model/riscv_vlen.sail", "loc": [ 1145, 1149 ] } ] }, "get_vtype_vma": { "function": { "number": 0, "source": "function get_vtype_vma() = decode_agtype(vtype[vma])", "pattern": { "type": "literal", "value": "()" }, "body": "decode_agtype(vtype[vma])" }, "links": [ { "type": "function", "id": "decode_agtype", "file": "model/riscv_sys_regs.sail", "loc": [ 27616, 27629 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_sys_regs.sail", "loc": [ 27630, 27635 ] } ] }, "get_vtype_vta": { "function": { "number": 0, "source": "function get_vtype_vta() = decode_agtype(vtype[vta])", "pattern": { "type": "literal", "value": "()" }, "body": "decode_agtype(vtype[vta])" }, "links": [ { "type": "function", "id": "decode_agtype", "file": "model/riscv_sys_regs.sail", "loc": [ 27705, 27718 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_sys_regs.sail", "loc": [ 27719, 27724 ] } ] }, "get_xret_target": { "function": { "number": 0, "source": "function get_xret_target(p) =\n match p {\n Machine => mepc,\n Supervisor => sepc,\n User => uepc\n }", "pattern": { "type": "id", "id": "p" }, "body": "match p {\n Machine => mepc,\n Supervisor => sepc,\n User => uepc\n }" }, "links": [ { "type": "register", "id": "uepc", "file": "model/riscv_sys_exceptions.sail", "loc": [ 1913, 1917 ] }, { "type": "register", "id": "sepc", "file": "model/riscv_sys_exceptions.sail", "loc": [ 1889, 1893 ] }, { "type": "register", "id": "mepc", "file": "model/riscv_sys_exceptions.sail", "loc": [ 1865, 1869 ] } ] }, "getbyte": { "function": { "number": 0, "source": "function getbyte(x, i) = (x >> to_bits(6, i * 8))[7..0]", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "i" } ] }, "body": "(x >> to_bits(6, i * 8))[7..0]" }, "links": [ { "type": "function", "id": "shift_bits_right", "file": "model/prelude.sail", "loc": [ 6319, 6335 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_types_kext.sail", "loc": [ 11341, 11348 ] } ] }, "gfmul": { "function": { "number": 0, "source": "function gfmul( x, y) = {\n (if bit_to_bool(y[0]) then x else 0x00) ^\n (if bit_to_bool(y[1]) then xt2( x) else 0x00) ^\n (if bit_to_bool(y[2]) then xt2(xt2( x)) else 0x00) ^\n (if bit_to_bool(y[3]) then xt2(xt2(xt2(x))) else 0x00)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": " (if bit_to_bool(y[0]) then x else 0x00) ^\n (if bit_to_bool(y[1]) then xt2( x) else 0x00) ^\n (if bit_to_bool(y[2]) then xt2(xt2( x)) else 0x00) ^\n (if bit_to_bool(y[3]) then xt2(xt2(xt2(x))) else 0x00)" }, "links": [ { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_types_kext.sail", "loc": [ 1523, 1534 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 1546, 1549 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 1550, 1553 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 1554, 1557 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_types_kext.sail", "loc": [ 1464, 1475 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 1487, 1490 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 1491, 1494 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_types_kext.sail", "loc": [ 1405, 1416 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 1428, 1431 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_types_kext.sail", "loc": [ 1346, 1357 ] } ] }, "handle_exception": { "function": { "number": 0, "source": "function handle_exception(e: ExceptionType) -> unit = {\n let t : sync_exception = struct { trap = e,\n excinfo = None(),\n ext = None() } in\n set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC))\n}", "pattern": { "type": "id", "id": "e" }, "body": " let t : sync_exception = struct { trap = e,\n excinfo = None(),\n ext = None() } in\n set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC))" }, "links": [ { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 18365, 18369 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 18311, 18315 ] }, { "type": "function", "id": "set_next_pc", "file": "model/riscv_sys_control.sail", "loc": [ 18379, 18390 ] }, { "type": "function", "id": "exception_handler", "file": "model/riscv_sys_control.sail", "loc": [ 18391, 18408 ] }, { "type": "register", "id": "PC", "file": "model/riscv_sys_control.sail", "loc": [ 18437, 18439 ] }, { "type": "function", "id": "CTL_TRAP", "file": "model/riscv_sys_control.sail", "loc": [ 18424, 18432 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 18409, 18422 ] } ] }, "handle_illegal": { "function": { "number": 0, "source": "function handle_illegal() -> unit = {\n let info = if plat_mtval_has_illegal_inst_bits ()\n then Some(instbits)\n else None();\n let t : sync_exception = struct { trap = E_Illegal_Instr(),\n excinfo = info,\n ext = None() };\n set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC))\n}", "pattern": { "type": "literal", "value": "()" }, "body": " let info = if plat_mtval_has_illegal_inst_bits ()\n then Some(instbits)\n else None();\n let t : sync_exception = struct { trap = E_Illegal_Instr(),\n excinfo = info,\n ext = None() };\n set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC))" }, "links": [ { "type": "function", "id": "plat_mtval_has_illegal_inst_bits", "file": "model/riscv_platform.sail", "loc": [ 19000, 19032 ] }, { "type": "function", "id": "Some", "file": "model/riscv_platform.sail", "loc": [ 19054, 19058 ] }, { "type": "register", "id": "instbits", "file": "model/riscv_platform.sail", "loc": [ 19059, 19067 ] }, { "type": "function", "id": "None", "file": "model/riscv_platform.sail", "loc": [ 19087, 19091 ] }, { "type": "function", "id": "None", "file": "model/riscv_platform.sail", "loc": [ 19258, 19262 ] }, { "type": "function", "id": "E_Illegal_Instr", "file": "model/riscv_platform.sail", "loc": [ 19141, 19156 ] }, { "type": "function", "id": "set_next_pc", "file": "model/riscv_platform.sail", "loc": [ 19270, 19281 ] }, { "type": "function", "id": "exception_handler", "file": "model/riscv_platform.sail", "loc": [ 19282, 19299 ] }, { "type": "register", "id": "PC", "file": "model/riscv_platform.sail", "loc": [ 19328, 19330 ] }, { "type": "function", "id": "CTL_TRAP", "file": "model/riscv_platform.sail", "loc": [ 19315, 19323 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_platform.sail", "loc": [ 19300, 19313 ] } ] }, "handle_interrupt": { "function": { "number": 0, "source": "function handle_interrupt(i : InterruptType, del_priv : Privilege) -> unit =\n set_next_pc(trap_handler(del_priv, true, interruptType_to_bits(i), PC, None(), None()))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "del_priv" } ] }, "body": "set_next_pc(trap_handler(del_priv, true, interruptType_to_bits(i), PC, None(), None()))" }, "links": [ { "type": "function", "id": "set_next_pc", "file": "model/riscv_sys_control.sail", "loc": [ 18524, 18535 ] }, { "type": "function", "id": "trap_handler", "file": "model/riscv_sys_control.sail", "loc": [ 18536, 18548 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 18603, 18607 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 18595, 18599 ] }, { "type": "register", "id": "PC", "file": "model/riscv_sys_control.sail", "loc": [ 18591, 18593 ] }, { "type": "function", "id": "interruptType_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 18565, 18586 ] } ] }, "handle_mem_exception": { "function": { "number": 0, "source": "function handle_mem_exception(addr : xlenbits, e : ExceptionType) -> unit = {\n let t : sync_exception = struct { trap = e,\n excinfo = Some(addr),\n ext = None() } in\n set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "e" } ] }, "body": " let t : sync_exception = struct { trap = e,\n excinfo = Some(addr),\n ext = None() } in\n set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC))" }, "links": [ { "type": "function", "id": "None", "file": "model/riscv_sys_control.sail", "loc": [ 18080, 18084 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_control.sail", "loc": [ 18022, 18026 ] }, { "type": "function", "id": "set_next_pc", "file": "model/riscv_sys_control.sail", "loc": [ 18094, 18105 ] }, { "type": "function", "id": "exception_handler", "file": "model/riscv_sys_control.sail", "loc": [ 18106, 18123 ] }, { "type": "register", "id": "PC", "file": "model/riscv_sys_control.sail", "loc": [ 18152, 18154 ] }, { "type": "function", "id": "CTL_TRAP", "file": "model/riscv_sys_control.sail", "loc": [ 18139, 18147 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 18124, 18137 ] } ] }, "handle_trap_extension": { "function": { "number": 0, "source": "function handle_trap_extension(p : Privilege, pc : xlenbits, u : option(unit)) -> unit = ()", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "p" }, { "type": "id", "id": "pc" }, { "type": "id", "id": "u" } ] }, "body": "()" } }, "haveAtomics": { "function": { "number": 0, "source": "function haveAtomics() -> bool = misa[A] == 0b1", "pattern": { "type": "literal", "value": "()" }, "body": "misa[A] == 0b1" }, "links": [ { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 5253, 5257 ] } ] }, "haveDExt": { "function": { "number": 0, "source": "function haveDExt() -> bool = (misa[D] == 0b1) & (mstatus[FS] != 0b00)", "pattern": { "type": "literal", "value": "()" }, "body": "(misa[D] == 0b1) & (mstatus[FS] != 0b00)" }, "links": [ { "type": "register", "id": "mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 10422, 10429 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 10403, 10407 ] } ] }, "haveDoubleFPU": { "function": { "number": 0, "source": "function haveDoubleFPU() -> bool = haveDExt() | haveZdinx()", "pattern": { "type": "literal", "value": "()" }, "body": "haveDExt() | haveZdinx()" }, "links": [ { "type": "function", "id": "haveZdinx", "file": "model/riscv_insts_dext.sail", "loc": [ 7461, 7470 ] }, { "type": "function", "id": "haveDExt", "file": "model/riscv_insts_dext.sail", "loc": [ 7448, 7456 ] } ] }, "haveFExt": { "function": { "number": 0, "source": "function haveFExt() -> bool = (misa[F] == 0b1) & (mstatus[FS] != 0b00)", "pattern": { "type": "literal", "value": "()" }, "body": "(misa[F] == 0b1) & (mstatus[FS] != 0b00)" }, "links": [ { "type": "register", "id": "mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 10348, 10355 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 10329, 10333 ] } ] }, "haveHalfFPU": { "function": { "number": 0, "source": "function haveHalfFPU() -> bool = haveZfh() | haveZhinx()", "pattern": { "type": "literal", "value": "()" }, "body": "haveZfh() | haveZhinx()" }, "links": [ { "type": "function", "id": "haveZhinx", "file": "model/riscv_insts_zfh.sail", "loc": [ 5466, 5475 ] }, { "type": "function", "id": "haveZfh", "file": "model/riscv_insts_zfh.sail", "loc": [ 5454, 5461 ] } ] }, "haveMulDiv": { "function": { "number": 0, "source": "function haveMulDiv() -> bool = misa[M] == 0b1", "pattern": { "type": "literal", "value": "()" }, "body": "misa[M] == 0b1" }, "links": [ { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 5349, 5353 ] } ] }, "haveNExt": { "function": { "number": 0, "source": "function haveNExt() -> bool = misa[N] == 0b1", "pattern": { "type": "literal", "value": "()" }, "body": "misa[N] == 0b1" }, "links": [ { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 5493, 5497 ] } ] }, "haveRVC": { "function": { "number": 0, "source": "function haveRVC() -> bool = misa[C] == 0b1", "pattern": { "type": "literal", "value": "()" }, "body": "misa[C] == 0b1" }, "links": [ { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 5301, 5305 ] } ] }, "haveSingleFPU": { "function": { "number": 0, "source": "function haveSingleFPU() -> bool = haveFExt() | haveZfinx()", "pattern": { "type": "literal", "value": "()" }, "body": "haveFExt() | haveZfinx()" }, "links": [ { "type": "function", "id": "haveZfinx", "file": "model/riscv_insts_fext.sail", "loc": [ 8331, 8340 ] }, { "type": "function", "id": "haveFExt", "file": "model/riscv_insts_fext.sail", "loc": [ 8318, 8326 ] } ] }, "haveSupMode": { "function": { "number": 0, "source": "function haveSupMode() -> bool = misa[S] == 0b1", "pattern": { "type": "literal", "value": "()" }, "body": "misa[S] == 0b1" }, "links": [ { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 5397, 5401 ] } ] }, "haveUsrMode": { "function": { "number": 0, "source": "function haveUsrMode() -> bool = misa[U] == 0b1", "pattern": { "type": "literal", "value": "()" }, "body": "misa[U] == 0b1" }, "links": [ { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 5445, 5449 ] } ] }, "haveVExt": { "function": { "number": 0, "source": "function haveVExt() -> bool = (misa[V] == 0b1) & (mstatus[VS] != 0b00)", "pattern": { "type": "literal", "value": "()" }, "body": "(misa[V] == 0b1) & (mstatus[VS] != 0b00)" }, "links": [ { "type": "register", "id": "mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 10710, 10717 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 10691, 10695 ] } ] }, "haveZba": { "function": { "number": 0, "source": "function haveZba() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZbb": { "function": { "number": 0, "source": "function haveZbb() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZbc": { "function": { "number": 0, "source": "function haveZbc() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZbkb": { "function": { "number": 0, "source": "function haveZbkb() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZbkc": { "function": { "number": 0, "source": "function haveZbkc() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZbkx": { "function": { "number": 0, "source": "function haveZbkx() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZbs": { "function": { "number": 0, "source": "function haveZbs() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZdinx": { "function": { "number": 0, "source": "function haveZdinx() -> bool = sys_enable_zfinx() & sizeof(flen) >= 64", "pattern": { "type": "literal", "value": "()" }, "body": "sys_enable_zfinx() & sizeof(flen) >= 64" }, "links": [ { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_sys_regs.sail", "loc": [ 10974, 10990 ] } ] }, "haveZfa": { "function": { "number": 0, "source": "function haveZfa() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZfh": { "function": { "number": 0, "source": "function haveZfh() -> bool = (misa[F] == 0b1) & (mstatus[FS] != 0b00)", "pattern": { "type": "literal", "value": "()" }, "body": "(misa[F] == 0b1) & (mstatus[FS] != 0b00)" }, "links": [ { "type": "register", "id": "mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 10566, 10573 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 10547, 10551 ] } ] }, "haveZfinx": { "function": { "number": 0, "source": "function haveZfinx() -> bool = sys_enable_zfinx()", "pattern": { "type": "literal", "value": "()" }, "body": "sys_enable_zfinx()" }, "links": [ { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_sys_regs.sail", "loc": [ 10922, 10938 ] } ] }, "haveZhinx": { "function": { "number": 0, "source": "function haveZhinx() -> bool = sys_enable_zfinx()", "pattern": { "type": "literal", "value": "()" }, "body": "sys_enable_zfinx()" }, "links": [ { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_sys_regs.sail", "loc": [ 10870, 10886 ] } ] }, "haveZicond": { "function": { "number": 0, "source": "function haveZicond() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZknd": { "function": { "number": 0, "source": "function haveZknd() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZkne": { "function": { "number": 0, "source": "function haveZkne() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZknh": { "function": { "number": 0, "source": "function haveZknh() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZkr": { "function": { "number": 0, "source": "function haveZkr() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZksed": { "function": { "number": 0, "source": "function haveZksed() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZksh": { "function": { "number": 0, "source": "function haveZksh() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "haveZmmul": { "function": { "number": 0, "source": "function haveZmmul() -> bool = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "hex_bits_backwards": { "function": { "number": 0, "source": "function hex_bits_backwards(n, str) = parse_hex_bits(n, str)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "str" } ] }, "body": "parse_hex_bits(n, str)" }, "links": [ { "type": "function", "id": "parse_hex_bits", "file": "model/hex_bits.sail", "loc": [ 5782, 5796 ] } ] }, "hex_bits_backwards_matches": { "function": { "number": 0, "source": "function hex_bits_backwards_matches(n, str) = valid_hex_bits(n, str)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "str" } ] }, "body": "valid_hex_bits(n, str)" }, "links": [ { "type": "function", "id": "valid_hex_bits", "file": "model/hex_bits.sail", "loc": [ 5851, 5865 ] } ] }, "hex_bits_forwards": { "function": { "number": 0, "source": "function hex_bits_forwards(bv) = (length(bv), hex_str(unsigned(bv)))", "pattern": { "type": "id", "id": "bv" }, "body": "(length(bv), hex_str(unsigned(bv)))" }, "links": [ { "type": "function", "id": "hex_str", "file": "model/hex_bits.sail", "loc": [ 5674, 5681 ] }, { "type": "function", "id": "unsigned", "file": "model/hex_bits.sail", "loc": [ 5682, 5690 ] } ] }, "hex_bits_forwards_matches": { "function": { "number": 0, "source": "function hex_bits_forwards_matches(bv) = true", "pattern": { "type": "id", "id": "bv" }, "body": "true" } }, "htif_load": { "function": { "number": 0, "source": "function htif_load(t, paddr, width) = {\n if get_config_print_platform()\n then print_platform(\"htif[\" ^ BitStr(paddr) ^ \"] -> \" ^ BitStr(htif_tohost));\n /* FIXME: For now, only allow the expected access widths. */\n if width == 8 & (paddr == plat_htif_tohost())\n then MemValue(sail_zero_extend(htif_tohost, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */\n else if width == 4 & paddr == plat_htif_tohost()\n then MemValue(sail_zero_extend(htif_tohost[31..0], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */\n else if width == 4 & paddr == plat_htif_tohost() + 4\n then MemValue(sail_zero_extend(htif_tohost[63..32], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */\n else match t {\n Execute() => MemException(E_Fetch_Access_Fault()),\n Read(Data) => MemException(E_Load_Access_Fault()),\n _ => MemException(E_SAMO_Access_Fault())\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "t" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" } ] }, "body": " if get_config_print_platform()\n then print_platform(\"htif[\" ^ BitStr(paddr) ^ \"] -> \" ^ BitStr(htif_tohost));\n /* FIXME: For now, only allow the expected access widths. */\n if width == 8 & (paddr == plat_htif_tohost())\n then MemValue(sail_zero_extend(htif_tohost, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */\n else if width == 4 & paddr == plat_htif_tohost()\n then MemValue(sail_zero_extend(htif_tohost[31..0], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */\n else if width == 4 & paddr == plat_htif_tohost() + 4\n then MemValue(sail_zero_extend(htif_tohost[63..32], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */\n else match t {\n Execute() => MemException(E_Fetch_Access_Fault()),\n Read(Data) => MemException(E_Load_Access_Fault()),\n _ => MemException(E_SAMO_Access_Fault())\n }" }, "links": [ { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 13604, 13620 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 13634, 13642 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 13643, 13659 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 13660, 13671 ] }, { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 13787, 13803 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 13816, 13824 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 13825, 13841 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 13842, 13853 ] }, { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 13969, 13985 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 14002, 14010 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 14011, 14027 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 14028, 14039 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 14269, 14281 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 14282, 14301 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 14214, 14226 ] }, { "type": "function", "id": "E_Load_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 14227, 14246 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 14158, 14170 ] }, { "type": "function", "id": "E_Fetch_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 14171, 14191 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 13400, 13425 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 13435, 13449 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 13493, 13504 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "htif_store": { "function": { "number": 0, "source": "function htif_store(paddr, width, data) = {\n if get_config_print_platform()\n then print_platform(\"htif[\" ^ BitStr(paddr) ^ \"] <- \" ^ BitStr(data));\n /* Store the written value so that we can ack it later. */\n if width == 8\n then { htif_cmd_write = bitone;\n htif_payload_writes = htif_payload_writes + 1;\n htif_tohost = zero_extend(data) }\n else if width == 4 & paddr == plat_htif_tohost()\n then { if data == htif_tohost[31 .. 0]\n then htif_payload_writes = htif_payload_writes + 1\n else htif_payload_writes = 0x1;\n htif_tohost = vector_update_subrange(htif_tohost, 31, 0, data) }\n else if width == 4 & paddr == plat_htif_tohost() + 4\n then { if data[15 .. 0] == htif_tohost[47 .. 32]\n then htif_payload_writes = htif_payload_writes + 1\n else htif_payload_writes = 0x1;\n htif_cmd_write = bitone;\n htif_tohost = vector_update_subrange(htif_tohost, 63, 32, data) }\n /* unaligned command writes are not supported and will not be detected */\n else { htif_tohost = zero_extend(data) };\n\n /* Execute if there were repeated writes of the same payload without\n * a cmd (e.g. in riscv-tests), or we have a complete htif command.\n */\n if (((htif_cmd_write == bitone) & (unsigned(htif_payload_writes) > 0))\n | (unsigned(htif_payload_writes) > 2))\n then {\n let cmd = Mk_htif_cmd(htif_tohost);\n match cmd[device] {\n 0x00 => { /* syscall-proxy */\n if get_config_print_platform()\n then print_platform(\"htif-syscall-proxy cmd: \" ^ BitStr(cmd[payload]));\n if cmd[payload][0] == bitone\n then {\n htif_done = true;\n htif_exit_code = (sail_zero_extend(cmd[payload], 64) >> 1)\n }\n else ()\n },\n 0x01 => { /* terminal */\n if get_config_print_platform()\n then print_platform(\"htif-term cmd: \" ^ BitStr(cmd[payload]));\n match cmd[cmd] {\n 0x00 => /* TODO: terminal input handling */ (),\n 0x01 => plat_term_write(cmd[payload][7..0]),\n c => print(\"Unknown term cmd: \" ^ BitStr(c))\n };\n /* reset to ack */\n reset_htif()\n },\n d => print(\"htif-???? cmd: \" ^ BitStr(data))\n }\n };\n MemValue(true)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "data" } ] }, "body": " if get_config_print_platform()\n then print_platform(\"htif[\" ^ BitStr(paddr) ^ \"] <- \" ^ BitStr(data));\n /* Store the written value so that we can ack it later. */\n if width == 8\n then { htif_cmd_write = bitone;\n htif_payload_writes = htif_payload_writes + 1;\n htif_tohost = zero_extend(data) }\n else if width == 4 & paddr == plat_htif_tohost()\n then { if data == htif_tohost[31 .. 0]\n then htif_payload_writes = htif_payload_writes + 1\n else htif_payload_writes = 0x1;\n htif_tohost = vector_update_subrange(htif_tohost, 31, 0, data) }\n else if width == 4 & paddr == plat_htif_tohost() + 4\n then { if data[15 .. 0] == htif_tohost[47 .. 32]\n then htif_payload_writes = htif_payload_writes + 1\n else htif_payload_writes = 0x1;\n htif_cmd_write = bitone;\n htif_tohost = vector_update_subrange(htif_tohost, 63, 32, data) }\n /* unaligned command writes are not supported and will not be detected */\n else { htif_tohost = zero_extend(data) };\n\n /* Execute if there were repeated writes of the same payload without\n * a cmd (e.g. in riscv-tests), or we have a complete htif command.\n */\n if (((htif_cmd_write == bitone) & (unsigned(htif_payload_writes) > 0))\n | (unsigned(htif_payload_writes) > 2))\n then {\n let cmd = Mk_htif_cmd(htif_tohost);\n match cmd[device] {\n 0x00 => { /* syscall-proxy */\n if get_config_print_platform()\n then print_platform(\"htif-syscall-proxy cmd: \" ^ BitStr(cmd[payload]));\n if cmd[payload][0] == bitone\n then {\n htif_done = true;\n htif_exit_code = (sail_zero_extend(cmd[payload], 64) >> 1)\n }\n else ()\n },\n 0x01 => { /* terminal */\n if get_config_print_platform()\n then print_platform(\"htif-term cmd: \" ^ BitStr(cmd[payload]));\n match cmd[cmd] {\n 0x00 => /* TODO: terminal input handling */ (),\n 0x01 => plat_term_write(cmd[payload][7..0]),\n c => print(\"Unknown term cmd: \" ^ BitStr(c))\n };\n /* reset to ack */\n reset_htif()\n },\n d => print(\"htif-???? cmd: \" ^ BitStr(data))\n }\n };\n MemValue(true)" }, "links": [ { "type": "function", "id": "MemValue", "file": "model/riscv_platform.sail", "loc": [ 16777, 16785 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 15848, 15856 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 15857, 15876 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 15801, 15809 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 15810, 15829 ] }, { "type": "register", "id": "htif_cmd_write", "file": "model/riscv_platform.sail", "loc": [ 15772, 15786 ] }, { "type": "function", "id": "Mk_htif_cmd", "file": "model/riscv_platform.sail", "loc": [ 15907, 15918 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 15919, 15930 ] }, { "type": "function", "id": "print", "file": "model/riscv_platform.sail", "loc": [ 16724, 16729 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "reset_htif", "file": "model/riscv_platform.sail", "loc": [ 16691, 16701 ] }, { "type": "function", "id": "print", "file": "model/riscv_platform.sail", "loc": [ 16605, 16610 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "plat_term_write", "file": "model/riscv_platform.sail", "loc": [ 16550, 16565 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 16350, 16375 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 16391, 16405 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "htif_exit_code", "file": "model/riscv_platform.sail", "loc": [ 16212, 16226 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/riscv_platform.sail", "loc": [ 16230, 16246 ] }, { "type": "register", "id": "htif_done", "file": "model/riscv_platform.sail", "loc": [ 16181, 16190 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 16006, 16031 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 16047, 16061 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 14843, 14854 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 14857, 14868 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 14784, 14803 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 14806, 14825 ] }, { "type": "register", "id": "htif_cmd_write", "file": "model/riscv_platform.sail", "loc": [ 14747, 14761 ] }, { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 14909, 14925 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 15093, 15104 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 15130, 15141 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 14953, 14964 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 14991, 15010 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 15013, 15032 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 15054, 15073 ] }, { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 15190, 15206 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 15425, 15436 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 15462, 15473 ] }, { "type": "register", "id": "htif_cmd_write", "file": "model/riscv_platform.sail", "loc": [ 15388, 15402 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 15247, 15258 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 15286, 15305 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 15308, 15327 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 15349, 15368 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 15579, 15590 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 15593, 15604 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 14552, 14577 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 14587, 14601 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "htif_tick": { "function": { "number": 0, "source": "function htif_tick() = {\n if get_config_print_platform()\n then print_platform(\"htif::tick \" ^ BitStr(htif_tohost));\n htif_tohost = htif_tohost /* prevent this function being optimized out */\n}", "pattern": { "type": "literal", "value": "()" }, "body": " if get_config_print_platform()\n then print_platform(\"htif::tick \" ^ BitStr(htif_tohost));\n htif_tohost = htif_tohost" }, "links": [ { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 16946, 16957 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 16960, 16971 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_platform.sail", "loc": [ 16856, 16881 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 16891, 16905 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 16929, 16940 ] } ] }, "illegal_fp_normal": { "function": { "number": 0, "source": "function illegal_fp_normal(vd, vm, SEW, rm_3b) = {\n not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_fp_op(SEW, rm_3b))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "rm_3b" } ] }, "body": " not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_fp_op(SEW, rm_3b))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6375, 6378 ] }, { "type": "function", "id": "valid_fp_op", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6379, 6390 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6346, 6349 ] }, { "type": "function", "id": "valid_rd_mask", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6350, 6363 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6325, 6328 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6329, 6340 ] } ] }, "illegal_fp_reduction": { "function": { "number": 0, "source": "function illegal_fp_reduction(SEW, rm_3b) = {\n not(valid_vtype()) | not(assert_vstart(0)) | not(valid_fp_op(SEW, rm_3b))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "SEW" }, { "type": "id", "id": "rm_3b" } ] }, "body": " not(valid_vtype()) | not(assert_vstart(0)) | not(valid_fp_op(SEW, rm_3b))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7530, 7533 ] }, { "type": "function", "id": "valid_fp_op", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7534, 7545 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7506, 7509 ] }, { "type": "function", "id": "assert_vstart", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7510, 7523 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7485, 7488 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7489, 7500 ] } ] }, "illegal_fp_reduction_widen": { "function": { "number": 0, "source": "function illegal_fp_reduction_widen(SEW, rm_3b, SEW_widen, LMUL_pow_widen) = {\n not(valid_vtype()) | not(assert_vstart(0)) | not(valid_fp_op(SEW, rm_3b)) |\n not(valid_eew_emul(SEW_widen, LMUL_pow_widen))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "SEW" }, { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "SEW_widen" }, { "type": "id", "id": "LMUL_pow_widen" } ] }, "body": " not(valid_vtype()) | not(assert_vstart(0)) | not(valid_fp_op(SEW, rm_3b)) |\n not(valid_eew_emul(SEW_widen, LMUL_pow_widen))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7882, 7885 ] }, { "type": "function", "id": "valid_eew_emul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7886, 7900 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7849, 7852 ] }, { "type": "function", "id": "valid_fp_op", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7853, 7864 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7825, 7828 ] }, { "type": "function", "id": "assert_vstart", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7829, 7842 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7804, 7807 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7808, 7819 ] } ] }, "illegal_fp_variable_width": { "function": { "number": 0, "source": "function illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_new, LMUL_pow_new) = {\n not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_fp_op(SEW, rm_3b)) |\n not(valid_eew_emul(SEW_new, LMUL_pow_new))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "SEW_new" }, { "type": "id", "id": "LMUL_pow_new" } ] }, "body": " not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_fp_op(SEW, rm_3b)) |\n not(valid_eew_emul(SEW_new, LMUL_pow_new))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7263, 7266 ] }, { "type": "function", "id": "valid_eew_emul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7267, 7281 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7230, 7233 ] }, { "type": "function", "id": "valid_fp_op", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7234, 7245 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7201, 7204 ] }, { "type": "function", "id": "valid_rd_mask", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7205, 7218 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7180, 7183 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 7184, 7195 ] } ] }, "illegal_fp_vd_masked": { "function": { "number": 0, "source": "function illegal_fp_vd_masked(vd, SEW, rm_3b) = {\n not(valid_vtype()) | vd == 0b00000 | not(valid_fp_op(SEW, rm_3b))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "rm_3b" } ] }, "body": " not(valid_vtype()) | vd == 0b00000 | not(valid_fp_op(SEW, rm_3b))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6642, 6645 ] }, { "type": "function", "id": "valid_fp_op", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6646, 6657 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6605, 6608 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6609, 6620 ] } ] }, "illegal_fp_vd_unmasked": { "function": { "number": 0, "source": "function illegal_fp_vd_unmasked(SEW, rm_3b) = {\n not(valid_vtype()) | not(valid_fp_op(SEW, rm_3b))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "SEW" }, { "type": "id", "id": "rm_3b" } ] }, "body": " not(valid_vtype()) | not(valid_fp_op(SEW, rm_3b))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6887, 6890 ] }, { "type": "function", "id": "valid_fp_op", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6891, 6902 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6866, 6869 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6870, 6881 ] } ] }, "illegal_indexed_load": { "function": { "number": 0, "source": "function illegal_indexed_load(vd, vm, nf, EEW_index, EMUL_pow_index, EMUL_pow_data) = {\n not(valid_vtype()) | not(valid_rd_mask(vd, vm)) |\n not(valid_eew_emul(EEW_index, EMUL_pow_index)) | not(valid_segment(nf, EMUL_pow_data))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "nf" }, { "type": "id", "id": "EEW_index" }, { "type": "id", "id": "EMUL_pow_index" }, { "type": "id", "id": "EMUL_pow_data" } ] }, "body": " not(valid_vtype()) | not(valid_rd_mask(vd, vm)) |\n not(valid_eew_emul(EEW_index, EMUL_pow_index)) | not(valid_segment(nf, EMUL_pow_data))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8777, 8780 ] }, { "type": "function", "id": "valid_segment", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8781, 8794 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8728, 8731 ] }, { "type": "function", "id": "valid_eew_emul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8732, 8746 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8697, 8700 ] }, { "type": "function", "id": "valid_rd_mask", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8701, 8714 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8676, 8679 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8680, 8691 ] } ] }, "illegal_indexed_store": { "function": { "number": 0, "source": "function illegal_indexed_store(nf, EEW_index, EMUL_pow_index, EMUL_pow_data) = {\n not(valid_vtype()) | not(valid_eew_emul(EEW_index, EMUL_pow_index)) |\n not(valid_segment(nf, EMUL_pow_data))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "EEW_index" }, { "type": "id", "id": "EMUL_pow_index" }, { "type": "id", "id": "EMUL_pow_data" } ] }, "body": " not(valid_vtype()) | not(valid_eew_emul(EEW_index, EMUL_pow_index)) |\n not(valid_segment(nf, EMUL_pow_data))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9097, 9100 ] }, { "type": "function", "id": "valid_segment", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9101, 9114 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9046, 9049 ] }, { "type": "function", "id": "valid_eew_emul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9050, 9064 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9025, 9028 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 9029, 9040 ] } ] }, "illegal_load": { "function": { "number": 0, "source": "function illegal_load(vd, vm, nf, EEW, EMUL_pow) = {\n not(valid_vtype()) | not(valid_rd_mask(vd, vm)) |\n not(valid_eew_emul(EEW, EMUL_pow)) | not(valid_segment(nf, EMUL_pow))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "nf" }, { "type": "id", "id": "EEW" }, { "type": "id", "id": "EMUL_pow" } ] }, "body": " not(valid_vtype()) | not(valid_rd_mask(vd, vm)) |\n not(valid_eew_emul(EEW, EMUL_pow)) | not(valid_segment(nf, EMUL_pow))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8180, 8183 ] }, { "type": "function", "id": "valid_segment", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8184, 8197 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8143, 8146 ] }, { "type": "function", "id": "valid_eew_emul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8147, 8161 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8112, 8115 ] }, { "type": "function", "id": "valid_rd_mask", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8116, 8129 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8091, 8094 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8095, 8106 ] } ] }, "illegal_normal": { "function": { "number": 0, "source": "function illegal_normal(vd, vm) = {\n not(valid_vtype()) | not(valid_rd_mask(vd, vm))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "vm" } ] }, "body": " not(valid_vtype()) | not(valid_rd_mask(vd, vm))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 4584, 4587 ] }, { "type": "function", "id": "valid_rd_mask", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 4588, 4601 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 4563, 4566 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 4567, 4578 ] } ] }, "illegal_reduction": { "function": { "number": 0, "source": "function illegal_reduction() = {\n not(valid_vtype()) | not(assert_vstart(0))\n}", "pattern": { "type": "literal", "value": "()" }, "body": " not(valid_vtype()) | not(assert_vstart(0))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5839, 5842 ] }, { "type": "function", "id": "assert_vstart", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5843, 5856 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5818, 5821 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5822, 5833 ] } ] }, "illegal_reduction_widen": { "function": { "number": 0, "source": "function illegal_reduction_widen(SEW_widen, LMUL_pow_widen) = {\n not(valid_vtype()) | not(assert_vstart(0)) | not(valid_eew_emul(SEW_widen, LMUL_pow_widen))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "SEW_widen" }, { "type": "id", "id": "LMUL_pow_widen" } ] }, "body": " not(valid_vtype()) | not(assert_vstart(0)) | not(valid_eew_emul(SEW_widen, LMUL_pow_widen))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6090, 6093 ] }, { "type": "function", "id": "valid_eew_emul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6094, 6108 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6066, 6069 ] }, { "type": "function", "id": "assert_vstart", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6070, 6083 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6045, 6048 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 6049, 6060 ] } ] }, "illegal_store": { "function": { "number": 0, "source": "function illegal_store(nf, EEW, EMUL_pow) = {\n not(valid_vtype()) | not(valid_eew_emul(EEW, EMUL_pow)) | not(valid_segment(nf, EMUL_pow))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "EEW" }, { "type": "id", "id": "EMUL_pow" } ] }, "body": " not(valid_vtype()) | not(valid_eew_emul(EEW, EMUL_pow)) | not(valid_segment(nf, EMUL_pow))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8437, 8440 ] }, { "type": "function", "id": "valid_segment", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8441, 8454 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8400, 8403 ] }, { "type": "function", "id": "valid_eew_emul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8404, 8418 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8379, 8382 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 8383, 8394 ] } ] }, "illegal_variable_width": { "function": { "number": 0, "source": "function illegal_variable_width(vd, vm, SEW_new, LMUL_pow_new) = {\n not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_eew_emul(SEW_new, LMUL_pow_new))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "SEW_new" }, { "type": "id", "id": "LMUL_pow_new" } ] }, "body": " not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_eew_emul(SEW_new, LMUL_pow_new))" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5457, 5460 ] }, { "type": "function", "id": "valid_eew_emul", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5461, 5475 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5428, 5431 ] }, { "type": "function", "id": "valid_rd_mask", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5432, 5445 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5407, 5410 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5411, 5422 ] } ] }, "illegal_vd_masked": { "function": { "number": 0, "source": "function illegal_vd_masked(vd) = {\n not(valid_vtype()) | vd == 0b00000\n}", "pattern": { "type": "id", "id": "vd" }, "body": " not(valid_vtype()) | vd == 0b00000" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 4749, 4752 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 4753, 4764 ] } ] }, "illegal_vd_unmasked": { "function": { "number": 0, "source": "function illegal_vd_unmasked() = {\n not(valid_vtype())\n}", "pattern": { "type": "literal", "value": "()" }, "body": " not(valid_vtype())" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5110, 5113 ] }, { "type": "function", "id": "valid_vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 5114, 5125 ] } ] }, "in32BitMode": { "function": { "number": 0, "source": "function in32BitMode() -> bool = {\n cur_Architecture() == RV32\n}", "pattern": { "type": "literal", "value": "()" }, "body": " cur_Architecture() == RV32" }, "links": [ { "type": "function", "id": "cur_Architecture", "file": "model/riscv_sys_regs.sail", "loc": [ 10183, 10199 ] } ] }, "init_TLB": { "function": { "number": 0, "source": "function init_TLB() -> unit =\n tlb = None()", "pattern": { "type": "literal", "value": "()" }, "body": "tlb = None()" }, "links": [ { "type": "register", "id": "tlb", "file": "model/riscv_vmem_tlb.sail", "loc": [ 1654, 1657 ] }, { "type": "function", "id": "None", "file": "model/riscv_vmem_tlb.sail", "loc": [ 1660, 1664 ] } ] }, "init_base_regs": { "function": { "number": 0, "source": "function init_base_regs () = {\n x1 = zero_reg;\n x2 = zero_reg;\n x3 = zero_reg;\n x4 = zero_reg;\n x5 = zero_reg;\n x6 = zero_reg;\n x7 = zero_reg;\n x8 = zero_reg;\n x9 = zero_reg;\n x10 = zero_reg;\n x11 = zero_reg;\n x12 = zero_reg;\n x13 = zero_reg;\n x14 = zero_reg;\n x15 = zero_reg;\n x16 = zero_reg;\n x17 = zero_reg;\n x18 = zero_reg;\n x19 = zero_reg;\n x20 = zero_reg;\n x21 = zero_reg;\n x22 = zero_reg;\n x23 = zero_reg;\n x24 = zero_reg;\n x25 = zero_reg;\n x26 = zero_reg;\n x27 = zero_reg;\n x28 = zero_reg;\n x29 = zero_reg;\n x30 = zero_reg;\n x31 = zero_reg\n}", "pattern": { "type": "literal", "value": "()" }, "body": " x1 = zero_reg;\n x2 = zero_reg;\n x3 = zero_reg;\n x4 = zero_reg;\n x5 = zero_reg;\n x6 = zero_reg;\n x7 = zero_reg;\n x8 = zero_reg;\n x9 = zero_reg;\n x10 = zero_reg;\n x11 = zero_reg;\n x12 = zero_reg;\n x13 = zero_reg;\n x14 = zero_reg;\n x15 = zero_reg;\n x16 = zero_reg;\n x17 = zero_reg;\n x18 = zero_reg;\n x19 = zero_reg;\n x20 = zero_reg;\n x21 = zero_reg;\n x22 = zero_reg;\n x23 = zero_reg;\n x24 = zero_reg;\n x25 = zero_reg;\n x26 = zero_reg;\n x27 = zero_reg;\n x28 = zero_reg;\n x29 = zero_reg;\n x30 = zero_reg;\n x31 = zero_reg" }, "links": [ { "type": "register", "id": "x31", "file": "model/riscv_regs.sail", "loc": [ 6187, 6190 ] }, { "type": "register", "id": "x30", "file": "model/riscv_regs.sail", "loc": [ 6169, 6172 ] }, { "type": "register", "id": "x29", "file": "model/riscv_regs.sail", "loc": [ 6151, 6154 ] }, { "type": "register", "id": "x28", "file": "model/riscv_regs.sail", "loc": [ 6133, 6136 ] }, { "type": "register", "id": "x27", "file": "model/riscv_regs.sail", "loc": [ 6115, 6118 ] }, { "type": "register", "id": "x26", "file": "model/riscv_regs.sail", "loc": [ 6097, 6100 ] }, { "type": "register", "id": "x25", "file": "model/riscv_regs.sail", "loc": [ 6079, 6082 ] }, { "type": "register", "id": "x24", "file": "model/riscv_regs.sail", "loc": [ 6061, 6064 ] }, { "type": "register", "id": "x23", "file": "model/riscv_regs.sail", "loc": [ 6043, 6046 ] }, { "type": "register", "id": "x22", "file": "model/riscv_regs.sail", "loc": [ 6025, 6028 ] }, { "type": "register", "id": "x21", "file": "model/riscv_regs.sail", "loc": [ 6007, 6010 ] }, { "type": "register", "id": "x20", "file": "model/riscv_regs.sail", "loc": [ 5989, 5992 ] }, { "type": "register", "id": "x19", "file": "model/riscv_regs.sail", "loc": [ 5971, 5974 ] }, { "type": "register", "id": "x18", "file": "model/riscv_regs.sail", "loc": [ 5953, 5956 ] }, { "type": "register", "id": "x17", "file": "model/riscv_regs.sail", "loc": [ 5935, 5938 ] }, { "type": "register", "id": "x16", "file": "model/riscv_regs.sail", "loc": [ 5917, 5920 ] }, { "type": "register", "id": "x15", "file": "model/riscv_regs.sail", "loc": [ 5899, 5902 ] }, { "type": "register", "id": "x14", "file": "model/riscv_regs.sail", "loc": [ 5881, 5884 ] }, { "type": "register", "id": "x13", "file": "model/riscv_regs.sail", "loc": [ 5863, 5866 ] }, { "type": "register", "id": "x12", "file": "model/riscv_regs.sail", "loc": [ 5845, 5848 ] }, { "type": "register", "id": "x11", "file": "model/riscv_regs.sail", "loc": [ 5827, 5830 ] }, { "type": "register", "id": "x10", "file": "model/riscv_regs.sail", "loc": [ 5809, 5812 ] }, { "type": "register", "id": "x9", "file": "model/riscv_regs.sail", "loc": [ 5791, 5793 ] }, { "type": "register", "id": "x8", "file": "model/riscv_regs.sail", "loc": [ 5773, 5775 ] }, { "type": "register", "id": "x7", "file": "model/riscv_regs.sail", "loc": [ 5755, 5757 ] }, { "type": "register", "id": "x6", "file": "model/riscv_regs.sail", "loc": [ 5737, 5739 ] }, { "type": "register", "id": "x5", "file": "model/riscv_regs.sail", "loc": [ 5719, 5721 ] }, { "type": "register", "id": "x4", "file": "model/riscv_regs.sail", "loc": [ 5701, 5703 ] }, { "type": "register", "id": "x3", "file": "model/riscv_regs.sail", "loc": [ 5683, 5685 ] }, { "type": "register", "id": "x2", "file": "model/riscv_regs.sail", "loc": [ 5665, 5667 ] }, { "type": "register", "id": "x1", "file": "model/riscv_regs.sail", "loc": [ 5647, 5649 ] } ] }, "init_fdext_regs": { "function": { "number": 0, "source": "function init_fdext_regs () = {\n f0 = zero_freg;\n f1 = zero_freg;\n f2 = zero_freg;\n f3 = zero_freg;\n f4 = zero_freg;\n f5 = zero_freg;\n f6 = zero_freg;\n f7 = zero_freg;\n f8 = zero_freg;\n f9 = zero_freg;\n f10 = zero_freg;\n f11 = zero_freg;\n f12 = zero_freg;\n f13 = zero_freg;\n f14 = zero_freg;\n f15 = zero_freg;\n f16 = zero_freg;\n f17 = zero_freg;\n f18 = zero_freg;\n f19 = zero_freg;\n f20 = zero_freg;\n f21 = zero_freg;\n f22 = zero_freg;\n f23 = zero_freg;\n f24 = zero_freg;\n f25 = zero_freg;\n f26 = zero_freg;\n f27 = zero_freg;\n f28 = zero_freg;\n f29 = zero_freg;\n f30 = zero_freg;\n f31 = zero_freg\n}", "pattern": { "type": "literal", "value": "()" }, "body": " f0 = zero_freg;\n f1 = zero_freg;\n f2 = zero_freg;\n f3 = zero_freg;\n f4 = zero_freg;\n f5 = zero_freg;\n f6 = zero_freg;\n f7 = zero_freg;\n f8 = zero_freg;\n f9 = zero_freg;\n f10 = zero_freg;\n f11 = zero_freg;\n f12 = zero_freg;\n f13 = zero_freg;\n f14 = zero_freg;\n f15 = zero_freg;\n f16 = zero_freg;\n f17 = zero_freg;\n f18 = zero_freg;\n f19 = zero_freg;\n f20 = zero_freg;\n f21 = zero_freg;\n f22 = zero_freg;\n f23 = zero_freg;\n f24 = zero_freg;\n f25 = zero_freg;\n f26 = zero_freg;\n f27 = zero_freg;\n f28 = zero_freg;\n f29 = zero_freg;\n f30 = zero_freg;\n f31 = zero_freg" }, "links": [ { "type": "register", "id": "f31", "file": "model/riscv_fdext_regs.sail", "loc": [ 11470, 11473 ] }, { "type": "register", "id": "f30", "file": "model/riscv_fdext_regs.sail", "loc": [ 11451, 11454 ] }, { "type": "register", "id": "f29", "file": "model/riscv_fdext_regs.sail", "loc": [ 11432, 11435 ] }, { "type": "register", "id": "f28", "file": "model/riscv_fdext_regs.sail", "loc": [ 11413, 11416 ] }, { "type": "register", "id": "f27", "file": "model/riscv_fdext_regs.sail", "loc": [ 11394, 11397 ] }, { "type": "register", "id": "f26", "file": "model/riscv_fdext_regs.sail", "loc": [ 11375, 11378 ] }, { "type": "register", "id": "f25", "file": "model/riscv_fdext_regs.sail", "loc": [ 11356, 11359 ] }, { "type": "register", "id": "f24", "file": "model/riscv_fdext_regs.sail", "loc": [ 11337, 11340 ] }, { "type": "register", "id": "f23", "file": "model/riscv_fdext_regs.sail", "loc": [ 11318, 11321 ] }, { "type": "register", "id": "f22", "file": "model/riscv_fdext_regs.sail", "loc": [ 11299, 11302 ] }, { "type": "register", "id": "f21", "file": "model/riscv_fdext_regs.sail", "loc": [ 11280, 11283 ] }, { "type": "register", "id": "f20", "file": "model/riscv_fdext_regs.sail", "loc": [ 11261, 11264 ] }, { "type": "register", "id": "f19", "file": "model/riscv_fdext_regs.sail", "loc": [ 11242, 11245 ] }, { "type": "register", "id": "f18", "file": "model/riscv_fdext_regs.sail", "loc": [ 11223, 11226 ] }, { "type": "register", "id": "f17", "file": "model/riscv_fdext_regs.sail", "loc": [ 11204, 11207 ] }, { "type": "register", "id": "f16", "file": "model/riscv_fdext_regs.sail", "loc": [ 11185, 11188 ] }, { "type": "register", "id": "f15", "file": "model/riscv_fdext_regs.sail", "loc": [ 11166, 11169 ] }, { "type": "register", "id": "f14", "file": "model/riscv_fdext_regs.sail", "loc": [ 11147, 11150 ] }, { "type": "register", "id": "f13", "file": "model/riscv_fdext_regs.sail", "loc": [ 11128, 11131 ] }, { "type": "register", "id": "f12", "file": "model/riscv_fdext_regs.sail", "loc": [ 11109, 11112 ] }, { "type": "register", "id": "f11", "file": "model/riscv_fdext_regs.sail", "loc": [ 11090, 11093 ] }, { "type": "register", "id": "f10", "file": "model/riscv_fdext_regs.sail", "loc": [ 11071, 11074 ] }, { "type": "register", "id": "f9", "file": "model/riscv_fdext_regs.sail", "loc": [ 11052, 11054 ] }, { "type": "register", "id": "f8", "file": "model/riscv_fdext_regs.sail", "loc": [ 11033, 11035 ] }, { "type": "register", "id": "f7", "file": "model/riscv_fdext_regs.sail", "loc": [ 11014, 11016 ] }, { "type": "register", "id": "f6", "file": "model/riscv_fdext_regs.sail", "loc": [ 10995, 10997 ] }, { "type": "register", "id": "f5", "file": "model/riscv_fdext_regs.sail", "loc": [ 10976, 10978 ] }, { "type": "register", "id": "f4", "file": "model/riscv_fdext_regs.sail", "loc": [ 10957, 10959 ] }, { "type": "register", "id": "f3", "file": "model/riscv_fdext_regs.sail", "loc": [ 10938, 10940 ] }, { "type": "register", "id": "f2", "file": "model/riscv_fdext_regs.sail", "loc": [ 10919, 10921 ] }, { "type": "register", "id": "f1", "file": "model/riscv_fdext_regs.sail", "loc": [ 10900, 10902 ] }, { "type": "register", "id": "f0", "file": "model/riscv_fdext_regs.sail", "loc": [ 10881, 10883 ] } ] }, "init_masked_result": { "function": { "number": 0, "source": "function init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val) = {\n let start_element = get_start_element();\n let end_element = get_end_element();\n let tail_ag : agtype = get_vtype_vta();\n let mask_ag : agtype = get_vtype_vma();\n mask : vector('n, dec, bool) = undefined;\n result : vector('n, dec, bits('m)) = undefined;\n\n /* Determine the actual number of elements when lmul < 1 */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / int_power(2, 0 - LMUL_pow);\n assert(num_elem >= real_num_elem);\n\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n /* Prestart elements defined by vstart */\n result[i] = vd_val[i];\n mask[i] = false\n } else if i > end_element then {\n /* Tail elements defined by vl */\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n };\n mask[i] = false\n } else if i >= real_num_elem then {\n /* Tail elements defined by lmul < 1 */\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n };\n mask[i] = false\n } else if not(vm_val[i]) then {\n /* Inactive body elements defined by vm */\n result[i] = match mask_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n };\n mask[i] = false\n } else {\n /* Active body elements */\n mask[i] = true;\n }\n };\n\n (result, mask)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "LMUL_pow" }, { "type": "id", "id": "vd_val" }, { "type": "id", "id": "vm_val" } ] }, "body": " let start_element = get_start_element();\n let end_element = get_end_element();\n let tail_ag : agtype = get_vtype_vta();\n let mask_ag : agtype = get_vtype_vma();\n mask : vector('n, dec, bool) = undefined;\n result : vector('n, dec, bits('m)) = undefined;\n\n /* Determine the actual number of elements when lmul < 1 */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / int_power(2, 0 - LMUL_pow);\n assert(num_elem >= real_num_elem);\n\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n /* Prestart elements defined by vstart */\n result[i] = vd_val[i];\n mask[i] = false\n } else if i > end_element then {\n /* Tail elements defined by vl */\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n };\n mask[i] = false\n } else if i >= real_num_elem then {\n /* Tail elements defined by lmul < 1 */\n result[i] = match tail_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n };\n mask[i] = false\n } else if not(vm_val[i]) then {\n /* Inactive body elements defined by vm */\n result[i] = match mask_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n };\n mask[i] = false\n } else {\n /* Active body elements */\n mask[i] = true;\n }\n };\n\n (result, mask)" }, "links": [ { "type": "function", "id": "get_start_element", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 10951, 10968 ] }, { "type": "function", "id": "get_end_element", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 10994, 11009 ] }, { "type": "function", "id": "get_vtype_vta", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 11038, 11051 ] }, { "type": "function", "id": "get_vtype_vma", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 11080, 11093 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 11323, 11332 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 12070, 12073 ] } ] }, "init_masked_result_carry": { "function": { "number": 0, "source": "function init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val) = {\n let start_element = get_start_element();\n let end_element = get_end_element();\n mask : vector('n, dec, bool) = undefined;\n result : vector('n, dec, bool) = undefined;\n\n /* Determine the actual number of elements when lmul < 1 */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / int_power(2, 0 - LMUL_pow);\n assert(num_elem >= real_num_elem);\n\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n /* Prestart elements defined by vstart */\n result[i] = vd_val[i];\n mask[i] = false\n } else if i > end_element then {\n /* Tail elements defined by vl */\n /* Mask tail is always agnostic */\n result[i] = vd_val[i]; /* TODO: configuration support */\n mask[i] = false\n } else if i >= real_num_elem then {\n /* Tail elements defined by lmul < 1 */\n /* Mask tail is always agnostic */\n result[i] = vd_val[i]; /* TODO: configuration support */\n mask[i] = false\n } else {\n /* Active body elements */\n mask[i] = true\n }\n };\n\n (result, mask)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "LMUL_pow" }, { "type": "id", "id": "vd_val" } ] }, "body": " let start_element = get_start_element();\n let end_element = get_end_element();\n mask : vector('n, dec, bool) = undefined;\n result : vector('n, dec, bool) = undefined;\n\n /* Determine the actual number of elements when lmul < 1 */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / int_power(2, 0 - LMUL_pow);\n assert(num_elem >= real_num_elem);\n\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n /* Prestart elements defined by vstart */\n result[i] = vd_val[i];\n mask[i] = false\n } else if i > end_element then {\n /* Tail elements defined by vl */\n /* Mask tail is always agnostic */\n result[i] = vd_val[i]; /* TODO: configuration support */\n mask[i] = false\n } else if i >= real_num_elem then {\n /* Tail elements defined by lmul < 1 */\n /* Mask tail is always agnostic */\n result[i] = vd_val[i]; /* TODO: configuration support */\n mask[i] = false\n } else {\n /* Active body elements */\n mask[i] = true\n }\n };\n\n (result, mask)" }, "links": [ { "type": "function", "id": "get_start_element", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 14223, 14240 ] }, { "type": "function", "id": "get_end_element", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 14266, 14281 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 14507, 14516 ] } ] }, "init_masked_result_cmp": { "function": { "number": 0, "source": "function init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val) = {\n let start_element = get_start_element();\n let end_element = get_end_element();\n let mask_ag : agtype = get_vtype_vma();\n mask : vector('n, dec, bool) = undefined;\n result : vector('n, dec, bool) = undefined;\n\n /* Determine the actual number of elements when lmul < 1 */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / int_power(2, 0 - LMUL_pow);\n assert(num_elem >= real_num_elem);\n\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n /* Prestart elements defined by vstart */\n result[i] = vd_val[i];\n mask[i] = false\n } else if i > end_element then {\n /* Tail elements defined by vl */\n /* Mask tail is always agnostic */\n result[i] = vd_val[i]; /* TODO: configuration support */\n mask[i] = false\n } else if i >= real_num_elem then {\n /* Tail elements defined by lmul < 1 */\n /* Mask tail is always agnostic */\n result[i] = vd_val[i]; /* TODO: configuration support */\n mask[i] = false\n } else if not(vm_val[i]) then {\n /* Inactive body elements defined by vm */\n result[i] = match mask_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n };\n mask[i] = false\n } else {\n /* Active body elements */\n mask[i] = true\n }\n };\n\n (result, mask)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "LMUL_pow" }, { "type": "id", "id": "vd_val" }, { "type": "id", "id": "vm_val" } ] }, "body": " let start_element = get_start_element();\n let end_element = get_end_element();\n let mask_ag : agtype = get_vtype_vma();\n mask : vector('n, dec, bool) = undefined;\n result : vector('n, dec, bool) = undefined;\n\n /* Determine the actual number of elements when lmul < 1 */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / int_power(2, 0 - LMUL_pow);\n assert(num_elem >= real_num_elem);\n\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n /* Prestart elements defined by vstart */\n result[i] = vd_val[i];\n mask[i] = false\n } else if i > end_element then {\n /* Tail elements defined by vl */\n /* Mask tail is always agnostic */\n result[i] = vd_val[i]; /* TODO: configuration support */\n mask[i] = false\n } else if i >= real_num_elem then {\n /* Tail elements defined by lmul < 1 */\n /* Mask tail is always agnostic */\n result[i] = vd_val[i]; /* TODO: configuration support */\n mask[i] = false\n } else if not(vm_val[i]) then {\n /* Inactive body elements defined by vm */\n result[i] = match mask_ag {\n UNDISTURBED => vd_val[i],\n AGNOSTIC => vd_val[i] /* TODO: configuration support */\n };\n mask[i] = false\n } else {\n /* Active body elements */\n mask[i] = true\n }\n };\n\n (result, mask)" }, "links": [ { "type": "function", "id": "get_start_element", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 15600, 15617 ] }, { "type": "function", "id": "get_end_element", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 15643, 15658 ] }, { "type": "function", "id": "get_vtype_vma", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 15687, 15700 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 15926, 15935 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 16593, 16596 ] } ] }, "init_masked_source": { "function": { "number": 0, "source": "function init_masked_source(num_elem, LMUL_pow, vm_val) = {\n let start_element = get_start_element();\n let end_element = get_end_element();\n mask : vector('n, dec, bool) = undefined;\n\n /* Determine the actual number of elements when lmul < 1 */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / int_power(2, 0 - LMUL_pow);\n assert(num_elem >= real_num_elem);\n\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n /* Prestart elements defined by vstart */\n mask[i] = false\n } else if i > end_element then {\n /* Tail elements defined by vl */\n mask[i] = false\n } else if i >= real_num_elem then {\n /* Tail elements defined by lmul < 1 */\n mask[i] = false\n } else if not(vm_val[i]) then {\n /* Inactive body elements defined by vm */\n mask[i] = false\n } else {\n /* Active body elements */\n mask[i] = true;\n }\n };\n\n mask\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "LMUL_pow" }, { "type": "id", "id": "vm_val" } ] }, "body": " let start_element = get_start_element();\n let end_element = get_end_element();\n mask : vector('n, dec, bool) = undefined;\n\n /* Determine the actual number of elements when lmul < 1 */\n let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / int_power(2, 0 - LMUL_pow);\n assert(num_elem >= real_num_elem);\n\n foreach (i from 0 to (num_elem - 1)) {\n if i < start_element then {\n /* Prestart elements defined by vstart */\n mask[i] = false\n } else if i > end_element then {\n /* Tail elements defined by vl */\n mask[i] = false\n } else if i >= real_num_elem then {\n /* Tail elements defined by lmul < 1 */\n mask[i] = false\n } else if not(vm_val[i]) then {\n /* Inactive body elements defined by vm */\n mask[i] = false\n } else {\n /* Active body elements */\n mask[i] = true;\n }\n };\n\n mask" }, "links": [ { "type": "function", "id": "get_start_element", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 12985, 13002 ] }, { "type": "function", "id": "get_end_element", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 13028, 13043 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 13223, 13232 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 13653, 13656 ] } ] }, "init_model": { "function": { "number": 0, "source": "function init_model () -> unit = {\n init_platform (); /* devices */\n init_sys (); /* processor */\n init_vmem (); /* virtual memory */\n\n /* initialize extensions last */\n ext_init ();\n ext_init_regs ();\n}", "pattern": { "type": "literal", "value": "()" }, "body": " init_platform (); /* devices */\n init_sys (); /* processor */\n init_vmem (); /* virtual memory */\n\n /* initialize extensions last */\n ext_init ();\n ext_init_regs ()" }, "links": [ { "type": "function", "id": "ext_init_regs", "file": "model/riscv_step.sail", "loc": [ 4209, 4222 ] }, { "type": "function", "id": "ext_init", "file": "model/riscv_step.sail", "loc": [ 4194, 4202 ] }, { "type": "function", "id": "init_vmem", "file": "model/riscv_step.sail", "loc": [ 4117, 4126 ] }, { "type": "function", "id": "init_sys", "file": "model/riscv_step.sail", "loc": [ 4081, 4089 ] }, { "type": "function", "id": "init_platform", "file": "model/riscv_step.sail", "loc": [ 4047, 4060 ] } ] }, "init_platform": { "function": { "number": 0, "source": "function init_platform() -> unit = {\n htif_tohost = zero_extend(0b0);\n htif_done = false;\n htif_exit_code = zero_extend(0b0);\n htif_cmd_write = bitzero;\n htif_payload_writes = zero_extend(0b0);\n}", "pattern": { "type": "literal", "value": "()" }, "body": " htif_tohost = zero_extend(0b0);\n htif_done = false;\n htif_exit_code = zero_extend(0b0);\n htif_cmd_write = bitzero;\n htif_payload_writes = zero_extend(0b0)" }, "links": [ { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 18792, 18811 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 18814, 18825 ] }, { "type": "register", "id": "htif_cmd_write", "file": "model/riscv_platform.sail", "loc": [ 18764, 18778 ] }, { "type": "register", "id": "htif_exit_code", "file": "model/riscv_platform.sail", "loc": [ 18727, 18741 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 18744, 18755 ] }, { "type": "register", "id": "htif_done", "file": "model/riscv_platform.sail", "loc": [ 18704, 18713 ] }, { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 18670, 18681 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 18684, 18695 ] } ] }, "init_pmp": { "function": { "number": 0, "source": "function init_pmp() -> unit = {\n assert(\n sys_pmp_count() == 0 | sys_pmp_count() == 16 | sys_pmp_count() == 64,\n \"sys_pmp_count() must be 0, 16, or 64\"\n );\n\n foreach (i from 0 to 63) {\n // On reset the PMP register's A and L bits are set to 0 unless the plaform\n // mandates a different value.\n pmpcfg_n[i] = [pmpcfg_n[i] with A = pmpAddrMatchType_to_bits(OFF), L = 0b0];\n };\n}", "pattern": { "type": "literal", "value": "()" }, "body": "function init_pmp() -> unit = {\n assert(\n sys_pmp_count() == 0 | sys_pmp_count() == 16 | sys_pmp_count() == 64,\n \"sys_pmp_count() must be 0, 16, or 64\"\n );\n\n foreach (i from 0 to 63) {\n // On reset the PMP register's A and L bits are set to 0 unless the plaform\n // mandates a different value.\n pmpcfg_n[i] = [pmpcfg_n[i] with A = pmpAddrMatchType_to_bits(OFF), L = 0b0];\n }" }, "links": [ { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_control.sail", "loc": [ 5008, 5016 ] }, { "type": "function", "id": "pmpAddrMatchType_to_bits", "file": "model/riscv_pmp_control.sail", "loc": [ 5044, 5068 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_control.sail", "loc": [ 5023, 5031 ] }, { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_pmp_control.sail", "loc": [ 4788, 4801 ] }, { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_pmp_control.sail", "loc": [ 4764, 4777 ] }, { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_pmp_control.sail", "loc": [ 4741, 4754 ] } ] }, "init_sys": { "function": { "number": 0, "source": "function init_sys() -> unit = {\n cur_privilege = Machine;\n\n mhartid = zero_extend(0b0);\n\n misa[MXL] = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);\n misa[A] = 0b1; /* atomics */\n misa[C] = bool_to_bits(sys_enable_rvc()); /* RVC */\n misa[I] = 0b1; /* base integer ISA */\n misa[M] = 0b1; /* integer multiply/divide */\n misa[U] = 0b1; /* user-mode */\n misa[S] = 0b1; /* supervisor-mode */\n misa[V] = bool_to_bits(sys_enable_vext()); /* vector extension */\n\n if sys_enable_fdext() & sys_enable_zfinx()\n then internal_error(__FILE__, __LINE__, \"F and Zfinx cannot both be enabled!\");\n\n /* We currently support both F and D */\n misa[F] = bool_to_bits(sys_enable_fdext()); /* single-precision */\n misa[D] = if sizeof(flen) >= 64\n then bool_to_bits(sys_enable_fdext()) /* double-precision */\n else 0b0;\n\n mstatus = set_mstatus_SXL(mstatus, misa[MXL]);\n mstatus = set_mstatus_UXL(mstatus, misa[MXL]);\n mstatus[SD] = 0b0;\n\n /* set to little-endian mode */\n if sizeof(xlen) == 64 then {\n mstatus = Mk_Mstatus([mstatus.bits with 37 .. 36 = 0b00])\n };\n mstatush.bits = zero_extend(0b0);\n\n mip.bits = zero_extend(0b0);\n mie.bits = zero_extend(0b0);\n mideleg.bits = zero_extend(0b0);\n medeleg.bits = zero_extend(0b0);\n mtvec.bits = zero_extend(0b0);\n mcause.bits = zero_extend(0b0);\n mepc = zero_extend(0b0);\n mtval = zero_extend(0b0);\n mscratch = zero_extend(0b0);\n\n mcycle = zero_extend(0b0);\n mtime = zero_extend(0b0);\n\n mcounteren.bits = zero_extend(0b0);\n\n minstret = zero_extend(0b0);\n minstret_increment = true;\n\n menvcfg.bits = zero_extend(0b0);\n senvcfg.bits = zero_extend(0b0);\n /* initialize vector csrs */\n elen = 0b1; /* ELEN=64 as the common case */\n vlen = 0b0100; /* VLEN=512 as a default value */\n vlenb = to_bits(sizeof(xlen), 2 ^ (get_vlen_pow() - 3)); /* vlenb holds the constant value VLEN/8 */\n /* VLEN value needs to be manually changed currently.\n * See riscv_vlen.sail for details.\n */\n vstart = zero_extend(0b0);\n vxsat = 0b0;\n vxrm = 0b00;\n vcsr[vxrm] = vxrm;\n vcsr[vxsat] = vxsat;\n vl = zero_extend(0b0);\n vtype[vill] = 0b1;\n vtype[reserved] = zero_extend(0b0);\n vtype[vma] = 0b0;\n vtype[vta] = 0b0;\n vtype[vsew] = 0b000;\n vtype[vlmul] = 0b000;\n\n // PMP's L and A fields are set to 0 on reset.\n init_pmp();\n\n // log compatibility with spike\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits) ^ \" (input: \" ^ BitStr(zero_extend(0b0) : xlenbits) ^ \")\")\n}", "pattern": { "type": "literal", "value": "()" }, "body": " cur_privilege = Machine;\n\n mhartid = zero_extend(0b0);\n\n misa[MXL] = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);\n misa[A] = 0b1; /* atomics */\n misa[C] = bool_to_bits(sys_enable_rvc()); /* RVC */\n misa[I] = 0b1; /* base integer ISA */\n misa[M] = 0b1; /* integer multiply/divide */\n misa[U] = 0b1; /* user-mode */\n misa[S] = 0b1; /* supervisor-mode */\n misa[V] = bool_to_bits(sys_enable_vext()); /* vector extension */\n\n if sys_enable_fdext() & sys_enable_zfinx()\n then internal_error(__FILE__, __LINE__, \"F and Zfinx cannot both be enabled!\");\n\n /* We currently support both F and D */\n misa[F] = bool_to_bits(sys_enable_fdext()); /* single-precision */\n misa[D] = if sizeof(flen) >= 64\n then bool_to_bits(sys_enable_fdext()) /* double-precision */\n else 0b0;\n\n mstatus = set_mstatus_SXL(mstatus, misa[MXL]);\n mstatus = set_mstatus_UXL(mstatus, misa[MXL]);\n mstatus[SD] = 0b0;\n\n /* set to little-endian mode */\n if sizeof(xlen) == 64 then {\n mstatus = Mk_Mstatus([mstatus.bits with 37 .. 36 = 0b00])\n };\n mstatush.bits = zero_extend(0b0);\n\n mip.bits = zero_extend(0b0);\n mie.bits = zero_extend(0b0);\n mideleg.bits = zero_extend(0b0);\n medeleg.bits = zero_extend(0b0);\n mtvec.bits = zero_extend(0b0);\n mcause.bits = zero_extend(0b0);\n mepc = zero_extend(0b0);\n mtval = zero_extend(0b0);\n mscratch = zero_extend(0b0);\n\n mcycle = zero_extend(0b0);\n mtime = zero_extend(0b0);\n\n mcounteren.bits = zero_extend(0b0);\n\n minstret = zero_extend(0b0);\n minstret_increment = true;\n\n menvcfg.bits = zero_extend(0b0);\n senvcfg.bits = zero_extend(0b0);\n /* initialize vector csrs */\n elen = 0b1; /* ELEN=64 as the common case */\n vlen = 0b0100; /* VLEN=512 as a default value */\n vlenb = to_bits(sizeof(xlen), 2 ^ (get_vlen_pow() - 3)); /* vlenb holds the constant value VLEN/8 */\n /* VLEN value needs to be manually changed currently.\n * See riscv_vlen.sail for details.\n */\n vstart = zero_extend(0b0);\n vxsat = 0b0;\n vxrm = 0b00;\n vcsr[vxrm] = vxrm;\n vcsr[vxsat] = vxsat;\n vl = zero_extend(0b0);\n vtype[vill] = 0b1;\n vtype[reserved] = zero_extend(0b0);\n vtype[vma] = 0b0;\n vtype[vta] = 0b0;\n vtype[vsew] = 0b000;\n vtype[vlmul] = 0b000;\n\n // PMP's L and A fields are set to 0 on reset.\n init_pmp();\n\n // log compatibility with spike\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits) ^ \" (input: \" ^ BitStr(zero_extend(0b0) : xlenbits) ^ \")\")" }, "links": [ { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 21391, 21411 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 21421, 21430 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 21495, 21506 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 21458, 21465 ] }, { "type": "function", "id": "init_pmp", "file": "model/riscv_sys_control.sail", "loc": [ 21337, 21345 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_sys_control.sail", "loc": [ 21259, 21264 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_sys_control.sail", "loc": [ 21231, 21236 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_sys_control.sail", "loc": [ 21205, 21210 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_sys_control.sail", "loc": [ 21179, 21184 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_sys_control.sail", "loc": [ 21140, 21145 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 21159, 21170 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_sys_control.sail", "loc": [ 21114, 21119 ] }, { "type": "register", "id": "vl", "file": "model/riscv_sys_control.sail", "loc": [ 21073, 21075 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 21094, 21105 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_sys_control.sail", "loc": [ 21045, 21049 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_sys_control.sail", "loc": [ 21064, 21069 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_sys_control.sail", "loc": [ 21018, 21022 ] }, { "type": "register", "id": "vxrm", "file": "model/riscv_sys_control.sail", "loc": [ 21037, 21041 ] }, { "type": "register", "id": "vxrm", "file": "model/riscv_sys_control.sail", "loc": [ 20989, 20993 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_sys_control.sail", "loc": [ 20961, 20966 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_sys_control.sail", "loc": [ 20920, 20926 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20941, 20952 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_sys_control.sail", "loc": [ 20704, 20709 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 20725, 20732 ] }, { "type": "function", "id": "pow2", "file": "model/riscv_sys_control.sail", "loc": [ 20747, 20750 ] }, { "type": "function", "id": "get_vlen_pow", "file": "model/riscv_sys_control.sail", "loc": [ 20752, 20764 ] }, { "type": "register", "id": "vlen", "file": "model/riscv_sys_control.sail", "loc": [ 20639, 20643 ] }, { "type": "register", "id": "elen", "file": "model/riscv_sys_control.sail", "loc": [ 20578, 20582 ] }, { "type": "register", "id": "senvcfg", "file": "model/riscv_sys_control.sail", "loc": [ 20512, 20519 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20527, 20538 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_sys_control.sail", "loc": [ 20477, 20484 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20492, 20503 ] }, { "type": "register", "id": "minstret_increment", "file": "model/riscv_sys_control.sail", "loc": [ 20447, 20465 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_sys_control.sail", "loc": [ 20406, 20414 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20427, 20438 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_sys_control.sail", "loc": [ 20367, 20377 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20385, 20396 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_sys_control.sail", "loc": [ 20328, 20333 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20346, 20357 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_sys_control.sail", "loc": [ 20290, 20296 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20308, 20319 ] }, { "type": "register", "id": "mscratch", "file": "model/riscv_sys_control.sail", "loc": [ 20251, 20259 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20269, 20280 ] }, { "type": "register", "id": "mtval", "file": "model/riscv_sys_control.sail", "loc": [ 20213, 20218 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20231, 20242 ] }, { "type": "register", "id": "mepc", "file": "model/riscv_sys_control.sail", "loc": [ 20175, 20179 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20193, 20204 ] }, { "type": "register", "id": "mcause", "file": "model/riscv_sys_control.sail", "loc": [ 20140, 20146 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20155, 20166 ] }, { "type": "register", "id": "mtvec", "file": "model/riscv_sys_control.sail", "loc": [ 20105, 20110 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20120, 20131 ] }, { "type": "register", "id": "medeleg", "file": "model/riscv_sys_control.sail", "loc": [ 20070, 20077 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20085, 20096 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_sys_control.sail", "loc": [ 20035, 20042 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20050, 20061 ] }, { "type": "register", "id": "mie", "file": "model/riscv_sys_control.sail", "loc": [ 20000, 20003 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 20015, 20026 ] }, { "type": "register", "id": "mip", "file": "model/riscv_sys_control.sail", "loc": [ 19965, 19968 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 19980, 19991 ] }, { "type": "register", "id": "mstatush", "file": "model/riscv_sys_control.sail", "loc": [ 19928, 19936 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 19944, 19955 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 19863, 19870 ] }, { "type": "function", "id": "Mk_Mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 19873, 19883 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 19885, 19892 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 19772, 19779 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 19723, 19730 ] }, { "type": "function", "id": "set_mstatus_UXL", "file": "model/riscv_sys_control.sail", "loc": [ 19733, 19748 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 19758, 19762 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 19749, 19756 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 19674, 19681 ] }, { "type": "function", "id": "set_mstatus_SXL", "file": "model/riscv_sys_control.sail", "loc": [ 19684, 19699 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 19709, 19713 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 19700, 19707 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 19531, 19535 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 19588, 19600 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_sys_control.sail", "loc": [ 19601, 19617 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 19455, 19459 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 19467, 19479 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_sys_control.sail", "loc": [ 19480, 19496 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_sys_control.sail", "loc": [ 19309, 19325 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_sys_control.sail", "loc": [ 19288, 19304 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_sys_control.sail", "loc": [ 19335, 19349 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 19212, 19216 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 19224, 19236 ] }, { "type": "function", "id": "sys_enable_vext", "file": "model/riscv_sys_control.sail", "loc": [ 19237, 19252 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 19143, 19147 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 19080, 19084 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 19003, 19007 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 18933, 18937 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 18876, 18880 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 18888, 18900 ] }, { "type": "function", "id": "sys_enable_rvc", "file": "model/riscv_sys_control.sail", "loc": [ 18901, 18915 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 18815, 18819 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_control.sail", "loc": [ 18744, 18748 ] }, { "type": "function", "id": "arch_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 18756, 18768 ] }, { "type": "register", "id": "mhartid", "file": "model/riscv_sys_control.sail", "loc": [ 18709, 18716 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 18723, 18734 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 18681, 18694 ] } ] }, "init_vmem": { "function": { "number": 0, "source": "function init_vmem() -> unit = init_TLB()", "pattern": { "type": "literal", "value": "()" }, "body": "init_TLB()" }, "links": [ { "type": "function", "id": "init_TLB", "file": "model/riscv_vmem.sail", "loc": [ 19633, 19641 ] } ] }, "init_vregs": { "function": { "number": 0, "source": "function init_vregs () = {\n let zero_vreg : vregtype = zeros();\n vr0 = zero_vreg;\n vr1 = zero_vreg;\n vr2 = zero_vreg;\n vr3 = zero_vreg;\n vr4 = zero_vreg;\n vr5 = zero_vreg;\n vr6 = zero_vreg;\n vr7 = zero_vreg;\n vr8 = zero_vreg;\n vr9 = zero_vreg;\n vr10 = zero_vreg;\n vr11 = zero_vreg;\n vr12 = zero_vreg;\n vr13 = zero_vreg;\n vr14 = zero_vreg;\n vr15 = zero_vreg;\n vr16 = zero_vreg;\n vr17 = zero_vreg;\n vr18 = zero_vreg;\n vr19 = zero_vreg;\n vr20 = zero_vreg;\n vr21 = zero_vreg;\n vr22 = zero_vreg;\n vr23 = zero_vreg;\n vr24 = zero_vreg;\n vr25 = zero_vreg;\n vr26 = zero_vreg;\n vr27 = zero_vreg;\n vr28 = zero_vreg;\n vr29 = zero_vreg;\n vr30 = zero_vreg;\n vr31 = zero_vreg\n}", "pattern": { "type": "literal", "value": "()" }, "body": " let zero_vreg : vregtype = zeros();\n vr0 = zero_vreg;\n vr1 = zero_vreg;\n vr2 = zero_vreg;\n vr3 = zero_vreg;\n vr4 = zero_vreg;\n vr5 = zero_vreg;\n vr6 = zero_vreg;\n vr7 = zero_vreg;\n vr8 = zero_vreg;\n vr9 = zero_vreg;\n vr10 = zero_vreg;\n vr11 = zero_vreg;\n vr12 = zero_vreg;\n vr13 = zero_vreg;\n vr14 = zero_vreg;\n vr15 = zero_vreg;\n vr16 = zero_vreg;\n vr17 = zero_vreg;\n vr18 = zero_vreg;\n vr19 = zero_vreg;\n vr20 = zero_vreg;\n vr21 = zero_vreg;\n vr22 = zero_vreg;\n vr23 = zero_vreg;\n vr24 = zero_vreg;\n vr25 = zero_vreg;\n vr26 = zero_vreg;\n vr27 = zero_vreg;\n vr28 = zero_vreg;\n vr29 = zero_vreg;\n vr30 = zero_vreg;\n vr31 = zero_vreg" }, "links": [ { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "register", "id": "vr31", "file": "model/riscv_vext_regs.sail", "loc": [ 5179, 5183 ] }, { "type": "register", "id": "vr30", "file": "model/riscv_vext_regs.sail", "loc": [ 5159, 5163 ] }, { "type": "register", "id": "vr29", "file": "model/riscv_vext_regs.sail", "loc": [ 5139, 5143 ] }, { "type": "register", "id": "vr28", "file": "model/riscv_vext_regs.sail", "loc": [ 5119, 5123 ] }, { "type": "register", "id": "vr27", "file": "model/riscv_vext_regs.sail", "loc": [ 5099, 5103 ] }, { "type": "register", "id": "vr26", "file": "model/riscv_vext_regs.sail", "loc": [ 5079, 5083 ] }, { "type": "register", "id": "vr25", "file": "model/riscv_vext_regs.sail", "loc": [ 5059, 5063 ] }, { "type": "register", "id": "vr24", "file": "model/riscv_vext_regs.sail", "loc": [ 5039, 5043 ] }, { "type": "register", "id": "vr23", "file": "model/riscv_vext_regs.sail", "loc": [ 5019, 5023 ] }, { "type": "register", "id": "vr22", "file": "model/riscv_vext_regs.sail", "loc": [ 4999, 5003 ] }, { "type": "register", "id": "vr21", "file": "model/riscv_vext_regs.sail", "loc": [ 4979, 4983 ] }, { "type": "register", "id": "vr20", "file": "model/riscv_vext_regs.sail", "loc": [ 4959, 4963 ] }, { "type": "register", "id": "vr19", "file": "model/riscv_vext_regs.sail", "loc": [ 4939, 4943 ] }, { "type": "register", "id": "vr18", "file": "model/riscv_vext_regs.sail", "loc": [ 4919, 4923 ] }, { "type": "register", "id": "vr17", "file": "model/riscv_vext_regs.sail", "loc": [ 4899, 4903 ] }, { "type": "register", "id": "vr16", "file": "model/riscv_vext_regs.sail", "loc": [ 4879, 4883 ] }, { "type": "register", "id": "vr15", "file": "model/riscv_vext_regs.sail", "loc": [ 4859, 4863 ] }, { "type": "register", "id": "vr14", "file": "model/riscv_vext_regs.sail", "loc": [ 4839, 4843 ] }, { "type": "register", "id": "vr13", "file": "model/riscv_vext_regs.sail", "loc": [ 4819, 4823 ] }, { "type": "register", "id": "vr12", "file": "model/riscv_vext_regs.sail", "loc": [ 4799, 4803 ] }, { "type": "register", "id": "vr11", "file": "model/riscv_vext_regs.sail", "loc": [ 4779, 4783 ] }, { "type": "register", "id": "vr10", "file": "model/riscv_vext_regs.sail", "loc": [ 4759, 4763 ] }, { "type": "register", "id": "vr9", "file": "model/riscv_vext_regs.sail", "loc": [ 4739, 4742 ] }, { "type": "register", "id": "vr8", "file": "model/riscv_vext_regs.sail", "loc": [ 4719, 4722 ] }, { "type": "register", "id": "vr7", "file": "model/riscv_vext_regs.sail", "loc": [ 4699, 4702 ] }, { "type": "register", "id": "vr6", "file": "model/riscv_vext_regs.sail", "loc": [ 4679, 4682 ] }, { "type": "register", "id": "vr5", "file": "model/riscv_vext_regs.sail", "loc": [ 4659, 4662 ] }, { "type": "register", "id": "vr4", "file": "model/riscv_vext_regs.sail", "loc": [ 4639, 4642 ] }, { "type": "register", "id": "vr3", "file": "model/riscv_vext_regs.sail", "loc": [ 4619, 4622 ] }, { "type": "register", "id": "vr2", "file": "model/riscv_vext_regs.sail", "loc": [ 4599, 4602 ] }, { "type": "register", "id": "vr1", "file": "model/riscv_vext_regs.sail", "loc": [ 4579, 4582 ] }, { "type": "register", "id": "vr0", "file": "model/riscv_vext_regs.sail", "loc": [ 4559, 4562 ] } ] }, "initial_analysis": { "function": { "number": 0, "source": "function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) = {\n iR = [| |] : regfps;\n oR = [| |] : regfps;\n aR = [| |] : regfps;\n ik = IK_simple() : instruction_kind;\n Nias = [| NIAFP_successor() |] : niafps;\n Dia = DIAFP_none() : diafp;\n\n match instr {\n EBREAK() => (),\n UTYPE(imm, rd, op) => {\n\t if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n RISCV_JAL(imm, rd) => {\n\t if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n let offset : bits(64) = sign_extend(imm) in\n Nias = [| NIAFP_concrete_address (PC + offset) |];\n ik = IK_branch();\n },\n RISCV_JALR(imm, rs, rd) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n let offset : bits(64) = sign_extend(imm) in\n Nias = [| NIAFP_indirect_address() |];\n ik = IK_branch();\n },\n BTYPE(imm, rs2, rs1, op) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n ik = IK_branch();\n let offset : bits(64) = sign_extend(imm) in\n Nias = [| NIAFP_concrete_address(PC + offset), NIAFP_successor() |];\n },\n ITYPE(imm, rs, rd, op) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n SHIFTIOP(imm, rs, rd, op) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n RTYPE(rs2, rs1, rd, op) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n CSR(csr, rs1, rd, is_imm, op) => {\n let isWrite : bool = match op {\n CSRRW => true,\n _ => if is_imm then unsigned(rs1) != 0 else unsigned(rs1) != 0\n };\n iR = RFull(csr_name(csr)) :: iR;\n if not(is_imm) then {\n iR = RFull(GPRstr(rs1)) :: iR;\n };\n if isWrite then {\n oR = RFull(csr_name(csr)) :: oR;\n };\n oR = RFull(GPRstr(rd)) :: oR;\n },\n LOAD(imm, rs, rd, unsign, width, aq, rl) => { /* XXX \"unsigned\" causes name conflict in lem shallow embedding... */\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n aR = iR;\n ik =\n match (aq, rl) {\n (false, false) => IK_mem_read (Read_plain),\n (true, false) => IK_mem_read (Read_RISCV_acquire),\n (true, true) => IK_mem_read (Read_RISCV_strong_acquire),\n\n _ => internal_error(__FILE__, __LINE__, \"LOAD type not implemented in initial_analysis\")\n }\n },\n STORE(imm, rs2, rs1, width, aq, rl) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;\n ik =\n match (aq, rl) {\n (false, false) => IK_mem_write (Write_plain),\n (false, true) => IK_mem_write (Write_RISCV_release),\n (true, true) => IK_mem_write (Write_RISCV_strong_release),\n\n _ => internal_error(__FILE__, __LINE__, \"STORE type not implemented in initial_analysis\")\n }\n },\n ADDIW(imm, rs, rd) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n SHIFTIWOP(imm, rs, rd, op) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n RTYPEW(rs2, rs1, rd, op) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n FENCE(pred, succ) => {\n ik =\n match (pred, succ) {\n\t\t (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_rw_rw ()),\n\t\t (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_r_rw ()),\n\t\t (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_r_r ()),\n\t\t (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_rw_w ()),\n\t\t (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_w_w ()),\n\t\t (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_w_rw ()),\n\t\t (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_rw_r ()),\n\t\t (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_r_w ()),\n\t\t (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_w_r ()),\n\n (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => IK_simple (),\n\n _ => internal_error(__FILE__, __LINE__, \"barrier type not implemented in initial_analysis\")\n };\n },\n FENCE_TSO(pred, succ) => {\n ik =\n match (pred, succ) {\n\t\t (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_tso ()),\n _ => internal_error(__FILE__, __LINE__, \"barrier type not implemented in initial_analysis\")\n };\n },\n FENCEI() => {\n ik = IK_simple (); // for RMEM, should morally be Barrier_RISCV_i\n },\n LOADRES(aq, rl, rs1, width, rd) => {\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n aR = iR;\n ik = match (aq, rl) {\n (false, false) => IK_mem_read (Read_RISCV_reserved),\n (true, false) => IK_mem_read (Read_RISCV_reserved_acquire),\n (true, true) => IK_mem_read (Read_RISCV_reserved_strong_acquire),\n (false, true) => internal_error(__FILE__, __LINE__, \"LOADRES type not implemented in initial_analysis\")\n };\n },\n STORECON(aq, rl, rs2, rs1, width, rd) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n ik = match (aq, rl) {\n (false, false) => IK_mem_write (Write_RISCV_conditional),\n (false, true) => IK_mem_write (Write_RISCV_conditional_release),\n (true, true) => IK_mem_write (Write_RISCV_conditional_strong_release),\n\n (true, false) => internal_error(__FILE__, __LINE__, \"STORECON type not implemented in initial_analysis\")\n };\n },\n AMO(op, aq, rl, rs2, rs1, width, rd) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n ik = match (aq, rl) {\n (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional),\n (false, true) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release),\n (true, false) => IK_mem_rmw (Read_RISCV_reserved_acquire,\n Write_RISCV_conditional),\n (true, true) => IK_mem_rmw (Read_RISCV_reserved_acquire,\n Write_RISCV_conditional_release)\n };\n },\n _ => ()\n };\n (iR,oR,aR,Nias,Dia,ik)\n}", "pattern": { "type": "id", "id": "instr" }, "body": "function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) = {\n iR = [| |] : regfps;\n oR = [| |] : regfps;\n aR = [| |] : regfps;\n ik = IK_simple() : instruction_kind;\n Nias = [| NIAFP_successor() |] : niafps;\n Dia = DIAFP_none() : diafp;\n\n match instr {\n EBREAK() => (),\n UTYPE(imm, rd, op) => {\n\t if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n RISCV_JAL(imm, rd) => {\n\t if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n let offset : bits(64) = sign_extend(imm) in\n Nias = [| NIAFP_concrete_address (PC + offset) |];\n ik = IK_branch();\n },\n RISCV_JALR(imm, rs, rd) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n let offset : bits(64) = sign_extend(imm) in\n Nias = [| NIAFP_indirect_address() |];\n ik = IK_branch();\n },\n BTYPE(imm, rs2, rs1, op) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n ik = IK_branch();\n let offset : bits(64) = sign_extend(imm) in\n Nias = [| NIAFP_concrete_address(PC + offset), NIAFP_successor() |];\n },\n ITYPE(imm, rs, rd, op) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n SHIFTIOP(imm, rs, rd, op) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n RTYPE(rs2, rs1, rd, op) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n CSR(csr, rs1, rd, is_imm, op) => {\n let isWrite : bool = match op {\n CSRRW => true,\n _ => if is_imm then unsigned(rs1) != 0 else unsigned(rs1) != 0\n };\n iR = RFull(csr_name(csr)) :: iR;\n if not(is_imm) then {\n iR = RFull(GPRstr(rs1)) :: iR;\n };\n if isWrite then {\n oR = RFull(csr_name(csr)) :: oR;\n };\n oR = RFull(GPRstr(rd)) :: oR;\n },\n LOAD(imm, rs, rd, unsign, width, aq, rl) => { /* XXX \"unsigned\" causes name conflict in lem shallow embedding... */\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n aR = iR;\n ik =\n match (aq, rl) {\n (false, false) => IK_mem_read (Read_plain),\n (true, false) => IK_mem_read (Read_RISCV_acquire),\n (true, true) => IK_mem_read (Read_RISCV_strong_acquire),\n\n _ => internal_error(__FILE__, __LINE__, \"LOAD type not implemented in initial_analysis\")\n }\n },\n STORE(imm, rs2, rs1, width, aq, rl) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;\n ik =\n match (aq, rl) {\n (false, false) => IK_mem_write (Write_plain),\n (false, true) => IK_mem_write (Write_RISCV_release),\n (true, true) => IK_mem_write (Write_RISCV_strong_release),\n\n _ => internal_error(__FILE__, __LINE__, \"STORE type not implemented in initial_analysis\")\n }\n },\n ADDIW(imm, rs, rd) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n SHIFTIWOP(imm, rs, rd, op) => {\n if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n RTYPEW(rs2, rs1, rd, op) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n },\n FENCE(pred, succ) => {\n ik =\n match (pred, succ) {\n\t\t (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_rw_rw ()),\n\t\t (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_r_rw ()),\n\t\t (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_r_r ()),\n\t\t (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_rw_w ()),\n\t\t (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_w_w ()),\n\t\t (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_w_rw ()),\n\t\t (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_rw_r ()),\n\t\t (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_r_w ()),\n\t\t (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_w_r ()),\n\n (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => IK_simple (),\n\n _ => internal_error(__FILE__, __LINE__, \"barrier type not implemented in initial_analysis\")\n };\n },\n FENCE_TSO(pred, succ) => {\n ik =\n match (pred, succ) {\n\t\t (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_tso ()),\n _ => internal_error(__FILE__, __LINE__, \"barrier type not implemented in initial_analysis\")\n };\n },\n FENCEI() => {\n ik = IK_simple (); // for RMEM, should morally be Barrier_RISCV_i\n },\n LOADRES(aq, rl, rs1, width, rd) => {\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n aR = iR;\n ik = match (aq, rl) {\n (false, false) => IK_mem_read (Read_RISCV_reserved),\n (true, false) => IK_mem_read (Read_RISCV_reserved_acquire),\n (true, true) => IK_mem_read (Read_RISCV_reserved_strong_acquire),\n (false, true) => internal_error(__FILE__, __LINE__, \"LOADRES type not implemented in initial_analysis\")\n };\n },\n STORECON(aq, rl, rs2, rs1, width, rd) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n ik = match (aq, rl) {\n (false, false) => IK_mem_write (Write_RISCV_conditional),\n (false, true) => IK_mem_write (Write_RISCV_conditional_release),\n (true, true) => IK_mem_write (Write_RISCV_conditional_strong_release),\n\n (true, false) => internal_error(__FILE__, __LINE__, \"STORECON type not implemented in initial_analysis\")\n };\n },\n AMO(op, aq, rl, rs2, rs1, width, rd) => {\n if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;\n if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;\n if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;\n if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;\n ik = match (aq, rl) {\n (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional),\n (false, true) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release),\n (true, false) => IK_mem_rmw (Read_RISCV_reserved_acquire,\n Write_RISCV_conditional),\n (true, true) => IK_mem_rmw (Read_RISCV_reserved_acquire,\n Write_RISCV_conditional_release)\n };\n },\n _ => ()\n };\n (iR,oR,aR,Nias,Dia,ik)\n}" }, "links": [ { "type": "function", "id": "IK_simple", "file": "model/riscv_analysis.sail", "loc": [ 9873, 9882 ] }, { "type": "function", "id": "NIAFP_successor", "file": "model/riscv_analysis.sail", "loc": [ 9917, 9932 ] }, { "type": "function", "id": "DIAFP_none", "file": "model/riscv_analysis.sail", "loc": [ 9956, 9966 ] }, { "type": "function", "id": "IK_mem_rmw", "file": "model/riscv_analysis.sail", "loc": [ 17901, 17911 ] }, { "type": "function", "id": "IK_mem_rmw", "file": "model/riscv_analysis.sail", "loc": [ 17730, 17740 ] }, { "type": "function", "id": "IK_mem_rmw", "file": "model/riscv_analysis.sail", "loc": [ 17630, 17640 ] }, { "type": "function", "id": "IK_mem_rmw", "file": "model/riscv_analysis.sail", "loc": [ 17538, 17548 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 17445, 17450 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 17451, 17457 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 17369, 17374 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 17375, 17381 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 17292, 17297 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 17298, 17304 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 17215, 17220 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 17221, 17227 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_analysis.sail", "loc": [ 17003, 17017 ] }, { "type": "function", "id": "IK_mem_write", "file": "model/riscv_analysis.sail", "loc": [ 16914, 16926 ] }, { "type": "function", "id": "IK_mem_write", "file": "model/riscv_analysis.sail", "loc": [ 16833, 16845 ] }, { "type": "function", "id": "IK_mem_write", "file": "model/riscv_analysis.sail", "loc": [ 16760, 16772 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 16667, 16672 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 16673, 16679 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 16592, 16597 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 16598, 16604 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 16516, 16521 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 16522, 16528 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 16440, 16445 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 16446, 16452 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_analysis.sail", "loc": [ 16232, 16246 ] }, { "type": "function", "id": "IK_mem_read", "file": "model/riscv_analysis.sail", "loc": [ 16150, 16161 ] }, { "type": "function", "id": "IK_mem_read", "file": "model/riscv_analysis.sail", "loc": [ 16075, 16086 ] }, { "type": "function", "id": "IK_mem_read", "file": "model/riscv_analysis.sail", "loc": [ 16008, 16019 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 15896, 15901 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 15902, 15908 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 15821, 15826 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 15827, 15833 ] }, { "type": "function", "id": "IK_simple", "file": "model/riscv_analysis.sail", "loc": [ 15660, 15669 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_analysis.sail", "loc": [ 15508, 15522 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 15451, 15461 ] }, { "type": "function", "id": "Barrier_RISCV_tso", "file": "model/riscv_analysis.sail", "loc": [ 15463, 15480 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_analysis.sail", "loc": [ 15203, 15217 ] }, { "type": "function", "id": "IK_simple", "file": "model/riscv_analysis.sail", "loc": [ 15166, 15175 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 15069, 15079 ] }, { "type": "function", "id": "Barrier_RISCV_w_r", "file": "model/riscv_analysis.sail", "loc": [ 15081, 15098 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 14987, 14997 ] }, { "type": "function", "id": "Barrier_RISCV_r_w", "file": "model/riscv_analysis.sail", "loc": [ 14999, 15016 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 14904, 14914 ] }, { "type": "function", "id": "Barrier_RISCV_rw_r", "file": "model/riscv_analysis.sail", "loc": [ 14916, 14934 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 14821, 14831 ] }, { "type": "function", "id": "Barrier_RISCV_w_rw", "file": "model/riscv_analysis.sail", "loc": [ 14833, 14851 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 14739, 14749 ] }, { "type": "function", "id": "Barrier_RISCV_w_w", "file": "model/riscv_analysis.sail", "loc": [ 14751, 14768 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 14656, 14666 ] }, { "type": "function", "id": "Barrier_RISCV_rw_w", "file": "model/riscv_analysis.sail", "loc": [ 14668, 14686 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 14574, 14584 ] }, { "type": "function", "id": "Barrier_RISCV_r_r", "file": "model/riscv_analysis.sail", "loc": [ 14586, 14603 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 14491, 14501 ] }, { "type": "function", "id": "Barrier_RISCV_r_rw", "file": "model/riscv_analysis.sail", "loc": [ 14503, 14521 ] }, { "type": "function", "id": "IK_barrier", "file": "model/riscv_analysis.sail", "loc": [ 14407, 14417 ] }, { "type": "function", "id": "Barrier_RISCV_rw_rw", "file": "model/riscv_analysis.sail", "loc": [ 14419, 14438 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 14243, 14248 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 14249, 14255 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 14167, 14172 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 14173, 14179 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 14090, 14095 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 14096, 14102 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 13969, 13974 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 13975, 13981 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 13894, 13899 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 13900, 13906 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 13772, 13777 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 13778, 13784 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 13697, 13702 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 13703, 13709 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_analysis.sail", "loc": [ 13506, 13520 ] }, { "type": "function", "id": "IK_mem_write", "file": "model/riscv_analysis.sail", "loc": [ 13440, 13452 ] }, { "type": "function", "id": "IK_mem_write", "file": "model/riscv_analysis.sail", "loc": [ 13369, 13381 ] }, { "type": "function", "id": "IK_mem_write", "file": "model/riscv_analysis.sail", "loc": [ 13306, 13318 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 13195, 13200 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 13201, 13207 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 13118, 13123 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 13124, 13130 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 13041, 13046 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 13047, 13053 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_analysis.sail", "loc": [ 12833, 12847 ] }, { "type": "function", "id": "IK_mem_read", "file": "model/riscv_analysis.sail", "loc": [ 12768, 12779 ] }, { "type": "function", "id": "IK_mem_read", "file": "model/riscv_analysis.sail", "loc": [ 12699, 12710 ] }, { "type": "function", "id": "IK_mem_read", "file": "model/riscv_analysis.sail", "loc": [ 12638, 12649 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 12506, 12511 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 12512, 12518 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 12431, 12436 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 12437, 12443 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_analysis.sail", "loc": [ 11890, 11898 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_analysis.sail", "loc": [ 11914, 11922 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 12225, 12230 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 12231, 12237 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 12159, 12164 ] }, { "type": "function", "id": "csr_name", "file": "model/riscv_analysis.sail", "loc": [ 12165, 12173 ] }, { "type": "function", "id": "not", "file": "model/riscv_analysis.sail", "loc": [ 12017, 12020 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 12059, 12064 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 12065, 12071 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 11971, 11976 ] }, { "type": "function", "id": "csr_name", "file": "model/riscv_analysis.sail", "loc": [ 11977, 11985 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 11689, 11694 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 11695, 11701 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 11613, 11618 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 11619, 11625 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 11536, 11541 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 11542, 11548 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 11416, 11421 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 11422, 11428 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 11341, 11346 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 11347, 11353 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 11220, 11225 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 11226, 11232 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 11146, 11151 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 11152, 11158 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_analysis.sail", "loc": [ 10953, 10964 ] }, { "type": "function", "id": "NIAFP_successor", "file": "model/riscv_analysis.sail", "loc": [ 11032, 11047 ] }, { "type": "function", "id": "NIAFP_concrete_address", "file": "model/riscv_analysis.sail", "loc": [ 10995, 11017 ] }, { "type": "register", "id": "PC", "file": "model/riscv_analysis.sail", "loc": [ 11018, 11020 ] }, { "type": "function", "id": "IK_branch", "file": "model/riscv_analysis.sail", "loc": [ 10904, 10913 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 10861, 10866 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 10867, 10873 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 10785, 10790 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 10791, 10797 ] }, { "type": "function", "id": "IK_branch", "file": "model/riscv_analysis.sail", "loc": [ 10679, 10688 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_analysis.sail", "loc": [ 10591, 10602 ] }, { "type": "function", "id": "NIAFP_indirect_address", "file": "model/riscv_analysis.sail", "loc": [ 10633, 10655 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 10530, 10535 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 10536, 10542 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 10456, 10461 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 10462, 10468 ] }, { "type": "function", "id": "IK_branch", "file": "model/riscv_analysis.sail", "loc": [ 10352, 10361 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_analysis.sail", "loc": [ 10252, 10263 ] }, { "type": "function", "id": "NIAFP_concrete_address", "file": "model/riscv_analysis.sail", "loc": [ 10294, 10316 ] }, { "type": "register", "id": "PC", "file": "model/riscv_analysis.sail", "loc": [ 10318, 10320 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 10191, 10196 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 10197, 10203 ] }, { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 10087, 10092 ] }, { "type": "function", "id": "GPRstr", "file": "model/riscv_analysis.sail", "loc": [ 10093, 10099 ] } ] }, "internal_error": { "function": { "number": 0, "source": "function internal_error(file, line, s) = {\n assert (false, file ^ \":\" ^ dec_str(line) ^ \": \" ^ s);\n throw Error_internal_error()\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "file" }, { "type": "id", "id": "line" }, { "type": "id", "id": "s" } ] }, "body": "function internal_error(file, line, s) = {\n assert (false, file ^ \":\" ^ dec_str(line) ^ \": \" ^ s);\n throw Error_internal_error()\n}" }, "links": [ { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_types.sail", "loc": [ 2709, 2716 ] } ] }, "interruptType_to_bits": { "function": { "number": 0, "source": "function interruptType_to_bits (i) =\n match (i) {\n I_U_Software => 0x00,\n I_S_Software => 0x01,\n I_M_Software => 0x03,\n I_U_Timer => 0x04,\n I_S_Timer => 0x05,\n I_M_Timer => 0x07,\n I_U_External => 0x08,\n I_S_External => 0x09,\n I_M_External => 0x0b\n }", "pattern": { "type": "id", "id": "i" }, "body": "match (i) {\n I_U_Software => 0x00,\n I_S_Software => 0x01,\n I_M_Software => 0x03,\n I_U_Timer => 0x04,\n I_S_Timer => 0x05,\n I_M_Timer => 0x07,\n I_U_External => 0x08,\n I_S_External => 0x09,\n I_M_External => 0x0b\n }" } }, "iop_of_num": { "function": { "number": 0, "source": "iop_of_num arg# = $[complete] match arg# {\n 0 => RISCV_ADDI,\n 1 => RISCV_SLTI,\n 2 => RISCV_SLTIU,\n 3 => RISCV_XORI,\n 4 => RISCV_ORI,\n _ => RISCV_ANDI\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_ADDI,\n 1 => RISCV_SLTI,\n 2 => RISCV_SLTIU,\n 3 => RISCV_XORI,\n 4 => RISCV_ORI,\n _ => RISCV_ANDI\n}" } }, "isRVC": { "function": { "number": 0, "source": "function isRVC(h : half) -> bool = not(h[1 .. 0] == 0b11)", "pattern": { "type": "id", "id": "h" }, "body": "not(h[1 .. 0] == 0b11)" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_fetch.sail", "loc": [ 813, 816 ] } ] }, "is_CSR_defined": { "function": { "number": 0, "source": "function is_CSR_defined (csr : csreg, p : Privilege) -> bool =\n match (csr) {\n /* machine mode: informational */\n 0xf11 => p == Machine, // mvendorid\n 0xf12 => p == Machine, // marchdid\n 0xf13 => p == Machine, // mimpid\n 0xf14 => p == Machine, // mhartid\n /* machine mode: trap setup */\n 0x300 => p == Machine, // mstatus\n 0x301 => p == Machine, // misa\n 0x302 => p == Machine & (haveSupMode() | haveNExt()), // medeleg\n 0x303 => p == Machine & (haveSupMode() | haveNExt()), // mideleg\n 0x304 => p == Machine, // mie\n 0x305 => p == Machine, // mtvec\n 0x306 => p == Machine & haveUsrMode(), // mcounteren\n 0x30A => p == Machine & haveUsrMode(), // menvcfg\n 0x310 => p == Machine & (sizeof(xlen) == 32), // mstatush\n 0x31A => p == Machine & haveUsrMode() & (sizeof(xlen) == 32), // menvcfgh\n 0x320 => p == Machine, // mcountinhibit\n /* machine mode: trap handling */\n 0x340 => p == Machine, // mscratch\n 0x341 => p == Machine, // mepc\n 0x342 => p == Machine, // mcause\n 0x343 => p == Machine, // mtval\n 0x344 => p == Machine, // mip\n\n // pmpcfgN\n 0x3A @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(idx) & (idx[0] == bitzero | sizeof(xlen) == 32),\n\n // pmpaddrN. Unfortunately the PMP index does not nicely align with the CSR index bits.\n 0x3B @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(0b00 @ idx),\n 0x3C @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(0b01 @ idx),\n 0x3D @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(0b10 @ idx),\n 0x3E @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(0b11 @ idx),\n 0xB00 => p == Machine, // mcycle\n 0xB02 => p == Machine, // minstret\n\n 0xB80 => p == Machine & (sizeof(xlen) == 32), // mcycleh\n 0xB82 => p == Machine & (sizeof(xlen) == 32), // minstreth\n\n /* disabled trigger/debug module */\n 0x7a0 => p == Machine,\n\n /* supervisor mode: trap setup */\n 0x100 => haveSupMode() & (p == Machine | p == Supervisor), // sstatus\n 0x102 => haveSupMode() & haveNExt() & (p == Machine | p == Supervisor), // sedeleg\n 0x103 => haveSupMode() & haveNExt() & (p == Machine | p == Supervisor), // sideleg\n 0x104 => haveSupMode() & (p == Machine | p == Supervisor), // sie\n 0x105 => haveSupMode() & (p == Machine | p == Supervisor), // stvec\n 0x106 => haveSupMode() & (p == Machine | p == Supervisor), // scounteren\n 0x10A => haveSupMode() & (p == Machine | p == Supervisor), // senvcfg\n\n /* supervisor mode: trap handling */\n 0x140 => haveSupMode() & (p == Machine | p == Supervisor), // sscratch\n 0x141 => haveSupMode() & (p == Machine | p == Supervisor), // sepc\n 0x142 => haveSupMode() & (p == Machine | p == Supervisor), // scause\n 0x143 => haveSupMode() & (p == Machine | p == Supervisor), // stval\n 0x144 => haveSupMode() & (p == Machine | p == Supervisor), // sip\n\n /* supervisor mode: address translation */\n 0x180 => haveSupMode() & (p == Machine | p == Supervisor), // satp\n\n /* user mode: counters */\n 0xC00 => haveUsrMode(), // cycle\n 0xC01 => haveUsrMode(), // time\n 0xC02 => haveUsrMode(), // instret\n\n 0xC80 => haveUsrMode() & (sizeof(xlen) == 32), // cycleh\n 0xC81 => haveUsrMode() & (sizeof(xlen) == 32), // timeh\n 0xC82 => haveUsrMode() & (sizeof(xlen) == 32), // instreth\n\n /* user mode: Zkr */\n 0x015 => haveZkr(),\n\n /* check extensions */\n _ => ext_is_CSR_defined(csr, p)\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "p" } ] }, "body": "match (csr) {\n /* machine mode: informational */\n 0xf11 => p == Machine, // mvendorid\n 0xf12 => p == Machine, // marchdid\n 0xf13 => p == Machine, // mimpid\n 0xf14 => p == Machine, // mhartid\n /* machine mode: trap setup */\n 0x300 => p == Machine, // mstatus\n 0x301 => p == Machine, // misa\n 0x302 => p == Machine & (haveSupMode() | haveNExt()), // medeleg\n 0x303 => p == Machine & (haveSupMode() | haveNExt()), // mideleg\n 0x304 => p == Machine, // mie\n 0x305 => p == Machine, // mtvec\n 0x306 => p == Machine & haveUsrMode(), // mcounteren\n 0x30A => p == Machine & haveUsrMode(), // menvcfg\n 0x310 => p == Machine & (sizeof(xlen) == 32), // mstatush\n 0x31A => p == Machine & haveUsrMode() & (sizeof(xlen) == 32), // menvcfgh\n 0x320 => p == Machine, // mcountinhibit\n /* machine mode: trap handling */\n 0x340 => p == Machine, // mscratch\n 0x341 => p == Machine, // mepc\n 0x342 => p == Machine, // mcause\n 0x343 => p == Machine, // mtval\n 0x344 => p == Machine, // mip\n\n // pmpcfgN\n 0x3A @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(idx) & (idx[0] == bitzero | sizeof(xlen) == 32),\n\n // pmpaddrN. Unfortunately the PMP index does not nicely align with the CSR index bits.\n 0x3B @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(0b00 @ idx),\n 0x3C @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(0b01 @ idx),\n 0x3D @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(0b10 @ idx),\n 0x3E @ idx : bits(4) => p == Machine & sys_pmp_count() > unsigned(0b11 @ idx),\n 0xB00 => p == Machine, // mcycle\n 0xB02 => p == Machine, // minstret\n\n 0xB80 => p == Machine & (sizeof(xlen) == 32), // mcycleh\n 0xB82 => p == Machine & (sizeof(xlen) == 32), // minstreth\n\n /* disabled trigger/debug module */\n 0x7a0 => p == Machine,\n\n /* supervisor mode: trap setup */\n 0x100 => haveSupMode() & (p == Machine | p == Supervisor), // sstatus\n 0x102 => haveSupMode() & haveNExt() & (p == Machine | p == Supervisor), // sedeleg\n 0x103 => haveSupMode() & haveNExt() & (p == Machine | p == Supervisor), // sideleg\n 0x104 => haveSupMode() & (p == Machine | p == Supervisor), // sie\n 0x105 => haveSupMode() & (p == Machine | p == Supervisor), // stvec\n 0x106 => haveSupMode() & (p == Machine | p == Supervisor), // scounteren\n 0x10A => haveSupMode() & (p == Machine | p == Supervisor), // senvcfg\n\n /* supervisor mode: trap handling */\n 0x140 => haveSupMode() & (p == Machine | p == Supervisor), // sscratch\n 0x141 => haveSupMode() & (p == Machine | p == Supervisor), // sepc\n 0x142 => haveSupMode() & (p == Machine | p == Supervisor), // scause\n 0x143 => haveSupMode() & (p == Machine | p == Supervisor), // stval\n 0x144 => haveSupMode() & (p == Machine | p == Supervisor), // sip\n\n /* supervisor mode: address translation */\n 0x180 => haveSupMode() & (p == Machine | p == Supervisor), // satp\n\n /* user mode: counters */\n 0xC00 => haveUsrMode(), // cycle\n 0xC01 => haveUsrMode(), // time\n 0xC02 => haveUsrMode(), // instret\n\n 0xC80 => haveUsrMode() & (sizeof(xlen) == 32), // cycleh\n 0xC81 => haveUsrMode() & (sizeof(xlen) == 32), // timeh\n 0xC82 => haveUsrMode() & (sizeof(xlen) == 32), // instreth\n\n /* user mode: Zkr */\n 0x015 => haveZkr(),\n\n /* check extensions */\n _ => ext_is_CSR_defined(csr, p)\n }" }, "links": [ { "type": "function", "id": "ext_is_CSR_defined", "file": "model/riscv_sys_control.sail", "loc": [ 4311, 4329 ] }, { "type": "function", "id": "haveZkr", "file": "model/riscv_sys_control.sail", "loc": [ 4259, 4266 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 4166, 4177 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 4102, 4113 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 4037, 4048 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 3994, 4005 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 3955, 3966 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 3915, 3926 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3813, 3824 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3695, 3706 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3623, 3634 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3550, 3561 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3479, 3490 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3404, 3415 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3288, 3299 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3211, 3222 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3139, 3150 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 3069, 3080 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_control.sail", "loc": [ 2998, 3006 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 2982, 2993 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_control.sail", "loc": [ 2911, 2919 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 2895, 2906 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 2821, 2832 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_sys_control.sail", "loc": [ 2478, 2486 ] }, { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_sys_control.sail", "loc": [ 2460, 2473 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_sys_control.sail", "loc": [ 2395, 2403 ] }, { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_sys_control.sail", "loc": [ 2377, 2390 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_sys_control.sail", "loc": [ 2312, 2320 ] }, { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_sys_control.sail", "loc": [ 2294, 2307 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_sys_control.sail", "loc": [ 2229, 2237 ] }, { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_sys_control.sail", "loc": [ 2211, 2224 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_sys_control.sail", "loc": [ 2017, 2025 ] }, { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_sys_control.sail", "loc": [ 1999, 2012 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 1627, 1638 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 1511, 1522 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 1454, 1465 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_control.sail", "loc": [ 1332, 1340 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 1316, 1327 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_control.sail", "loc": [ 1263, 1271 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 1247, 1258 ] } ] }, "is_aligned_addr": { "function": { "number": 0, "source": "function is_aligned_addr forall 'n. (addr : xlenbits, width : int('n)) -> bool =\n unsigned(addr) % width == 0", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": "unsigned(addr) % width == 0" }, "links": [ { "type": "function", "id": "emod_int", "file": "model/prelude.sail", "loc": [ 2111, 2119 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_mem.sail", "loc": [ 1735, 1743 ] } ] }, "is_fiom_active": { "function": { "number": 0, "source": "function is_fiom_active() -> bool = {\n match cur_privilege {\n Machine => false,\n Supervisor => menvcfg[FIOM] == 0b1,\n User => (menvcfg[FIOM] | senvcfg[FIOM]) == 0b1,\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " match cur_privilege {\n Machine => false,\n Supervisor => menvcfg[FIOM] == 0b1,\n User => (menvcfg[FIOM] | senvcfg[FIOM]) == 0b1,\n }" }, "links": [ { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_regs.sail", "loc": [ 25738, 25751 ] }, { "type": "register", "id": "senvcfg", "file": "model/riscv_sys_regs.sail", "loc": [ 25845, 25852 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_sys_regs.sail", "loc": [ 25829, 25836 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_sys_regs.sail", "loc": [ 25794, 25801 ] } ] }, "is_none": { "function": { "number": 0, "source": "is_none opt = $[complete] match opt {\n Some(_) => false,\n None(()) => true\n}", "pattern": { "type": "id", "id": "opt" }, "body": "$[complete] match opt {\n Some(_) => false,\n None(()) => true\n}" } }, "is_some": { "function": { "number": 0, "source": "is_some opt = $[complete] match opt {\n Some(_) => true,\n None(()) => false\n}", "pattern": { "type": "id", "id": "opt" }, "body": "$[complete] match opt {\n Some(_) => true,\n None(()) => false\n}" } }, "is_valid_vAddr": { "function": { "number": 0, "source": "function is_valid_vAddr(struct { va_size_bits, _ } : SV_Params,\n vAddr : bits(64)) -> bool =\n vAddr == sign_extend(vAddr[va_size_bits - 1 .. 0])", "pattern": { "type": "tuple", "patterns": [ { "type": "struct", "fields": { "va_size_bits": { "type": "id", "id": "va_size_bits" }, "vpn_size_bits": { "type": "wildcard" }, "pte_msbs_size_bits": { "type": "wildcard" }, "pte_msbs_lsb_index": { "type": "wildcard" }, "pte_PPNs_size_bits": { "type": "wildcard" }, "pte_PPNs_lsb_index": { "type": "wildcard" }, "pte_PPN_j_size_bits": { "type": "wildcard" }, "log_pte_size_bytes": { "type": "wildcard" }, "levels": { "type": "wildcard" } }, "wildcard": false }, { "type": "id", "id": "vAddr" } ] }, "body": "vAddr == sign_extend(vAddr[va_size_bits - 1 .. 0])" }, "links": [ { "type": "function", "id": "sign_extend", "file": "model/riscv_vmem.sail", "loc": [ 2737, 2748 ] } ] }, "legalize_mcounteren": { "function": { "number": 0, "source": "function legalize_mcounteren(c : Counteren, v : xlenbits) -> Counteren = {\n /* no HPM counters yet */\n [c with IR = [v[2]], TM = [v[1]], CY = [v[0]]]\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "c" }, { "type": "id", "id": "v" } ] }, "body": " [c with IR = [v[2]], TM = [v[1]], CY = [v[0]]]" } }, "legalize_mcountinhibit": { "function": { "number": 0, "source": "function legalize_mcountinhibit(c : Counterin, v : xlenbits) -> Counterin = {\n [c with IR = [v[2]], CY = [v[0]]]\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "c" }, { "type": "id", "id": "v" } ] }, "body": " [c with IR = [v[2]], CY = [v[0]]]" } }, "legalize_medeleg": { "function": { "number": 0, "source": "function legalize_medeleg(o : Medeleg, v : xlenbits) -> Medeleg = {\n /* M-EnvCalls delegation is not supported */\n [Mk_Medeleg(v) with MEnvCall = 0b0]\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " [Mk_Medeleg(v) with MEnvCall = 0b0]" }, "links": [ { "type": "function", "id": "Mk_Medeleg", "file": "model/riscv_sys_regs.sail", "loc": [ 13064, 13074 ] } ] }, "legalize_menvcfg": { "function": { "number": 0, "source": "function legalize_menvcfg(o : MEnvcfg, v : bits(64)) -> MEnvcfg = {\n let v = Mk_MEnvcfg(v);\n let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0];\n // Other extensions are not implemented yet so all other fields are read only zero.\n o\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " let v = Mk_MEnvcfg(v);\n let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0];\n // Other extensions are not implemented yet so all other fields are read only zero.\n o" }, "links": [ { "type": "function", "id": "Mk_MEnvcfg", "file": "model/riscv_sys_regs.sail", "loc": [ 25071, 25081 ] }, { "type": "function", "id": "sys_enable_writable_fiom", "file": "model/riscv_sys_regs.sail", "loc": [ 25114, 25138 ] } ] }, "legalize_mideleg": { "function": { "number": 0, "source": "function legalize_mideleg(o : Minterrupts, v : xlenbits) -> Minterrupts = {\n /* M-mode interrupt delegation bits \"should\" be hardwired to 0. */\n /* FIXME: needs verification against eventual spec language. */\n [Mk_Minterrupts(v) with MEI = 0b0, MTI = 0b0, MSI = 0b0]\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " [Mk_Minterrupts(v) with MEI = 0b0, MTI = 0b0, MSI = 0b0]" }, "links": [ { "type": "function", "id": "Mk_Minterrupts", "file": "model/riscv_sys_regs.sail", "loc": [ 12410, 12424 ] } ] }, "legalize_mie": { "function": { "number": 0, "source": "function legalize_mie(o : Minterrupts, v : xlenbits) -> Minterrupts = {\n let v = Mk_Minterrupts(v);\n let m = [o with\n MEI = v[MEI],\n MTI = v[MTI],\n MSI = v[MSI],\n SEI = v[SEI],\n STI = v[STI],\n SSI = v[SSI]\n ];\n /* The U-mode bits will be modified if we have the 'N' extension. */\n if haveUsrMode() & haveNExt() then {\n [m with UEI = v[UEI], UTI = v[UTI], USI = v[USI]]\n } else m\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " let v = Mk_Minterrupts(v);\n let m = [o with\n MEI = v[MEI],\n MTI = v[MTI],\n MSI = v[MSI],\n SEI = v[SEI],\n STI = v[STI],\n SSI = v[SSI]\n ];\n /* The U-mode bits will be modified if we have the 'N' extension. */\n if haveUsrMode() & haveNExt() then {\n [m with UEI = v[UEI], UTI = v[UTI], USI = v[USI]]\n } else m" }, "links": [ { "type": "function", "id": "Mk_Minterrupts", "file": "model/riscv_sys_regs.sail", "loc": [ 11869, 11883 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_regs.sail", "loc": [ 12110, 12118 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_regs.sail", "loc": [ 12094, 12105 ] } ] }, "legalize_mip": { "function": { "number": 0, "source": "function legalize_mip(o : Minterrupts, v : xlenbits) -> Minterrupts = {\n /* The only writable bits are the S-mode bits, and with the 'N'\n * extension, the U-mode bits. */\n let v = Mk_Minterrupts(v);\n let m = [o with SEI = v[SEI], STI = v[STI], SSI = v[SSI]];\n if haveUsrMode() & haveNExt() then {\n [m with UEI = v[UEI], UTI = v[UTI], USI = v[USI]]\n } else m\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " let v = Mk_Minterrupts(v);\n let m = [o with SEI = v[SEI], STI = v[STI], SSI = v[SSI]];\n if haveUsrMode() & haveNExt() then {\n [m with UEI = v[UEI], UTI = v[UTI], USI = v[USI]]\n } else m" }, "links": [ { "type": "function", "id": "Mk_Minterrupts", "file": "model/riscv_sys_regs.sail", "loc": [ 11600, 11614 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_regs.sail", "loc": [ 11701, 11709 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_regs.sail", "loc": [ 11685, 11696 ] } ] }, "legalize_misa": { "function": { "number": 0, "source": "function legalize_misa(m : Misa, v : xlenbits) -> Misa = {\n let v = Mk_Misa(v);\n /* Suppress updates to MISA if MISA is not writable or if by disabling C next PC would become misaligned or an extension vetoes */\n if not(sys_enable_writable_misa()) | (v[C] == 0b0 & (nextPC[1] == bitone | ext_veto_disable_C()))\n then m\n else {\n /* Suppress enabling C if C was disabled at boot (i.e. not supported) */\n let m = if not(sys_enable_rvc()) then m else [m with C = v[C]];\n /* Suppress updates to misa.{f,d} if disabled at boot */\n if not(sys_enable_fdext())\n then m\n else [m with F = v[F], D = v[D] & v[F]]\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "v" } ] }, "body": " let v = Mk_Misa(v);\n /* Suppress updates to MISA if MISA is not writable or if by disabling C next PC would become misaligned or an extension vetoes */\n if not(sys_enable_writable_misa()) | (v[C] == 0b0 & (nextPC[1] == bitone | ext_veto_disable_C()))\n then m\n else {\n /* Suppress enabling C if C was disabled at boot (i.e. not supported) */\n let m = if not(sys_enable_rvc()) then m else [m with C = v[C]];\n /* Suppress updates to misa.{f,d} if disabled at boot */\n if not(sys_enable_fdext())\n then m\n else [m with F = v[F], D = v[D] & v[F]]\n }" }, "links": [ { "type": "function", "id": "Mk_Misa", "file": "model/riscv_sys_regs.sail", "loc": [ 4541, 4548 ] }, { "type": "function", "id": "ext_veto_disable_C", "file": "model/riscv_sys_regs.sail", "loc": [ 4765, 4783 ] }, { "type": "register", "id": "nextPC", "file": "model/riscv_sys_regs.sail", "loc": [ 4743, 4749 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_regs.sail", "loc": [ 4693, 4696 ] }, { "type": "function", "id": "sys_enable_writable_misa", "file": "model/riscv_sys_regs.sail", "loc": [ 4697, 4721 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_regs.sail", "loc": [ 4898, 4901 ] }, { "type": "function", "id": "sys_enable_rvc", "file": "model/riscv_sys_regs.sail", "loc": [ 4902, 4916 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_regs.sail", "loc": [ 5021, 5024 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_sys_regs.sail", "loc": [ 5025, 5041 ] } ] }, "legalize_mstatus": { "function": { "number": 0, "source": "function legalize_mstatus(o : Mstatus, v : xlenbits) -> Mstatus = {\n /*\n * Populate all defined fields using the bits of v, stripping anything\n * that does not have a matching bitfield entry. All bits above 32 are handled\n * explicitly later.\n */\n let m : Mstatus = Mk_Mstatus(zero_extend(v[22 .. 7] @ 0b0 @ v[5 .. 3] @ 0b0 @ v[1 .. 0]));\n\n /* We don't have any extension context yet. */\n let m = [m with XS = extStatus_to_bits(Off)];\n\n /* FS is WARL, and making FS writable can support the M-mode emulation of an FPU\n * to support code running in S/U-modes. Spike does this, and for now, we match it,\n * but only if Zfinx isn't enabled.\n * FIXME: This should be made a platform parameter.\n */\n let m = if sys_enable_zfinx() then [m with FS = extStatus_to_bits(Off)] else m;\n let dirty = extStatus_of_bits(m[FS]) == Dirty | extStatus_of_bits(m[XS]) == Dirty |\n extStatus_of_bits(m[VS]) == Dirty;\n let m = [m with SD = bool_to_bits(dirty)];\n\n /* We don't support dynamic changes to SXL and UXL. */\n let m = set_mstatus_SXL(m, get_mstatus_SXL(o));\n let m = set_mstatus_UXL(m, get_mstatus_UXL(o));\n\n /* We don't currently support changing MBE and SBE. */\n let m = if sizeof(xlen) == 64 then {\n Mk_Mstatus([m.bits with 37 .. 36 = 0b00])\n } else m;\n\n /* Hardwired to zero in the absence of 'U' or 'N'. */\n let m = if not(haveNExt()) then {\n let m = [m with UPIE = 0b0];\n let m = [m with UIE = 0b0];\n m\n } else m;\n\n if not(haveUsrMode()) then {\n let m = [m with MPRV = 0b0];\n m\n } else m\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " let m : Mstatus = Mk_Mstatus(zero_extend(v[22 .. 7] @ 0b0 @ v[5 .. 3] @ 0b0 @ v[1 .. 0]));\n\n /* We don't have any extension context yet. */\n let m = [m with XS = extStatus_to_bits(Off)];\n\n /* FS is WARL, and making FS writable can support the M-mode emulation of an FPU\n * to support code running in S/U-modes. Spike does this, and for now, we match it,\n * but only if Zfinx isn't enabled.\n * FIXME: This should be made a platform parameter.\n */\n let m = if sys_enable_zfinx() then [m with FS = extStatus_to_bits(Off)] else m;\n let dirty = extStatus_of_bits(m[FS]) == Dirty | extStatus_of_bits(m[XS]) == Dirty |\n extStatus_of_bits(m[VS]) == Dirty;\n let m = [m with SD = bool_to_bits(dirty)];\n\n /* We don't support dynamic changes to SXL and UXL. */\n let m = set_mstatus_SXL(m, get_mstatus_SXL(o));\n let m = set_mstatus_UXL(m, get_mstatus_UXL(o));\n\n /* We don't currently support changing MBE and SBE. */\n let m = if sizeof(xlen) == 64 then {\n Mk_Mstatus([m.bits with 37 .. 36 = 0b00])\n } else m;\n\n /* Hardwired to zero in the absence of 'U' or 'N'. */\n let m = if not(haveNExt()) then {\n let m = [m with UPIE = 0b0];\n let m = [m with UIE = 0b0];\n m\n } else m;\n\n if not(haveUsrMode()) then {\n let m = [m with MPRV = 0b0];\n m\n } else m" }, "links": [ { "type": "function", "id": "Mk_Mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 8417, 8427 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 8428, 8439 ] }, { "type": "function", "id": "extStatus_to_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 8563, 8580 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_sys_regs.sail", "loc": [ 8870, 8886 ] }, { "type": "function", "id": "extStatus_to_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 8907, 8924 ] }, { "type": "function", "id": "extStatus_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 9039, 9056 ] }, { "type": "function", "id": "extStatus_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 8989, 9006 ] }, { "type": "function", "id": "extStatus_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 8953, 8970 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 9097, 9109 ] }, { "type": "function", "id": "set_mstatus_SXL", "file": "model/riscv_sys_regs.sail", "loc": [ 9187, 9202 ] }, { "type": "function", "id": "get_mstatus_SXL", "file": "model/riscv_sys_regs.sail", "loc": [ 9206, 9221 ] }, { "type": "function", "id": "set_mstatus_UXL", "file": "model/riscv_sys_regs.sail", "loc": [ 9237, 9252 ] }, { "type": "function", "id": "get_mstatus_UXL", "file": "model/riscv_sys_regs.sail", "loc": [ 9256, 9271 ] }, { "type": "function", "id": "Mk_Mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 9387, 9397 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_regs.sail", "loc": [ 9519, 9522 ] }, { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_regs.sail", "loc": [ 9523, 9531 ] }, { "type": "function", "id": "not", "file": "model/riscv_sys_regs.sail", "loc": [ 9666, 9669 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_regs.sail", "loc": [ 9670, 9681 ] } ] }, "legalize_satp": { "function": { "number": 0, "source": "function legalize_satp(a : Architecture,\n o : xlenbits, // previous value of satp\n v : xlenbits) // proposed new value of satp\n -> xlenbits = { // new legal value of satp\n if sizeof(xlen) == 32 then {\n // The slice and extend ops below are no-ops when xlen==32,\n // but appease the type-checker when xlen==64 (when this code is not executed!)\n let o32 : bits(32) = o[31 .. 0];\n let v32 : bits(32) = v[31 .. 0];\n let new_satp : bits(32) = legalize_satp32(a, o32, v32);\n zero_extend(new_satp);\n } else if sizeof(xlen) == 64 then {\n // The extend and truncate ops below are no-ops when xlen==64,\n // but appease the type-checker when xlen==32 (when this code is not executed!)\n let o64 : bits(64) = zero_extend(o);\n let v64 : bits(64) = zero_extend(v);\n let new_satp : bits(64) = legalize_satp64(a, o64, v64);\n truncate(new_satp, sizeof(xlen))\n } else\n internal_error(__FILE__, __LINE__, \"Unsupported xlen\" ^ dec_str(sizeof(xlen)))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "a" }, { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " if sizeof(xlen) == 32 then {\n // The slice and extend ops below are no-ops when xlen==32,\n // but appease the type-checker when xlen==64 (when this code is not executed!)\n let o32 : bits(32) = o[31 .. 0];\n let v32 : bits(32) = v[31 .. 0];\n let new_satp : bits(32) = legalize_satp32(a, o32, v32);\n zero_extend(new_satp);\n } else if sizeof(xlen) == 64 then {\n // The extend and truncate ops below are no-ops when xlen==64,\n // but appease the type-checker when xlen==32 (when this code is not executed!)\n let o64 : bits(64) = zero_extend(o);\n let v64 : bits(64) = zero_extend(v);\n let new_satp : bits(64) = legalize_satp64(a, o64, v64);\n truncate(new_satp, sizeof(xlen))\n } else\n internal_error(__FILE__, __LINE__, \"Unsupported xlen\" ^ dec_str(sizeof(xlen)))" }, "links": [ { "type": "function", "id": "legalize_satp32", "file": "model/riscv_vmem.sail", "loc": [ 8490, 8505 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 8524, 8535 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 8766, 8777 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 8812, 8823 ] }, { "type": "function", "id": "legalize_satp64", "file": "model/riscv_vmem.sail", "loc": [ 8858, 8873 ] }, { "type": "function", "id": "truncate", "file": "model/riscv_vmem.sail", "loc": [ 8892, 8900 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_vmem.sail", "loc": [ 8938, 8952 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_vmem.sail", "loc": [ 8994, 9001 ] } ] }, "legalize_satp32": { "function": { "number": 0, "source": "function legalize_satp32(a : Architecture, o : bits(32), v : bits(32)) -> bits(32) = {\n /* all 32-bit satp modes are valid */\n v\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "a" }, { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " v" } }, "legalize_satp64": { "function": { "number": 0, "source": "function legalize_satp64(a : Architecture, o : bits(64), v : bits(64)) -> bits(64) = {\n let s = Mk_Satp64(v);\n match satp64Mode_of_bits(a, s[Mode]) {\n None() => o,\n Some(Sv32) => o, /* Sv32 is unsupported for now */\n Some(_) => s.bits\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "a" }, { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " let s = Mk_Satp64(v);\n match satp64Mode_of_bits(a, s[Mode]) {\n None() => o,\n Some(Sv32) => o, /* Sv32 is unsupported for now */\n Some(_) => s.bits\n }" }, "links": [ { "type": "function", "id": "Mk_Satp64", "file": "model/riscv_sys_regs.sail", "loc": [ 21810, 21819 ] }, { "type": "function", "id": "satp64Mode_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 21832, 21850 ] } ] }, "legalize_scounteren": { "function": { "number": 0, "source": "function legalize_scounteren(c : Counteren, v : xlenbits) -> Counteren = {\n /* no HPM counters yet */\n [c with IR = [v[2]], TM = [v[1]], CY = [v[0]]]\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "c" }, { "type": "id", "id": "v" } ] }, "body": " [c with IR = [v[2]], TM = [v[1]], CY = [v[0]]]" } }, "legalize_sedeleg": { "function": { "number": 0, "source": "function legalize_sedeleg(s : Sedeleg, v : xlenbits) -> Sedeleg = {\n Mk_Sedeleg(zero_extend(v[8..0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "s" }, { "type": "id", "id": "v" } ] }, "body": " Mk_Sedeleg(zero_extend(v[8..0]))" }, "links": [ { "type": "function", "id": "Mk_Sedeleg", "file": "model/riscv_sys_regs.sail", "loc": [ 18752, 18762 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 18763, 18774 ] } ] }, "legalize_senvcfg": { "function": { "number": 0, "source": "function legalize_senvcfg(o : SEnvcfg, v : xlenbits) -> SEnvcfg = {\n let v = Mk_SEnvcfg(v);\n let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0];\n // Other extensions are not implemented yet so all other fields are read only zero.\n o\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " let v = Mk_SEnvcfg(v);\n let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0];\n // Other extensions are not implemented yet so all other fields are read only zero.\n o" }, "links": [ { "type": "function", "id": "Mk_SEnvcfg", "file": "model/riscv_sys_regs.sail", "loc": [ 25336, 25346 ] }, { "type": "function", "id": "sys_enable_writable_fiom", "file": "model/riscv_sys_regs.sail", "loc": [ 25379, 25403 ] } ] }, "legalize_sie": { "function": { "number": 0, "source": "function legalize_sie(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterrupts = {\n lift_sie(m, d, Mk_Sinterrupts(v))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "d" }, { "type": "id", "id": "v" } ] }, "body": " lift_sie(m, d, Mk_Sinterrupts(v))" }, "links": [ { "type": "function", "id": "lift_sie", "file": "model/riscv_sys_regs.sail", "loc": [ 21229, 21237 ] }, { "type": "function", "id": "Mk_Sinterrupts", "file": "model/riscv_sys_regs.sail", "loc": [ 21244, 21258 ] } ] }, "legalize_sip": { "function": { "number": 0, "source": "function legalize_sip(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterrupts = {\n lift_sip(m, d, Mk_Sinterrupts(v))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "d" }, { "type": "id", "id": "v" } ] }, "body": " lift_sip(m, d, Mk_Sinterrupts(v))" }, "links": [ { "type": "function", "id": "lift_sip", "file": "model/riscv_sys_regs.sail", "loc": [ 20451, 20459 ] }, { "type": "function", "id": "Mk_Sinterrupts", "file": "model/riscv_sys_regs.sail", "loc": [ 20466, 20480 ] } ] }, "legalize_sstatus": { "function": { "number": 0, "source": "function legalize_sstatus(m : Mstatus, v : xlenbits) -> Mstatus = {\n legalize_mstatus(m, lift_sstatus(m, Mk_Sstatus(v)).bits)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "v" } ] }, "body": " legalize_mstatus(m, lift_sstatus(m, Mk_Sstatus(v)).bits)" }, "links": [ { "type": "function", "id": "legalize_mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 18336, 18352 ] }, { "type": "function", "id": "lift_sstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 18356, 18368 ] }, { "type": "function", "id": "Mk_Sstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 18372, 18382 ] } ] }, "legalize_tvec": { "function": { "number": 0, "source": "function legalize_tvec(o : Mtvec, v : xlenbits) -> Mtvec = {\n let v = Mk_Mtvec(v);\n match (trapVectorMode_of_bits(v[Mode])) {\n TV_Direct => v,\n TV_Vector => v,\n _ => [v with Mode = o[Mode]]\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "v" } ] }, "body": " let v = Mk_Mtvec(v);\n match (trapVectorMode_of_bits(v[Mode])) {\n TV_Direct => v,\n TV_Vector => v,\n _ => [v with Mode = o[Mode]]\n }" }, "links": [ { "type": "function", "id": "Mk_Mtvec", "file": "model/riscv_sys_regs.sail", "loc": [ 13322, 13330 ] }, { "type": "function", "id": "trapVectorMode_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 13343, 13365 ] } ] }, "legalize_uie": { "function": { "number": 0, "source": "function legalize_uie(s : Sinterrupts, d : Sinterrupts, v : xlenbits) -> Sinterrupts = {\n lift_uie(s, d, Mk_Uinterrupts(v))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "s" }, { "type": "id", "id": "d" }, { "type": "id", "id": "v" } ] }, "body": " lift_uie(s, d, Mk_Uinterrupts(v))" }, "links": [ { "type": "function", "id": "lift_uie", "file": "model/riscv_next_regs.sail", "loc": [ 3226, 3234 ] }, { "type": "function", "id": "Mk_Uinterrupts", "file": "model/riscv_next_regs.sail", "loc": [ 3241, 3255 ] } ] }, "legalize_uip": { "function": { "number": 0, "source": "function legalize_uip(s : Sinterrupts, d : Sinterrupts, v : xlenbits) -> Sinterrupts = {\n lift_uip(s, d, Mk_Uinterrupts(v))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "s" }, { "type": "id", "id": "d" }, { "type": "id", "id": "v" } ] }, "body": " lift_uip(s, d, Mk_Uinterrupts(v))" }, "links": [ { "type": "function", "id": "lift_uip", "file": "model/riscv_next_regs.sail", "loc": [ 2676, 2684 ] }, { "type": "function", "id": "Mk_Uinterrupts", "file": "model/riscv_next_regs.sail", "loc": [ 2691, 2705 ] } ] }, "legalize_ustatus": { "function": { "number": 0, "source": "function legalize_ustatus(m : Mstatus, v : xlenbits) -> Mstatus = {\n let u = Mk_Ustatus(v);\n let s = lower_mstatus(m); // lower current mstatus to sstatus\n let s = lift_ustatus(s, u); // get updated sstatus\n let m = lift_sstatus(m, s); // lift it to an updated mstatus\n m\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "v" } ] }, "body": " let u = Mk_Ustatus(v);\n let s = lower_mstatus(m); // lower current mstatus to sstatus\n let s = lift_ustatus(s, u); // get updated sstatus\n let m = lift_sstatus(m, s); // lift it to an updated mstatus\n m" }, "links": [ { "type": "function", "id": "Mk_Ustatus", "file": "model/riscv_next_regs.sail", "loc": [ 1263, 1273 ] }, { "type": "function", "id": "lower_mstatus", "file": "model/riscv_next_regs.sail", "loc": [ 1288, 1301 ] }, { "type": "function", "id": "lift_ustatus", "file": "model/riscv_next_regs.sail", "loc": [ 1356, 1368 ] }, { "type": "function", "id": "lift_sstatus", "file": "model/riscv_next_regs.sail", "loc": [ 1411, 1423 ] } ] }, "legalize_xepc": { "function": { "number": 0, "source": "function legalize_xepc(v : xlenbits) -> xlenbits =\n /* allow writing xepc[1] only if misa.C is enabled or could be enabled\n XXX specification says this legalization should be done on read */\n if (sys_enable_writable_misa() & sys_enable_rvc()) | misa[C] == 0b1\n then [v with 0 = bitzero]\n else v & sign_extend(0b100)", "pattern": { "type": "id", "id": "v" }, "body": "if (sys_enable_writable_misa() & sys_enable_rvc()) | misa[C] == 0b1\n then [v with 0 = bitzero]\n else v & sign_extend(0b100)" }, "links": [ { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 14402, 14406 ] }, { "type": "function", "id": "sys_enable_rvc", "file": "model/riscv_sys_regs.sail", "loc": [ 14382, 14396 ] }, { "type": "function", "id": "sys_enable_writable_misa", "file": "model/riscv_sys_regs.sail", "loc": [ 14353, 14377 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 14456, 14467 ] } ] }, "lift_sie": { "function": { "number": 0, "source": "function lift_sie(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = {\n let m : Minterrupts = o;\n let m = if d[SEI] == 0b1 then [m with SEI = s[SEI]] else m;\n let m = if d[STI] == 0b1 then [m with STI = s[STI]] else m;\n let m = if d[SSI] == 0b1 then [m with SSI = s[SSI]] else m;\n if haveNExt() then {\n let m = if d[UEI] == 0b1 then [m with UEI = s[UEI]] else m;\n let m = if d[UTI] == 0b1 then [m with UTI = s[UTI]] else m;\n let m = if d[USI] == 0b1 then [m with USI = s[USI]] else m;\n m\n } else m\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "d" }, { "type": "id", "id": "s" } ] }, "body": " let m : Minterrupts = o;\n let m = if d[SEI] == 0b1 then [m with SEI = s[SEI]] else m;\n let m = if d[STI] == 0b1 then [m with STI = s[STI]] else m;\n let m = if d[SSI] == 0b1 then [m with SSI = s[SSI]] else m;\n if haveNExt() then {\n let m = if d[UEI] == 0b1 then [m with UEI = s[UEI]] else m;\n let m = if d[UTI] == 0b1 then [m with UTI = s[UTI]] else m;\n let m = if d[USI] == 0b1 then [m with USI = s[USI]] else m;\n m\n } else m" }, "links": [ { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_regs.sail", "loc": [ 20908, 20916 ] } ] }, "lift_sip": { "function": { "number": 0, "source": "function lift_sip(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = {\n let m : Minterrupts = o;\n let m = if d[SSI] == 0b1 then [m with SSI = s[SSI]] else m;\n if haveNExt() then {\n let m = if d[UEI] == 0b1 then [m with UEI = s[UEI]] else m;\n let m = if d[USI] == 0b1 then [m with USI = s[USI]] else m;\n m\n } else m\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "d" }, { "type": "id", "id": "s" } ] }, "body": " let m : Minterrupts = o;\n let m = if d[SSI] == 0b1 then [m with SSI = s[SSI]] else m;\n if haveNExt() then {\n let m = if d[UEI] == 0b1 then [m with UEI = s[UEI]] else m;\n let m = if d[USI] == 0b1 then [m with USI = s[USI]] else m;\n m\n } else m" }, "links": [ { "type": "function", "id": "haveNExt", "file": "model/riscv_sys_regs.sail", "loc": [ 20194, 20202 ] } ] }, "lift_sstatus": { "function": { "number": 0, "source": "function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = {\n let m = [m with MXR = s[MXR]];\n let m = [m with SUM = s[SUM]];\n\n let m = [m with XS = s[XS]];\n // See comment for mstatus.FS.\n let m = [m with FS = s[FS]];\n let m = [m with VS = s[VS]];\n let dirty = extStatus_of_bits(m[FS]) == Dirty | extStatus_of_bits(m[XS]) == Dirty |\n extStatus_of_bits(m[VS]) == Dirty;\n let m = [m with SD = bool_to_bits(dirty)];\n\n let m = [m with SPP = s[SPP]];\n let m = [m with SPIE = s[SPIE]];\n let m = [m with UPIE = s[UPIE]];\n let m = [m with SIE = s[SIE]];\n let m = [m with UIE = s[UIE]];\n m\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "s" } ] }, "body": " let m = [m with MXR = s[MXR]];\n let m = [m with SUM = s[SUM]];\n\n let m = [m with XS = s[XS]];\n // See comment for mstatus.FS.\n let m = [m with FS = s[FS]];\n let m = [m with VS = s[VS]];\n let dirty = extStatus_of_bits(m[FS]) == Dirty | extStatus_of_bits(m[XS]) == Dirty |\n extStatus_of_bits(m[VS]) == Dirty;\n let m = [m with SD = bool_to_bits(dirty)];\n\n let m = [m with SPP = s[SPP]];\n let m = [m with SPIE = s[SPIE]];\n let m = [m with UPIE = s[UPIE]];\n let m = [m with SIE = s[SIE]];\n let m = [m with UIE = s[UIE]];\n m" }, "links": [ { "type": "function", "id": "extStatus_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 18009, 18026 ] }, { "type": "function", "id": "extStatus_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 17959, 17976 ] }, { "type": "function", "id": "extStatus_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 17923, 17940 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 18067, 18079 ] } ] }, "lift_uie": { "function": { "number": 0, "source": "function lift_uie(o : Sinterrupts, d : Sinterrupts, u : Uinterrupts) -> Sinterrupts = {\n let s : Sinterrupts = o;\n let s = if d[UEI] == 0b1 then [s with UEI = u[UEI]] else s;\n let s = if d[UTI] == 0b1 then [s with UTI = u[UTI]] else s;\n let s = if d[USI] == 0b1 then [s with USI = u[USI]] else s;\n s\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "d" }, { "type": "id", "id": "u" } ] }, "body": " let s : Sinterrupts = o;\n let s = if d[UEI] == 0b1 then [s with UEI = u[UEI]] else s;\n let s = if d[UTI] == 0b1 then [s with UTI = u[UTI]] else s;\n let s = if d[USI] == 0b1 then [s with USI = u[USI]] else s;\n s" } }, "lift_uip": { "function": { "number": 0, "source": "function lift_uip(o : Sinterrupts, d : Sinterrupts, u : Uinterrupts) -> Sinterrupts = {\n let s : Sinterrupts = o;\n let s = if d[USI] == 0b1 then [s with USI = u[USI]] else s;\n s\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "o" }, { "type": "id", "id": "d" }, { "type": "id", "id": "u" } ] }, "body": " let s : Sinterrupts = o;\n let s = if d[USI] == 0b1 then [s with USI = u[USI]] else s;\n s" } }, "lift_ustatus": { "function": { "number": 0, "source": "function lift_ustatus(s : Sstatus, u : Ustatus) -> Sstatus = {\n let s = [s with UPIE = u[UPIE]];\n let s = [s with UIE = u[UIE]];\n s\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "s" }, { "type": "id", "id": "u" } ] }, "body": " let s = [s with UPIE = u[UPIE]];\n let s = [s with UIE = u[UIE]];\n s" } }, "log2": { "function": { "number": 0, "source": "function log2(n) = {\n let result : int = match n {\n 1 => 0,\n 2 => 1,\n 4 => 2,\n 8 => 3,\n 16 => 4,\n 32 => 5,\n 64 => 6\n };\n result\n}", "pattern": { "type": "id", "id": "n" }, "body": " let result : int = match n {\n 1 => 0,\n 2 => 1,\n 4 => 2,\n 8 => 3,\n 16 => 4,\n 32 => 5,\n 64 => 6\n };\n result" } }, "lookup_TLB": { "function": { "number": 0, "source": "function lookup_TLB (asid : asidbits, vaddr : bits(64)) -> option((nat, TLB_Entry)) =\n match tlb {\n None() => None(),\n Some(e) => if match_TLB_Entry(e, asid, vaddr) then Some((0, e)) else None()\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "asid" }, { "type": "id", "id": "vaddr" } ] }, "body": "match tlb {\n None() => None(),\n Some(e) => if match_TLB_Entry(e, asid, vaddr) then Some((0, e)) else None()\n }" }, "links": [ { "type": "register", "id": "tlb", "file": "model/riscv_vmem_tlb.sail", "loc": [ 2645, 2648 ] }, { "type": "function", "id": "match_TLB_Entry", "file": "model/riscv_vmem_tlb.sail", "loc": [ 2692, 2707 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vmem_tlb.sail", "loc": [ 2729, 2733 ] }, { "type": "function", "id": "None", "file": "model/riscv_vmem_tlb.sail", "loc": [ 2747, 2751 ] }, { "type": "function", "id": "None", "file": "model/riscv_vmem_tlb.sail", "loc": [ 2666, 2670 ] } ] }, "loop": { "function": { "number": 0, "source": "function loop () : unit -> unit = {\n let insns_per_tick = plat_insns_per_tick();\n i : int = 0;\n step_no : int = 0;\n while not(htif_done) do {\n let stepped = step(step_no);\n if stepped then step_no = step_no + 1;\n\n /* check htif exit */\n if htif_done then {\n let exit_val = unsigned(htif_exit_code);\n if exit_val == 0 then print(\"SUCCESS\")\n else print_int(\"FAILURE: \", exit_val);\n } else {\n /* update time */\n i = i + 1;\n if i == insns_per_tick then {\n tick_clock();\n /* for now, we drive the platform i/o at every clock tick. */\n tick_platform();\n i = 0;\n }\n }\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " let insns_per_tick = plat_insns_per_tick();\n i : int = 0;\n step_no : int = 0;\n while not(htif_done) do {\n let stepped = step(step_no);\n if stepped then step_no = step_no + 1;\n\n /* check htif exit */\n if htif_done then {\n let exit_val = unsigned(htif_exit_code);\n if exit_val == 0 then print(\"SUCCESS\")\n else print_int(\"FAILURE: \", exit_val);\n } else {\n /* update time */\n i = i + 1;\n if i == insns_per_tick then {\n tick_clock();\n /* for now, we drive the platform i/o at every clock tick. */\n tick_platform();\n i = 0;\n }\n }\n }" }, "links": [ { "type": "function", "id": "plat_insns_per_tick", "file": "model/riscv_step.sail", "loc": [ 3387, 3406 ] }, { "type": "function", "id": "not", "file": "model/riscv_step.sail", "loc": [ 3454, 3457 ] }, { "type": "register", "id": "htif_done", "file": "model/riscv_step.sail", "loc": [ 3458, 3467 ] }, { "type": "function", "id": "step", "file": "model/riscv_step.sail", "loc": [ 3492, 3496 ] }, { "type": "register", "id": "htif_done", "file": "model/riscv_step.sail", "loc": [ 3584, 3593 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_step.sail", "loc": [ 3622, 3630 ] }, { "type": "register", "id": "htif_exit_code", "file": "model/riscv_step.sail", "loc": [ 3631, 3645 ] }, { "type": "function", "id": "print", "file": "model/riscv_step.sail", "loc": [ 3676, 3681 ] }, { "type": "function", "id": "print_int", "file": "model/riscv_step.sail", "loc": [ 3704, 3713 ] }, { "type": "function", "id": "tick_platform", "file": "model/riscv_step.sail", "loc": [ 3928, 3941 ] }, { "type": "function", "id": "tick_clock", "file": "model/riscv_step.sail", "loc": [ 3836, 3846 ] } ] }, "lower_mie": { "function": { "number": 0, "source": "function lower_mie(m : Minterrupts, d : Minterrupts) -> Sinterrupts = {\n let s : Sinterrupts = Mk_Sinterrupts(zero_extend(0b0));\n let s = [s with SEI = m[SEI] & d[SEI]];\n let s = [s with STI = m[STI] & d[STI]];\n let s = [s with SSI = m[SSI] & d[SSI]];\n let s = [s with UEI = m[UEI] & d[UEI]];\n let s = [s with UTI = m[UTI] & d[UTI]];\n let s = [s with USI = m[USI] & d[USI]];\n s\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "d" } ] }, "body": " let s : Sinterrupts = Mk_Sinterrupts(zero_extend(0b0));\n let s = [s with SEI = m[SEI] & d[SEI]];\n let s = [s with STI = m[STI] & d[STI]];\n let s = [s with SSI = m[SSI] & d[SSI]];\n let s = [s with UEI = m[UEI] & d[UEI]];\n let s = [s with UTI = m[UTI] & d[UTI]];\n let s = [s with USI = m[USI] & d[USI]];\n s" }, "links": [ { "type": "function", "id": "Mk_Sinterrupts", "file": "model/riscv_sys_regs.sail", "loc": [ 19605, 19619 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 19620, 19631 ] } ] }, "lower_mip": { "function": { "number": 0, "source": "function lower_mip(m : Minterrupts, d : Minterrupts) -> Sinterrupts = {\n let s : Sinterrupts = Mk_Sinterrupts(zero_extend(0b0));\n let s = [s with SEI = m[SEI] & d[SEI]];\n let s = [s with STI = m[STI] & d[STI]];\n let s = [s with SSI = m[SSI] & d[SSI]];\n\n let s = [s with UEI = m[UEI] & d[UEI]];\n let s = [s with UTI = m[UTI] & d[UTI]];\n let s = [s with USI = m[USI] & d[USI]];\n s\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "d" } ] }, "body": " let s : Sinterrupts = Mk_Sinterrupts(zero_extend(0b0));\n let s = [s with SEI = m[SEI] & d[SEI]];\n let s = [s with STI = m[STI] & d[STI]];\n let s = [s with SSI = m[SSI] & d[SSI]];\n\n let s = [s with UEI = m[UEI] & d[UEI]];\n let s = [s with UTI = m[UTI] & d[UTI]];\n let s = [s with USI = m[USI] & d[USI]];\n s" }, "links": [ { "type": "function", "id": "Mk_Sinterrupts", "file": "model/riscv_sys_regs.sail", "loc": [ 19142, 19156 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 19157, 19168 ] } ] }, "lower_mstatus": { "function": { "number": 0, "source": "function lower_mstatus(m : Mstatus) -> Sstatus = {\n let s = Mk_Sstatus(zero_extend(0b0));\n let s = [s with SD = m[SD]];\n let s = set_sstatus_UXL(s, get_mstatus_UXL(m));\n let s = [s with MXR = m[MXR]];\n let s = [s with SUM = m[SUM]];\n let s = [s with XS = m[XS]];\n let s = [s with FS = m[FS]];\n let s = [s with VS = m[VS]];\n let s = [s with SPP = m[SPP]];\n let s = [s with SPIE = m[SPIE]];\n let s = [s with UPIE = m[UPIE]];\n let s = [s with SIE = m[SIE]];\n let s = [s with UIE = m[UIE]];\n s\n}", "pattern": { "type": "id", "id": "m" }, "body": " let s = Mk_Sstatus(zero_extend(0b0));\n let s = [s with SD = m[SD]];\n let s = set_sstatus_UXL(s, get_mstatus_UXL(m));\n let s = [s with MXR = m[MXR]];\n let s = [s with SUM = m[SUM]];\n let s = [s with XS = m[XS]];\n let s = [s with FS = m[FS]];\n let s = [s with VS = m[VS]];\n let s = [s with SPP = m[SPP]];\n let s = [s with SPIE = m[SPIE]];\n let s = [s with UPIE = m[UPIE]];\n let s = [s with SIE = m[SIE]];\n let s = [s with UIE = m[UIE]];\n s" }, "links": [ { "type": "function", "id": "Mk_Sstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 17207, 17217 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 17218, 17229 ] }, { "type": "function", "id": "set_sstatus_UXL", "file": "model/riscv_sys_regs.sail", "loc": [ 17278, 17293 ] }, { "type": "function", "id": "get_mstatus_UXL", "file": "model/riscv_sys_regs.sail", "loc": [ 17297, 17312 ] } ] }, "lower_sie": { "function": { "number": 0, "source": "function lower_sie(s : Sinterrupts, d : Sinterrupts) -> Uinterrupts = {\n let u : Uinterrupts = Mk_Uinterrupts(zero_extend(0b0));\n let u = [u with UEI = s[UEI] & d[UEI]];\n let u = [u with UTI = s[UTI] & d[UTI]];\n let u = [u with USI = s[USI] & d[USI]];\n u\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "s" }, { "type": "id", "id": "d" } ] }, "body": " let u : Uinterrupts = Mk_Uinterrupts(zero_extend(0b0));\n let u = [u with UEI = s[UEI] & d[UEI]];\n let u = [u with UTI = s[UTI] & d[UTI]];\n let u = [u with USI = s[USI] & d[USI]];\n u" }, "links": [ { "type": "function", "id": "Mk_Uinterrupts", "file": "model/riscv_next_regs.sail", "loc": [ 2120, 2134 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_next_regs.sail", "loc": [ 2135, 2146 ] } ] }, "lower_sip": { "function": { "number": 0, "source": "function lower_sip(s : Sinterrupts, d : Sinterrupts) -> Uinterrupts = {\n let u : Uinterrupts = Mk_Uinterrupts(zero_extend(0b0));\n let u = [u with UEI = s[UEI] & d[UEI]];\n let u = [u with UTI = s[UTI] & d[UTI]];\n let u = [u with USI = s[USI] & d[USI]];\n u\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "s" }, { "type": "id", "id": "d" } ] }, "body": " let u : Uinterrupts = Mk_Uinterrupts(zero_extend(0b0));\n let u = [u with UEI = s[UEI] & d[UEI]];\n let u = [u with UTI = s[UTI] & d[UTI]];\n let u = [u with USI = s[USI] & d[USI]];\n u" }, "links": [ { "type": "function", "id": "Mk_Uinterrupts", "file": "model/riscv_next_regs.sail", "loc": [ 1792, 1806 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_next_regs.sail", "loc": [ 1807, 1818 ] } ] }, "lower_sstatus": { "function": { "number": 0, "source": "function lower_sstatus(s : Sstatus) -> Ustatus = {\n let u = Mk_Ustatus(zero_extend(0b0));\n let u = [u with UPIE = s[UPIE]];\n let u = [u with UIE = s[UIE]];\n u\n}", "pattern": { "type": "id", "id": "s" }, "body": " let u = Mk_Ustatus(zero_extend(0b0));\n let u = [u with UPIE = s[UPIE]];\n let u = [u with UIE = s[UIE]];\n u" }, "links": [ { "type": "function", "id": "Mk_Ustatus", "file": "model/riscv_next_regs.sail", "loc": [ 942, 952 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_next_regs.sail", "loc": [ 953, 964 ] } ] }, "lrsc_width_str": { "function": { "number": 0, "source": "function lrsc_width_str(width : word_width) -> string =\n match (width) {\n BYTE => \".b\",\n HALF => \".h\",\n WORD => \".w\",\n DOUBLE => \".d\"\n }", "pattern": { "type": "id", "id": "width" }, "body": "match (width) {\n BYTE => \".b\",\n HALF => \".h\",\n WORD => \".w\",\n DOUBLE => \".d\"\n }" } }, "main": { "function": { "number": 0, "source": "function main () : unit -> unit = {\n // initialize extensions\n ext_init ();\n\n // PC = __GetSlice_int(64, elf_entry(), 0);\n PC = sail_zero_extend(0x1000, sizeof(xlen));\n print_bits(\"PC = \", PC);\n\n try {\n init_model();\n loop()\n } catch {\n Error_not_implemented(s) => print_string(\"Error: Not implemented: \", s),\n Error_internal_error() => print(\"Error: internal error\")\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " ext_init ();\n\n // PC = __GetSlice_int(64, elf_entry(), 0);\n PC = sail_zero_extend(0x1000, sizeof(xlen));\n print_bits(\"PC = \", PC);\n\n try {\n init_model();\n loop()\n } catch {\n Error_not_implemented(s) => print_string(\"Error: Not implemented: \", s),\n Error_internal_error() => print(\"Error: internal error\")\n }" }, "links": [ { "type": "function", "id": "loop", "file": "model/main.sail", "loc": [ 875, 879 ] }, { "type": "function", "id": "init_model", "file": "model/main.sail", "loc": [ 857, 867 ] }, { "type": "function", "id": "print", "file": "model/main.sail", "loc": [ 1001, 1006 ] }, { "type": "function", "id": "print_string", "file": "model/main.sail", "loc": [ 926, 938 ] }, { "type": "function", "id": "print_bits", "file": "model/main.sail", "loc": [ 819, 829 ] }, { "type": "register", "id": "PC", "file": "model/main.sail", "loc": [ 839, 841 ] }, { "type": "register", "id": "PC", "file": "model/main.sail", "loc": [ 772, 774 ] }, { "type": "function", "id": "sail_zero_extend", "file": "model/main.sail", "loc": [ 777, 793 ] }, { "type": "function", "id": "ext_init", "file": "model/main.sail", "loc": [ 710, 718 ] } ] }, "maskfunct3_of_num": { "function": { "number": 0, "source": "maskfunct3_of_num arg# = $[complete] match arg# {\n 0 => VV_VMERGE,\n 1 => VI_VMERGE,\n _ => VX_VMERGE\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VV_VMERGE,\n 1 => VI_VMERGE,\n _ => VX_VMERGE\n}" } }, "match_TLB_Entry": { "function": { "number": 0, "source": "function match_TLB_Entry(ent : TLB_Entry,\n asid : asidbits,\n vaddr : bits(64)) -> bool =\n (ent.global | (ent.asid == asid))\n & (ent.vAddr == (ent.vMatchMask & vaddr))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "ent" }, { "type": "id", "id": "asid" }, { "type": "id", "id": "vaddr" } ] }, "body": "(ent.global | (ent.asid == asid))\n & (ent.vAddr == (ent.vMatchMask & vaddr))" } }, "mem_read": { "function": { "number": 0, "source": "function mem_read (typ, paddr, width, aq, rel, res) =\n mem_read_priv(typ, effectivePrivilege(typ, mstatus, cur_privilege), paddr, width, aq, rel, res)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "typ" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rel" }, { "type": "id", "id": "res" } ] }, "body": "mem_read_priv(typ, effectivePrivilege(typ, mstatus, cur_privilege), paddr, width, aq, rel, res)" }, "links": [ { "type": "function", "id": "mem_read_priv", "file": "model/riscv_mem.sail", "loc": [ 8218, 8231 ] }, { "type": "function", "id": "effectivePrivilege", "file": "model/riscv_mem.sail", "loc": [ 8237, 8255 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_mem.sail", "loc": [ 8270, 8283 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_mem.sail", "loc": [ 8261, 8268 ] } ] }, "mem_read_meta": { "function": { "number": 0, "source": "function mem_read_meta (typ, paddr, width, aq, rl, res, meta) =\n mem_read_priv_meta(typ, effectivePrivilege(typ, mstatus, cur_privilege), paddr, width, aq, rl, res, meta)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "typ" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "res" }, { "type": "id", "id": "meta" } ] }, "body": "mem_read_priv_meta(typ, effectivePrivilege(typ, mstatus, cur_privilege), paddr, width, aq, rl, res, meta)" }, "links": [ { "type": "function", "id": "mem_read_priv_meta", "file": "model/riscv_mem.sail", "loc": [ 7761, 7779 ] }, { "type": "function", "id": "effectivePrivilege", "file": "model/riscv_mem.sail", "loc": [ 7785, 7803 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_mem.sail", "loc": [ 7818, 7831 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_mem.sail", "loc": [ 7809, 7816 ] } ] }, "mem_read_priv": { "function": { "number": 0, "source": "function mem_read_priv (typ, priv, paddr, width, aq, rl, res) =\n MemoryOpResult_drop_meta(mem_read_priv_meta(typ, priv, paddr, width, aq, rl, res, false))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "typ" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "res" } ] }, "body": "MemoryOpResult_drop_meta(mem_read_priv_meta(typ, priv, paddr, width, aq, rl, res, false))" }, "links": [ { "type": "function", "id": "MemoryOpResult_drop_meta", "file": "model/riscv_mem.sail", "loc": [ 7990, 8014 ] }, { "type": "function", "id": "mem_read_priv_meta", "file": "model/riscv_mem.sail", "loc": [ 8015, 8033 ] } ] }, "mem_read_priv_meta": { "function": { "number": 0, "source": "function mem_read_priv_meta (typ, priv, paddr, width, aq, rl, res, meta) = {\n let result : MemoryOpResult((bits(8 * 'n), mem_meta)) =\n if (aq | res) & not(is_aligned_addr(paddr, width))\n then MemException(E_Load_Addr_Align())\n else match (aq, rl, res) {\n (false, true, false) => throw(Error_not_implemented(\"load.rl\")),\n (false, true, true) => throw(Error_not_implemented(\"lr.rl\")),\n (_, _, _) => pmp_mem_read(typ, priv, paddr, width, aq, rl, res, meta)\n };\n rvfi_read(paddr, width, result);\n result\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "typ" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "res" }, { "type": "id", "id": "meta" } ] }, "body": " let result : MemoryOpResult((bits(8 * 'n), mem_meta)) =\n if (aq | res) & not(is_aligned_addr(paddr, width))\n then MemException(E_Load_Addr_Align())\n else match (aq, rl, res) {\n (false, true, false) => throw(Error_not_implemented(\"load.rl\")),\n (false, true, true) => throw(Error_not_implemented(\"lr.rl\")),\n (_, _, _) => pmp_mem_read(typ, priv, paddr, width, aq, rl, res, meta)\n };\n rvfi_read(paddr, width, result);\n result" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_mem.sail", "loc": [ 7302, 7305 ] }, { "type": "function", "id": "is_aligned_addr", "file": "model/riscv_mem.sail", "loc": [ 7306, 7321 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 7346, 7358 ] }, { "type": "function", "id": "E_Load_Addr_Align", "file": "model/riscv_mem.sail", "loc": [ 7359, 7376 ] }, { "type": "function", "id": "pmp_mem_read", "file": "model/riscv_mem.sail", "loc": [ 7584, 7596 ] }, { "type": "function", "id": "Error_not_implemented", "file": "model/riscv_mem.sail", "loc": [ 7520, 7541 ] }, { "type": "function", "id": "Error_not_implemented", "file": "model/riscv_mem.sail", "loc": [ 7448, 7469 ] }, { "type": "function", "id": "rvfi_read", "file": "model/riscv_mem.sail", "loc": [ 7650, 7659 ] } ] }, "mem_write_ea": { "function": { "number": 0, "source": "function mem_write_ea (addr, width, aq, rl, con) = {\n if (rl | con) & not(is_aligned_addr(addr, width))\n then MemException(E_SAMO_Addr_Align())\n else match (aq, rl, con) {\n (false, false, false) => MemValue(write_ram_ea(Write_plain, addr, width)),\n (false, true, false) => MemValue(write_ram_ea(Write_RISCV_release, addr, width)),\n (false, false, true) => MemValue(write_ram_ea(Write_RISCV_conditional, addr, width)),\n (false, true , true) => MemValue(write_ram_ea(Write_RISCV_conditional_release, addr, width)),\n (true, false, false) => throw(Error_not_implemented(\"store.aq\")),\n (true, true, false) => MemValue(write_ram_ea(Write_RISCV_strong_release, addr, width)),\n (true, false, true) => throw(Error_not_implemented(\"sc.aq\")),\n (true, true , true) => MemValue(write_ram_ea(Write_RISCV_conditional_strong_release, addr, width))\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "con" } ] }, "body": " if (rl | con) & not(is_aligned_addr(addr, width))\n then MemException(E_SAMO_Addr_Align())\n else match (aq, rl, con) {\n (false, false, false) => MemValue(write_ram_ea(Write_plain, addr, width)),\n (false, true, false) => MemValue(write_ram_ea(Write_RISCV_release, addr, width)),\n (false, false, true) => MemValue(write_ram_ea(Write_RISCV_conditional, addr, width)),\n (false, true , true) => MemValue(write_ram_ea(Write_RISCV_conditional_release, addr, width)),\n (true, false, false) => throw(Error_not_implemented(\"store.aq\")),\n (true, true, false) => MemValue(write_ram_ea(Write_RISCV_strong_release, addr, width)),\n (true, false, true) => throw(Error_not_implemented(\"sc.aq\")),\n (true, true , true) => MemValue(write_ram_ea(Write_RISCV_conditional_strong_release, addr, width))\n }" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_mem.sail", "loc": [ 8506, 8509 ] }, { "type": "function", "id": "is_aligned_addr", "file": "model/riscv_mem.sail", "loc": [ 8510, 8525 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 8547, 8559 ] }, { "type": "function", "id": "E_SAMO_Addr_Align", "file": "model/riscv_mem.sail", "loc": [ 8560, 8577 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_mem.sail", "loc": [ 9228, 9236 ] }, { "type": "function", "id": "write_ram_ea", "file": "model/riscv_mem.sail", "loc": [ 9237, 9249 ] }, { "type": "function", "id": "Error_not_implemented", "file": "model/riscv_mem.sail", "loc": [ 9166, 9187 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_mem.sail", "loc": [ 9066, 9074 ] }, { "type": "function", "id": "write_ram_ea", "file": "model/riscv_mem.sail", "loc": [ 9075, 9087 ] }, { "type": "function", "id": "Error_not_implemented", "file": "model/riscv_mem.sail", "loc": [ 9001, 9022 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_mem.sail", "loc": [ 8896, 8904 ] }, { "type": "function", "id": "write_ram_ea", "file": "model/riscv_mem.sail", "loc": [ 8905, 8917 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_mem.sail", "loc": [ 8805, 8813 ] }, { "type": "function", "id": "write_ram_ea", "file": "model/riscv_mem.sail", "loc": [ 8814, 8826 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_mem.sail", "loc": [ 8718, 8726 ] }, { "type": "function", "id": "write_ram_ea", "file": "model/riscv_mem.sail", "loc": [ 8727, 8739 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_mem.sail", "loc": [ 8639, 8647 ] }, { "type": "function", "id": "write_ram_ea", "file": "model/riscv_mem.sail", "loc": [ 8648, 8660 ] } ] }, "mem_write_value": { "function": { "number": 0, "source": "function mem_write_value (paddr, width, value, aq, rl, con) = {\n mem_write_value_meta(paddr, width, value, default_write_acc, default_meta, aq, rl, con)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "value" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "con" } ] }, "body": " mem_write_value_meta(paddr, width, value, default_write_acc, default_meta, aq, rl, con)" }, "links": [ { "type": "function", "id": "mem_write_value_meta", "file": "model/riscv_mem.sail", "loc": [ 14453, 14473 ] } ] }, "mem_write_value_meta": { "function": { "number": 0, "source": "function mem_write_value_meta (paddr, width, value, ext_acc, meta, aq, rl, con) = {\n let typ = Write(ext_acc);\n let ep = effectivePrivilege(typ, mstatus, cur_privilege);\n mem_write_value_priv_meta(paddr, width, value, typ, ep, meta, aq, rl, con)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "value" }, { "type": "id", "id": "ext_acc" }, { "type": "id", "id": "meta" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "con" } ] }, "body": " let typ = Write(ext_acc);\n let ep = effectivePrivilege(typ, mstatus, cur_privilege);\n mem_write_value_priv_meta(paddr, width, value, typ, ep, meta, aq, rl, con)" }, "links": [ { "type": "function", "id": "Write", "file": "model/riscv_mem.sail", "loc": [ 14027, 14032 ] }, { "type": "function", "id": "effectivePrivilege", "file": "model/riscv_mem.sail", "loc": [ 14054, 14072 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_mem.sail", "loc": [ 14087, 14100 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_mem.sail", "loc": [ 14078, 14085 ] }, { "type": "function", "id": "mem_write_value_priv_meta", "file": "model/riscv_mem.sail", "loc": [ 14105, 14130 ] } ] }, "mem_write_value_priv": { "function": { "number": 0, "source": "function mem_write_value_priv (paddr, width, value, priv, aq, rl, con) =\n mem_write_value_priv_meta(paddr, width, value, Write(default_write_acc), priv, default_meta, aq, rl, con)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "value" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "con" } ] }, "body": "mem_write_value_priv_meta(paddr, width, value, Write(default_write_acc), priv, default_meta, aq, rl, con)" }, "links": [ { "type": "function", "id": "mem_write_value_priv_meta", "file": "model/riscv_mem.sail", "loc": [ 13575, 13600 ] }, { "type": "function", "id": "Write", "file": "model/riscv_mem.sail", "loc": [ 13622, 13627 ] } ] }, "mem_write_value_priv_meta": { "function": { "number": 0, "source": "function mem_write_value_priv_meta (paddr, width, value, typ, priv, meta, aq, rl, con) = {\n if (rl | con) & not(is_aligned_addr(paddr, width))\n then MemException(E_SAMO_Addr_Align())\n else {\n let wk : write_kind = match (aq, rl, con) {\n (false, false, false) => Write_plain,\n (false, true, false) => Write_RISCV_release,\n (false, false, true) => Write_RISCV_conditional,\n (false, true , true) => Write_RISCV_conditional_release,\n (true, true, false) => Write_RISCV_strong_release,\n (true, true , true) => Write_RISCV_conditional_strong_release,\n // throw an illegal instruction here?\n (true, false, false) => throw(Error_not_implemented(\"store.aq\")),\n (true, false, true) => throw(Error_not_implemented(\"sc.aq\"))\n };\n let result = pmp_mem_write(wk, paddr, width, value, typ, priv, meta);\n rvfi_write(paddr, width, value, meta, result);\n result\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "value" }, { "type": "id", "id": "typ" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "meta" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "con" } ] }, "body": " if (rl | con) & not(is_aligned_addr(paddr, width))\n then MemException(E_SAMO_Addr_Align())\n else {\n let wk : write_kind = match (aq, rl, con) {\n (false, false, false) => Write_plain,\n (false, true, false) => Write_RISCV_release,\n (false, false, true) => Write_RISCV_conditional,\n (false, true , true) => Write_RISCV_conditional_release,\n (true, true, false) => Write_RISCV_strong_release,\n (true, true , true) => Write_RISCV_conditional_strong_release,\n // throw an illegal instruction here?\n (true, false, false) => throw(Error_not_implemented(\"store.aq\")),\n (true, false, true) => throw(Error_not_implemented(\"sc.aq\"))\n };\n let result = pmp_mem_write(wk, paddr, width, value, typ, priv, meta);\n rvfi_write(paddr, width, value, meta, result);\n result\n }" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_mem.sail", "loc": [ 12456, 12459 ] }, { "type": "function", "id": "is_aligned_addr", "file": "model/riscv_mem.sail", "loc": [ 12460, 12475 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 12498, 12510 ] }, { "type": "function", "id": "E_SAMO_Addr_Align", "file": "model/riscv_mem.sail", "loc": [ 12511, 12528 ] }, { "type": "function", "id": "Error_not_implemented", "file": "model/riscv_mem.sail", "loc": [ 13089, 13110 ] }, { "type": "function", "id": "Error_not_implemented", "file": "model/riscv_mem.sail", "loc": [ 13016, 13037 ] }, { "type": "function", "id": "pmp_mem_write", "file": "model/riscv_mem.sail", "loc": [ 13145, 13158 ] }, { "type": "function", "id": "rvfi_write", "file": "model/riscv_mem.sail", "loc": [ 13206, 13216 ] } ] }, "mmfunct6_of_num": { "function": { "number": 0, "source": "mmfunct6_of_num arg# = $[complete] match arg# {\n 0 => MM_VMAND,\n 1 => MM_VMNAND,\n 2 => MM_VMANDNOT,\n 3 => MM_VMXOR,\n 4 => MM_VMOR,\n 5 => MM_VMNOR,\n 6 => MM_VMORNOT,\n _ => MM_VMXNOR\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => MM_VMAND,\n 1 => MM_VMNAND,\n 2 => MM_VMANDNOT,\n 3 => MM_VMXOR,\n 4 => MM_VMOR,\n 5 => MM_VMNOR,\n 6 => MM_VMORNOT,\n _ => MM_VMXNOR\n}" } }, "mmio_read": { "function": { "number": 0, "source": "function mmio_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), paddr : xlenbits, width : int('n)) -> MemoryOpResult(bits(8 * 'n)) =\n if within_clint(paddr, width)\n then clint_load(t, paddr, width)\n else if within_htif_readable(paddr, width) & (1 <= 'n)\n then htif_load(t, paddr, width)\n else match t {\n Execute() => MemException(E_Fetch_Access_Fault()),\n Read(Data) => MemException(E_Load_Access_Fault()),\n _ => MemException(E_SAMO_Access_Fault())\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "t" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" } ] }, "body": "if within_clint(paddr, width)\n then clint_load(t, paddr, width)\n else if within_htif_readable(paddr, width) & (1 <= 'n)\n then htif_load(t, paddr, width)\n else match t {\n Execute() => MemException(E_Fetch_Access_Fault()),\n Read(Data) => MemException(E_Load_Access_Fault()),\n _ => MemException(E_SAMO_Access_Fault())\n }" }, "links": [ { "type": "function", "id": "within_clint", "file": "model/riscv_platform.sail", "loc": [ 17898, 17910 ] }, { "type": "function", "id": "clint_load", "file": "model/riscv_platform.sail", "loc": [ 17932, 17942 ] }, { "type": "function", "id": "within_htif_readable", "file": "model/riscv_platform.sail", "loc": [ 17970, 17990 ] }, { "type": "function", "id": "htif_load", "file": "model/riscv_platform.sail", "loc": [ 18024, 18033 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 18197, 18209 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 18210, 18229 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 18142, 18154 ] }, { "type": "function", "id": "E_Load_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 18155, 18174 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 18086, 18098 ] }, { "type": "function", "id": "E_Fetch_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 18099, 18119 ] } ] }, "mmio_write": { "function": { "number": 0, "source": "function mmio_write forall 'n, 0 <'n <= max_mem_access . (paddr : xlenbits, width : int('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) =\n if within_clint(paddr, width)\n then clint_store(paddr, width, data)\n else if within_htif_writable(paddr, width) & 'n <= 8\n then htif_store(paddr, width, data)\n else MemException(E_SAMO_Access_Fault())", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "data" } ] }, "body": "if within_clint(paddr, width)\n then clint_store(paddr, width, data)\n else if within_htif_writable(paddr, width) & 'n <= 8\n then htif_store(paddr, width, data)\n else MemException(E_SAMO_Access_Fault())" }, "links": [ { "type": "function", "id": "within_clint", "file": "model/riscv_platform.sail", "loc": [ 18384, 18396 ] }, { "type": "function", "id": "clint_store", "file": "model/riscv_platform.sail", "loc": [ 18418, 18429 ] }, { "type": "function", "id": "within_htif_writable", "file": "model/riscv_platform.sail", "loc": [ 18460, 18480 ] }, { "type": "function", "id": "htif_store", "file": "model/riscv_platform.sail", "loc": [ 18512, 18522 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_platform.sail", "loc": [ 18550, 18562 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_platform.sail", "loc": [ 18563, 18582 ] } ] }, "msbs_of_PTE": { "function": { "number": 0, "source": "function msbs_of_PTE(sv_params : SV_Params, pte : bits(64)) -> bits(64) = {\n let mask : bits(64) = zero_extend(ones(sv_params.pte_msbs_size_bits));\n (pte >> sv_params.pte_msbs_lsb_index) & mask\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "pte" } ] }, "body": " let mask : bits(64) = zero_extend(ones(sv_params.pte_msbs_size_bits));\n (pte >> sv_params.pte_msbs_lsb_index) & mask" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem_pte.sail", "loc": [ 1308, 1319 ] }, { "type": "function", "id": "ones", "file": "model/riscv_vmem_pte.sail", "loc": [ 1320, 1324 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] } ] }, "mvvfunct6_of_num": { "function": { "number": 0, "source": "mvvfunct6_of_num arg# = $[complete] match arg# {\n 0 => MVV_VAADDU,\n 1 => MVV_VAADD,\n 2 => MVV_VASUBU,\n 3 => MVV_VASUB,\n 4 => MVV_VMUL,\n 5 => MVV_VMULH,\n 6 => MVV_VMULHU,\n 7 => MVV_VMULHSU,\n 8 => MVV_VDIVU,\n 9 => MVV_VDIV,\n 10 => MVV_VREMU,\n _ => MVV_VREM\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => MVV_VAADDU,\n 1 => MVV_VAADD,\n 2 => MVV_VASUBU,\n 3 => MVV_VASUB,\n 4 => MVV_VMUL,\n 5 => MVV_VMULH,\n 6 => MVV_VMULHU,\n 7 => MVV_VMULHSU,\n 8 => MVV_VDIVU,\n 9 => MVV_VDIV,\n 10 => MVV_VREMU,\n _ => MVV_VREM\n}" } }, "mvvmafunct6_of_num": { "function": { "number": 0, "source": "mvvmafunct6_of_num arg# = $[complete] match arg# {\n 0 => MVV_VMACC,\n 1 => MVV_VNMSAC,\n 2 => MVV_VMADD,\n _ => MVV_VNMSUB\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => MVV_VMACC,\n 1 => MVV_VNMSAC,\n 2 => MVV_VMADD,\n _ => MVV_VNMSUB\n}" } }, "mvxfunct6_of_num": { "function": { "number": 0, "source": "mvxfunct6_of_num arg# = $[complete] match arg# {\n 0 => MVX_VAADDU,\n 1 => MVX_VAADD,\n 2 => MVX_VASUBU,\n 3 => MVX_VASUB,\n 4 => MVX_VSLIDE1UP,\n 5 => MVX_VSLIDE1DOWN,\n 6 => MVX_VMUL,\n 7 => MVX_VMULH,\n 8 => MVX_VMULHU,\n 9 => MVX_VMULHSU,\n 10 => MVX_VDIVU,\n 11 => MVX_VDIV,\n 12 => MVX_VREMU,\n _ => MVX_VREM\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => MVX_VAADDU,\n 1 => MVX_VAADD,\n 2 => MVX_VASUBU,\n 3 => MVX_VASUB,\n 4 => MVX_VSLIDE1UP,\n 5 => MVX_VSLIDE1DOWN,\n 6 => MVX_VMUL,\n 7 => MVX_VMULH,\n 8 => MVX_VMULHU,\n 9 => MVX_VMULHSU,\n 10 => MVX_VDIVU,\n 11 => MVX_VDIV,\n 12 => MVX_VREMU,\n _ => MVX_VREM\n}" } }, "mvxmafunct6_of_num": { "function": { "number": 0, "source": "mvxmafunct6_of_num arg# = $[complete] match arg# {\n 0 => MVX_VMACC,\n 1 => MVX_VNMSAC,\n 2 => MVX_VMADD,\n _ => MVX_VNMSUB\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => MVX_VMACC,\n 1 => MVX_VNMSAC,\n 2 => MVX_VMADD,\n _ => MVX_VNMSUB\n}" } }, "n_leading_spaces": { "function": { "number": 0, "source": "function n_leading_spaces s =\n match s {\n \"\" => 0,\n _ => match string_take(s, 1) {\n \" \" => 1 + n_leading_spaces(string_drop(s, 1)),\n _ => 0\n }\n }", "pattern": { "type": "id", "id": "s" }, "body": "match s {\n \"\" => 0,\n _ => match string_take(s, 1) {\n \" \" => 1 + n_leading_spaces(string_drop(s, 1)),\n _ => 0\n }\n }" }, "links": [ { "type": "function", "id": "string_take", "file": "model/mapping.sail", "loc": [ 5936, 5947 ] }, { "type": "function", "id": "n_leading_spaces", "file": "model/mapping.sail", "loc": [ 5973, 5989 ] }, { "type": "function", "id": "string_drop", "file": "model/mapping.sail", "loc": [ 5990, 6001 ] } ] }, "nan_box_H": { "function": { "number": 0, "source": "function nan_box_H val_16b =\n if (sizeof(flen) == 32)\n then 0x_FFFF @ val_16b\n else 0x_FFFF_FFFF_FFFF @ val_16b", "pattern": { "type": "id", "id": "val_16b" }, "body": "if (sizeof(flen) == 32)\n then 0x_FFFF @ val_16b\n else 0x_FFFF_FFFF_FFFF @ val_16b" } }, "nan_box_S": { "function": { "number": 0, "source": "function nan_box_S val_32b = {\n assert(sys_enable_fdext());\n if (sizeof(flen) == 32)\n then val_32b\n else 0x_FFFF_FFFF @ val_32b\n}", "pattern": { "type": "id", "id": "val_32b" }, "body": "function nan_box_S val_32b = {\n assert(sys_enable_fdext());\n if (sizeof(flen) == 32)\n then val_32b\n else 0x_FFFF_FFFF @ val_32b" }, "links": [ { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 2423, 2439 ] } ] }, "nan_unbox_H": { "function": { "number": 0, "source": "function nan_unbox_H regval =\n if (sizeof(flen) == 32)\n then if regval [32..16] == 0x_FFFF\n then regval [15..0]\n else canonical_NaN_H()\n else if regval [63..16] == 0x_FFFF_FFFF_FFFF\n then regval [15..0]\n else canonical_NaN_H()", "pattern": { "type": "id", "id": "regval" }, "body": "if (sizeof(flen) == 32)\n then if regval [32..16] == 0x_FFFF\n then regval [15..0]\n else canonical_NaN_H()\n else if regval [63..16] == 0x_FFFF_FFFF_FFFF\n then regval [15..0]\n else canonical_NaN_H()" }, "links": [ { "type": "function", "id": "canonical_NaN_H", "file": "model/riscv_fdext_regs.sail", "loc": [ 2223, 2238 ] }, { "type": "function", "id": "canonical_NaN_H", "file": "model/riscv_fdext_regs.sail", "loc": [ 2327, 2342 ] } ] }, "nan_unbox_S": { "function": { "number": 0, "source": "function nan_unbox_S regval = {\n assert(sys_enable_fdext());\n if (sizeof(flen) == 32)\n then regval\n else if regval [63..32] == 0x_FFFF_FFFF\n then regval [31..0]\n else canonical_NaN_S()\n}", "pattern": { "type": "id", "id": "regval" }, "body": "function nan_unbox_S regval = {\n assert(sys_enable_fdext());\n if (sizeof(flen) == 32)\n then regval\n else if regval [63..32] == 0x_FFFF_FFFF\n then regval [31..0]\n else canonical_NaN_S()" }, "links": [ { "type": "function", "id": "canonical_NaN_S", "file": "model/riscv_fdext_regs.sail", "loc": [ 2740, 2755 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 2598, 2614 ] } ] }, "negate_D": { "function": { "number": 0, "source": "function negate_D (x64) = {\n let (sign, exp, mant) = fsplit_D (x64);\n let new_sign = if (sign == 0b0) then 0b1 else 0b0;\n fmake_D (new_sign, exp, mant)\n}", "pattern": { "type": "id", "id": "x64" }, "body": " let (sign, exp, mant) = fsplit_D (x64);\n let new_sign = if (sign == 0b0) then 0b1 else 0b0;\n fmake_D (new_sign, exp, mant)" }, "links": [ { "type": "function", "id": "fsplit_D", "file": "model/riscv_insts_dext.sail", "loc": [ 4705, 4713 ] }, { "type": "function", "id": "fmake_D", "file": "model/riscv_insts_dext.sail", "loc": [ 4776, 4783 ] } ] }, "negate_H": { "function": { "number": 0, "source": "function negate_H (xf16) = {\n let (sign, exp, mant) = fsplit_H (xf16);\n let new_sign = if (sign == 0b0) then 0b1 else 0b0;\n fmake_H (new_sign, exp, mant)\n}", "pattern": { "type": "id", "id": "xf16" }, "body": " let (sign, exp, mant) = fsplit_H (xf16);\n let new_sign = if (sign == 0b0) then 0b1 else 0b0;\n fmake_H (new_sign, exp, mant)" }, "links": [ { "type": "function", "id": "fsplit_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 1989, 1997 ] }, { "type": "function", "id": "fmake_H", "file": "model/riscv_insts_zfh.sail", "loc": [ 2061, 2068 ] } ] }, "negate_S": { "function": { "number": 0, "source": "function negate_S (x32) = {\n let (sign, exp, mant) = fsplit_S (x32);\n let new_sign = if (sign == 0b0) then 0b1 else 0b0;\n fmake_S (new_sign, exp, mant)\n}", "pattern": { "type": "id", "id": "x32" }, "body": " let (sign, exp, mant) = fsplit_S (x32);\n let new_sign = if (sign == 0b0) then 0b1 else 0b0;\n fmake_S (new_sign, exp, mant)" }, "links": [ { "type": "function", "id": "fsplit_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5577, 5585 ] }, { "type": "function", "id": "fmake_S", "file": "model/riscv_insts_fext.sail", "loc": [ 5648, 5655 ] } ] }, "negate_fp": { "function": { "number": 0, "source": "function negate_fp(xf) = {\n match 'm {\n 16 => negate_H(xf),\n 32 => negate_S(xf),\n 64 => negate_D(xf)\n }\n}", "pattern": { "type": "id", "id": "xf" }, "body": " match 'm {\n 16 => negate_H(xf),\n 32 => negate_S(xf),\n 64 => negate_D(xf)\n }" }, "links": [ { "type": "function", "id": "negate_D", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22922, 22930 ] }, { "type": "function", "id": "negate_S", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22898, 22906 ] }, { "type": "function", "id": "negate_H", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22874, 22882 ] } ] }, "neq_anything": { "function": { "number": 0, "source": "neq_anything (x, y) = not_bool(eq_anything(x, y))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "not_bool(eq_anything(x, y))" } }, "neq_bits": { "function": { "number": 0, "source": "neq_bits (x, y) = not_bool(eq_bits(x, y))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "not_bool(eq_bits(x, y))" } }, "neq_bool": { "function": { "number": 0, "source": "neq_bool (x, y) = not_bool(eq_bool(x, y))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "not_bool(eq_bool(x, y))" } }, "neq_int": { "function": { "number": 0, "source": "neq_int (x, y) = not_bool(eq_int(x, y))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "not_bool(eq_int(x, y))" } }, "nifunct6_of_num": { "function": { "number": 0, "source": "nifunct6_of_num arg# = $[complete] match arg# {\n 0 => NI_VNCLIPU,\n _ => NI_VNCLIP\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => NI_VNCLIPU,\n _ => NI_VNCLIP\n}" } }, "nisfunct6_of_num": { "function": { "number": 0, "source": "nisfunct6_of_num arg# = $[complete] match arg# {\n 0 => NIS_VNSRL,\n _ => NIS_VNSRA\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => NIS_VNSRL,\n _ => NIS_VNSRA\n}" } }, "not": { "function": { "number": 0, "source": "function not(b) = not_bool(b)", "pattern": { "type": "id", "id": "b" }, "body": "not_bool(b)" }, "links": [ { "type": "function", "id": "not_bool", "file": "model/prelude.sail", "loc": [ 1109, 1117 ] } ] }, "not_bit": { "function": { "number": 0, "source": "function not_bit(b) = if b == bitone then bitzero else bitone", "pattern": { "type": "id", "id": "b" }, "body": "if b == bitone then bitzero else bitone" } }, "not_implemented": { "function": { "number": 0, "source": "function not_implemented message = throw(Error_not_implemented(message))", "pattern": { "type": "id", "id": "message" }, "body": "throw(Error_not_implemented(message))" }, "links": [ { "type": "function", "id": "Error_not_implemented", "file": "model/riscv_types.sail", "loc": [ 2532, 2553 ] } ] }, "num_of_Architecture": { "function": { "number": 0, "source": "num_of_Architecture arg# = $[complete] match arg# {\n RV32 => 0,\n RV64 => 1,\n RV128 => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RV32 => 0,\n RV64 => 1,\n RV128 => 2\n}" } }, "num_of_ExceptionType": { "function": { "number": 0, "source": "function num_of_ExceptionType(e) =\n match (e) {\n E_Fetch_Addr_Align() => 0,\n E_Fetch_Access_Fault() => 1,\n E_Illegal_Instr() => 2,\n E_Breakpoint() => 3,\n E_Load_Addr_Align() => 4,\n E_Load_Access_Fault() => 5,\n E_SAMO_Addr_Align() => 6,\n E_SAMO_Access_Fault() => 7,\n E_U_EnvCall() => 8,\n E_S_EnvCall() => 9,\n E_Reserved_10() => 10,\n E_M_EnvCall() => 11,\n E_Fetch_Page_Fault() => 12,\n E_Load_Page_Fault() => 13,\n E_Reserved_14() => 14,\n E_SAMO_Page_Fault() => 15,\n\n /* extensions */\n E_Extension(e) => num_of_ext_exc_type(e)\n\n }", "pattern": { "type": "id", "id": "e" }, "body": "match (e) {\n E_Fetch_Addr_Align() => 0,\n E_Fetch_Access_Fault() => 1,\n E_Illegal_Instr() => 2,\n E_Breakpoint() => 3,\n E_Load_Addr_Align() => 4,\n E_Load_Access_Fault() => 5,\n E_SAMO_Addr_Align() => 6,\n E_SAMO_Access_Fault() => 7,\n E_U_EnvCall() => 8,\n E_S_EnvCall() => 9,\n E_Reserved_10() => 10,\n E_M_EnvCall() => 11,\n E_Fetch_Page_Fault() => 12,\n E_Load_Page_Fault() => 13,\n E_Reserved_14() => 14,\n E_SAMO_Page_Fault() => 15,\n\n /* extensions */\n E_Extension(e) => num_of_ext_exc_type(e)\n\n }" }, "links": [ { "type": "function", "id": "num_of_ext_exc_type", "file": "model/riscv_types.sail", "loc": [ 6558, 6577 ] } ] }, "num_of_ExtStatus": { "function": { "number": 0, "source": "num_of_ExtStatus arg# = $[complete] match arg# {\n Off => 0,\n Initial => 1,\n Clean => 2,\n Dirty => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n Off => 0,\n Initial => 1,\n Clean => 2,\n Dirty => 3\n}" } }, "num_of_InterruptType": { "function": { "number": 0, "source": "num_of_InterruptType arg# = $[complete] match arg# {\n I_U_Software => 0,\n I_S_Software => 1,\n I_M_Software => 2,\n I_U_Timer => 3,\n I_S_Timer => 4,\n I_M_Timer => 5,\n I_U_External => 6,\n I_S_External => 7,\n I_M_External => 8\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n I_U_Software => 0,\n I_S_Software => 1,\n I_M_Software => 2,\n I_U_Timer => 3,\n I_S_Timer => 4,\n I_M_Timer => 5,\n I_U_External => 6,\n I_S_External => 7,\n I_M_External => 8\n}" } }, "num_of_PmpAddrMatchType": { "function": { "number": 0, "source": "num_of_PmpAddrMatchType arg# = $[complete] match arg# {\n OFF => 0,\n TOR => 1,\n NA4 => 2,\n NAPOT => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n OFF => 0,\n TOR => 1,\n NA4 => 2,\n NAPOT => 3\n}" } }, "num_of_Privilege": { "function": { "number": 0, "source": "num_of_Privilege arg# = $[complete] match arg# {\n User => 0,\n Supervisor => 1,\n Machine => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n User => 0,\n Supervisor => 1,\n Machine => 2\n}" } }, "num_of_Retired": { "function": { "number": 0, "source": "num_of_Retired arg# = $[complete] match arg# {\n RETIRE_SUCCESS => 0,\n RETIRE_FAIL => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RETIRE_SUCCESS => 0,\n RETIRE_FAIL => 1\n}" } }, "num_of_SATPMode": { "function": { "number": 0, "source": "num_of_SATPMode arg# = $[complete] match arg# {\n Sbare => 0,\n Sv32 => 1,\n Sv39 => 2,\n Sv48 => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n Sbare => 0,\n Sv32 => 1,\n Sv39 => 2,\n Sv48 => 3\n}" } }, "num_of_TrapVectorMode": { "function": { "number": 0, "source": "num_of_TrapVectorMode arg# = $[complete] match arg# {\n TV_Direct => 0,\n TV_Vector => 1,\n TV_Reserved => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n TV_Direct => 0,\n TV_Vector => 1,\n TV_Reserved => 2\n}" } }, "num_of_a64_barrier_domain": { "function": { "number": 0, "source": "num_of_a64_barrier_domain arg# = $[complete] match arg# {\n A64_FullShare => 0,\n A64_InnerShare => 1,\n A64_OuterShare => 2,\n A64_NonShare => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n A64_FullShare => 0,\n A64_InnerShare => 1,\n A64_OuterShare => 2,\n A64_NonShare => 3\n}" } }, "num_of_a64_barrier_type": { "function": { "number": 0, "source": "num_of_a64_barrier_type arg# = $[complete] match arg# {\n A64_barrier_all => 0,\n A64_barrier_LD => 1,\n A64_barrier_ST => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n A64_barrier_all => 0,\n A64_barrier_LD => 1,\n A64_barrier_ST => 2\n}" } }, "num_of_agtype": { "function": { "number": 0, "source": "num_of_agtype arg# = $[complete] match arg# {\n UNDISTURBED => 0,\n AGNOSTIC => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n UNDISTURBED => 0,\n AGNOSTIC => 1\n}" } }, "num_of_amoop": { "function": { "number": 0, "source": "num_of_amoop arg# = $[complete] match arg# {\n AMOSWAP => 0,\n AMOADD => 1,\n AMOXOR => 2,\n AMOAND => 3,\n AMOOR => 4,\n AMOMIN => 5,\n AMOMAX => 6,\n AMOMINU => 7,\n AMOMAXU => 8\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n AMOSWAP => 0,\n AMOADD => 1,\n AMOXOR => 2,\n AMOAND => 3,\n AMOOR => 4,\n AMOMIN => 5,\n AMOMAX => 6,\n AMOMINU => 7,\n AMOMAXU => 8\n}" } }, "num_of_biop_zbs": { "function": { "number": 0, "source": "num_of_biop_zbs arg# = $[complete] match arg# {\n RISCV_BCLRI => 0,\n RISCV_BEXTI => 1,\n RISCV_BINVI => 2,\n RISCV_BSETI => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_BCLRI => 0,\n RISCV_BEXTI => 1,\n RISCV_BINVI => 2,\n RISCV_BSETI => 3\n}" } }, "num_of_bop": { "function": { "number": 0, "source": "num_of_bop arg# = $[complete] match arg# {\n RISCV_BEQ => 0,\n RISCV_BNE => 1,\n RISCV_BLT => 2,\n RISCV_BGE => 3,\n RISCV_BLTU => 4,\n RISCV_BGEU => 5\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_BEQ => 0,\n RISCV_BNE => 1,\n RISCV_BLT => 2,\n RISCV_BGE => 3,\n RISCV_BLTU => 4,\n RISCV_BGEU => 5\n}" } }, "num_of_brop_zba": { "function": { "number": 0, "source": "num_of_brop_zba arg# = $[complete] match arg# {\n RISCV_SH1ADD => 0,\n RISCV_SH2ADD => 1,\n RISCV_SH3ADD => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_SH1ADD => 0,\n RISCV_SH2ADD => 1,\n RISCV_SH3ADD => 2\n}" } }, "num_of_brop_zbb": { "function": { "number": 0, "source": "num_of_brop_zbb arg# = $[complete] match arg# {\n RISCV_ANDN => 0,\n RISCV_ORN => 1,\n RISCV_XNOR => 2,\n RISCV_MAX => 3,\n RISCV_MAXU => 4,\n RISCV_MIN => 5,\n RISCV_MINU => 6,\n RISCV_ROL => 7,\n RISCV_ROR => 8\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_ANDN => 0,\n RISCV_ORN => 1,\n RISCV_XNOR => 2,\n RISCV_MAX => 3,\n RISCV_MAXU => 4,\n RISCV_MIN => 5,\n RISCV_MINU => 6,\n RISCV_ROL => 7,\n RISCV_ROR => 8\n}" } }, "num_of_brop_zbkb": { "function": { "number": 0, "source": "num_of_brop_zbkb arg# = $[complete] match arg# {\n RISCV_PACK => 0,\n RISCV_PACKH => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_PACK => 0,\n RISCV_PACKH => 1\n}" } }, "num_of_brop_zbs": { "function": { "number": 0, "source": "num_of_brop_zbs arg# = $[complete] match arg# {\n RISCV_BCLR => 0,\n RISCV_BEXT => 1,\n RISCV_BINV => 2,\n RISCV_BSET => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_BCLR => 0,\n RISCV_BEXT => 1,\n RISCV_BINV => 2,\n RISCV_BSET => 3\n}" } }, "num_of_bropw_zba": { "function": { "number": 0, "source": "num_of_bropw_zba arg# = $[complete] match arg# {\n RISCV_ADDUW => 0,\n RISCV_SH1ADDUW => 1,\n RISCV_SH2ADDUW => 2,\n RISCV_SH3ADDUW => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_ADDUW => 0,\n RISCV_SH1ADDUW => 1,\n RISCV_SH2ADDUW => 2,\n RISCV_SH3ADDUW => 3\n}" } }, "num_of_bropw_zbb": { "function": { "number": 0, "source": "num_of_bropw_zbb arg# = $[complete] match arg# {\n RISCV_ROLW => 0,\n RISCV_RORW => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_ROLW => 0,\n RISCV_RORW => 1\n}" } }, "num_of_cache_op_kind": { "function": { "number": 0, "source": "num_of_cache_op_kind arg# = $[complete] match arg# {\n Cache_op_D_IVAC => 0,\n Cache_op_D_ISW => 1,\n Cache_op_D_CSW => 2,\n Cache_op_D_CISW => 3,\n Cache_op_D_ZVA => 4,\n Cache_op_D_CVAC => 5,\n Cache_op_D_CVAU => 6,\n Cache_op_D_CIVAC => 7,\n Cache_op_I_IALLUIS => 8,\n Cache_op_I_IALLU => 9,\n Cache_op_I_IVAU => 10\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n Cache_op_D_IVAC => 0,\n Cache_op_D_ISW => 1,\n Cache_op_D_CSW => 2,\n Cache_op_D_CISW => 3,\n Cache_op_D_ZVA => 4,\n Cache_op_D_CVAC => 5,\n Cache_op_D_CVAU => 6,\n Cache_op_D_CIVAC => 7,\n Cache_op_I_IALLUIS => 8,\n Cache_op_I_IALLU => 9,\n Cache_op_I_IVAU => 10\n}" } }, "num_of_csrop": { "function": { "number": 0, "source": "num_of_csrop arg# = $[complete] match arg# {\n CSRRW => 0,\n CSRRS => 1,\n CSRRC => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n CSRRW => 0,\n CSRRS => 1,\n CSRRC => 2\n}" } }, "num_of_ext_exc_type": { "function": { "number": 0, "source": "function num_of_ext_exc_type(e) = 24", "pattern": { "type": "id", "id": "e" }, "body": "24" } }, "num_of_extop_zbb": { "function": { "number": 0, "source": "num_of_extop_zbb arg# = $[complete] match arg# {\n RISCV_SEXTB => 0,\n RISCV_SEXTH => 1,\n RISCV_ZEXTH => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_SEXTB => 0,\n RISCV_SEXTH => 1,\n RISCV_ZEXTH => 2\n}" } }, "num_of_f_bin_op_D": { "function": { "number": 0, "source": "num_of_f_bin_op_D arg# = $[complete] match arg# {\n FSGNJ_D => 0,\n FSGNJN_D => 1,\n FSGNJX_D => 2,\n FMIN_D => 3,\n FMAX_D => 4,\n FEQ_D => 5,\n FLT_D => 6,\n FLE_D => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FSGNJ_D => 0,\n FSGNJN_D => 1,\n FSGNJX_D => 2,\n FMIN_D => 3,\n FMAX_D => 4,\n FEQ_D => 5,\n FLT_D => 6,\n FLE_D => 7\n}" } }, "num_of_f_bin_op_H": { "function": { "number": 0, "source": "num_of_f_bin_op_H arg# = $[complete] match arg# {\n FSGNJ_H => 0,\n FSGNJN_H => 1,\n FSGNJX_H => 2,\n FMIN_H => 3,\n FMAX_H => 4,\n FEQ_H => 5,\n FLT_H => 6,\n FLE_H => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FSGNJ_H => 0,\n FSGNJN_H => 1,\n FSGNJX_H => 2,\n FMIN_H => 3,\n FMAX_H => 4,\n FEQ_H => 5,\n FLT_H => 6,\n FLE_H => 7\n}" } }, "num_of_f_bin_op_S": { "function": { "number": 0, "source": "num_of_f_bin_op_S arg# = $[complete] match arg# {\n FSGNJ_S => 0,\n FSGNJN_S => 1,\n FSGNJX_S => 2,\n FMIN_S => 3,\n FMAX_S => 4,\n FEQ_S => 5,\n FLT_S => 6,\n FLE_S => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FSGNJ_S => 0,\n FSGNJN_S => 1,\n FSGNJX_S => 2,\n FMIN_S => 3,\n FMAX_S => 4,\n FEQ_S => 5,\n FLT_S => 6,\n FLE_S => 7\n}" } }, "num_of_f_bin_rm_op_D": { "function": { "number": 0, "source": "num_of_f_bin_rm_op_D arg# = $[complete] match arg# {\n FADD_D => 0,\n FSUB_D => 1,\n FMUL_D => 2,\n FDIV_D => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FADD_D => 0,\n FSUB_D => 1,\n FMUL_D => 2,\n FDIV_D => 3\n}" } }, "num_of_f_bin_rm_op_H": { "function": { "number": 0, "source": "num_of_f_bin_rm_op_H arg# = $[complete] match arg# {\n FADD_H => 0,\n FSUB_H => 1,\n FMUL_H => 2,\n FDIV_H => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FADD_H => 0,\n FSUB_H => 1,\n FMUL_H => 2,\n FDIV_H => 3\n}" } }, "num_of_f_bin_rm_op_S": { "function": { "number": 0, "source": "num_of_f_bin_rm_op_S arg# = $[complete] match arg# {\n FADD_S => 0,\n FSUB_S => 1,\n FMUL_S => 2,\n FDIV_S => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FADD_S => 0,\n FSUB_S => 1,\n FMUL_S => 2,\n FDIV_S => 3\n}" } }, "num_of_f_madd_op_D": { "function": { "number": 0, "source": "num_of_f_madd_op_D arg# = $[complete] match arg# {\n FMADD_D => 0,\n FMSUB_D => 1,\n FNMSUB_D => 2,\n FNMADD_D => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FMADD_D => 0,\n FMSUB_D => 1,\n FNMSUB_D => 2,\n FNMADD_D => 3\n}" } }, "num_of_f_madd_op_H": { "function": { "number": 0, "source": "num_of_f_madd_op_H arg# = $[complete] match arg# {\n FMADD_H => 0,\n FMSUB_H => 1,\n FNMSUB_H => 2,\n FNMADD_H => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FMADD_H => 0,\n FMSUB_H => 1,\n FNMSUB_H => 2,\n FNMADD_H => 3\n}" } }, "num_of_f_madd_op_S": { "function": { "number": 0, "source": "num_of_f_madd_op_S arg# = $[complete] match arg# {\n FMADD_S => 0,\n FMSUB_S => 1,\n FNMSUB_S => 2,\n FNMADD_S => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FMADD_S => 0,\n FMSUB_S => 1,\n FNMSUB_S => 2,\n FNMADD_S => 3\n}" } }, "num_of_f_un_op_D": { "function": { "number": 0, "source": "num_of_f_un_op_D arg# = $[complete] match arg# {\n FCLASS_D => 0,\n FMV_X_D => 1,\n FMV_D_X => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FCLASS_D => 0,\n FMV_X_D => 1,\n FMV_D_X => 2\n}" } }, "num_of_f_un_op_H": { "function": { "number": 0, "source": "num_of_f_un_op_H arg# = $[complete] match arg# {\n FCLASS_H => 0,\n FMV_X_H => 1,\n FMV_H_X => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FCLASS_H => 0,\n FMV_X_H => 1,\n FMV_H_X => 2\n}" } }, "num_of_f_un_op_S": { "function": { "number": 0, "source": "num_of_f_un_op_S arg# = $[complete] match arg# {\n FCLASS_S => 0,\n FMV_X_W => 1,\n FMV_W_X => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FCLASS_S => 0,\n FMV_X_W => 1,\n FMV_W_X => 2\n}" } }, "num_of_f_un_rm_op_D": { "function": { "number": 0, "source": "num_of_f_un_rm_op_D arg# = $[complete] match arg# {\n FSQRT_D => 0,\n FCVT_W_D => 1,\n FCVT_WU_D => 2,\n FCVT_D_W => 3,\n FCVT_D_WU => 4,\n FCVT_S_D => 5,\n FCVT_D_S => 6,\n FCVT_L_D => 7,\n FCVT_LU_D => 8,\n FCVT_D_L => 9,\n FCVT_D_LU => 10\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FSQRT_D => 0,\n FCVT_W_D => 1,\n FCVT_WU_D => 2,\n FCVT_D_W => 3,\n FCVT_D_WU => 4,\n FCVT_S_D => 5,\n FCVT_D_S => 6,\n FCVT_L_D => 7,\n FCVT_LU_D => 8,\n FCVT_D_L => 9,\n FCVT_D_LU => 10\n}" } }, "num_of_f_un_rm_op_H": { "function": { "number": 0, "source": "num_of_f_un_rm_op_H arg# = $[complete] match arg# {\n FSQRT_H => 0,\n FCVT_W_H => 1,\n FCVT_WU_H => 2,\n FCVT_H_W => 3,\n FCVT_H_WU => 4,\n FCVT_H_S => 5,\n FCVT_H_D => 6,\n FCVT_S_H => 7,\n FCVT_D_H => 8,\n FCVT_L_H => 9,\n FCVT_LU_H => 10,\n FCVT_H_L => 11,\n FCVT_H_LU => 12\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FSQRT_H => 0,\n FCVT_W_H => 1,\n FCVT_WU_H => 2,\n FCVT_H_W => 3,\n FCVT_H_WU => 4,\n FCVT_H_S => 5,\n FCVT_H_D => 6,\n FCVT_S_H => 7,\n FCVT_D_H => 8,\n FCVT_L_H => 9,\n FCVT_LU_H => 10,\n FCVT_H_L => 11,\n FCVT_H_LU => 12\n}" } }, "num_of_f_un_rm_op_S": { "function": { "number": 0, "source": "num_of_f_un_rm_op_S arg# = $[complete] match arg# {\n FSQRT_S => 0,\n FCVT_W_S => 1,\n FCVT_WU_S => 2,\n FCVT_S_W => 3,\n FCVT_S_WU => 4,\n FCVT_L_S => 5,\n FCVT_LU_S => 6,\n FCVT_S_L => 7,\n FCVT_S_LU => 8\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FSQRT_S => 0,\n FCVT_W_S => 1,\n FCVT_WU_S => 2,\n FCVT_S_W => 3,\n FCVT_S_WU => 4,\n FCVT_L_S => 5,\n FCVT_LU_S => 6,\n FCVT_S_L => 7,\n FCVT_S_LU => 8\n}" } }, "num_of_fvffunct6": { "function": { "number": 0, "source": "num_of_fvffunct6 arg# = $[complete] match arg# {\n VF_VADD => 0,\n VF_VSUB => 1,\n VF_VMIN => 2,\n VF_VMAX => 3,\n VF_VSGNJ => 4,\n VF_VSGNJN => 5,\n VF_VSGNJX => 6,\n VF_VDIV => 7,\n VF_VRDIV => 8,\n VF_VMUL => 9,\n VF_VRSUB => 10,\n VF_VSLIDE1UP => 11,\n VF_VSLIDE1DOWN => 12\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VF_VADD => 0,\n VF_VSUB => 1,\n VF_VMIN => 2,\n VF_VMAX => 3,\n VF_VSGNJ => 4,\n VF_VSGNJN => 5,\n VF_VSGNJX => 6,\n VF_VDIV => 7,\n VF_VRDIV => 8,\n VF_VMUL => 9,\n VF_VRSUB => 10,\n VF_VSLIDE1UP => 11,\n VF_VSLIDE1DOWN => 12\n}" } }, "num_of_fvfmafunct6": { "function": { "number": 0, "source": "num_of_fvfmafunct6 arg# = $[complete] match arg# {\n VF_VMADD => 0,\n VF_VNMADD => 1,\n VF_VMSUB => 2,\n VF_VNMSUB => 3,\n VF_VMACC => 4,\n VF_VNMACC => 5,\n VF_VMSAC => 6,\n VF_VNMSAC => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VF_VMADD => 0,\n VF_VNMADD => 1,\n VF_VMSUB => 2,\n VF_VNMSUB => 3,\n VF_VMACC => 4,\n VF_VNMACC => 5,\n VF_VMSAC => 6,\n VF_VNMSAC => 7\n}" } }, "num_of_fvfmfunct6": { "function": { "number": 0, "source": "num_of_fvfmfunct6 arg# = $[complete] match arg# {\n VFM_VMFEQ => 0,\n VFM_VMFLE => 1,\n VFM_VMFLT => 2,\n VFM_VMFNE => 3,\n VFM_VMFGT => 4,\n VFM_VMFGE => 5\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VFM_VMFEQ => 0,\n VFM_VMFLE => 1,\n VFM_VMFLT => 2,\n VFM_VMFNE => 3,\n VFM_VMFGT => 4,\n VFM_VMFGE => 5\n}" } }, "num_of_fvvfunct6": { "function": { "number": 0, "source": "num_of_fvvfunct6 arg# = $[complete] match arg# {\n FVV_VADD => 0,\n FVV_VSUB => 1,\n FVV_VMIN => 2,\n FVV_VMAX => 3,\n FVV_VSGNJ => 4,\n FVV_VSGNJN => 5,\n FVV_VSGNJX => 6,\n FVV_VDIV => 7,\n FVV_VMUL => 8\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FVV_VADD => 0,\n FVV_VSUB => 1,\n FVV_VMIN => 2,\n FVV_VMAX => 3,\n FVV_VSGNJ => 4,\n FVV_VSGNJN => 5,\n FVV_VSGNJX => 6,\n FVV_VDIV => 7,\n FVV_VMUL => 8\n}" } }, "num_of_fvvmafunct6": { "function": { "number": 0, "source": "num_of_fvvmafunct6 arg# = $[complete] match arg# {\n FVV_VMADD => 0,\n FVV_VNMADD => 1,\n FVV_VMSUB => 2,\n FVV_VNMSUB => 3,\n FVV_VMACC => 4,\n FVV_VNMACC => 5,\n FVV_VMSAC => 6,\n FVV_VNMSAC => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FVV_VMADD => 0,\n FVV_VNMADD => 1,\n FVV_VMSUB => 2,\n FVV_VNMSUB => 3,\n FVV_VMACC => 4,\n FVV_VNMACC => 5,\n FVV_VMSAC => 6,\n FVV_VNMSAC => 7\n}" } }, "num_of_fvvmfunct6": { "function": { "number": 0, "source": "num_of_fvvmfunct6 arg# = $[complete] match arg# {\n FVVM_VMFEQ => 0,\n FVVM_VMFLE => 1,\n FVVM_VMFLT => 2,\n FVVM_VMFNE => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FVVM_VMFEQ => 0,\n FVVM_VMFLE => 1,\n FVVM_VMFLT => 2,\n FVVM_VMFNE => 3\n}" } }, "num_of_fwffunct6": { "function": { "number": 0, "source": "num_of_fwffunct6 arg# = $[complete] match arg# {\n FWF_VADD => 0,\n FWF_VSUB => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FWF_VADD => 0,\n FWF_VSUB => 1\n}" } }, "num_of_fwvffunct6": { "function": { "number": 0, "source": "num_of_fwvffunct6 arg# = $[complete] match arg# {\n FWVF_VADD => 0,\n FWVF_VSUB => 1,\n FWVF_VMUL => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FWVF_VADD => 0,\n FWVF_VSUB => 1,\n FWVF_VMUL => 2\n}" } }, "num_of_fwvfmafunct6": { "function": { "number": 0, "source": "num_of_fwvfmafunct6 arg# = $[complete] match arg# {\n FWVF_VMACC => 0,\n FWVF_VNMACC => 1,\n FWVF_VMSAC => 2,\n FWVF_VNMSAC => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FWVF_VMACC => 0,\n FWVF_VNMACC => 1,\n FWVF_VMSAC => 2,\n FWVF_VNMSAC => 3\n}" } }, "num_of_fwvfunct6": { "function": { "number": 0, "source": "num_of_fwvfunct6 arg# = $[complete] match arg# {\n FWV_VADD => 0,\n FWV_VSUB => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FWV_VADD => 0,\n FWV_VSUB => 1\n}" } }, "num_of_fwvvfunct6": { "function": { "number": 0, "source": "num_of_fwvvfunct6 arg# = $[complete] match arg# {\n FWVV_VADD => 0,\n FWVV_VSUB => 1,\n FWVV_VMUL => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FWVV_VADD => 0,\n FWVV_VSUB => 1,\n FWVV_VMUL => 2\n}" } }, "num_of_fwvvmafunct6": { "function": { "number": 0, "source": "num_of_fwvvmafunct6 arg# = $[complete] match arg# {\n FWVV_VMACC => 0,\n FWVV_VNMACC => 1,\n FWVV_VMSAC => 2,\n FWVV_VNMSAC => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FWVV_VMACC => 0,\n FWVV_VNMACC => 1,\n FWVV_VMSAC => 2,\n FWVV_VNMSAC => 3\n}" } }, "num_of_iop": { "function": { "number": 0, "source": "num_of_iop arg# = $[complete] match arg# {\n RISCV_ADDI => 0,\n RISCV_SLTI => 1,\n RISCV_SLTIU => 2,\n RISCV_XORI => 3,\n RISCV_ORI => 4,\n RISCV_ANDI => 5\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_ADDI => 0,\n RISCV_SLTI => 1,\n RISCV_SLTIU => 2,\n RISCV_XORI => 3,\n RISCV_ORI => 4,\n RISCV_ANDI => 5\n}" } }, "num_of_maskfunct3": { "function": { "number": 0, "source": "num_of_maskfunct3 arg# = $[complete] match arg# {\n VV_VMERGE => 0,\n VI_VMERGE => 1,\n VX_VMERGE => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VV_VMERGE => 0,\n VI_VMERGE => 1,\n VX_VMERGE => 2\n}" } }, "num_of_mmfunct6": { "function": { "number": 0, "source": "num_of_mmfunct6 arg# = $[complete] match arg# {\n MM_VMAND => 0,\n MM_VMNAND => 1,\n MM_VMANDNOT => 2,\n MM_VMXOR => 3,\n MM_VMOR => 4,\n MM_VMNOR => 5,\n MM_VMORNOT => 6,\n MM_VMXNOR => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n MM_VMAND => 0,\n MM_VMNAND => 1,\n MM_VMANDNOT => 2,\n MM_VMXOR => 3,\n MM_VMOR => 4,\n MM_VMNOR => 5,\n MM_VMORNOT => 6,\n MM_VMXNOR => 7\n}" } }, "num_of_mvvfunct6": { "function": { "number": 0, "source": "num_of_mvvfunct6 arg# = $[complete] match arg# {\n MVV_VAADDU => 0,\n MVV_VAADD => 1,\n MVV_VASUBU => 2,\n MVV_VASUB => 3,\n MVV_VMUL => 4,\n MVV_VMULH => 5,\n MVV_VMULHU => 6,\n MVV_VMULHSU => 7,\n MVV_VDIVU => 8,\n MVV_VDIV => 9,\n MVV_VREMU => 10,\n MVV_VREM => 11\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n MVV_VAADDU => 0,\n MVV_VAADD => 1,\n MVV_VASUBU => 2,\n MVV_VASUB => 3,\n MVV_VMUL => 4,\n MVV_VMULH => 5,\n MVV_VMULHU => 6,\n MVV_VMULHSU => 7,\n MVV_VDIVU => 8,\n MVV_VDIV => 9,\n MVV_VREMU => 10,\n MVV_VREM => 11\n}" } }, "num_of_mvvmafunct6": { "function": { "number": 0, "source": "num_of_mvvmafunct6 arg# = $[complete] match arg# {\n MVV_VMACC => 0,\n MVV_VNMSAC => 1,\n MVV_VMADD => 2,\n MVV_VNMSUB => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n MVV_VMACC => 0,\n MVV_VNMSAC => 1,\n MVV_VMADD => 2,\n MVV_VNMSUB => 3\n}" } }, "num_of_mvxfunct6": { "function": { "number": 0, "source": "num_of_mvxfunct6 arg# = $[complete] match arg# {\n MVX_VAADDU => 0,\n MVX_VAADD => 1,\n MVX_VASUBU => 2,\n MVX_VASUB => 3,\n MVX_VSLIDE1UP => 4,\n MVX_VSLIDE1DOWN => 5,\n MVX_VMUL => 6,\n MVX_VMULH => 7,\n MVX_VMULHU => 8,\n MVX_VMULHSU => 9,\n MVX_VDIVU => 10,\n MVX_VDIV => 11,\n MVX_VREMU => 12,\n MVX_VREM => 13\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n MVX_VAADDU => 0,\n MVX_VAADD => 1,\n MVX_VASUBU => 2,\n MVX_VASUB => 3,\n MVX_VSLIDE1UP => 4,\n MVX_VSLIDE1DOWN => 5,\n MVX_VMUL => 6,\n MVX_VMULH => 7,\n MVX_VMULHU => 8,\n MVX_VMULHSU => 9,\n MVX_VDIVU => 10,\n MVX_VDIV => 11,\n MVX_VREMU => 12,\n MVX_VREM => 13\n}" } }, "num_of_mvxmafunct6": { "function": { "number": 0, "source": "num_of_mvxmafunct6 arg# = $[complete] match arg# {\n MVX_VMACC => 0,\n MVX_VNMSAC => 1,\n MVX_VMADD => 2,\n MVX_VNMSUB => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n MVX_VMACC => 0,\n MVX_VNMSAC => 1,\n MVX_VMADD => 2,\n MVX_VNMSUB => 3\n}" } }, "num_of_nifunct6": { "function": { "number": 0, "source": "num_of_nifunct6 arg# = $[complete] match arg# {\n NI_VNCLIPU => 0,\n NI_VNCLIP => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n NI_VNCLIPU => 0,\n NI_VNCLIP => 1\n}" } }, "num_of_nisfunct6": { "function": { "number": 0, "source": "num_of_nisfunct6 arg# = $[complete] match arg# {\n NIS_VNSRL => 0,\n NIS_VNSRA => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n NIS_VNSRL => 0,\n NIS_VNSRA => 1\n}" } }, "num_of_nvfunct6": { "function": { "number": 0, "source": "num_of_nvfunct6 arg# = $[complete] match arg# {\n NV_VNCLIPU => 0,\n NV_VNCLIP => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n NV_VNCLIPU => 0,\n NV_VNCLIP => 1\n}" } }, "num_of_nvsfunct6": { "function": { "number": 0, "source": "num_of_nvsfunct6 arg# = $[complete] match arg# {\n NVS_VNSRL => 0,\n NVS_VNSRA => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n NVS_VNSRL => 0,\n NVS_VNSRA => 1\n}" } }, "num_of_nxfunct6": { "function": { "number": 0, "source": "num_of_nxfunct6 arg# = $[complete] match arg# {\n NX_VNCLIPU => 0,\n NX_VNCLIP => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n NX_VNCLIPU => 0,\n NX_VNCLIP => 1\n}" } }, "num_of_nxsfunct6": { "function": { "number": 0, "source": "num_of_nxsfunct6 arg# = $[complete] match arg# {\n NXS_VNSRL => 0,\n NXS_VNSRA => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n NXS_VNSRL => 0,\n NXS_VNSRA => 1\n}" } }, "num_of_pmpAddrMatch": { "function": { "number": 0, "source": "num_of_pmpAddrMatch arg# = $[complete] match arg# {\n PMP_NoMatch => 0,\n PMP_PartialMatch => 1,\n PMP_Match => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n PMP_NoMatch => 0,\n PMP_PartialMatch => 1,\n PMP_Match => 2\n}" } }, "num_of_pmpMatch": { "function": { "number": 0, "source": "num_of_pmpMatch arg# = $[complete] match arg# {\n PMP_Success => 0,\n PMP_Continue => 1,\n PMP_Fail => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n PMP_Success => 0,\n PMP_Continue => 1,\n PMP_Fail => 2\n}" } }, "num_of_read_kind": { "function": { "number": 0, "source": "num_of_read_kind arg# = $[complete] match arg# {\n Read_plain => 0,\n Read_reserve => 1,\n Read_acquire => 2,\n Read_exclusive => 3,\n Read_exclusive_acquire => 4,\n Read_stream => 5,\n Read_ifetch => 6,\n Read_RISCV_acquire => 7,\n Read_RISCV_strong_acquire => 8,\n Read_RISCV_reserved => 9,\n Read_RISCV_reserved_acquire => 10,\n Read_RISCV_reserved_strong_acquire => 11,\n Read_X86_locked => 12\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n Read_plain => 0,\n Read_reserve => 1,\n Read_acquire => 2,\n Read_exclusive => 3,\n Read_exclusive_acquire => 4,\n Read_stream => 5,\n Read_ifetch => 6,\n Read_RISCV_acquire => 7,\n Read_RISCV_strong_acquire => 8,\n Read_RISCV_reserved => 9,\n Read_RISCV_reserved_acquire => 10,\n Read_RISCV_reserved_strong_acquire => 11,\n Read_X86_locked => 12\n}" } }, "num_of_rfvvfunct6": { "function": { "number": 0, "source": "num_of_rfvvfunct6 arg# = $[complete] match arg# {\n FVV_VFREDOSUM => 0,\n FVV_VFREDUSUM => 1,\n FVV_VFREDMAX => 2,\n FVV_VFREDMIN => 3,\n FVV_VFWREDOSUM => 4,\n FVV_VFWREDUSUM => 5\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FVV_VFREDOSUM => 0,\n FVV_VFREDUSUM => 1,\n FVV_VFREDMAX => 2,\n FVV_VFREDMIN => 3,\n FVV_VFWREDOSUM => 4,\n FVV_VFWREDUSUM => 5\n}" } }, "num_of_rivvfunct6": { "function": { "number": 0, "source": "num_of_rivvfunct6 arg# = $[complete] match arg# {\n IVV_VWREDSUMU => 0,\n IVV_VWREDSUM => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n IVV_VWREDSUMU => 0,\n IVV_VWREDSUM => 1\n}" } }, "num_of_rmvvfunct6": { "function": { "number": 0, "source": "num_of_rmvvfunct6 arg# = $[complete] match arg# {\n MVV_VREDSUM => 0,\n MVV_VREDAND => 1,\n MVV_VREDOR => 2,\n MVV_VREDXOR => 3,\n MVV_VREDMINU => 4,\n MVV_VREDMIN => 5,\n MVV_VREDMAXU => 6,\n MVV_VREDMAX => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n MVV_VREDSUM => 0,\n MVV_VREDAND => 1,\n MVV_VREDOR => 2,\n MVV_VREDXOR => 3,\n MVV_VREDMINU => 4,\n MVV_VREDMIN => 5,\n MVV_VREDMAXU => 6,\n MVV_VREDMAX => 7\n}" } }, "num_of_rop": { "function": { "number": 0, "source": "num_of_rop arg# = $[complete] match arg# {\n RISCV_ADD => 0,\n RISCV_SUB => 1,\n RISCV_SLL => 2,\n RISCV_SLT => 3,\n RISCV_SLTU => 4,\n RISCV_XOR => 5,\n RISCV_SRL => 6,\n RISCV_SRA => 7,\n RISCV_OR => 8,\n RISCV_AND => 9\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_ADD => 0,\n RISCV_SUB => 1,\n RISCV_SLL => 2,\n RISCV_SLT => 3,\n RISCV_SLTU => 4,\n RISCV_XOR => 5,\n RISCV_SRL => 6,\n RISCV_SRA => 7,\n RISCV_OR => 8,\n RISCV_AND => 9\n}" } }, "num_of_ropw": { "function": { "number": 0, "source": "num_of_ropw arg# = $[complete] match arg# {\n RISCV_ADDW => 0,\n RISCV_SUBW => 1,\n RISCV_SLLW => 2,\n RISCV_SRLW => 3,\n RISCV_SRAW => 4\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_ADDW => 0,\n RISCV_SUBW => 1,\n RISCV_SLLW => 2,\n RISCV_SRLW => 3,\n RISCV_SRAW => 4\n}" } }, "num_of_rounding_mode": { "function": { "number": 0, "source": "num_of_rounding_mode arg# = $[complete] match arg# {\n RM_RNE => 0,\n RM_RTZ => 1,\n RM_RDN => 2,\n RM_RUP => 3,\n RM_RMM => 4,\n RM_DYN => 5\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RM_RNE => 0,\n RM_RTZ => 1,\n RM_RDN => 2,\n RM_RUP => 3,\n RM_RMM => 4,\n RM_DYN => 5\n}" } }, "num_of_seed_opst": { "function": { "number": 0, "source": "num_of_seed_opst arg# = $[complete] match arg# {\n BIST => 0,\n ES16 => 1,\n WAIT => 2,\n DEAD => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n BIST => 0,\n ES16 => 1,\n WAIT => 2,\n DEAD => 3\n}" } }, "num_of_sop": { "function": { "number": 0, "source": "num_of_sop arg# = $[complete] match arg# {\n RISCV_SLLI => 0,\n RISCV_SRLI => 1,\n RISCV_SRAI => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_SLLI => 0,\n RISCV_SRLI => 1,\n RISCV_SRAI => 2\n}" } }, "num_of_sopw": { "function": { "number": 0, "source": "num_of_sopw arg# = $[complete] match arg# {\n RISCV_SLLIW => 0,\n RISCV_SRLIW => 1,\n RISCV_SRAIW => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_SLLIW => 0,\n RISCV_SRLIW => 1,\n RISCV_SRAIW => 2\n}" } }, "num_of_trans_kind": { "function": { "number": 0, "source": "num_of_trans_kind arg# = $[complete] match arg# {\n Transaction_start => 0,\n Transaction_commit => 1,\n Transaction_abort => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n Transaction_start => 0,\n Transaction_commit => 1,\n Transaction_abort => 2\n}" } }, "num_of_uop": { "function": { "number": 0, "source": "num_of_uop arg# = $[complete] match arg# {\n RISCV_LUI => 0,\n RISCV_AUIPC => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_LUI => 0,\n RISCV_AUIPC => 1\n}" } }, "num_of_vext2funct6": { "function": { "number": 0, "source": "num_of_vext2funct6 arg# = $[complete] match arg# {\n VEXT2_ZVF2 => 0,\n VEXT2_SVF2 => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VEXT2_ZVF2 => 0,\n VEXT2_SVF2 => 1\n}" } }, "num_of_vext4funct6": { "function": { "number": 0, "source": "num_of_vext4funct6 arg# = $[complete] match arg# {\n VEXT4_ZVF4 => 0,\n VEXT4_SVF4 => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VEXT4_ZVF4 => 0,\n VEXT4_SVF4 => 1\n}" } }, "num_of_vext8funct6": { "function": { "number": 0, "source": "num_of_vext8funct6 arg# = $[complete] match arg# {\n VEXT8_ZVF8 => 0,\n VEXT8_SVF8 => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VEXT8_ZVF8 => 0,\n VEXT8_SVF8 => 1\n}" } }, "num_of_vfnunary0": { "function": { "number": 0, "source": "num_of_vfnunary0 arg# = $[complete] match arg# {\n FNV_CVT_XU_F => 0,\n FNV_CVT_X_F => 1,\n FNV_CVT_F_XU => 2,\n FNV_CVT_F_X => 3,\n FNV_CVT_F_F => 4,\n FNV_CVT_ROD_F_F => 5,\n FNV_CVT_RTZ_XU_F => 6,\n FNV_CVT_RTZ_X_F => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FNV_CVT_XU_F => 0,\n FNV_CVT_X_F => 1,\n FNV_CVT_F_XU => 2,\n FNV_CVT_F_X => 3,\n FNV_CVT_F_F => 4,\n FNV_CVT_ROD_F_F => 5,\n FNV_CVT_RTZ_XU_F => 6,\n FNV_CVT_RTZ_X_F => 7\n}" } }, "num_of_vfunary0": { "function": { "number": 0, "source": "num_of_vfunary0 arg# = $[complete] match arg# {\n FV_CVT_XU_F => 0,\n FV_CVT_X_F => 1,\n FV_CVT_F_XU => 2,\n FV_CVT_F_X => 3,\n FV_CVT_RTZ_XU_F => 4,\n FV_CVT_RTZ_X_F => 5\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FV_CVT_XU_F => 0,\n FV_CVT_X_F => 1,\n FV_CVT_F_XU => 2,\n FV_CVT_F_X => 3,\n FV_CVT_RTZ_XU_F => 4,\n FV_CVT_RTZ_X_F => 5\n}" } }, "num_of_vfunary1": { "function": { "number": 0, "source": "num_of_vfunary1 arg# = $[complete] match arg# {\n FVV_VSQRT => 0,\n FVV_VRSQRT7 => 1,\n FVV_VREC7 => 2,\n FVV_VCLASS => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FVV_VSQRT => 0,\n FVV_VRSQRT7 => 1,\n FVV_VREC7 => 2,\n FVV_VCLASS => 3\n}" } }, "num_of_vfwunary0": { "function": { "number": 0, "source": "num_of_vfwunary0 arg# = $[complete] match arg# {\n FWV_CVT_XU_F => 0,\n FWV_CVT_X_F => 1,\n FWV_CVT_F_XU => 2,\n FWV_CVT_F_X => 3,\n FWV_CVT_F_F => 4,\n FWV_CVT_RTZ_XU_F => 5,\n FWV_CVT_RTZ_X_F => 6\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n FWV_CVT_XU_F => 0,\n FWV_CVT_X_F => 1,\n FWV_CVT_F_XU => 2,\n FWV_CVT_F_X => 3,\n FWV_CVT_F_F => 4,\n FWV_CVT_RTZ_XU_F => 5,\n FWV_CVT_RTZ_X_F => 6\n}" } }, "num_of_vicmpfunct6": { "function": { "number": 0, "source": "num_of_vicmpfunct6 arg# = $[complete] match arg# {\n VICMP_VMSEQ => 0,\n VICMP_VMSNE => 1,\n VICMP_VMSLEU => 2,\n VICMP_VMSLE => 3,\n VICMP_VMSGTU => 4,\n VICMP_VMSGT => 5\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VICMP_VMSEQ => 0,\n VICMP_VMSNE => 1,\n VICMP_VMSLEU => 2,\n VICMP_VMSLE => 3,\n VICMP_VMSGTU => 4,\n VICMP_VMSGT => 5\n}" } }, "num_of_vifunct6": { "function": { "number": 0, "source": "num_of_vifunct6 arg# = $[complete] match arg# {\n VI_VADD => 0,\n VI_VRSUB => 1,\n VI_VAND => 2,\n VI_VOR => 3,\n VI_VXOR => 4,\n VI_VSADDU => 5,\n VI_VSADD => 6,\n VI_VSLL => 7,\n VI_VSRL => 8,\n VI_VSRA => 9,\n VI_VSSRL => 10,\n VI_VSSRA => 11\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VI_VADD => 0,\n VI_VRSUB => 1,\n VI_VAND => 2,\n VI_VOR => 3,\n VI_VXOR => 4,\n VI_VSADDU => 5,\n VI_VSADD => 6,\n VI_VSLL => 7,\n VI_VSRL => 8,\n VI_VSRA => 9,\n VI_VSSRL => 10,\n VI_VSSRA => 11\n}" } }, "num_of_vimcfunct6": { "function": { "number": 0, "source": "num_of_vimcfunct6 arg# = $[complete] match arg# {VIMC_VMADC => 0}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {VIMC_VMADC => 0}" } }, "num_of_vimfunct6": { "function": { "number": 0, "source": "num_of_vimfunct6 arg# = $[complete] match arg# {VIM_VMADC => 0}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {VIM_VMADC => 0}" } }, "num_of_vimsfunct6": { "function": { "number": 0, "source": "num_of_vimsfunct6 arg# = $[complete] match arg# {VIMS_VADC => 0}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {VIMS_VADC => 0}" } }, "num_of_visgfunct6": { "function": { "number": 0, "source": "num_of_visgfunct6 arg# = $[complete] match arg# {\n VI_VSLIDEUP => 0,\n VI_VSLIDEDOWN => 1,\n VI_VRGATHER => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VI_VSLIDEUP => 0,\n VI_VSLIDEDOWN => 1,\n VI_VRGATHER => 2\n}" } }, "num_of_vlewidth": { "function": { "number": 0, "source": "num_of_vlewidth arg# = $[complete] match arg# {\n VLE8 => 0,\n VLE16 => 1,\n VLE32 => 2,\n VLE64 => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VLE8 => 0,\n VLE16 => 1,\n VLE32 => 2,\n VLE64 => 3\n}" } }, "num_of_vmlsop": { "function": { "number": 0, "source": "num_of_vmlsop arg# = $[complete] match arg# {\n VLM => 0,\n VSM => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VLM => 0,\n VSM => 1\n}" } }, "num_of_vsetop": { "function": { "number": 0, "source": "num_of_vsetop arg# = $[complete] match arg# {\n VSETVLI => 0,\n VSETVL => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VSETVLI => 0,\n VSETVL => 1\n}" } }, "num_of_vvcmpfunct6": { "function": { "number": 0, "source": "num_of_vvcmpfunct6 arg# = $[complete] match arg# {\n VVCMP_VMSEQ => 0,\n VVCMP_VMSNE => 1,\n VVCMP_VMSLTU => 2,\n VVCMP_VMSLT => 3,\n VVCMP_VMSLEU => 4,\n VVCMP_VMSLE => 5\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VVCMP_VMSEQ => 0,\n VVCMP_VMSNE => 1,\n VVCMP_VMSLTU => 2,\n VVCMP_VMSLT => 3,\n VVCMP_VMSLEU => 4,\n VVCMP_VMSLE => 5\n}" } }, "num_of_vvfunct6": { "function": { "number": 0, "source": "num_of_vvfunct6 arg# = $[complete] match arg# {\n VV_VADD => 0,\n VV_VSUB => 1,\n VV_VMINU => 2,\n VV_VMIN => 3,\n VV_VMAXU => 4,\n VV_VMAX => 5,\n VV_VAND => 6,\n VV_VOR => 7,\n VV_VXOR => 8,\n VV_VRGATHER => 9,\n VV_VRGATHEREI16 => 10,\n VV_VSADDU => 11,\n VV_VSADD => 12,\n VV_VSSUBU => 13,\n VV_VSSUB => 14,\n VV_VSLL => 15,\n VV_VSMUL => 16,\n VV_VSRL => 17,\n VV_VSRA => 18,\n VV_VSSRL => 19,\n VV_VSSRA => 20\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VV_VADD => 0,\n VV_VSUB => 1,\n VV_VMINU => 2,\n VV_VMIN => 3,\n VV_VMAXU => 4,\n VV_VMAX => 5,\n VV_VAND => 6,\n VV_VOR => 7,\n VV_VXOR => 8,\n VV_VRGATHER => 9,\n VV_VRGATHEREI16 => 10,\n VV_VSADDU => 11,\n VV_VSADD => 12,\n VV_VSSUBU => 13,\n VV_VSSUB => 14,\n VV_VSLL => 15,\n VV_VSMUL => 16,\n VV_VSRL => 17,\n VV_VSRA => 18,\n VV_VSSRL => 19,\n VV_VSSRA => 20\n}" } }, "num_of_vvmcfunct6": { "function": { "number": 0, "source": "num_of_vvmcfunct6 arg# = $[complete] match arg# {\n VVMC_VMADC => 0,\n VVMC_VMSBC => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VVMC_VMADC => 0,\n VVMC_VMSBC => 1\n}" } }, "num_of_vvmfunct6": { "function": { "number": 0, "source": "num_of_vvmfunct6 arg# = $[complete] match arg# {\n VVM_VMADC => 0,\n VVM_VMSBC => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VVM_VMADC => 0,\n VVM_VMSBC => 1\n}" } }, "num_of_vvmsfunct6": { "function": { "number": 0, "source": "num_of_vvmsfunct6 arg# = $[complete] match arg# {\n VVMS_VADC => 0,\n VVMS_VSBC => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VVMS_VADC => 0,\n VVMS_VSBC => 1\n}" } }, "num_of_vxcmpfunct6": { "function": { "number": 0, "source": "num_of_vxcmpfunct6 arg# = $[complete] match arg# {\n VXCMP_VMSEQ => 0,\n VXCMP_VMSNE => 1,\n VXCMP_VMSLTU => 2,\n VXCMP_VMSLT => 3,\n VXCMP_VMSLEU => 4,\n VXCMP_VMSLE => 5,\n VXCMP_VMSGTU => 6,\n VXCMP_VMSGT => 7\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VXCMP_VMSEQ => 0,\n VXCMP_VMSNE => 1,\n VXCMP_VMSLTU => 2,\n VXCMP_VMSLT => 3,\n VXCMP_VMSLEU => 4,\n VXCMP_VMSLE => 5,\n VXCMP_VMSGTU => 6,\n VXCMP_VMSGT => 7\n}" } }, "num_of_vxfunct6": { "function": { "number": 0, "source": "num_of_vxfunct6 arg# = $[complete] match arg# {\n VX_VADD => 0,\n VX_VSUB => 1,\n VX_VRSUB => 2,\n VX_VMINU => 3,\n VX_VMIN => 4,\n VX_VMAXU => 5,\n VX_VMAX => 6,\n VX_VAND => 7,\n VX_VOR => 8,\n VX_VXOR => 9,\n VX_VSADDU => 10,\n VX_VSADD => 11,\n VX_VSSUBU => 12,\n VX_VSSUB => 13,\n VX_VSLL => 14,\n VX_VSMUL => 15,\n VX_VSRL => 16,\n VX_VSRA => 17,\n VX_VSSRL => 18,\n VX_VSSRA => 19\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VX_VADD => 0,\n VX_VSUB => 1,\n VX_VRSUB => 2,\n VX_VMINU => 3,\n VX_VMIN => 4,\n VX_VMAXU => 5,\n VX_VMAX => 6,\n VX_VAND => 7,\n VX_VOR => 8,\n VX_VXOR => 9,\n VX_VSADDU => 10,\n VX_VSADD => 11,\n VX_VSSUBU => 12,\n VX_VSSUB => 13,\n VX_VSLL => 14,\n VX_VSMUL => 15,\n VX_VSRL => 16,\n VX_VSRA => 17,\n VX_VSSRL => 18,\n VX_VSSRA => 19\n}" } }, "num_of_vxmcfunct6": { "function": { "number": 0, "source": "num_of_vxmcfunct6 arg# = $[complete] match arg# {\n VXMC_VMADC => 0,\n VXMC_VMSBC => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VXMC_VMADC => 0,\n VXMC_VMSBC => 1\n}" } }, "num_of_vxmfunct6": { "function": { "number": 0, "source": "num_of_vxmfunct6 arg# = $[complete] match arg# {\n VXM_VMADC => 0,\n VXM_VMSBC => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VXM_VMADC => 0,\n VXM_VMSBC => 1\n}" } }, "num_of_vxmsfunct6": { "function": { "number": 0, "source": "num_of_vxmsfunct6 arg# = $[complete] match arg# {\n VXMS_VADC => 0,\n VXMS_VSBC => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VXMS_VADC => 0,\n VXMS_VSBC => 1\n}" } }, "num_of_vxsgfunct6": { "function": { "number": 0, "source": "num_of_vxsgfunct6 arg# = $[complete] match arg# {\n VX_VSLIDEUP => 0,\n VX_VSLIDEDOWN => 1,\n VX_VRGATHER => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n VX_VSLIDEUP => 0,\n VX_VSLIDEDOWN => 1,\n VX_VRGATHER => 2\n}" } }, "num_of_wmvvfunct6": { "function": { "number": 0, "source": "num_of_wmvvfunct6 arg# = $[complete] match arg# {\n WMVV_VWMACCU => 0,\n WMVV_VWMACC => 1,\n WMVV_VWMACCSU => 2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n WMVV_VWMACCU => 0,\n WMVV_VWMACC => 1,\n WMVV_VWMACCSU => 2\n}" } }, "num_of_wmvxfunct6": { "function": { "number": 0, "source": "num_of_wmvxfunct6 arg# = $[complete] match arg# {\n WMVX_VWMACCU => 0,\n WMVX_VWMACC => 1,\n WMVX_VWMACCUS => 2,\n WMVX_VWMACCSU => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n WMVX_VWMACCU => 0,\n WMVX_VWMACC => 1,\n WMVX_VWMACCUS => 2,\n WMVX_VWMACCSU => 3\n}" } }, "num_of_word_width": { "function": { "number": 0, "source": "num_of_word_width arg# = $[complete] match arg# {\n BYTE => 0,\n HALF => 1,\n WORD => 2,\n DOUBLE => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n BYTE => 0,\n HALF => 1,\n WORD => 2,\n DOUBLE => 3\n}" } }, "num_of_write_kind": { "function": { "number": 0, "source": "num_of_write_kind arg# = $[complete] match arg# {\n Write_plain => 0,\n Write_conditional => 1,\n Write_release => 2,\n Write_exclusive => 3,\n Write_exclusive_release => 4,\n Write_RISCV_release => 5,\n Write_RISCV_strong_release => 6,\n Write_RISCV_conditional => 7,\n Write_RISCV_conditional_release => 8,\n Write_RISCV_conditional_strong_release => 9,\n Write_X86_locked => 10\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n Write_plain => 0,\n Write_conditional => 1,\n Write_release => 2,\n Write_exclusive => 3,\n Write_exclusive_release => 4,\n Write_RISCV_release => 5,\n Write_RISCV_strong_release => 6,\n Write_RISCV_conditional => 7,\n Write_RISCV_conditional_release => 8,\n Write_RISCV_conditional_strong_release => 9,\n Write_X86_locked => 10\n}" } }, "num_of_wvfunct6": { "function": { "number": 0, "source": "num_of_wvfunct6 arg# = $[complete] match arg# {\n WV_VADD => 0,\n WV_VSUB => 1,\n WV_VADDU => 2,\n WV_VSUBU => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n WV_VADD => 0,\n WV_VSUB => 1,\n WV_VADDU => 2,\n WV_VSUBU => 3\n}" } }, "num_of_wvvfunct6": { "function": { "number": 0, "source": "num_of_wvvfunct6 arg# = $[complete] match arg# {\n WVV_VADD => 0,\n WVV_VSUB => 1,\n WVV_VADDU => 2,\n WVV_VSUBU => 3,\n WVV_VWMUL => 4,\n WVV_VWMULU => 5,\n WVV_VWMULSU => 6\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n WVV_VADD => 0,\n WVV_VSUB => 1,\n WVV_VADDU => 2,\n WVV_VSUBU => 3,\n WVV_VWMUL => 4,\n WVV_VWMULU => 5,\n WVV_VWMULSU => 6\n}" } }, "num_of_wvxfunct6": { "function": { "number": 0, "source": "num_of_wvxfunct6 arg# = $[complete] match arg# {\n WVX_VADD => 0,\n WVX_VSUB => 1,\n WVX_VADDU => 2,\n WVX_VSUBU => 3,\n WVX_VWMUL => 4,\n WVX_VWMULU => 5,\n WVX_VWMULSU => 6\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n WVX_VADD => 0,\n WVX_VSUB => 1,\n WVX_VADDU => 2,\n WVX_VSUBU => 3,\n WVX_VWMUL => 4,\n WVX_VWMULU => 5,\n WVX_VWMULSU => 6\n}" } }, "num_of_wxfunct6": { "function": { "number": 0, "source": "num_of_wxfunct6 arg# = $[complete] match arg# {\n WX_VADD => 0,\n WX_VSUB => 1,\n WX_VADDU => 2,\n WX_VSUBU => 3\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n WX_VADD => 0,\n WX_VSUB => 1,\n WX_VADDU => 2,\n WX_VSUBU => 3\n}" } }, "num_of_zicondop": { "function": { "number": 0, "source": "num_of_zicondop arg# = $[complete] match arg# {\n RISCV_CZERO_EQZ => 0,\n RISCV_CZERO_NEZ => 1\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n RISCV_CZERO_EQZ => 0,\n RISCV_CZERO_NEZ => 1\n}" } }, "nvFlag": { "function": { "number": 0, "source": "function nvFlag() -> bits(5) = 0b_10000", "pattern": { "type": "literal", "value": "()" }, "body": "0b_10000" } }, "nvfunct6_of_num": { "function": { "number": 0, "source": "nvfunct6_of_num arg# = $[complete] match arg# {\n 0 => NV_VNCLIPU,\n _ => NV_VNCLIP\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => NV_VNCLIPU,\n _ => NV_VNCLIP\n}" } }, "nvsfunct6_of_num": { "function": { "number": 0, "source": "nvsfunct6_of_num arg# = $[complete] match arg# {\n 0 => NVS_VNSRL,\n _ => NVS_VNSRA\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => NVS_VNSRL,\n _ => NVS_VNSRA\n}" } }, "nxFlag": { "function": { "number": 0, "source": "function nxFlag() -> bits(5) = 0b_00001", "pattern": { "type": "literal", "value": "()" }, "body": "0b_00001" } }, "nxfunct6_of_num": { "function": { "number": 0, "source": "nxfunct6_of_num arg# = $[complete] match arg# {\n 0 => NX_VNCLIPU,\n _ => NX_VNCLIP\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => NX_VNCLIPU,\n _ => NX_VNCLIP\n}" } }, "nxsfunct6_of_num": { "function": { "number": 0, "source": "nxsfunct6_of_num arg# = $[complete] match arg# {\n 0 => NXS_VNSRL,\n _ => NXS_VNSRA\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => NXS_VNSRL,\n _ => NXS_VNSRA\n}" } }, "ofFlag": { "function": { "number": 0, "source": "function ofFlag() -> bits(5) = 0b_00100", "pattern": { "type": "literal", "value": "()" }, "body": "0b_00100" } }, "offset_of_va": { "function": { "number": 0, "source": "function offset_of_va(va : bits(64)) -> bits(PAGESIZE_BITS) = va[pagesize_bits - 1 .. 0]", "pattern": { "type": "id", "id": "va" }, "body": "va[pagesize_bits - 1 .. 0]" } }, "ones": { "function": { "number": 0, "source": "function ones (n) = sail_ones (n)", "pattern": { "type": "id", "id": "n" }, "body": "sail_ones (n)" }, "links": [ { "type": "function", "id": "sail_ones", "file": "model/prelude.sail", "loc": [ 4523, 4532 ] } ] }, "opt_spc_backwards": { "function": { "number": 0, "source": "function opt_spc_backwards _ = ()", "pattern": { "type": "wildcard" }, "body": "()" } }, "opt_spc_backwards_matches": { "function": { "number": 0, "source": "function opt_spc_backwards_matches s = n_leading_spaces(s) == string_length(s)", "pattern": { "type": "id", "id": "s" }, "body": "n_leading_spaces(s) == string_length(s)" }, "links": [ { "type": "function", "id": "string_length", "file": "model/mapping.sail", "loc": [ 6726, 6739 ] }, { "type": "function", "id": "n_leading_spaces", "file": "model/mapping.sail", "loc": [ 6703, 6719 ] } ] }, "opt_spc_forwards": { "function": { "number": 0, "source": "function opt_spc_forwards() = \"\"", "pattern": { "type": "literal", "value": "()" }, "body": "\"\"" } }, "opt_spc_forwards_matches": { "function": { "number": 0, "source": "function opt_spc_forwards_matches() = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "pc_alignment_mask": { "function": { "number": 0, "source": "function pc_alignment_mask() -> xlenbits =\n ~(zero_extend(if misa[C] == 0b1 then 0b00 else 0b10))", "pattern": { "type": "literal", "value": "()" }, "body": "~(zero_extend(if misa[C] == 0b1 then 0b00 else 0b10))" }, "links": [ { "type": "function", "id": "not_vec", "file": "model/prelude.sail", "loc": [ 997, 1004 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 14555, 14566 ] }, { "type": "register", "id": "misa", "file": "model/riscv_sys_regs.sail", "loc": [ 14570, 14574 ] } ] }, "phys_mem_read": { "function": { "number": 0, "source": "function phys_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), paddr : xlenbits, width : int('n), aq : bool, rl: bool, res : bool, meta : bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) = {\n let result = (match read_kind_of_flags(aq, rl, res) {\n Some(rk) => Some(read_ram(rk, paddr, width, meta)),\n None() => None()\n }) : option((bits(8 * 'n), mem_meta));\n match (t, result) {\n (Execute(), None()) => MemException(E_Fetch_Access_Fault()),\n (Read(Data), None()) => MemException(E_Load_Access_Fault()),\n (_, None()) => MemException(E_SAMO_Access_Fault()),\n (_, Some(v, m)) => { if get_config_print_mem()\n then print_mem(\"mem[\" ^ to_str(t) ^ \",\" ^ BitStr(paddr) ^ \"] -> \" ^ BitStr(v));\n MemValue(v, m) }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "t" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "res" }, { "type": "id", "id": "meta" } ] }, "body": " let result = (match read_kind_of_flags(aq, rl, res) {\n Some(rk) => Some(read_ram(rk, paddr, width, meta)),\n None() => None()\n }) : option((bits(8 * 'n), mem_meta));\n match (t, result) {\n (Execute(), None()) => MemException(E_Fetch_Access_Fault()),\n (Read(Data), None()) => MemException(E_Load_Access_Fault()),\n (_, None()) => MemException(E_SAMO_Access_Fault()),\n (_, Some(v, m)) => { if get_config_print_mem()\n then print_mem(\"mem[\" ^ to_str(t) ^ \",\" ^ BitStr(paddr) ^ \"] -> \" ^ BitStr(v));\n MemValue(v, m) }\n }" }, "links": [ { "type": "function", "id": "read_kind_of_flags", "file": "model/riscv_mem.sail", "loc": [ 2686, 2704 ] }, { "type": "function", "id": "None", "file": "model/riscv_mem.sail", "loc": [ 2792, 2796 ] }, { "type": "function", "id": "Some", "file": "model/riscv_mem.sail", "loc": [ 2736, 2740 ] }, { "type": "function", "id": "read_ram", "file": "model/riscv_mem.sail", "loc": [ 2741, 2749 ] }, { "type": "function", "id": "MemValue", "file": "model/riscv_mem.sail", "loc": [ 3256, 3264 ] }, { "type": "function", "id": "get_config_print_mem", "file": "model/riscv_mem.sail", "loc": [ 3093, 3113 ] }, { "type": "function", "id": "print_mem", "file": "model/riscv_mem.sail", "loc": [ 3151, 3160 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "accessType_to_str", "file": "model/riscv_vmem_types.sail", "loc": [ 1051, 1068 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 3021, 3033 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_mem.sail", "loc": [ 3034, 3053 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 2956, 2968 ] }, { "type": "function", "id": "E_Load_Access_Fault", "file": "model/riscv_mem.sail", "loc": [ 2969, 2988 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 2890, 2902 ] }, { "type": "function", "id": "E_Fetch_Access_Fault", "file": "model/riscv_mem.sail", "loc": [ 2903, 2923 ] } ] }, "phys_mem_segments": { "function": { "number": 0, "source": "function phys_mem_segments() =\n (plat_rom_base (), plat_rom_size ()) ::\n (plat_ram_base (), plat_ram_size ()) ::\n [||]", "pattern": { "type": "literal", "value": "()" }, "body": "(plat_rom_base (), plat_rom_size ()) ::\n (plat_ram_base (), plat_ram_size ()) ::\n [||]" }, "links": [ { "type": "function", "id": "plat_rom_size", "file": "model/riscv_platform.sail", "loc": [ 3957, 3970 ] }, { "type": "function", "id": "plat_rom_base", "file": "model/riscv_platform.sail", "loc": [ 3939, 3952 ] }, { "type": "function", "id": "plat_ram_size", "file": "model/riscv_platform.sail", "loc": [ 3999, 4012 ] }, { "type": "function", "id": "plat_ram_base", "file": "model/riscv_platform.sail", "loc": [ 3981, 3994 ] } ] }, "phys_mem_write": { "function": { "number": 0, "source": "function phys_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk : write_kind, paddr : xlenbits, width : int('n), data : bits(8 * 'n), meta : mem_meta) -> MemoryOpResult(bool) = {\n let result = MemValue(write_ram(wk, paddr, width, data, meta));\n if get_config_print_mem()\n then print_mem(\"mem[\" ^ BitStr(paddr) ^ \"] <- \" ^ BitStr(data));\n result\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "wk" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "data" }, { "type": "id", "id": "meta" } ] }, "body": " let result = MemValue(write_ram(wk, paddr, width, data, meta));\n if get_config_print_mem()\n then print_mem(\"mem[\" ^ BitStr(paddr) ^ \"] <- \" ^ BitStr(data));\n result" }, "links": [ { "type": "function", "id": "MemValue", "file": "model/riscv_mem.sail", "loc": [ 10537, 10545 ] }, { "type": "function", "id": "write_ram", "file": "model/riscv_mem.sail", "loc": [ 10546, 10555 ] }, { "type": "function", "id": "get_config_print_mem", "file": "model/riscv_mem.sail", "loc": [ 10595, 10615 ] }, { "type": "function", "id": "print_mem", "file": "model/riscv_mem.sail", "loc": [ 10625, 10634 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "plat_htif_tohost": { "function": { "number": 0, "source": "function plat_htif_tohost () = to_bits(sizeof(xlen), elf_tohost ())", "pattern": { "type": "literal", "value": "()" }, "body": "to_bits(sizeof(xlen), elf_tohost ())" }, "links": [ { "type": "function", "id": "to_bits", "file": "model/riscv_platform.sail", "loc": [ 3790, 3797 ] }, { "type": "function", "id": "elf_tohost", "file": "model/riscv_platform.sail", "loc": [ 3812, 3822 ] } ] }, "platform_wfi": { "function": { "number": 0, "source": "function platform_wfi() -> unit = {\n cancel_reservation();\n /* speed execution by getting the timer to fire at the next instruction,\n * since we currently don't have any other devices raising interrupts.\n */\n if mtime <_u mtimecmp then {\n mtime = mtimecmp;\n mcycle = mtimecmp;\n }\n}", "pattern": { "type": "literal", "value": "()" }, "body": " cancel_reservation();\n /* speed execution by getting the timer to fire at the next instruction,\n * since we currently don't have any other devices raising interrupts.\n */\n if mtime <_u mtimecmp then {\n mtime = mtimecmp;\n mcycle = mtimecmp;\n }" }, "links": [ { "type": "function", "id": "(operator <_u)", "file": "model/riscv_platform.sail", "loc": [ 19605, 19608 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 19609, 19617 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 19599, 19604 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_platform.sail", "loc": [ 19652, 19658 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 19661, 19669 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 19629, 19634 ] }, { "type": "register", "id": "mtimecmp", "file": "model/riscv_platform.sail", "loc": [ 19638, 19646 ] }, { "type": "function", "id": "cancel_reservation", "file": "model/riscv_platform.sail", "loc": [ 19418, 19436 ] } ] }, "pmpAddrMatchType_of_bits": { "function": { "number": 0, "source": "function pmpAddrMatchType_of_bits(bs) = {\n match bs {\n 0b00 => OFF,\n 0b01 => TOR,\n 0b10 => NA4,\n 0b11 => NAPOT\n }\n}", "pattern": { "type": "id", "id": "bs" }, "body": " match bs {\n 0b00 => OFF,\n 0b01 => TOR,\n 0b10 => NA4,\n 0b11 => NAPOT\n }" } }, "pmpAddrMatchType_to_bits": { "function": { "number": 0, "source": "function pmpAddrMatchType_to_bits(bs) = {\n match bs {\n OFF => 0b00,\n TOR => 0b01,\n NA4 => 0b10,\n NAPOT => 0b11\n }\n}", "pattern": { "type": "id", "id": "bs" }, "body": " match bs {\n OFF => 0b00,\n TOR => 0b01,\n NA4 => 0b10,\n NAPOT => 0b11\n }" } }, "pmpAddrMatch_of_num": { "function": { "number": 0, "source": "pmpAddrMatch_of_num arg# = $[complete] match arg# {\n 0 => PMP_NoMatch,\n 1 => PMP_PartialMatch,\n _ => PMP_Match\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => PMP_NoMatch,\n 1 => PMP_PartialMatch,\n _ => PMP_Match\n}" } }, "pmpAddrRange": { "function": { "number": 0, "source": "function pmpAddrRange(cfg: Pmpcfg_ent, pmpaddr: xlenbits, prev_pmpaddr: xlenbits) -> pmp_addr_range = {\n match pmpAddrMatchType_of_bits(cfg[A]) {\n OFF => None(),\n TOR => { Some ((prev_pmpaddr << 2, pmpaddr << 2)) },\n NA4 => {\n // NA4 is not selectable when the PMP grain G >= 1. See pmpWriteCfg().\n assert(sys_pmp_grain() < 1, \"NA4 cannot be selected when PMP grain G >= 1.\");\n let lo = pmpaddr << 2;\n Some((lo, lo + 4))\n },\n NAPOT => {\n // Example pmpaddr: 0b00010101111\n // ^--- last 0 dictates region size & alignment\n let mask = pmpaddr ^ (pmpaddr + 1);\n // pmpaddr + 1: 0b00010110000\n // mask: 0b00000011111\n // ~mask: 0b11111100000\n let lo = pmpaddr & (~ (mask));\n // mask + 1: 0b00000100000\n let len = mask + 1;\n Some((lo << 2, (lo + len) << 2))\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "cfg" }, { "type": "id", "id": "pmpaddr" }, { "type": "id", "id": "prev_pmpaddr" } ] }, "body": " match pmpAddrMatchType_of_bits(cfg[A]) {\n OFF => None(),\n TOR => { Some ((prev_pmpaddr << 2, pmpaddr << 2)) },\n NA4 => {\n // NA4 is not selectable when the PMP grain G >= 1. See pmpWriteCfg().\n assert(sys_pmp_grain() < 1, \"NA4 cannot be selected when PMP grain G >= 1.\");\n let lo = pmpaddr << 2;\n Some((lo, lo + 4))\n },\n NAPOT => {\n // Example pmpaddr: 0b00010101111\n // ^--- last 0 dictates region size & alignment\n let mask = pmpaddr ^ (pmpaddr + 1);\n // pmpaddr + 1: 0b00010110000\n // mask: 0b00000011111\n // ~mask: 0b11111100000\n let lo = pmpaddr & (~ (mask));\n // mask + 1: 0b00000100000\n let len = mask + 1;\n Some((lo << 2, (lo + len) << 2))\n }\n }" }, "links": [ { "type": "function", "id": "pmpAddrMatchType_of_bits", "file": "model/riscv_pmp_control.sail", "loc": [ 915, 939 ] }, { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "not_vec", "file": "model/prelude.sail", "loc": [ 997, 1004 ] }, { "type": "function", "id": "Some", "file": "model/riscv_pmp_control.sail", "loc": [ 1810, 1814 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "Some", "file": "model/riscv_pmp_control.sail", "loc": [ 1277, 1281 ] }, { "type": "function", "id": "sys_pmp_grain", "file": "model/riscv_pmp_control.sail", "loc": [ 1153, 1166 ] }, { "type": "function", "id": "Some", "file": "model/riscv_pmp_control.sail", "loc": [ 986, 990 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "None", "file": "model/riscv_pmp_control.sail", "loc": [ 963, 967 ] } ] }, "pmpCheck": { "function": { "number": 0, "source": "function pmpCheck forall 'n, 'n > 0. (addr: xlenbits, width: int('n), acc: AccessType(ext_access_type), priv: Privilege)\n -> option(ExceptionType) = {\n let width : xlenbits = to_bits(sizeof(xlen), width);\n\n foreach (i from 0 to 63) {\n let prev_pmpaddr = (if i > 0 then pmpReadAddrReg(i - 1) else zeros());\n match pmpMatchEntry(addr, width, acc, priv, pmpcfg_n[i], pmpReadAddrReg(i), prev_pmpaddr) {\n PMP_Success => { return None(); },\n PMP_Fail => { return Some(accessToFault(acc)); },\n PMP_Continue => (),\n }\n };\n if priv == Machine then None() else Some(accessToFault(acc))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "acc" }, { "type": "id", "id": "priv" } ] }, "body": " let width : xlenbits = to_bits(sizeof(xlen), width);\n\n foreach (i from 0 to 63) {\n let prev_pmpaddr = (if i > 0 then pmpReadAddrReg(i - 1) else zeros());\n match pmpMatchEntry(addr, width, acc, priv, pmpcfg_n[i], pmpReadAddrReg(i), prev_pmpaddr) {\n PMP_Success => { return None(); },\n PMP_Fail => { return Some(accessToFault(acc)); },\n PMP_Continue => (),\n }\n };\n if priv == Machine then None() else Some(accessToFault(acc))" }, "links": [ { "type": "function", "id": "to_bits", "file": "model/riscv_pmp_control.sail", "loc": [ 4259, 4266 ] }, { "type": "function", "id": "None", "file": "model/riscv_pmp_control.sail", "loc": [ 4655, 4659 ] }, { "type": "function", "id": "Some", "file": "model/riscv_pmp_control.sail", "loc": [ 4667, 4671 ] }, { "type": "function", "id": "accessToFault", "file": "model/riscv_pmp_control.sail", "loc": [ 4672, 4685 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_pmp_control.sail", "loc": [ 4357, 4371 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "pmpMatchEntry", "file": "model/riscv_pmp_control.sail", "loc": [ 4404, 4417 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_pmp_control.sail", "loc": [ 4455, 4469 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_control.sail", "loc": [ 4442, 4450 ] }, { "type": "function", "id": "Some", "file": "model/riscv_pmp_control.sail", "loc": [ 4563, 4567 ] }, { "type": "function", "id": "accessToFault", "file": "model/riscv_pmp_control.sail", "loc": [ 4568, 4581 ] }, { "type": "function", "id": "None", "file": "model/riscv_pmp_control.sail", "loc": [ 4521, 4525 ] } ] }, "pmpCheckPerms": { "function": { "number": 0, "source": "function pmpCheckPerms(ent, acc, priv) = {\n match priv {\n Machine => if pmpLocked(ent)\n then pmpCheckRWX(ent, acc)\n else true,\n _ => pmpCheckRWX(ent, acc)\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "ent" }, { "type": "id", "id": "acc" }, { "type": "id", "id": "priv" } ] }, "body": " match priv {\n Machine => if pmpLocked(ent)\n then pmpCheckRWX(ent, acc)\n else true,\n _ => pmpCheckRWX(ent, acc)\n }" }, "links": [ { "type": "function", "id": "pmpCheckRWX", "file": "model/riscv_pmp_control.sail", "loc": [ 2489, 2500 ] }, { "type": "function", "id": "pmpLocked", "file": "model/riscv_pmp_control.sail", "loc": [ 2391, 2400 ] }, { "type": "function", "id": "pmpCheckRWX", "file": "model/riscv_pmp_control.sail", "loc": [ 2426, 2437 ] } ] }, "pmpCheckRWX": { "function": { "number": 0, "source": "function pmpCheckRWX(ent, acc) = {\n match acc {\n Read(_) => ent[R] == 0b1,\n Write(_) => ent[W] == 0b1,\n ReadWrite(_) => ent[R] == 0b1 & ent[W] == 0b1,\n Execute() => ent[X] == 0b1\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "ent" }, { "type": "id", "id": "acc" } ] }, "body": " match acc {\n Read(_) => ent[R] == 0b1,\n Write(_) => ent[W] == 0b1,\n ReadWrite(_) => ent[R] == 0b1 & ent[W] == 0b1,\n Execute() => ent[X] == 0b1\n }" } }, "pmpLocked": { "function": { "number": 0, "source": "function pmpLocked(cfg: Pmpcfg_ent) -> bool =\n cfg[L] == 0b1", "pattern": { "type": "id", "id": "cfg" }, "body": "cfg[L] == 0b1" } }, "pmpMatchAddr": { "function": { "number": 0, "source": "function pmpMatchAddr(addr: xlenbits, width: xlenbits, rng: pmp_addr_range) -> pmpAddrMatch = {\n match rng {\n None() => PMP_NoMatch,\n Some((lo, hi)) => if hi <=_u lo /* to handle mis-configuration */\n then PMP_NoMatch\n else {\n if (addr + width <=_u lo) | (hi <=_u addr)\n then PMP_NoMatch\n else if (lo <=_u addr) & (addr + width <=_u hi)\n then PMP_Match\n else PMP_PartialMatch\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "rng" } ] }, "body": " match rng {\n None() => PMP_NoMatch,\n Some((lo, hi)) => if hi <=_u lo /* to handle mis-configuration */\n then PMP_NoMatch\n else {\n if (addr + width <=_u lo) | (hi <=_u addr)\n then PMP_NoMatch\n else if (lo <=_u addr) & (addr + width <=_u hi)\n then PMP_Match\n else PMP_PartialMatch\n }\n }" }, "links": [ { "type": "function", "id": "(operator <=_u)", "file": "model/riscv_pmp_control.sail", "loc": [ 2779, 2783 ] }, { "type": "function", "id": "(operator <=_u)", "file": "model/riscv_pmp_control.sail", "loc": [ 2952, 2956 ] }, { "type": "function", "id": "(operator <=_u)", "file": "model/riscv_pmp_control.sail", "loc": [ 2937, 2941 ] }, { "type": "function", "id": "(operator <=_u)", "file": "model/riscv_pmp_control.sail", "loc": [ 3070, 3074 ] }, { "type": "function", "id": "(operator <=_u)", "file": "model/riscv_pmp_control.sail", "loc": [ 3043, 3047 ] } ] }, "pmpMatchEntry": { "function": { "number": 0, "source": "function pmpMatchEntry(addr: xlenbits, width: xlenbits, acc: AccessType(ext_access_type), priv: Privilege,\n ent: Pmpcfg_ent, pmpaddr: xlenbits, prev_pmpaddr: xlenbits) -> pmpMatch = {\n let rng = pmpAddrRange(ent, pmpaddr, prev_pmpaddr);\n match pmpMatchAddr(addr, width, rng) {\n PMP_NoMatch => PMP_Continue,\n PMP_PartialMatch => PMP_Fail,\n PMP_Match => if pmpCheckPerms(ent, acc, priv)\n then PMP_Success\n else PMP_Fail\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "acc" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "ent" }, { "type": "id", "id": "pmpaddr" }, { "type": "id", "id": "prev_pmpaddr" } ] }, "body": " let rng = pmpAddrRange(ent, pmpaddr, prev_pmpaddr);\n match pmpMatchAddr(addr, width, rng) {\n PMP_NoMatch => PMP_Continue,\n PMP_PartialMatch => PMP_Fail,\n PMP_Match => if pmpCheckPerms(ent, acc, priv)\n then PMP_Success\n else PMP_Fail\n }" }, "links": [ { "type": "function", "id": "pmpAddrRange", "file": "model/riscv_pmp_control.sail", "loc": [ 3474, 3486 ] }, { "type": "function", "id": "pmpMatchAddr", "file": "model/riscv_pmp_control.sail", "loc": [ 3524, 3536 ] }, { "type": "function", "id": "pmpCheckPerms", "file": "model/riscv_pmp_control.sail", "loc": [ 3658, 3671 ] } ] }, "pmpMatch_of_num": { "function": { "number": 0, "source": "pmpMatch_of_num arg# = $[complete] match arg# {\n 0 => PMP_Success,\n 1 => PMP_Continue,\n _ => PMP_Fail\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => PMP_Success,\n 1 => PMP_Continue,\n _ => PMP_Fail\n}" } }, "pmpReadAddrReg": { "function": { "number": 0, "source": "function pmpReadAddrReg(n : range(0, 63)) -> xlenbits = {\n let G = sys_pmp_grain();\n let match_type = pmpcfg_n[n].A();\n let addr = pmpaddr_n[n];\n\n match match_type[1] {\n bitone if G >= 2 => {\n // [G-2..0] read as all ones to form mask, therefore we need G-1 bits.\n let mask : xlenbits = zero_extend(ones(min(G - 1, sizeof(xlen))));\n addr | mask\n },\n\n bitzero if G >= 1 => {\n // [G-1..0] read as all zeros to form mask, therefore we need G bits.\n let mask : xlenbits = zero_extend(ones(min(G , sizeof(xlen))));\n addr & ~(mask)\n },\n\n _ => addr,\n }\n}", "pattern": { "type": "id", "id": "n" }, "body": " let G = sys_pmp_grain();\n let match_type = pmpcfg_n[n].A();\n let addr = pmpaddr_n[n];\n\n match match_type[1] {\n bitone if G >= 2 => {\n // [G-2..0] read as all ones to form mask, therefore we need G-1 bits.\n let mask : xlenbits = zero_extend(ones(min(G - 1, sizeof(xlen))));\n addr | mask\n },\n\n bitzero if G >= 1 => {\n // [G-1..0] read as all zeros to form mask, therefore we need G bits.\n let mask : xlenbits = zero_extend(ones(min(G , sizeof(xlen))));\n addr & ~(mask)\n },\n\n _ => addr,\n }" }, "links": [ { "type": "function", "id": "sys_pmp_grain", "file": "model/riscv_pmp_regs.sail", "loc": [ 2085, 2098 ] }, { "type": "function", "id": "_get_Pmpcfg_ent_A", "file": "", "loc": [ 19, 36 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 2121, 2129 ] }, { "type": "register", "id": "pmpaddr_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 2151, 2160 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_pmp_regs.sail", "loc": [ 2523, 2534 ] }, { "type": "function", "id": "ones", "file": "model/riscv_pmp_regs.sail", "loc": [ 2535, 2539 ] }, { "type": "function", "id": "min_int", "file": "model/prelude.sail", "loc": [ 2540, 2547 ] }, { "type": "function", "id": "not_vec", "file": "model/prelude.sail", "loc": [ 997, 1004 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_pmp_regs.sail", "loc": [ 2321, 2332 ] }, { "type": "function", "id": "ones", "file": "model/riscv_pmp_regs.sail", "loc": [ 2333, 2337 ] }, { "type": "function", "id": "min_int", "file": "model/prelude.sail", "loc": [ 2540, 2547 ] } ] }, "pmpReadCfgReg": { "function": { "number": 0, "source": "function pmpReadCfgReg(n : range(0, 15)) -> xlenbits = {\n if sizeof(xlen) == 32\n then {\n pmpcfg_n[n*4 + 3].bits @\n pmpcfg_n[n*4 + 2].bits @\n pmpcfg_n[n*4 + 1].bits @\n pmpcfg_n[n*4 + 0].bits\n }\n else {\n assert(n % 2 == 0, \"Unexpected pmp config reg read\");\n pmpcfg_n[n*4 + 7].bits @\n pmpcfg_n[n*4 + 6].bits @\n pmpcfg_n[n*4 + 5].bits @\n pmpcfg_n[n*4 + 4].bits @\n pmpcfg_n[n*4 + 3].bits @\n pmpcfg_n[n*4 + 2].bits @\n pmpcfg_n[n*4 + 1].bits @\n pmpcfg_n[n*4 + 0].bits\n }\n}", "pattern": { "type": "id", "id": "n" }, "body": " if sizeof(xlen) == 32\n then {\n pmpcfg_n[n*4 + 3].bits @\n pmpcfg_n[n*4 + 2].bits @\n pmpcfg_n[n*4 + 1].bits @\n pmpcfg_n[n*4 + 0].bits\n }\n else {\n assert(n % 2 == 0, \"Unexpected pmp config reg read\");\n pmpcfg_n[n*4 + 7].bits @\n pmpcfg_n[n*4 + 6].bits @\n pmpcfg_n[n*4 + 5].bits @\n pmpcfg_n[n*4 + 4].bits @\n pmpcfg_n[n*4 + 3].bits @\n pmpcfg_n[n*4 + 2].bits @\n pmpcfg_n[n*4 + 1].bits @\n pmpcfg_n[n*4 + 0].bits\n }" }, "links": [ { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1686, 1694 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1657, 1665 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1628, 1636 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1599, 1607 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1987, 1995 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1958, 1966 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1929, 1937 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1900, 1908 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1871, 1879 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1842, 1850 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1813, 1821 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 1784, 1792 ] }, { "type": "function", "id": "emod_int", "file": "model/prelude.sail", "loc": [ 2111, 2119 ] } ] }, "pmpTORLocked": { "function": { "number": 0, "source": "function pmpTORLocked(cfg: Pmpcfg_ent) -> bool =\n (cfg[L] == 0b1) & (pmpAddrMatchType_of_bits(cfg[A]) == TOR)", "pattern": { "type": "id", "id": "cfg" }, "body": "(cfg[L] == 0b1) & (pmpAddrMatchType_of_bits(cfg[A]) == TOR)" }, "links": [ { "type": "function", "id": "pmpAddrMatchType_of_bits", "file": "model/riscv_pmp_regs.sail", "loc": [ 2790, 2814 ] } ] }, "pmpWriteAddr": { "function": { "number": 0, "source": "function pmpWriteAddr(locked: bool, tor_locked: bool, reg: xlenbits, v: xlenbits) -> xlenbits =\n if sizeof(xlen) == 32\n then { if (locked | tor_locked) then reg else v }\n else { if (locked | tor_locked) then reg else zero_extend(v[53..0]) }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "locked" }, { "type": "id", "id": "tor_locked" }, { "type": "id", "id": "reg" }, { "type": "id", "id": "v" } ] }, "body": "if sizeof(xlen) == 32\n then { if (locked | tor_locked) then reg else v }\n else { if (locked | tor_locked) then reg else zero_extend(v[53..0]) }" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_pmp_regs.sail", "loc": [ 4435, 4446 ] } ] }, "pmpWriteAddrReg": { "function": { "number": 0, "source": "function pmpWriteAddrReg(n : range(0, 63), v : xlenbits) -> unit = {\n pmpaddr_n[n] = pmpWriteAddr(\n pmpLocked(pmpcfg_n[n]),\n if n + 1 < 64 then pmpTORLocked(pmpcfg_n[n + 1]) else false,\n pmpaddr_n[n],\n v,\n );\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "v" } ] }, "body": " pmpaddr_n[n] = pmpWriteAddr(\n pmpLocked(pmpcfg_n[n]),\n if n + 1 < 64 then pmpTORLocked(pmpcfg_n[n + 1]) else false,\n pmpaddr_n[n],\n v,\n )" }, "links": [ { "type": "register", "id": "pmpaddr_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 4531, 4540 ] }, { "type": "function", "id": "pmpWriteAddr", "file": "model/riscv_pmp_regs.sail", "loc": [ 4546, 4558 ] }, { "type": "register", "id": "pmpaddr_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 4657, 4666 ] }, { "type": "function", "id": "pmpTORLocked", "file": "model/riscv_pmp_regs.sail", "loc": [ 4611, 4623 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 4624, 4632 ] }, { "type": "function", "id": "pmpLocked", "file": "model/riscv_pmp_regs.sail", "loc": [ 4564, 4573 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 4574, 4582 ] } ] }, "pmpWriteCfg": { "function": { "number": 0, "source": "function pmpWriteCfg(n: range(0, 63), cfg: Pmpcfg_ent, v: bits(8)) -> Pmpcfg_ent =\n if pmpLocked(cfg) then cfg\n else {\n // Bits 5 and 6 are zero.\n let cfg = Mk_Pmpcfg_ent(v & 0x9f);\n\n // \"The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved.\"\n // In this implementation if R=0 and W=1 then R, W and X are all set to 0.\n // This is the least risky option from a security perspective.\n let cfg = if cfg.W() == 0b1 & cfg.R() == 0b0 then [cfg with X = 0b0, W = 0b0, R = 0b0] else cfg;\n\n // \"When G >= 1, the NA4 mode is not selectable.\"\n // In this implementation we set it to OFF if NA4 is selected.\n // This is the least risky option from a security perspective.\n let cfg = if sys_pmp_grain() >= 1 & pmpAddrMatchType_of_bits(cfg.A()) == NA4\n then [cfg with A = pmpAddrMatchType_to_bits(OFF)]\n else cfg;\n\n cfg\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "cfg" }, { "type": "id", "id": "v" } ] }, "body": "if pmpLocked(cfg) then cfg\n else {\n // Bits 5 and 6 are zero.\n let cfg = Mk_Pmpcfg_ent(v & 0x9f);\n\n // \"The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved.\"\n // In this implementation if R=0 and W=1 then R, W and X are all set to 0.\n // This is the least risky option from a security perspective.\n let cfg = if cfg.W() == 0b1 & cfg.R() == 0b0 then [cfg with X = 0b0, W = 0b0, R = 0b0] else cfg;\n\n // \"When G >= 1, the NA4 mode is not selectable.\"\n // In this implementation we set it to OFF if NA4 is selected.\n // This is the least risky option from a security perspective.\n let cfg = if sys_pmp_grain() >= 1 & pmpAddrMatchType_of_bits(cfg.A()) == NA4\n then [cfg with A = pmpAddrMatchType_to_bits(OFF)]\n else cfg;\n\n cfg\n }" }, "links": [ { "type": "function", "id": "pmpLocked", "file": "model/riscv_pmp_regs.sail", "loc": [ 2920, 2929 ] }, { "type": "function", "id": "Mk_Pmpcfg_ent", "file": "model/riscv_pmp_regs.sail", "loc": [ 2997, 3010 ] }, { "type": "function", "id": "_get_Pmpcfg_ent_R", "file": "", "loc": [ 19, 36 ] }, { "type": "function", "id": "_get_Pmpcfg_ent_W", "file": "", "loc": [ 19, 36 ] }, { "type": "function", "id": "pmpAddrMatchType_of_bits", "file": "model/riscv_pmp_regs.sail", "loc": [ 3618, 3642 ] }, { "type": "function", "id": "_get_Pmpcfg_ent_A", "file": "", "loc": [ 19, 36 ] }, { "type": "function", "id": "sys_pmp_grain", "file": "model/riscv_pmp_regs.sail", "loc": [ 3595, 3608 ] }, { "type": "function", "id": "pmpAddrMatchType_to_bits", "file": "model/riscv_pmp_regs.sail", "loc": [ 3692, 3716 ] } ] }, "pmpWriteCfgReg": { "function": { "number": 0, "source": "function pmpWriteCfgReg(n : range(0, 15), v : xlenbits) -> unit = {\n if sizeof(xlen) == 32\n then {\n foreach (i from 0 to 3) {\n let idx = n*4 + i;\n pmpcfg_n[idx] = pmpWriteCfg(idx, pmpcfg_n[idx], v[8*i+7 .. 8*i]);\n }\n }\n else {\n assert(n % 2 == 0, \"Unexpected pmp config reg write\");\n foreach (i from 0 to 7) {\n let idx = n*4 + i;\n pmpcfg_n[idx] = pmpWriteCfg(idx, pmpcfg_n[idx], v[8*i+7 .. 8*i]);\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "v" } ] }, "body": " if sizeof(xlen) == 32\n then {\n foreach (i from 0 to 3) {\n let idx = n*4 + i;\n pmpcfg_n[idx] = pmpWriteCfg(idx, pmpcfg_n[idx], v[8*i+7 .. 8*i]);\n }\n }\n else {\n assert(n % 2 == 0, \"Unexpected pmp config reg write\");\n foreach (i from 0 to 7) {\n let idx = n*4 + i;\n pmpcfg_n[idx] = pmpWriteCfg(idx, pmpcfg_n[idx], v[8*i+7 .. 8*i]);\n }\n }" }, "links": [ { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 3923, 3931 ] }, { "type": "function", "id": "pmpWriteCfg", "file": "model/riscv_pmp_regs.sail", "loc": [ 3940, 3951 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 3958, 3966 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 4131, 4139 ] }, { "type": "function", "id": "pmpWriteCfg", "file": "model/riscv_pmp_regs.sail", "loc": [ 4148, 4159 ] }, { "type": "register", "id": "pmpcfg_n", "file": "model/riscv_pmp_regs.sail", "loc": [ 4166, 4174 ] }, { "type": "function", "id": "emod_int", "file": "model/prelude.sail", "loc": [ 2111, 2119 ] } ] }, "pmp_mem_read": { "function": { "number": 0, "source": "function pmp_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), p : Privilege, paddr : xlenbits, width : int('n), aq : bool, rl : bool, res: bool, meta : bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) =\n if sys_pmp_count() == 0\n then checked_mem_read(t, paddr, width, aq, rl, res, meta)\n else {\n match pmpCheck(paddr, width, t, p) {\n None() => checked_mem_read(t, paddr, width, aq, rl, res, meta),\n Some(e) => MemException(e)\n }\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "t" }, { "type": "id", "id": "p" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "res" }, { "type": "id", "id": "meta" } ] }, "body": "if sys_pmp_count() == 0\n then checked_mem_read(t, paddr, width, aq, rl, res, meta)\n else {\n match pmpCheck(paddr, width, t, p) {\n None() => checked_mem_read(t, paddr, width, aq, rl, res, meta),\n Some(e) => MemException(e)\n }\n }" }, "links": [ { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_mem.sail", "loc": [ 4413, 4426 ] }, { "type": "function", "id": "checked_mem_read", "file": "model/riscv_mem.sail", "loc": [ 4441, 4457 ] }, { "type": "function", "id": "pmpCheck", "file": "model/riscv_mem.sail", "loc": [ 4513, 4521 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 4632, 4644 ] }, { "type": "function", "id": "checked_mem_read", "file": "model/riscv_mem.sail", "loc": [ 4561, 4577 ] } ] }, "pmp_mem_write": { "function": { "number": 0, "source": "function pmp_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk: write_kind, paddr : xlenbits, width : int('n), data: bits(8 * 'n), typ: AccessType(ext_access_type), priv: Privilege, meta: mem_meta) -> MemoryOpResult(bool) =\n if sys_pmp_count() == 0\n then checked_mem_write(wk, paddr, width, data, meta)\n else {\n match pmpCheck(paddr, width, typ, priv) {\n None() => checked_mem_write(wk, paddr, width, data, meta),\n Some(e) => MemException(e)\n }\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "wk" }, { "type": "id", "id": "paddr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "data" }, { "type": "id", "id": "typ" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "meta" } ] }, "body": "if sys_pmp_count() == 0\n then checked_mem_write(wk, paddr, width, data, meta)\n else {\n match pmpCheck(paddr, width, typ, priv) {\n None() => checked_mem_write(wk, paddr, width, data, meta),\n Some(e) => MemException(e)\n }\n }" }, "links": [ { "type": "function", "id": "sys_pmp_count", "file": "model/riscv_mem.sail", "loc": [ 11587, 11600 ] }, { "type": "function", "id": "checked_mem_write", "file": "model/riscv_mem.sail", "loc": [ 11615, 11632 ] }, { "type": "function", "id": "pmpCheck", "file": "model/riscv_mem.sail", "loc": [ 11682, 11690 ] }, { "type": "function", "id": "MemException", "file": "model/riscv_mem.sail", "loc": [ 11801, 11813 ] }, { "type": "function", "id": "checked_mem_write", "file": "model/riscv_mem.sail", "loc": [ 11735, 11752 ] } ] }, "prepare_trap_vector": { "function": { "number": 0, "source": "function prepare_trap_vector(p : Privilege, cause : Mcause) -> xlenbits = {\n let tvec : Mtvec = match p {\n Machine => mtvec,\n Supervisor => stvec,\n User => utvec\n };\n match tvec_addr(tvec, cause) {\n Some(epc) => epc,\n None() => internal_error(__FILE__, __LINE__, \"Invalid tvec mode\")\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "p" }, { "type": "id", "id": "cause" } ] }, "body": " let tvec : Mtvec = match p {\n Machine => mtvec,\n Supervisor => stvec,\n User => utvec\n };\n match tvec_addr(tvec, cause) {\n Some(epc) => epc,\n None() => internal_error(__FILE__, __LINE__, \"Invalid tvec mode\")\n }" }, "links": [ { "type": "register", "id": "utvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 1271, 1276 ] }, { "type": "register", "id": "stvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 1227, 1232 ] }, { "type": "register", "id": "mtvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 1183, 1188 ] }, { "type": "function", "id": "tvec_addr", "file": "model/riscv_sys_exceptions.sail", "loc": [ 1309, 1318 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_sys_exceptions.sail", "loc": [ 1373, 1387 ] } ] }, "prepare_xret_target": { "function": { "number": 0, "source": "function prepare_xret_target(p) =\n get_xret_target(p)", "pattern": { "type": "id", "id": "p" }, "body": "get_xret_target(p)" }, "links": [ { "type": "function", "id": "get_xret_target", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2268, 2283 ] } ] }, "print_insn": { "function": { "number": 0, "source": "function print_insn insn = assembly(insn)", "pattern": { "type": "id", "id": "insn" }, "body": "assembly(insn)" } }, "privLevel_of_bits": { "function": { "number": 0, "source": "function privLevel_of_bits (p) =\n match (p) {\n 0b00 => User,\n 0b01 => Supervisor,\n 0b11 => Machine,\n 0b10 => internal_error(__FILE__, __LINE__, \"Invalid privilege level: \" ^ BitStr(p))\n }", "pattern": { "type": "id", "id": "p" }, "body": "match (p) {\n 0b00 => User,\n 0b01 => Supervisor,\n 0b11 => Machine,\n 0b10 => internal_error(__FILE__, __LINE__, \"Invalid privilege level: \" ^ BitStr(p))\n }" }, "links": [ { "type": "function", "id": "internal_error", "file": "model/riscv_types.sail", "loc": [ 3358, 3372 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "privLevel_to_bits": { "function": { "number": 0, "source": "function privLevel_to_bits (p) =\n match (p) {\n User => 0b00,\n Supervisor => 0b01,\n Machine => 0b11\n }", "pattern": { "type": "id", "id": "p" }, "body": "match (p) {\n User => 0b00,\n Supervisor => 0b01,\n Machine => 0b11\n }" } }, "privLevel_to_str": { "function": { "number": 0, "source": "function privLevel_to_str (p) =\n match (p) {\n User => \"U\",\n Supervisor => \"S\",\n Machine => \"M\"\n }", "pattern": { "type": "id", "id": "p" }, "body": "match (p) {\n User => \"U\",\n Supervisor => \"S\",\n Machine => \"M\"\n }" } }, "processPending": { "function": { "number": 0, "source": "function processPending(xip : Minterrupts, xie : Minterrupts, xideleg : xlenbits,\n priv_enabled : bool) -> interrupt_set = {\n /* interrupts that are enabled but not delegated are pending */\n let effective_pend = xip.bits & xie.bits & (~ (xideleg));\n /* the others are delegated */\n let effective_delg = xip.bits & xideleg;\n /* we have pending interrupts if this privilege is enabled */\n if priv_enabled & (effective_pend != zero_extend(0b0))\n then Ints_Pending(effective_pend)\n else if effective_delg != zero_extend(0b0)\n then Ints_Delegated(effective_delg)\n else Ints_Empty()\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "xip" }, { "type": "id", "id": "xie" }, { "type": "id", "id": "xideleg" }, { "type": "id", "id": "priv_enabled" } ] }, "body": " let effective_pend = xip.bits & xie.bits & (~ (xideleg));\n /* the others are delegated */\n let effective_delg = xip.bits & xideleg;\n /* we have pending interrupts if this privilege is enabled */\n if priv_enabled & (effective_pend != zero_extend(0b0))\n then Ints_Pending(effective_pend)\n else if effective_delg != zero_extend(0b0)\n then Ints_Delegated(effective_delg)\n else Ints_Empty()" }, "links": [ { "type": "function", "id": "not_vec", "file": "model/prelude.sail", "loc": [ 997, 1004 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 9677, 9688 ] }, { "type": "function", "id": "Ints_Pending", "file": "model/riscv_sys_control.sail", "loc": [ 9705, 9717 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 9762, 9773 ] }, { "type": "function", "id": "Ints_Delegated", "file": "model/riscv_sys_control.sail", "loc": [ 9789, 9803 ] }, { "type": "function", "id": "Ints_Empty", "file": "model/riscv_sys_control.sail", "loc": [ 9830, 9840 ] } ] }, "process_fload16": { "function": { "number": 0, "source": "function process_fload16(rd, addr, value) =\n match value {\n MemValue(result) => { F(rd) = nan_box(result); RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "addr" }, { "type": "id", "id": "value" } ] }, "body": "match value {\n MemValue(result) => { F(rd) = nan_box(result); RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }\n }" }, "links": [ { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_fext.sail", "loc": [ 10164, 10184 ] }, { "type": "function", "id": "wF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6041, 6048 ] }, { "type": "function", "id": "nan_box_H", "file": "model/riscv_fdext_regs.sail", "loc": [ 2782, 2791 ] } ] }, "process_fload32": { "function": { "number": 0, "source": "function process_fload32(rd, addr, value) =\n match value {\n MemValue(result) => { F(rd) = nan_box(result); RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "addr" }, { "type": "id", "id": "value" } ] }, "body": "match value {\n MemValue(result) => { F(rd) = nan_box(result); RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }\n }" }, "links": [ { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_fext.sail", "loc": [ 9859, 9879 ] }, { "type": "function", "id": "wF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6041, 6048 ] }, { "type": "function", "id": "nan_box_S", "file": "model/riscv_fdext_regs.sail", "loc": [ 2793, 2802 ] } ] }, "process_fload64": { "function": { "number": 0, "source": "function process_fload64(rd, addr, value) =\n if sizeof(flen) == 64\n then match value {\n MemValue(result) => { F(rd) = result; RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }\n }\n else {\n /* should not get here */\n RETIRE_FAIL\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "addr" }, { "type": "id", "id": "value" } ] }, "body": "if sizeof(flen) == 64\n then match value {\n MemValue(result) => { F(rd) = result; RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }\n }\n else {\n /* should not get here */\n RETIRE_FAIL\n }" }, "links": [ { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_fext.sail", "loc": [ 9490, 9510 ] }, { "type": "function", "id": "wF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6041, 6048 ] } ] }, "process_fstore": { "function": { "number": 0, "source": "function process_fstore(vaddr, value) =\n match value {\n MemValue(true) => { RETIRE_SUCCESS },\n MemValue(false) => { internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\") },\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vaddr" }, { "type": "id", "id": "value" } ] }, "body": "match value {\n MemValue(true) => { RETIRE_SUCCESS },\n MemValue(false) => { internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\") },\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }" }, "links": [ { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_fext.sail", "loc": [ 13182, 13202 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_insts_fext.sail", "loc": [ 13079, 13093 ] } ] }, "process_load": { "function": { "number": 0, "source": "function process_load(rd, vaddr, value, is_unsigned) =\n match extend_value(is_unsigned, value) {\n MemValue(result) => { X(rd) = result; RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "vaddr" }, { "type": "id", "id": "value" }, { "type": "id", "id": "is_unsigned" } ] }, "body": "match extend_value(is_unsigned, value) {\n MemValue(result) => { X(rd) = result; RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }\n }" }, "links": [ { "type": "function", "id": "extend_value", "file": "model/riscv_insts_base.sail", "loc": [ 11906, 11918 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_base.sail", "loc": [ 12027, 12047 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] } ] }, "process_loadres": { "function": { "number": 0, "source": "function process_loadres(rd, addr, value, is_unsigned) =\n match extend_value(is_unsigned, value) {\n MemValue(result) => { load_reservation(addr); X(rd) = result; RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "addr" }, { "type": "id", "id": "value" }, { "type": "id", "id": "is_unsigned" } ] }, "body": "match extend_value(is_unsigned, value) {\n MemValue(result) => { load_reservation(addr); X(rd) = result; RETIRE_SUCCESS },\n MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL }\n }" }, "links": [ { "type": "function", "id": "extend_value", "file": "model/riscv_insts_aext.sail", "loc": [ 2350, 2362 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_aext.sail", "loc": [ 2495, 2515 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] }, { "type": "function", "id": "load_reservation", "file": "model/riscv_insts_aext.sail", "loc": [ 2411, 2427 ] } ] }, "process_rfvv_single": { "function": { "number": 0, "source": "function process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) = {\n let rm_3b = fcsr[FRM];\n let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */\n\n if illegal_fp_reduction(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */\n\n let 'n = num_elem_vs;\n let 'd = num_elem_vd;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);\n let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);\n\n sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */\n foreach (i from 0 to (num_elem_vs - 1)) {\n if mask[i] then {\n sum = match funct6 {\n /* currently ordered/unordered sum reductions do the same operations */\n FVV_VFREDOSUM => fp_add(rm_3b, sum, vs2_val[i]),\n FVV_VFREDUSUM => fp_add(rm_3b, sum, vs2_val[i]),\n FVV_VFREDMAX => fp_max(sum, vs2_val[i]),\n FVV_VFREDMIN => fp_min(sum, vs2_val[i])\n }\n }\n };\n\n write_single_element(SEW, 0, vd, sum);\n /* other elements in vd are treated as tail elements, currently remain unchanged */\n /* TODO: configuration support for agnostic behavior */\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" }, { "type": "id", "id": "num_elem_vs" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "LMUL_pow" } ] }, "body": " let rm_3b = fcsr[FRM];\n let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */\n\n if illegal_fp_reduction(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW != 8);\n\n if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */\n\n let 'n = num_elem_vs;\n let 'd = num_elem_vd;\n let 'm = SEW;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);\n let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);\n\n sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */\n foreach (i from 0 to (num_elem_vs - 1)) {\n if mask[i] then {\n sum = match funct6 {\n /* currently ordered/unordered sum reductions do the same operations */\n FVV_VFREDOSUM => fp_add(rm_3b, sum, vs2_val[i]),\n FVV_VFREDUSUM => fp_add(rm_3b, sum, vs2_val[i]),\n FVV_VFREDMAX => fp_max(sum, vs2_val[i]),\n FVV_VFREDMIN => fp_min(sum, vs2_val[i])\n }\n }\n };\n\n write_single_element(SEW, 0, vd, sum);\n /* other elements in vd are treated as tail elements, currently remain unchanged */\n /* TODO: configuration support for agnostic behavior */\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "register", "id": "fcsr", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7060, 7064 ] }, { "type": "function", "id": "get_num_elem", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7091, 7103 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7458, 7468 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7540, 7549 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7620, 7629 ] }, { "type": "function", "id": "init_masked_source", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7708, 7726 ] }, { "type": "function", "id": "read_single_element", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7779, 7798 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8451, 8457 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8266, 8286 ] }, { "type": "function", "id": "fp_min", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8220, 8226 ] }, { "type": "function", "id": "fp_max", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8168, 8174 ] }, { "type": "function", "id": "fp_add", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8109, 8115 ] }, { "type": "function", "id": "fp_add", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8050, 8056 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7261, 7269 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7270, 7272 ] }, { "type": "function", "id": "illegal_fp_reduction", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7155, 7175 ] }, { "type": "function", "id": "handle_illegal", "file": "model/riscv_insts_vext_red.sail", "loc": [ 7195, 7209 ] } ] }, "process_rfvv_widen": { "function": { "number": 0, "source": "function process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) = {\n let rm_3b = fcsr[FRM];\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */\n\n if illegal_fp_reduction_widen(SEW, rm_3b, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */\n\n let 'n = num_elem_vs;\n let 'd = num_elem_vd;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);\n let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);\n\n sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */\n foreach (i from 0 to (num_elem_vs - 1)) {\n if mask[i] then {\n /* currently ordered/unordered sum reductions do the same operations */\n sum = fp_add(rm_3b, sum, fp_widen(vs2_val[i]))\n }\n };\n\n write_single_element(SEW_widen, 0, vd, sum);\n /* other elements in vd are treated as tail elements, currently remain unchanged */\n /* TODO: configuration support for agnostic behavior */\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" }, { "type": "id", "id": "num_elem_vs" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "LMUL_pow" } ] }, "body": " let rm_3b = fcsr[FRM];\n let SEW_widen = SEW * 2;\n let LMUL_pow_widen = LMUL_pow + 1;\n let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */\n\n if illegal_fp_reduction_widen(SEW, rm_3b, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL };\n assert(SEW >= 16 & SEW_widen <= 64);\n\n if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */\n\n let 'n = num_elem_vs;\n let 'd = num_elem_vd;\n let 'm = SEW;\n let 'o = SEW_widen;\n\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);\n let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd);\n let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);\n\n sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */\n foreach (i from 0 to (num_elem_vs - 1)) {\n if mask[i] then {\n /* currently ordered/unordered sum reductions do the same operations */\n sum = fp_add(rm_3b, sum, fp_widen(vs2_val[i]))\n }\n };\n\n write_single_element(SEW_widen, 0, vd, sum);\n /* other elements in vd are treated as tail elements, currently remain unchanged */\n /* TODO: configuration support for agnostic behavior */\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "register", "id": "fcsr", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8756, 8760 ] }, { "type": "function", "id": "get_num_elem", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8856, 8868 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9303, 9313 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9385, 9394 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9471, 9480 ] }, { "type": "function", "id": "init_masked_source", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9559, 9577 ] }, { "type": "function", "id": "read_single_element", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9630, 9649 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_red.sail", "loc": [ 10109, 10115 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9918, 9938 ] }, { "type": "function", "id": "fp_add", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9863, 9869 ] }, { "type": "function", "id": "fp_widen", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9882, 9890 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9084, 9092 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_red.sail", "loc": [ 9093, 9095 ] }, { "type": "function", "id": "illegal_fp_reduction_widen", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8926, 8952 ] }, { "type": "function", "id": "handle_illegal", "file": "model/riscv_insts_vext_red.sail", "loc": [ 8999, 9013 ] } ] }, "process_vlre": { "function": { "number": 0, "source": "function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = {\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let start_element = get_start_element();\n if start_element >= nf * elem_per_reg then return RETIRE_SUCCESS; /* no elements are written if vstart >= evl */\n let elem_to_align : int = start_element % elem_per_reg;\n cur_field : int = start_element / elem_per_reg;\n cur_elem : int = start_element;\n\n if elem_to_align > 0 then {\n foreach (i from elem_to_align to (elem_per_reg - 1)) {\n vstart = to_bits(16, cur_elem);\n let elem_offset = cur_elem * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, cur_field), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n };\n cur_elem = cur_elem + 1\n };\n cur_field = cur_field + 1\n };\n\n foreach (j from cur_field to (nf - 1)) {\n foreach (i from 0 to (elem_per_reg - 1)) {\n vstart = to_bits(16, cur_elem);\n let elem_offset = cur_elem * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n };\n cur_elem = cur_elem + 1\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vd" }, { "type": "id", "id": "load_width_bytes" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "elem_per_reg" } ] }, "body": " let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let start_element = get_start_element();\n if start_element >= nf * elem_per_reg then return RETIRE_SUCCESS; /* no elements are written if vstart >= evl */\n let elem_to_align : int = start_element % elem_per_reg;\n cur_field : int = start_element / elem_per_reg;\n cur_elem : int = start_element;\n\n if elem_to_align > 0 then {\n foreach (i from elem_to_align to (elem_per_reg - 1)) {\n vstart = to_bits(16, cur_elem);\n let elem_offset = cur_elem * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, cur_field), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n };\n cur_elem = cur_elem + 1\n };\n cur_field = cur_field + 1\n };\n\n foreach (j from cur_field to (nf - 1)) {\n foreach (i from 0 to (elem_per_reg - 1)) {\n vstart = to_bits(16, cur_elem);\n let elem_offset = cur_elem * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n };\n cur_elem = cur_elem + 1\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "get_start_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 32539, 32556 ] }, { "type": "function", "id": "emod_int", "file": "model/prelude.sail", "loc": [ 2111, 2119 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 35073, 35079 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34157, 34174 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34216, 34220 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34180, 34187 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34379, 34395 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34432, 34452 ] }, { "type": "function", "id": "E_Load_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34460, 34477 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34524, 34537 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34545, 34549 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34709, 34717 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34718, 34722 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34925, 34945 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34814, 34834 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34865, 34872 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34597, 34617 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34278, 34305 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34060, 34066 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 34069, 34076 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33011, 33028 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33070, 33074 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33034, 33041 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33233, 33249 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33286, 33306 ] }, { "type": "function", "id": "E_Load_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33314, 33331 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33378, 33391 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33399, 33403 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33563, 33571 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33572, 33576 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33787, 33807 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33668, 33688 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33719, 33726 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33451, 33471 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 33132, 33159 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 32914, 32920 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 32923, 32930 ] } ] }, "process_vlseg": { "function": { "number": 0, "source": "function process_vlseg (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = {\n let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd);\n\n let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = (i * nf + j) * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n } else { /* prestart, masked or tail segments */\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0];\n write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem)\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vd" }, { "type": "id", "id": "load_width_bytes" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "EMUL_pow" }, { "type": "id", "id": "num_elem" } ] }, "body": " let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd);\n\n let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = (i * nf + j) * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n } else { /* prestart, masked or tail segments */\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0];\n write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem)\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 2800, 2809 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 2930, 2940 ] }, { "type": "function", "id": "read_vreg_seg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3017, 3030 ] }, { "type": "function", "id": "init_masked_result", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3106, 3124 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 4674, 4680 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3418, 3435 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3477, 3481 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3441, 3448 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3648, 3664 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3705, 3725 ] }, { "type": "function", "id": "E_Load_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3733, 3750 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3801, 3814 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3822, 3826 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3998, 4006 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 4007, 4011 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 4233, 4253 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 4107, 4127 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 4158, 4165 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3878, 3898 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3541, 3568 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3281, 3287 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 3290, 3297 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 4561, 4581 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 4612, 4619 ] } ] }, "process_vlsegff": { "function": { "number": 0, "source": "function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = {\n let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd);\n let tail_ag : agtype = get_vtype_vta();\n\n let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val);\n\n trimmed : bool = false;\n foreach (i from 0 to (num_elem - 1)) {\n if not(trimmed) then {\n if vm_val[i] then { /* active segments */\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = (i * nf + j) * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => {\n if i == 0 then { ext_handle_data_check_error(e); return RETIRE_FAIL }\n else {\n vl = to_bits(sizeof(xlen), i);\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n trimmed = true\n }\n },\n Ext_DataAddr_OK(vaddr) => {\n if check_misaligned(vaddr, width_type) then {\n if i == 0 then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else {\n vl = to_bits(sizeof(xlen), i);\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n trimmed = true\n }\n } else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => {\n if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n else {\n vl = to_bits(sizeof(xlen), i);\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n trimmed = true\n }\n },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),\n MemException(e) => {\n if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n else {\n vl = to_bits(sizeof(xlen), i);\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n trimmed = true\n }\n }\n }\n }\n }\n }\n }\n }\n } else { /* prestart, masked or tail segments */\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0];\n write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem)\n }\n }\n } else {\n /* if vl is trimmed, elements past the new vl are treated as tail elements */\n if tail_ag == AGNOSTIC then {\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (vd_seg[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0];\n write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem)\n }\n /* TODO: configuration support for agnostic behavior */\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vd" }, { "type": "id", "id": "load_width_bytes" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "EMUL_pow" }, { "type": "id", "id": "num_elem" } ] }, "body": " let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd);\n let tail_ag : agtype = get_vtype_vta();\n\n let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val);\n\n trimmed : bool = false;\n foreach (i from 0 to (num_elem - 1)) {\n if not(trimmed) then {\n if vm_val[i] then { /* active segments */\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = (i * nf + j) * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => {\n if i == 0 then { ext_handle_data_check_error(e); return RETIRE_FAIL }\n else {\n vl = to_bits(sizeof(xlen), i);\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n trimmed = true\n }\n },\n Ext_DataAddr_OK(vaddr) => {\n if check_misaligned(vaddr, width_type) then {\n if i == 0 then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else {\n vl = to_bits(sizeof(xlen), i);\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n trimmed = true\n }\n } else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => {\n if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n else {\n vl = to_bits(sizeof(xlen), i);\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n trimmed = true\n }\n },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),\n MemException(e) => {\n if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n else {\n vl = to_bits(sizeof(xlen), i);\n print_reg(\"CSR vl <- \" ^ BitStr(vl));\n trimmed = true\n }\n }\n }\n }\n }\n }\n }\n }\n } else { /* prestart, masked or tail segments */\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0];\n write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem)\n }\n }\n } else {\n /* if vl is trimmed, elements past the new vl are treated as tail elements */\n if tail_ag == AGNOSTIC then {\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (vd_seg[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0];\n write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem)\n }\n /* TODO: configuration support for agnostic behavior */\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6199, 6208 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6329, 6339 ] }, { "type": "function", "id": "read_vreg_seg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6416, 6429 ] }, { "type": "function", "id": "get_vtype_vta", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6506, 6519 ] }, { "type": "function", "id": "init_masked_result", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6547, 6565 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 9577, 9583 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "not", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6705, 6708 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6891, 6908 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6950, 6954 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 6914, 6921 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7341, 7357 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7417, 7437 ] }, { "type": "function", "id": "E_Load_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7445, 7462 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7578, 7587 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7610, 7612 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7529, 7531 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7534, 7541 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7694, 7707 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7715, 7719 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8133, 8141 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8142, 8146 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8407, 8427 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8568, 8577 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8600, 8602 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8513, 8515 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8518, 8525 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8242, 8262 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8293, 8300 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7806, 7826 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7955, 7964 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7987, 7989 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7904, 7906 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7909, 7916 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7047, 7074 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7184, 7193 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7216, 7218 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7137, 7139 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 7142, 7149 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 8992, 9012 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 9043, 9050 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 9390, 9410 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 9441, 9448 ] } ] }, "process_vlsseg": { "function": { "number": 0, "source": "function process_vlsseg (nf, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) = {\n let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd);\n let rs2_val : int = signed(get_scalar(rs2, sizeof(xlen)));\n\n let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = i * rs2_val + j * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n } else { /* prestart, masked or tail segments */\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0];\n write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem)\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vd" }, { "type": "id", "id": "load_width_bytes" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "EMUL_pow" }, { "type": "id", "id": "num_elem" } ] }, "body": " let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd);\n let rs2_val : int = signed(get_scalar(rs2, sizeof(xlen)));\n\n let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = i * rs2_val + j * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {\n MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n } else { /* prestart, masked or tail segments */\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0];\n write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem)\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 14652, 14661 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 14783, 14793 ] }, { "type": "function", "id": "read_vreg_seg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 14871, 14884 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 14958, 14964 ] }, { "type": "function", "id": "get_scalar", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 14965, 14975 ] }, { "type": "function", "id": "init_masked_result", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15021, 15039 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 16570, 16576 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15336, 15353 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15395, 15399 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15359, 15366 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15564, 15580 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15619, 15639 ] }, { "type": "function", "id": "E_Load_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15647, 15664 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15713, 15726 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15734, 15738 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15904, 15912 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15913, 15917 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 16135, 16155 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 16011, 16031 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 16062, 16069 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15788, 15808 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15459, 15486 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15196, 15202 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 15205, 15212 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 16457, 16477 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 16508, 16515 ] } ] }, "process_vlxseg": { "function": { "number": 0, "source": "function process_vlxseg (nf, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, mop) = {\n let EMUL_data_reg : int = if EMUL_data_pow <= 0 then 1 else int_power(2, EMUL_data_pow);\n let width_type : word_width = bytes_wordwidth(EEW_data_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_seg : vector('n, dec, bits('f * 'db * 8)) = read_vreg_seg(num_elem, EEW_data_bytes * 8, EMUL_data_pow, nf, vd);\n let vs2_val : vector('n, dec, bits('ib * 8)) = read_vreg(num_elem, EEW_index_bytes * 8, EMUL_index_pow, vs2);\n\n let (result, mask) = init_masked_result(num_elem, nf * EEW_data_bytes * 8, EMUL_data_pow, vd_seg, vm_val);\n\n /* currently mop = 1 (unordered) or 3 (ordered) do the same operations */\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset : int = signed(vs2_val[i]) + j * EEW_data_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, EEW_data_bytes, false, false, false) {\n MemValue(elem) => write_single_element(EEW_data_bytes * 8, i, vd + to_bits(5, j * EMUL_data_reg), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n } else { /* prestart, masked or tail segments */\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (result[i] >> (j * EEW_data_bytes * 8))[(EEW_data_bytes * 8 - 1) .. 0];\n write_single_element(EEW_data_bytes * 8, i, vd + to_bits(5, j * EMUL_data_reg), skipped_elem)\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vd" }, { "type": "id", "id": "EEW_index_bytes" }, { "type": "id", "id": "EEW_data_bytes" }, { "type": "id", "id": "EMUL_index_pow" }, { "type": "id", "id": "EMUL_data_pow" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "num_elem" }, { "type": "id", "id": "mop" } ] }, "body": " let EMUL_data_reg : int = if EMUL_data_pow <= 0 then 1 else int_power(2, EMUL_data_pow);\n let width_type : word_width = bytes_wordwidth(EEW_data_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vd_seg : vector('n, dec, bits('f * 'db * 8)) = read_vreg_seg(num_elem, EEW_data_bytes * 8, EMUL_data_pow, nf, vd);\n let vs2_val : vector('n, dec, bits('ib * 8)) = read_vreg(num_elem, EEW_index_bytes * 8, EMUL_index_pow, vs2);\n\n let (result, mask) = init_masked_result(num_elem, nf * EEW_data_bytes * 8, EMUL_data_pow, vd_seg, vm_val);\n\n /* currently mop = 1 (unordered) or 3 (ordered) do the same operations */\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset : int = signed(vs2_val[i]) + j * EEW_data_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, EEW_data_bytes, false, false, false) {\n MemValue(elem) => write_single_element(EEW_data_bytes * 8, i, vd + to_bits(5, j * EMUL_data_reg), elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n } else { /* prestart, masked or tail segments */\n foreach (j from 0 to (nf - 1)) {\n let skipped_elem = (result[i] >> (j * EEW_data_bytes * 8))[(EEW_data_bytes * 8 - 1) .. 0];\n write_single_element(EEW_data_bytes * 8, i, vd + to_bits(5, j * EMUL_data_reg), skipped_elem)\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 21926, 21935 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22060, 22070 ] }, { "type": "function", "id": "read_vreg_seg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22149, 22162 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22266, 22275 ] }, { "type": "function", "id": "init_masked_result", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22353, 22371 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23992, 23998 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22703, 22709 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22758, 22775 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22817, 22821 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22781, 22788 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22986, 23002 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23041, 23061 ] }, { "type": "function", "id": "E_Load_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23069, 23086 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23135, 23148 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23156, 23160 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23326, 23334 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23335, 23339 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23558, 23578 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23431, 23451 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23480, 23487 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23210, 23230 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22881, 22908 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22607, 22613 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 22616, 22623 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23876, 23896 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 23925, 23932 ] } ] }, "process_vm": { "function": { "number": 0, "source": "function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = {\n let width_type : word_width = BYTE;\n let start_element = get_start_element();\n let vd_or_vs3_val : vector('n, dec, bits(8)) = read_vreg(num_elem, 8, 0, vd_or_vs3);\n\n foreach (i from start_element to (num_elem - 1)) {\n if i < evl then { /* active elements */\n vstart = to_bits(16, i);\n if op == VLM then { /* load */\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), i), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, 1, false, false, false) {\n MemValue(elem) => write_single_element(8, i, vd_or_vs3, elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n } else if op == VSM then { /* store */\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), i), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, 1, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let res : MemoryOpResult(bool) = mem_write_value(paddr, 1, vd_or_vs3_val[i], false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n } else { /* tail elements for mask load, always with agnostic policy */\n if op == VLM then {\n write_single_element(8, i, vd_or_vs3, vd_or_vs3_val[i])\n /* TODO: configuration support for agnostic behavior */\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vd_or_vs3" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "num_elem" }, { "type": "id", "id": "evl" }, { "type": "id", "id": "op" } ] }, "body": " let width_type : word_width = BYTE;\n let start_element = get_start_element();\n let vd_or_vs3_val : vector('n, dec, bits(8)) = read_vreg(num_elem, 8, 0, vd_or_vs3);\n\n foreach (i from start_element to (num_elem - 1)) {\n if i < evl then { /* active elements */\n vstart = to_bits(16, i);\n if op == VLM then { /* load */\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), i), Read(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Read(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n match mem_read(Read(Data), paddr, 1, false, false, false) {\n MemValue(elem) => write_single_element(8, i, vd_or_vs3, elem),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n } else if op == VSM then { /* store */\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), i), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, 1, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let res : MemoryOpResult(bool) = mem_write_value(paddr, 1, vd_or_vs3_val[i], false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n } else { /* tail elements for mask load, always with agnostic policy */\n if op == VLM then {\n write_single_element(8, i, vd_or_vs3, vd_or_vs3_val[i])\n /* TODO: configuration support for agnostic behavior */\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "get_start_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41237, 41254 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41307, 41316 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 43995, 44001 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41525, 41542 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41574, 41578 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41548, 41555 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41743, 41759 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41798, 41818 ] }, { "type": "function", "id": "E_Load_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41826, 41843 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41892, 41905 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41913, 41917 ] }, { "type": "function", "id": "mem_read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42083, 42091 ] }, { "type": "function", "id": "Read", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42092, 42096 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42260, 42280 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42175, 42195 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41967, 41987 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41638, 41665 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42430, 42447 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42479, 42484 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42453, 42460 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42649, 42665 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42704, 42724 ] }, { "type": "function", "id": "E_SAMO_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42732, 42749 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42798, 42811 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42819, 42824 ] }, { "type": "function", "id": "mem_write_ea", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 43019, 43031 ] }, { "type": "function", "id": "mem_write_value", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 43277, 43292 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 43582, 43602 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 43463, 43477 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 43135, 43155 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42874, 42894 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 42544, 42571 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41449, 41455 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 41458, 41465 ] }, { "type": "function", "id": "write_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 43853, 43873 ] } ] }, "process_vsre": { "function": { "number": 0, "source": "function process_vsre (nf, load_width_bytes, rs1, vs3, elem_per_reg) = {\n let width_type : word_width = BYTE;\n let start_element = get_start_element();\n if start_element >= nf * elem_per_reg then return RETIRE_SUCCESS; /* no elements are written if vstart >= evl */\n let elem_to_align : int = start_element % elem_per_reg;\n cur_field : int = start_element / elem_per_reg;\n cur_elem : int = start_element;\n\n if elem_to_align > 0 then {\n foreach (i from elem_to_align to (elem_per_reg - 1)) {\n vstart = to_bits(16, cur_elem);\n let elem_offset : int = cur_elem * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let elem : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, cur_field));\n let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem, false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n };\n cur_elem = cur_elem + 1\n };\n cur_field = cur_field + 1\n };\n\n foreach (j from cur_field to (nf - 1)) {\n let vs3_val : vector('n, dec, bits('b * 8)) = read_vreg(elem_per_reg, load_width_bytes * 8, 0, vs3 + to_bits(5, j));\n foreach (i from 0 to (elem_per_reg - 1)) {\n vstart = to_bits(16, cur_elem);\n let elem_offset = cur_elem * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, vs3_val[i], false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n };\n cur_elem = cur_elem + 1\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "load_width_bytes" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs3" }, { "type": "id", "id": "elem_per_reg" } ] }, "body": " let width_type : word_width = BYTE;\n let start_element = get_start_element();\n if start_element >= nf * elem_per_reg then return RETIRE_SUCCESS; /* no elements are written if vstart >= evl */\n let elem_to_align : int = start_element % elem_per_reg;\n cur_field : int = start_element / elem_per_reg;\n cur_elem : int = start_element;\n\n if elem_to_align > 0 then {\n foreach (i from elem_to_align to (elem_per_reg - 1)) {\n vstart = to_bits(16, cur_elem);\n let elem_offset : int = cur_elem * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let elem : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, cur_field));\n let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem, false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n };\n cur_elem = cur_elem + 1\n };\n cur_field = cur_field + 1\n };\n\n foreach (j from cur_field to (nf - 1)) {\n let vs3_val : vector('n, dec, bits('b * 8)) = read_vreg(elem_per_reg, load_width_bytes * 8, 0, vs3 + to_bits(5, j));\n foreach (i from 0 to (elem_per_reg - 1)) {\n vstart = to_bits(16, cur_elem);\n let elem_offset = cur_elem * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, vs3_val[i], false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n };\n cur_elem = cur_elem + 1\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "get_start_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 36365, 36382 ] }, { "type": "function", "id": "emod_int", "file": "model/prelude.sail", "loc": [ 2111, 2119 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39979, 39985 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38418, 38427 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38473, 38480 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38639, 38656 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38698, 38703 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38662, 38669 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38862, 38878 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38915, 38935 ] }, { "type": "function", "id": "E_SAMO_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38943, 38960 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39007, 39020 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39028, 39033 ] }, { "type": "function", "id": "mem_write_ea", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39222, 39234 ] }, { "type": "function", "id": "mem_write_value", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39487, 39502 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39793, 39813 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39676, 39690 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39349, 39369 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 39081, 39101 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38761, 38788 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38542, 38548 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38551, 38558 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 36843, 36860 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 36902, 36907 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 36866, 36873 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37066, 37082 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37119, 37139 ] }, { "type": "function", "id": "E_SAMO_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37147, 37164 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37211, 37224 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37232, 37237 ] }, { "type": "function", "id": "mem_write_ea", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37426, 37438 ] }, { "type": "function", "id": "read_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37684, 37703 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37735, 37742 ] }, { "type": "function", "id": "mem_write_value", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37810, 37825 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 38110, 38130 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37993, 38007 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37553, 37573 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 37285, 37305 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 36965, 36992 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 36740, 36746 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 36749, 36756 ] } ] }, "process_vsseg": { "function": { "number": 0, "source": "function process_vsseg (nf, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) = {\n let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs3_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vs3);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_pow, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if vm_val[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = (i * nf + j) * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, j * EMUL_reg));\n let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem_val, false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs3" }, { "type": "id", "id": "load_width_bytes" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "EMUL_pow" }, { "type": "id", "id": "num_elem" } ] }, "body": " let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs3_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vs3);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_pow, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if vm_val[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = (i * nf + j) * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, j * EMUL_reg));\n let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem_val, false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11063, 11072 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11194, 11204 ] }, { "type": "function", "id": "read_vreg_seg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11282, 11295 ] }, { "type": "function", "id": "init_masked_source", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11388, 11406 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 13154, 13160 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11667, 11684 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11726, 11731 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11690, 11697 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11896, 11912 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11951, 11971 ] }, { "type": "function", "id": "E_SAMO_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11979, 11996 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12045, 12058 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12066, 12071 ] }, { "type": "function", "id": "mem_write_ea", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12266, 12278 ] }, { "type": "function", "id": "read_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12536, 12555 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12587, 12594 ] }, { "type": "function", "id": "mem_write_value", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12667, 12682 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12979, 12999 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12860, 12874 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12397, 12417 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 12121, 12141 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11791, 11818 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11530, 11536 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 11539, 11546 ] } ] }, "process_vssseg": { "function": { "number": 0, "source": "function process_vssseg (nf, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) = {\n let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs3_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vs3);\n let rs2_val : int = signed(get_scalar(rs2, sizeof(xlen)));\n let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_pow, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = i * rs2_val + j * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, j * EMUL_reg));\n let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem_val, false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs3" }, { "type": "id", "id": "load_width_bytes" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "EMUL_pow" }, { "type": "id", "id": "num_elem" } ] }, "body": " let EMUL_reg : int = if EMUL_pow <= 0 then 1 else int_power(2, EMUL_pow);\n let width_type : word_width = bytes_wordwidth(load_width_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs3_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vs3);\n let rs2_val : int = signed(get_scalar(rs2, sizeof(xlen)));\n let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_pow, vm_val);\n\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset = i * rs2_val + j * load_width_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, j * EMUL_reg));\n let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem_val, false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18117, 18126 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18248, 18258 ] }, { "type": "function", "id": "read_vreg_seg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18336, 18349 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18424, 18430 ] }, { "type": "function", "id": "get_scalar", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18431, 18441 ] }, { "type": "function", "id": "init_masked_source", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18503, 18521 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 20270, 20276 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18783, 18800 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18842, 18847 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18806, 18813 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19012, 19028 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19067, 19087 ] }, { "type": "function", "id": "E_SAMO_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19095, 19112 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19161, 19174 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19182, 19187 ] }, { "type": "function", "id": "mem_write_ea", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19382, 19394 ] }, { "type": "function", "id": "read_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19652, 19671 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19703, 19710 ] }, { "type": "function", "id": "mem_write_value", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19783, 19798 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 20095, 20115 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19976, 19990 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19513, 19533 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 19237, 19257 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18907, 18934 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18643, 18649 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 18652, 18659 ] } ] }, "process_vsxseg": { "function": { "number": 0, "source": "function process_vsxseg (nf, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, mop) = {\n let EMUL_data_reg : int = if EMUL_data_pow <= 0 then 1 else int_power(2, EMUL_data_pow);\n let width_type : word_width = bytes_wordwidth(EEW_data_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs3_seg : vector('n, dec, bits('f * 'db * 8)) = read_vreg_seg(num_elem, EEW_data_bytes * 8, EMUL_data_pow, nf, vs3);\n let vs2_val : vector('n, dec, bits('ib * 8)) = read_vreg(num_elem, EEW_index_bytes * 8, EMUL_index_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_data_pow, vm_val);\n\n /* currently mop = 1 (unordered) or 3 (ordered) do the same operations */\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset : int = signed(vs2_val[i]) + j * EEW_data_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, EEW_data_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let elem_val : bits('db * 8) = read_single_element(EEW_data_bytes * 8, i, vs3 + to_bits(5, j * EMUL_data_reg));\n let res : MemoryOpResult(bool) = mem_write_value(paddr, EEW_data_bytes, elem_val, false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs3" }, { "type": "id", "id": "EEW_index_bytes" }, { "type": "id", "id": "EEW_data_bytes" }, { "type": "id", "id": "EMUL_index_pow" }, { "type": "id", "id": "EMUL_data_pow" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "num_elem" }, { "type": "id", "id": "mop" } ] }, "body": " let EMUL_data_reg : int = if EMUL_data_pow <= 0 then 1 else int_power(2, EMUL_data_pow);\n let width_type : word_width = bytes_wordwidth(EEW_data_bytes);\n let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);\n let vs3_seg : vector('n, dec, bits('f * 'db * 8)) = read_vreg_seg(num_elem, EEW_data_bytes * 8, EMUL_data_pow, nf, vs3);\n let vs2_val : vector('n, dec, bits('ib * 8)) = read_vreg(num_elem, EEW_index_bytes * 8, EMUL_index_pow, vs2);\n let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_data_pow, vm_val);\n\n /* currently mop = 1 (unordered) or 3 (ordered) do the same operations */\n foreach (i from 0 to (num_elem - 1)) {\n if mask[i] then { /* active segments */\n vstart = to_bits(16, i);\n foreach (j from 0 to (nf - 1)) {\n let elem_offset : int = signed(vs2_val[i]) + j * EEW_data_bytes;\n match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) {\n Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL },\n Ext_DataAddr_OK(vaddr) =>\n if check_misaligned(vaddr, width_type)\n then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }\n else match translateAddr(vaddr, Write(Data)) {\n TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n TR_Address(paddr, _) => {\n let eares : MemoryOpResult(unit) = mem_write_ea(paddr, EEW_data_bytes, false, false, false);\n match (eares) {\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },\n MemValue(_) => {\n let elem_val : bits('db * 8) = read_single_element(EEW_data_bytes * 8, i, vs3 + to_bits(5, j * EMUL_data_reg));\n let res : MemoryOpResult(bool) = mem_write_value(paddr, EEW_data_bytes, elem_val, false, false, false);\n match (res) {\n MemValue(true) => (),\n MemValue(false) => internal_error(__FILE__, __LINE__, \"store got false from mem_write_value\"),\n MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }\n }\n }\n }\n }\n }\n }\n }\n }\n };\n\n vstart = zeros();\n RETIRE_SUCCESS" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27146, 27155 ] }, { "type": "function", "id": "read_vmask", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27280, 27290 ] }, { "type": "function", "id": "read_vreg_seg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27369, 27382 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27487, 27496 ] }, { "type": "function", "id": "init_masked_source", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27590, 27608 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 29449, 29455 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27907, 27913 ] }, { "type": "function", "id": "ext_data_get_addr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27962, 27979 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28021, 28026 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27985, 27992 ] }, { "type": "function", "id": "check_misaligned", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28191, 28207 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28246, 28266 ] }, { "type": "function", "id": "E_SAMO_Addr_Align", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28274, 28291 ] }, { "type": "function", "id": "translateAddr", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28340, 28353 ] }, { "type": "function", "id": "Write", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28361, 28366 ] }, { "type": "function", "id": "mem_write_ea", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28561, 28573 ] }, { "type": "function", "id": "read_single_element", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28830, 28849 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28879, 28886 ] }, { "type": "function", "id": "mem_write_value", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28964, 28979 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 29274, 29294 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 29155, 29169 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28690, 28710 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28416, 28436 ] }, { "type": "function", "id": "ext_handle_data_check_error", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 28086, 28113 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27811, 27817 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_mem.sail", "loc": [ 27820, 27827 ] } ] }, "pt_walk": { "function": { "number": 0, "source": "function pt_walk(sv_params,\n va,\n ac,\n priv,\n mxr,\n do_sum,\n pt_base,\n level,\n global,\n ext_ptw) = {\n let vpn_j = vpn_j_of_va(sv_params, va, level);\n let pte_offset = vpn_j << sv_params.log_pte_size_bytes;\n let pte_addr = pt_base + pte_offset;\n\n // In Sv32, physical addrs are actually 34 bits, not XLEN(=32) bits.\n // Below, 'pte_phys_addr' is XLEN bits because it's an arg to\n // 'mem_read_priv()' [riscv_mem.sail] where it's declared as xlenbits.\n // That def and this use need to be fixed together (TODO)\n let pte_phys_addr : xlenbits = pte_addr[(sizeof(xlen) - 1) .. 0];\n\n // Read this-level PTE from mem\n let mem_result = mem_read_priv(Read(Data), // AccessType\n Supervisor, // Privilege\n pte_phys_addr,\n 8, // atom (8)\n false, // aq\n false, // rl\n false); // res\n\n match mem_result {\n MemException(_) => PTW_Failure(PTW_Access(), ext_ptw),\n MemValue(pte) => {\n let pte_flags = Mk_PTE_Flags(pte[7 .. 0]);\n if pte_is_invalid(pte_flags) then\n PTW_Failure(PTW_Invalid_PTE(), ext_ptw)\n else {\n let ppns : bits(64) = PPNs_of_PTE(sv_params, pte);\n let global' = global | (pte_flags[G] == 0b1);\n if pte_is_ptr(pte_flags) then {\n // Non-Leaf PTE\n if level > 0 then {\n // follow the pointer to walk next level\n let pt_base' : bits(64) = ppns << pagesize_bits;\n let level' = level - 1;\n pt_walk(sv_params, va, ac, priv, mxr, do_sum,\n pt_base', level', global', ext_ptw)\n }\n else\n // level 0 PTE, but contains a pointer instead of a leaf\n PTW_Failure(PTW_Invalid_PTE(), ext_ptw)\n }\n else {\n // Leaf PTE\n let ext_pte = msbs_of_PTE(sv_params, pte);\n let pte_check = check_PTE_permission(ac, priv, mxr, do_sum, pte_flags,\n ext_pte, ext_ptw);\n match pte_check {\n PTE_Check_Failure(ext_ptw, ext_ptw_fail) =>\n PTW_Failure(ext_get_ptw_error(ext_ptw_fail), ext_ptw),\n PTE_Check_Success(ext_ptw) =>\n if level > 0 then {\n // Superpage; construct mask for lower-level PPNs from the PTE\n let mask_bits = level * sv_params.pte_PPN_j_size_bits;\n // Clear the lowest `mask_bits` bits.\n let ppns_masked = (ppns >> mask_bits) << mask_bits;\n if not(ppns == ppns_masked) then\n // misaligned superpage mapping\n PTW_Failure(PTW_Misaligned(), ext_ptw)\n else {\n // Compose final PA in superpage:\n // Superpage PPN + lower VPNs + pagesize_bits page-offset\n let mask : bits(64) = ~ (ones() << mask_bits);\n let ppn = ppns | (vpns_of_va(sv_params, va) & mask);\n let pa = (ppn << pagesize_bits) | zero_extend(offset_of_va(va));\n PTW_Success(pa, pte, pte_addr, level, global', ext_ptw)\n }\n }\n else {\n let pa = (ppns << pagesize_bits) | zero_extend(offset_of_va(va));\n PTW_Success(pa, pte, pte_addr, level, global', ext_ptw)\n }\n }\n }\n }\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "va" }, { "type": "id", "id": "ac" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "mxr" }, { "type": "id", "id": "do_sum" }, { "type": "id", "id": "pt_base" }, { "type": "id", "id": "level" }, { "type": "id", "id": "global" }, { "type": "id", "id": "ext_ptw" } ] }, "body": " let vpn_j = vpn_j_of_va(sv_params, va, level);\n let pte_offset = vpn_j << sv_params.log_pte_size_bytes;\n let pte_addr = pt_base + pte_offset;\n\n // In Sv32, physical addrs are actually 34 bits, not XLEN(=32) bits.\n // Below, 'pte_phys_addr' is XLEN bits because it's an arg to\n // 'mem_read_priv()' [riscv_mem.sail] where it's declared as xlenbits.\n // That def and this use need to be fixed together (TODO)\n let pte_phys_addr : xlenbits = pte_addr[(sizeof(xlen) - 1) .. 0];\n\n // Read this-level PTE from mem\n let mem_result = mem_read_priv(Read(Data), // AccessType\n Supervisor, // Privilege\n pte_phys_addr,\n 8, // atom (8)\n false, // aq\n false, // rl\n false); // res\n\n match mem_result {\n MemException(_) => PTW_Failure(PTW_Access(), ext_ptw),\n MemValue(pte) => {\n let pte_flags = Mk_PTE_Flags(pte[7 .. 0]);\n if pte_is_invalid(pte_flags) then\n PTW_Failure(PTW_Invalid_PTE(), ext_ptw)\n else {\n let ppns : bits(64) = PPNs_of_PTE(sv_params, pte);\n let global' = global | (pte_flags[G] == 0b1);\n if pte_is_ptr(pte_flags) then {\n // Non-Leaf PTE\n if level > 0 then {\n // follow the pointer to walk next level\n let pt_base' : bits(64) = ppns << pagesize_bits;\n let level' = level - 1;\n pt_walk(sv_params, va, ac, priv, mxr, do_sum,\n pt_base', level', global', ext_ptw)\n }\n else\n // level 0 PTE, but contains a pointer instead of a leaf\n PTW_Failure(PTW_Invalid_PTE(), ext_ptw)\n }\n else {\n // Leaf PTE\n let ext_pte = msbs_of_PTE(sv_params, pte);\n let pte_check = check_PTE_permission(ac, priv, mxr, do_sum, pte_flags,\n ext_pte, ext_ptw);\n match pte_check {\n PTE_Check_Failure(ext_ptw, ext_ptw_fail) =>\n PTW_Failure(ext_get_ptw_error(ext_ptw_fail), ext_ptw),\n PTE_Check_Success(ext_ptw) =>\n if level > 0 then {\n // Superpage; construct mask for lower-level PPNs from the PTE\n let mask_bits = level * sv_params.pte_PPN_j_size_bits;\n // Clear the lowest `mask_bits` bits.\n let ppns_masked = (ppns >> mask_bits) << mask_bits;\n if not(ppns == ppns_masked) then\n // misaligned superpage mapping\n PTW_Failure(PTW_Misaligned(), ext_ptw)\n else {\n // Compose final PA in superpage:\n // Superpage PPN + lower VPNs + pagesize_bits page-offset\n let mask : bits(64) = ~ (ones() << mask_bits);\n let ppn = ppns | (vpns_of_va(sv_params, va) & mask);\n let pa = (ppn << pagesize_bits) | zero_extend(offset_of_va(va));\n PTW_Success(pa, pte, pte_addr, level, global', ext_ptw)\n }\n }\n else {\n let pa = (ppns << pagesize_bits) | zero_extend(offset_of_va(va));\n PTW_Success(pa, pte, pte_addr, level, global', ext_ptw)\n }\n }\n }\n }\n }\n }" }, "links": [ { "type": "function", "id": "vpn_j_of_va", "file": "model/riscv_vmem.sail", "loc": [ 4105, 4116 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "mem_read_priv", "file": "model/riscv_vmem.sail", "loc": [ 4630, 4643 ] }, { "type": "function", "id": "Read", "file": "model/riscv_vmem.sail", "loc": [ 4644, 4648 ] }, { "type": "function", "id": "Mk_PTE_Flags", "file": "model/riscv_vmem.sail", "loc": [ 5193, 5205 ] }, { "type": "function", "id": "pte_is_invalid", "file": "model/riscv_vmem.sail", "loc": [ 5229, 5243 ] }, { "type": "function", "id": "PTW_Failure", "file": "model/riscv_vmem.sail", "loc": [ 5268, 5279 ] }, { "type": "function", "id": "PTW_Invalid_PTE", "file": "model/riscv_vmem.sail", "loc": [ 5280, 5295 ] }, { "type": "function", "id": "PPNs_of_PTE", "file": "model/riscv_vmem.sail", "loc": [ 5351, 5362 ] }, { "type": "function", "id": "pte_is_ptr", "file": "model/riscv_vmem.sail", "loc": [ 5453, 5463 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "pt_walk", "file": "model/riscv_vmem.sail", "loc": [ 5713, 5720 ] }, { "type": "function", "id": "PTW_Failure", "file": "model/riscv_vmem.sail", "loc": [ 5923, 5934 ] }, { "type": "function", "id": "PTW_Invalid_PTE", "file": "model/riscv_vmem.sail", "loc": [ 5935, 5950 ] }, { "type": "function", "id": "msbs_of_PTE", "file": "model/riscv_vmem.sail", "loc": [ 6036, 6047 ] }, { "type": "function", "id": "check_PTE_permission", "file": "model/riscv_vmem.sail", "loc": [ 6091, 6111 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "not", "file": "model/riscv_vmem.sail", "loc": [ 6732, 6735 ] }, { "type": "function", "id": "PTW_Failure", "file": "model/riscv_vmem.sail", "loc": [ 6830, 6841 ] }, { "type": "function", "id": "PTW_Misaligned", "file": "model/riscv_vmem.sail", "loc": [ 6842, 6856 ] }, { "type": "function", "id": "not_vec", "file": "model/prelude.sail", "loc": [ 997, 1004 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "ones", "file": "model/riscv_vmem.sail", "loc": [ 7063, 7067 ] }, { "type": "function", "id": "vpns_of_va", "file": "model/riscv_vmem.sail", "loc": [ 7121, 7131 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 7209, 7220 ] }, { "type": "function", "id": "offset_of_va", "file": "model/riscv_vmem.sail", "loc": [ 7221, 7233 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "PTW_Success", "file": "model/riscv_vmem.sail", "loc": [ 7258, 7269 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 7420, 7431 ] }, { "type": "function", "id": "offset_of_va", "file": "model/riscv_vmem.sail", "loc": [ 7432, 7444 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "PTW_Success", "file": "model/riscv_vmem.sail", "loc": [ 7467, 7478 ] }, { "type": "function", "id": "PTW_Failure", "file": "model/riscv_vmem.sail", "loc": [ 6310, 6321 ] }, { "type": "function", "id": "ext_get_ptw_error", "file": "model/riscv_vmem.sail", "loc": [ 6322, 6339 ] }, { "type": "function", "id": "PTW_Failure", "file": "model/riscv_vmem.sail", "loc": [ 5110, 5121 ] }, { "type": "function", "id": "PTW_Access", "file": "model/riscv_vmem.sail", "loc": [ 5122, 5132 ] } ] }, "pte_is_invalid": { "function": { "number": 0, "source": "function pte_is_invalid(pte_flags : PTE_Flags) -> bool = (pte_flags[V] == 0b0)\n | ((pte_flags[W] == 0b1)\n & (pte_flags[R] == 0b0))", "pattern": { "type": "id", "id": "pte_flags" }, "body": "(pte_flags[V] == 0b0)\n | ((pte_flags[W] == 0b1)\n & (pte_flags[R] == 0b0))" } }, "pte_is_ptr": { "function": { "number": 0, "source": "function pte_is_ptr(pte_flags : PTE_Flags) -> bool = (pte_flags[X] == 0b0)\n & (pte_flags[W] == 0b0)\n & (pte_flags[R] == 0b0)", "pattern": { "type": "id", "id": "pte_flags" }, "body": "(pte_flags[X] == 0b0)\n & (pte_flags[W] == 0b0)\n & (pte_flags[R] == 0b0)" } }, "ptw_error_to_str": { "function": { "number": 0, "source": "function ptw_error_to_str(e : PTW_Error) -> string = {\n match e {\n PTW_Invalid_Addr() => \"invalid-source-addr\",\n PTW_Access() => \"mem-access-error\",\n PTW_Invalid_PTE() => \"invalid-pte\",\n PTW_No_Permission() => \"no-permission\",\n PTW_Misaligned() => \"misaligned-superpage\",\n PTW_PTE_Update() => \"pte-update-needed\",\n PTW_Ext_Error(e) => \"extension-error\"\n }\n}", "pattern": { "type": "id", "id": "e" }, "body": " match e {\n PTW_Invalid_Addr() => \"invalid-source-addr\",\n PTW_Access() => \"mem-access-error\",\n PTW_Invalid_PTE() => \"invalid-pte\",\n PTW_No_Permission() => \"no-permission\",\n PTW_Misaligned() => \"misaligned-superpage\",\n PTW_PTE_Update() => \"pte-update-needed\",\n PTW_Ext_Error(e) => \"extension-error\"\n }" } }, "rF": { "function": { "number": 0, "source": "function rF r = {\n assert(sys_enable_fdext());\n let v : fregtype =\n match r {\n 0 => f0,\n 1 => f1,\n 2 => f2,\n 3 => f3,\n 4 => f4,\n 5 => f5,\n 6 => f6,\n 7 => f7,\n 8 => f8,\n 9 => f9,\n 10 => f10,\n 11 => f11,\n 12 => f12,\n 13 => f13,\n 14 => f14,\n 15 => f15,\n 16 => f16,\n 17 => f17,\n 18 => f18,\n 19 => f19,\n 20 => f20,\n 21 => f21,\n 22 => f22,\n 23 => f23,\n 24 => f24,\n 25 => f25,\n 26 => f26,\n 27 => f27,\n 28 => f28,\n 29 => f29,\n 30 => f30,\n 31 => f31,\n _ => {assert(false, \"invalid floating point register number\"); zero_freg}\n };\n fregval_from_freg(v)\n}", "pattern": { "type": "id", "id": "r" }, "body": "function rF r = {\n assert(sys_enable_fdext());\n let v : fregtype =\n match r {\n 0 => f0,\n 1 => f1,\n 2 => f2,\n 3 => f3,\n 4 => f4,\n 5 => f5,\n 6 => f6,\n 7 => f7,\n 8 => f8,\n 9 => f9,\n 10 => f10,\n 11 => f11,\n 12 => f12,\n 13 => f13,\n 14 => f14,\n 15 => f15,\n 16 => f16,\n 17 => f17,\n 18 => f18,\n 19 => f19,\n 20 => f20,\n 21 => f21,\n 22 => f22,\n 23 => f23,\n 24 => f24,\n 25 => f25,\n 26 => f26,\n 27 => f27,\n 28 => f28,\n 29 => f29,\n 30 => f30,\n 31 => f31,\n _ => {assert(false, \"invalid floating point register number\"); zero_freg}\n };\n fregval_from_freg(v)" }, "links": [ { "type": "register", "id": "f31", "file": "model/riscv_fdext_regs.sail", "loc": [ 4715, 4718 ] }, { "type": "register", "id": "f30", "file": "model/riscv_fdext_regs.sail", "loc": [ 4698, 4701 ] }, { "type": "register", "id": "f29", "file": "model/riscv_fdext_regs.sail", "loc": [ 4681, 4684 ] }, { "type": "register", "id": "f28", "file": "model/riscv_fdext_regs.sail", "loc": [ 4664, 4667 ] }, { "type": "register", "id": "f27", "file": "model/riscv_fdext_regs.sail", "loc": [ 4647, 4650 ] }, { "type": "register", "id": "f26", "file": "model/riscv_fdext_regs.sail", "loc": [ 4630, 4633 ] }, { "type": "register", "id": "f25", "file": "model/riscv_fdext_regs.sail", "loc": [ 4613, 4616 ] }, { "type": "register", "id": "f24", "file": "model/riscv_fdext_regs.sail", "loc": [ 4596, 4599 ] }, { "type": "register", "id": "f23", "file": "model/riscv_fdext_regs.sail", "loc": [ 4579, 4582 ] }, { "type": "register", "id": "f22", "file": "model/riscv_fdext_regs.sail", "loc": [ 4562, 4565 ] }, { "type": "register", "id": "f21", "file": "model/riscv_fdext_regs.sail", "loc": [ 4545, 4548 ] }, { "type": "register", "id": "f20", "file": "model/riscv_fdext_regs.sail", "loc": [ 4528, 4531 ] }, { "type": "register", "id": "f19", "file": "model/riscv_fdext_regs.sail", "loc": [ 4511, 4514 ] }, { "type": "register", "id": "f18", "file": "model/riscv_fdext_regs.sail", "loc": [ 4494, 4497 ] }, { "type": "register", "id": "f17", "file": "model/riscv_fdext_regs.sail", "loc": [ 4477, 4480 ] }, { "type": "register", "id": "f16", "file": "model/riscv_fdext_regs.sail", "loc": [ 4460, 4463 ] }, { "type": "register", "id": "f15", "file": "model/riscv_fdext_regs.sail", "loc": [ 4443, 4446 ] }, { "type": "register", "id": "f14", "file": "model/riscv_fdext_regs.sail", "loc": [ 4426, 4429 ] }, { "type": "register", "id": "f13", "file": "model/riscv_fdext_regs.sail", "loc": [ 4409, 4412 ] }, { "type": "register", "id": "f12", "file": "model/riscv_fdext_regs.sail", "loc": [ 4392, 4395 ] }, { "type": "register", "id": "f11", "file": "model/riscv_fdext_regs.sail", "loc": [ 4375, 4378 ] }, { "type": "register", "id": "f10", "file": "model/riscv_fdext_regs.sail", "loc": [ 4358, 4361 ] }, { "type": "register", "id": "f9", "file": "model/riscv_fdext_regs.sail", "loc": [ 4342, 4344 ] }, { "type": "register", "id": "f8", "file": "model/riscv_fdext_regs.sail", "loc": [ 4327, 4329 ] }, { "type": "register", "id": "f7", "file": "model/riscv_fdext_regs.sail", "loc": [ 4312, 4314 ] }, { "type": "register", "id": "f6", "file": "model/riscv_fdext_regs.sail", "loc": [ 4297, 4299 ] }, { "type": "register", "id": "f5", "file": "model/riscv_fdext_regs.sail", "loc": [ 4282, 4284 ] }, { "type": "register", "id": "f4", "file": "model/riscv_fdext_regs.sail", "loc": [ 4267, 4269 ] }, { "type": "register", "id": "f3", "file": "model/riscv_fdext_regs.sail", "loc": [ 4252, 4254 ] }, { "type": "register", "id": "f2", "file": "model/riscv_fdext_regs.sail", "loc": [ 4237, 4239 ] }, { "type": "register", "id": "f1", "file": "model/riscv_fdext_regs.sail", "loc": [ 4222, 4224 ] }, { "type": "register", "id": "f0", "file": "model/riscv_fdext_regs.sail", "loc": [ 4207, 4209 ] }, { "type": "function", "id": "fregval_from_freg", "file": "model/riscv_fdext_regs.sail", "loc": [ 4810, 4827 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 4140, 4156 ] } ] }, "rF_D": { "function": { "number": 0, "source": "function rF_D(i) = {\n assert(sizeof(flen) >= 64);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n F(i)\n}", "pattern": { "type": "id", "id": "i" }, "body": "function rF_D(i) = {\n assert(sizeof(flen) >= 64);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n F(i)" }, "links": [ { "type": "function", "id": "rF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6032, 6039 ] }, { "type": "function", "id": "not", "file": "model/riscv_fdext_regs.sail", "loc": [ 6845, 6848 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 6849, 6865 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 6824, 6840 ] } ] }, "rF_H": { "function": { "number": 0, "source": "function rF_H(i) = {\n assert(sizeof(flen) >= 16);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n nan_unbox(F(i))\n}", "pattern": { "type": "id", "id": "i" }, "body": "function rF_H(i) = {\n assert(sizeof(flen) >= 16);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n nan_unbox(F(i))" }, "links": [ { "type": "function", "id": "nan_unbox_H", "file": "model/riscv_fdext_regs.sail", "loc": [ 2828, 2839 ] }, { "type": "function", "id": "rF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6032, 6039 ] }, { "type": "function", "id": "not", "file": "model/riscv_fdext_regs.sail", "loc": [ 6171, 6174 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 6175, 6191 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 6150, 6166 ] } ] }, "rF_S": { "function": { "number": 0, "source": "function rF_S(i) = {\n assert(sizeof(flen) >= 32);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n nan_unbox(F(i))\n}", "pattern": { "type": "id", "id": "i" }, "body": "function rF_S(i) = {\n assert(sizeof(flen) >= 32);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n nan_unbox(F(i))" }, "links": [ { "type": "function", "id": "nan_unbox_S", "file": "model/riscv_fdext_regs.sail", "loc": [ 2841, 2852 ] }, { "type": "function", "id": "rF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6032, 6039 ] }, { "type": "function", "id": "not", "file": "model/riscv_fdext_regs.sail", "loc": [ 6508, 6511 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 6512, 6528 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 6487, 6503 ] } ] }, "rF_bits": { "function": { "number": 0, "source": "function rF_bits(i: bits(5)) -> flenbits = rF(unsigned(i))", "pattern": { "type": "id", "id": "i" }, "body": "rF(unsigned(i))" }, "links": [ { "type": "function", "id": "rF", "file": "model/riscv_fdext_regs.sail", "loc": [ 5916, 5918 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_fdext_regs.sail", "loc": [ 5919, 5927 ] } ] }, "rF_or_X_D": { "function": { "number": 0, "source": "function rF_or_X_D(i) = {\n assert(sizeof(flen) >= 64);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_D(i)\n else if sizeof(xlen) >= 64\n then X(i)[63..0]\n else {\n assert(i[0] == bitzero);\n if i == zeros() then zeros() else X(i + 1) @ X(i)\n }\n}", "pattern": { "type": "id", "id": "i" }, "body": "function rF_or_X_D(i) = {\n assert(sizeof(flen) >= 64);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_D(i)\n else if sizeof(xlen) >= 64\n then X(i)[63..0]\n else {\n assert(i[0] == bitzero);\n if i == zeros() then zeros() else X(i + 1) @ X(i)\n }" }, "links": [ { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 7704, 7720 ] }, { "type": "function", "id": "rF_D", "file": "model/riscv_fdext_regs.sail", "loc": [ 7127, 7131 ] }, { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] }, { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 7676, 7692 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 7654, 7670 ] } ] }, "rF_or_X_H": { "function": { "number": 0, "source": "function rF_or_X_H(i) = {\n assert(sizeof(flen) >= 16);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_H(i)\n else X(i)[15..0]\n}", "pattern": { "type": "id", "id": "i" }, "body": "function rF_or_X_H(i) = {\n assert(sizeof(flen) >= 16);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_H(i)\n else X(i)[15..0]" }, "links": [ { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 7292, 7308 ] }, { "type": "function", "id": "rF_H", "file": "model/riscv_fdext_regs.sail", "loc": [ 7067, 7071 ] }, { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 7264, 7280 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 7242, 7258 ] } ] }, "rF_or_X_S": { "function": { "number": 0, "source": "function rF_or_X_S(i) = {\n assert(sizeof(flen) >= 32);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_S(i)\n else X(i)[31..0]\n}", "pattern": { "type": "id", "id": "i" }, "body": "function rF_or_X_S(i) = {\n assert(sizeof(flen) >= 32);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_S(i)\n else X(i)[31..0]" }, "links": [ { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 7498, 7514 ] }, { "type": "function", "id": "rF_S", "file": "model/riscv_fdext_regs.sail", "loc": [ 7097, 7101 ] }, { "type": "function", "id": "rX_bits", "file": "model/riscv_regs.sail", "loc": [ 3752, 3759 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 7470, 7486 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 7448, 7464 ] } ] }, "rV": { "function": { "number": 0, "source": "function rV r = {\n let zero_vreg : vregtype = zeros();\n let v : vregtype =\n match r {\n 0 => vr0,\n 1 => vr1,\n 2 => vr2,\n 3 => vr3,\n 4 => vr4,\n 5 => vr5,\n 6 => vr6,\n 7 => vr7,\n 8 => vr8,\n 9 => vr9,\n 10 => vr10,\n 11 => vr11,\n 12 => vr12,\n 13 => vr13,\n 14 => vr14,\n 15 => vr15,\n 16 => vr16,\n 17 => vr17,\n 18 => vr18,\n 19 => vr19,\n 20 => vr20,\n 21 => vr21,\n 22 => vr22,\n 23 => vr23,\n 24 => vr24,\n 25 => vr25,\n 26 => vr26,\n 27 => vr27,\n 28 => vr28,\n 29 => vr29,\n 30 => vr30,\n 31 => vr31,\n _ => {assert(false, \"invalid vector register number\"); zero_vreg}\n };\n v\n}", "pattern": { "type": "id", "id": "r" }, "body": " let zero_vreg : vregtype = zeros();\n let v : vregtype =\n match r {\n 0 => vr0,\n 1 => vr1,\n 2 => vr2,\n 3 => vr3,\n 4 => vr4,\n 5 => vr5,\n 6 => vr6,\n 7 => vr7,\n 8 => vr8,\n 9 => vr9,\n 10 => vr10,\n 11 => vr11,\n 12 => vr12,\n 13 => vr13,\n 14 => vr14,\n 15 => vr15,\n 16 => vr16,\n 17 => vr17,\n 18 => vr18,\n 19 => vr19,\n 20 => vr20,\n 21 => vr21,\n 22 => vr22,\n 23 => vr23,\n 24 => vr24,\n 25 => vr25,\n 26 => vr26,\n 27 => vr27,\n 28 => vr28,\n 29 => vr29,\n 30 => vr30,\n 31 => vr31,\n _ => {assert(false, \"invalid vector register number\"); zero_vreg}\n };\n v" }, "links": [ { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "register", "id": "vr31", "file": "model/riscv_vext_regs.sail", "loc": [ 3173, 3177 ] }, { "type": "register", "id": "vr30", "file": "model/riscv_vext_regs.sail", "loc": [ 3155, 3159 ] }, { "type": "register", "id": "vr29", "file": "model/riscv_vext_regs.sail", "loc": [ 3137, 3141 ] }, { "type": "register", "id": "vr28", "file": "model/riscv_vext_regs.sail", "loc": [ 3119, 3123 ] }, { "type": "register", "id": "vr27", "file": "model/riscv_vext_regs.sail", "loc": [ 3101, 3105 ] }, { "type": "register", "id": "vr26", "file": "model/riscv_vext_regs.sail", "loc": [ 3083, 3087 ] }, { "type": "register", "id": "vr25", "file": "model/riscv_vext_regs.sail", "loc": [ 3065, 3069 ] }, { "type": "register", "id": "vr24", "file": "model/riscv_vext_regs.sail", "loc": [ 3047, 3051 ] }, { "type": "register", "id": "vr23", "file": "model/riscv_vext_regs.sail", "loc": [ 3029, 3033 ] }, { "type": "register", "id": "vr22", "file": "model/riscv_vext_regs.sail", "loc": [ 3011, 3015 ] }, { "type": "register", "id": "vr21", "file": "model/riscv_vext_regs.sail", "loc": [ 2993, 2997 ] }, { "type": "register", "id": "vr20", "file": "model/riscv_vext_regs.sail", "loc": [ 2975, 2979 ] }, { "type": "register", "id": "vr19", "file": "model/riscv_vext_regs.sail", "loc": [ 2957, 2961 ] }, { "type": "register", "id": "vr18", "file": "model/riscv_vext_regs.sail", "loc": [ 2939, 2943 ] }, { "type": "register", "id": "vr17", "file": "model/riscv_vext_regs.sail", "loc": [ 2921, 2925 ] }, { "type": "register", "id": "vr16", "file": "model/riscv_vext_regs.sail", "loc": [ 2903, 2907 ] }, { "type": "register", "id": "vr15", "file": "model/riscv_vext_regs.sail", "loc": [ 2885, 2889 ] }, { "type": "register", "id": "vr14", "file": "model/riscv_vext_regs.sail", "loc": [ 2867, 2871 ] }, { "type": "register", "id": "vr13", "file": "model/riscv_vext_regs.sail", "loc": [ 2849, 2853 ] }, { "type": "register", "id": "vr12", "file": "model/riscv_vext_regs.sail", "loc": [ 2831, 2835 ] }, { "type": "register", "id": "vr11", "file": "model/riscv_vext_regs.sail", "loc": [ 2813, 2817 ] }, { "type": "register", "id": "vr10", "file": "model/riscv_vext_regs.sail", "loc": [ 2795, 2799 ] }, { "type": "register", "id": "vr9", "file": "model/riscv_vext_regs.sail", "loc": [ 2778, 2781 ] }, { "type": "register", "id": "vr8", "file": "model/riscv_vext_regs.sail", "loc": [ 2762, 2765 ] }, { "type": "register", "id": "vr7", "file": "model/riscv_vext_regs.sail", "loc": [ 2746, 2749 ] }, { "type": "register", "id": "vr6", "file": "model/riscv_vext_regs.sail", "loc": [ 2730, 2733 ] }, { "type": "register", "id": "vr5", "file": "model/riscv_vext_regs.sail", "loc": [ 2714, 2717 ] }, { "type": "register", "id": "vr4", "file": "model/riscv_vext_regs.sail", "loc": [ 2698, 2701 ] }, { "type": "register", "id": "vr3", "file": "model/riscv_vext_regs.sail", "loc": [ 2682, 2685 ] }, { "type": "register", "id": "vr2", "file": "model/riscv_vext_regs.sail", "loc": [ 2666, 2669 ] }, { "type": "register", "id": "vr1", "file": "model/riscv_vext_regs.sail", "loc": [ 2650, 2653 ] }, { "type": "register", "id": "vr0", "file": "model/riscv_vext_regs.sail", "loc": [ 2634, 2637 ] } ] }, "rV_bits": { "function": { "number": 0, "source": "function rV_bits(i: bits(5)) -> vregtype = rV(unsigned(i))", "pattern": { "type": "id", "id": "i" }, "body": "rV(unsigned(i))" }, "links": [ { "type": "function", "id": "rV", "file": "model/riscv_vext_regs.sail", "loc": [ 4319, 4321 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 4322, 4330 ] } ] }, "rX": { "function": { "number": 0, "source": "function rX r = {\n let v : regtype =\n match r {\n 0 => zero_reg,\n 1 => x1,\n 2 => x2,\n 3 => x3,\n 4 => x4,\n 5 => x5,\n 6 => x6,\n 7 => x7,\n 8 => x8,\n 9 => x9,\n 10 => x10,\n 11 => x11,\n 12 => x12,\n 13 => x13,\n 14 => x14,\n 15 => x15,\n 16 => x16,\n 17 => x17,\n 18 => x18,\n 19 => x19,\n 20 => x20,\n 21 => x21,\n 22 => x22,\n 23 => x23,\n 24 => x24,\n 25 => x25,\n 26 => x26,\n 27 => x27,\n 28 => x28,\n 29 => x29,\n 30 => x30,\n 31 => x31,\n _ => {assert(false, \"invalid register number\"); zero_reg}\n };\n regval_from_reg(v)\n}", "pattern": { "type": "id", "id": "r" }, "body": " let v : regtype =\n match r {\n 0 => zero_reg,\n 1 => x1,\n 2 => x2,\n 3 => x3,\n 4 => x4,\n 5 => x5,\n 6 => x6,\n 7 => x7,\n 8 => x8,\n 9 => x9,\n 10 => x10,\n 11 => x11,\n 12 => x12,\n 13 => x13,\n 14 => x14,\n 15 => x15,\n 16 => x16,\n 17 => x17,\n 18 => x18,\n 19 => x19,\n 20 => x20,\n 21 => x21,\n 22 => x22,\n 23 => x23,\n 24 => x24,\n 25 => x25,\n 26 => x26,\n 27 => x27,\n 28 => x28,\n 29 => x29,\n 30 => x30,\n 31 => x31,\n _ => {assert(false, \"invalid register number\"); zero_reg}\n };\n regval_from_reg(v)" }, "links": [ { "type": "register", "id": "x31", "file": "model/riscv_regs.sail", "loc": [ 2211, 2214 ] }, { "type": "register", "id": "x30", "file": "model/riscv_regs.sail", "loc": [ 2194, 2197 ] }, { "type": "register", "id": "x29", "file": "model/riscv_regs.sail", "loc": [ 2177, 2180 ] }, { "type": "register", "id": "x28", "file": "model/riscv_regs.sail", "loc": [ 2160, 2163 ] }, { "type": "register", "id": "x27", "file": "model/riscv_regs.sail", "loc": [ 2143, 2146 ] }, { "type": "register", "id": "x26", "file": "model/riscv_regs.sail", "loc": [ 2126, 2129 ] }, { "type": "register", "id": "x25", "file": "model/riscv_regs.sail", "loc": [ 2109, 2112 ] }, { "type": "register", "id": "x24", "file": "model/riscv_regs.sail", "loc": [ 2092, 2095 ] }, { "type": "register", "id": "x23", "file": "model/riscv_regs.sail", "loc": [ 2075, 2078 ] }, { "type": "register", "id": "x22", "file": "model/riscv_regs.sail", "loc": [ 2058, 2061 ] }, { "type": "register", "id": "x21", "file": "model/riscv_regs.sail", "loc": [ 2041, 2044 ] }, { "type": "register", "id": "x20", "file": "model/riscv_regs.sail", "loc": [ 2024, 2027 ] }, { "type": "register", "id": "x19", "file": "model/riscv_regs.sail", "loc": [ 2007, 2010 ] }, { "type": "register", "id": "x18", "file": "model/riscv_regs.sail", "loc": [ 1990, 1993 ] }, { "type": "register", "id": "x17", "file": "model/riscv_regs.sail", "loc": [ 1973, 1976 ] }, { "type": "register", "id": "x16", "file": "model/riscv_regs.sail", "loc": [ 1956, 1959 ] }, { "type": "register", "id": "x15", "file": "model/riscv_regs.sail", "loc": [ 1939, 1942 ] }, { "type": "register", "id": "x14", "file": "model/riscv_regs.sail", "loc": [ 1922, 1925 ] }, { "type": "register", "id": "x13", "file": "model/riscv_regs.sail", "loc": [ 1905, 1908 ] }, { "type": "register", "id": "x12", "file": "model/riscv_regs.sail", "loc": [ 1888, 1891 ] }, { "type": "register", "id": "x11", "file": "model/riscv_regs.sail", "loc": [ 1871, 1874 ] }, { "type": "register", "id": "x10", "file": "model/riscv_regs.sail", "loc": [ 1854, 1857 ] }, { "type": "register", "id": "x9", "file": "model/riscv_regs.sail", "loc": [ 1838, 1840 ] }, { "type": "register", "id": "x8", "file": "model/riscv_regs.sail", "loc": [ 1823, 1825 ] }, { "type": "register", "id": "x7", "file": "model/riscv_regs.sail", "loc": [ 1808, 1810 ] }, { "type": "register", "id": "x6", "file": "model/riscv_regs.sail", "loc": [ 1793, 1795 ] }, { "type": "register", "id": "x5", "file": "model/riscv_regs.sail", "loc": [ 1778, 1780 ] }, { "type": "register", "id": "x4", "file": "model/riscv_regs.sail", "loc": [ 1763, 1765 ] }, { "type": "register", "id": "x3", "file": "model/riscv_regs.sail", "loc": [ 1748, 1750 ] }, { "type": "register", "id": "x2", "file": "model/riscv_regs.sail", "loc": [ 1733, 1735 ] }, { "type": "register", "id": "x1", "file": "model/riscv_regs.sail", "loc": [ 1718, 1720 ] }, { "type": "function", "id": "regval_from_reg", "file": "model/riscv_regs.sail", "loc": [ 2290, 2305 ] } ] }, "rX_bits": { "function": { "number": 0, "source": "function rX_bits(i: bits(5)) -> xlenbits = rX(unsigned(i))", "pattern": { "type": "id", "id": "i" }, "body": "rX(unsigned(i))" }, "links": [ { "type": "function", "id": "rX", "file": "model/riscv_regs.sail", "loc": [ 3636, 3638 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_regs.sail", "loc": [ 3639, 3647 ] } ] }, "readCSR": { "function": { "number": 0, "source": "function readCSR csr : csreg -> xlenbits = {\n let res : xlenbits =\n match (csr, sizeof(xlen)) {\n /* machine mode */\n (0xF11, _) => zero_extend(mvendorid),\n (0xF12, _) => marchid,\n (0xF13, _) => mimpid,\n (0xF14, _) => mhartid,\n (0x300, _) => mstatus.bits,\n (0x301, _) => misa.bits,\n (0x302, _) => medeleg.bits,\n (0x303, _) => mideleg.bits,\n (0x304, _) => mie.bits,\n (0x305, _) => get_mtvec(),\n (0x306, _) => zero_extend(mcounteren.bits),\n (0x30A, _) => menvcfg.bits[sizeof(xlen) - 1 .. 0],\n (0x310, 32) => mstatush.bits,\n (0x31A, 32) => menvcfg.bits[63 .. 32],\n (0x320, _) => zero_extend(mcountinhibit.bits),\n\n (0x340, _) => mscratch,\n (0x341, _) => get_xret_target(Machine) & pc_alignment_mask(),\n (0x342, _) => mcause.bits,\n (0x343, _) => mtval,\n (0x344, _) => mip.bits,\n\n // pmpcfgN\n (0x3A @ idx : bits(4), _) if idx[0] == bitzero | sizeof(xlen) == 32 => pmpReadCfgReg(unsigned(idx)),\n // pmpaddrN. Unfortunately the PMP index does not nicely align with the CSR index bits.\n (0x3B @ idx : bits(4), _) => pmpReadAddrReg(unsigned(0b00 @ idx)),\n (0x3C @ idx : bits(4), _) => pmpReadAddrReg(unsigned(0b01 @ idx)),\n (0x3D @ idx : bits(4), _) => pmpReadAddrReg(unsigned(0b10 @ idx)),\n (0x3E @ idx : bits(4), _) => pmpReadAddrReg(unsigned(0b11 @ idx)),\n\n /* machine mode counters */\n (0xB00, _) => mcycle[(sizeof(xlen) - 1) .. 0],\n (0xB02, _) => minstret[(sizeof(xlen) - 1) .. 0],\n (0xB80, 32) => mcycle[63 .. 32],\n (0xB82, 32) => minstret[63 .. 32],\n\n /* vector */\n (0x008, _) => zero_extend(vstart),\n (0x009, _) => zero_extend(vxsat),\n (0x00A, _) => zero_extend(vxrm),\n (0x00F, _) => zero_extend(vcsr.bits),\n (0xC20, _) => vl,\n (0xC21, _) => vtype.bits,\n (0xC22, _) => vlenb,\n\n /* trigger/debug */\n (0x7a0, _) => ~(tselect), /* this indicates we don't have any trigger support */\n\n /* supervisor mode */\n (0x100, _) => lower_mstatus(mstatus).bits,\n (0x102, _) => sedeleg.bits,\n (0x103, _) => sideleg.bits,\n (0x104, _) => lower_mie(mie, mideleg).bits,\n (0x105, _) => get_stvec(),\n (0x106, _) => zero_extend(scounteren.bits),\n (0x10A, _) => senvcfg.bits[sizeof(xlen) - 1 .. 0],\n (0x140, _) => sscratch,\n (0x141, _) => get_xret_target(Supervisor) & pc_alignment_mask(),\n (0x142, _) => scause.bits,\n (0x143, _) => stval,\n (0x144, _) => lower_mip(mip, mideleg).bits,\n (0x180, _) => satp,\n\n /* user mode counters */\n (0xC00, _) => mcycle[(sizeof(xlen) - 1) .. 0],\n (0xC01, _) => mtime[(sizeof(xlen) - 1) .. 0],\n (0xC02, _) => minstret[(sizeof(xlen) - 1) .. 0],\n (0xC80, 32) => mcycle[63 .. 32],\n (0xC81, 32) => mtime[63 .. 32],\n (0xC82, 32) => minstret[63 .. 32],\n\n /* user mode: Zkr */\n (0x015, _) => read_seed_csr(),\n\n _ => /* check extensions */\n match ext_read_CSR(csr) {\n Some(res) => res,\n None() => { print_bits(\"unhandled read to CSR \", csr);\n zero_extend(0x0) }\n }\n };\n if get_config_print_reg()\n then print_reg(\"CSR \" ^ to_str(csr) ^ \" -> \" ^ BitStr(res));\n res\n}", "pattern": { "type": "id", "id": "csr" }, "body": " let res : xlenbits =\n match (csr, sizeof(xlen)) {\n /* machine mode */\n (0xF11, _) => zero_extend(mvendorid),\n (0xF12, _) => marchid,\n (0xF13, _) => mimpid,\n (0xF14, _) => mhartid,\n (0x300, _) => mstatus.bits,\n (0x301, _) => misa.bits,\n (0x302, _) => medeleg.bits,\n (0x303, _) => mideleg.bits,\n (0x304, _) => mie.bits,\n (0x305, _) => get_mtvec(),\n (0x306, _) => zero_extend(mcounteren.bits),\n (0x30A, _) => menvcfg.bits[sizeof(xlen) - 1 .. 0],\n (0x310, 32) => mstatush.bits,\n (0x31A, 32) => menvcfg.bits[63 .. 32],\n (0x320, _) => zero_extend(mcountinhibit.bits),\n\n (0x340, _) => mscratch,\n (0x341, _) => get_xret_target(Machine) & pc_alignment_mask(),\n (0x342, _) => mcause.bits,\n (0x343, _) => mtval,\n (0x344, _) => mip.bits,\n\n // pmpcfgN\n (0x3A @ idx : bits(4), _) if idx[0] == bitzero | sizeof(xlen) == 32 => pmpReadCfgReg(unsigned(idx)),\n // pmpaddrN. Unfortunately the PMP index does not nicely align with the CSR index bits.\n (0x3B @ idx : bits(4), _) => pmpReadAddrReg(unsigned(0b00 @ idx)),\n (0x3C @ idx : bits(4), _) => pmpReadAddrReg(unsigned(0b01 @ idx)),\n (0x3D @ idx : bits(4), _) => pmpReadAddrReg(unsigned(0b10 @ idx)),\n (0x3E @ idx : bits(4), _) => pmpReadAddrReg(unsigned(0b11 @ idx)),\n\n /* machine mode counters */\n (0xB00, _) => mcycle[(sizeof(xlen) - 1) .. 0],\n (0xB02, _) => minstret[(sizeof(xlen) - 1) .. 0],\n (0xB80, 32) => mcycle[63 .. 32],\n (0xB82, 32) => minstret[63 .. 32],\n\n /* vector */\n (0x008, _) => zero_extend(vstart),\n (0x009, _) => zero_extend(vxsat),\n (0x00A, _) => zero_extend(vxrm),\n (0x00F, _) => zero_extend(vcsr.bits),\n (0xC20, _) => vl,\n (0xC21, _) => vtype.bits,\n (0xC22, _) => vlenb,\n\n /* trigger/debug */\n (0x7a0, _) => ~(tselect), /* this indicates we don't have any trigger support */\n\n /* supervisor mode */\n (0x100, _) => lower_mstatus(mstatus).bits,\n (0x102, _) => sedeleg.bits,\n (0x103, _) => sideleg.bits,\n (0x104, _) => lower_mie(mie, mideleg).bits,\n (0x105, _) => get_stvec(),\n (0x106, _) => zero_extend(scounteren.bits),\n (0x10A, _) => senvcfg.bits[sizeof(xlen) - 1 .. 0],\n (0x140, _) => sscratch,\n (0x141, _) => get_xret_target(Supervisor) & pc_alignment_mask(),\n (0x142, _) => scause.bits,\n (0x143, _) => stval,\n (0x144, _) => lower_mip(mip, mideleg).bits,\n (0x180, _) => satp,\n\n /* user mode counters */\n (0xC00, _) => mcycle[(sizeof(xlen) - 1) .. 0],\n (0xC01, _) => mtime[(sizeof(xlen) - 1) .. 0],\n (0xC02, _) => minstret[(sizeof(xlen) - 1) .. 0],\n (0xC80, 32) => mcycle[63 .. 32],\n (0xC81, 32) => mtime[63 .. 32],\n (0xC82, 32) => minstret[63 .. 32],\n\n /* user mode: Zkr */\n (0x015, _) => read_seed_csr(),\n\n _ => /* check extensions */\n match ext_read_CSR(csr) {\n Some(res) => res,\n None() => { print_bits(\"unhandled read to CSR \", csr);\n zero_extend(0x0) }\n }\n };\n if get_config_print_reg()\n then print_reg(\"CSR \" ^ to_str(csr) ^ \" -> \" ^ BitStr(res));\n res" }, "links": [ { "type": "function", "id": "ext_read_CSR", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4082, 4094 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4256, 4267 ] }, { "type": "function", "id": "print_bits", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4177, 4187 ] }, { "type": "function", "id": "read_seed_csr", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3997, 4010 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3932, 3940 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3896, 3901 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3859, 3865 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3805, 3813 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3754, 3759 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3702, 3708 ] }, { "type": "register", "id": "satp", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3647, 3651 ] }, { "type": "function", "id": "lower_mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3598, 3607 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3613, 3620 ] }, { "type": "register", "id": "mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3608, 3611 ] }, { "type": "register", "id": "stval", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3572, 3577 ] }, { "type": "register", "id": "scause", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3540, 3546 ] }, { "type": "function", "id": "pc_alignment_mask", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3500, 3517 ] }, { "type": "function", "id": "get_xret_target", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3470, 3485 ] }, { "type": "register", "id": "sscratch", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3441, 3449 ] }, { "type": "register", "id": "senvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3385, 3392 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3336, 3347 ] }, { "type": "register", "id": "scounteren", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3348, 3358 ] }, { "type": "function", "id": "get_stvec", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3304, 3313 ] }, { "type": "function", "id": "lower_mie", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3255, 3264 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3270, 3277 ] }, { "type": "register", "id": "mie", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3265, 3268 ] }, { "type": "register", "id": "sideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3222, 3229 ] }, { "type": "register", "id": "sedeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3189, 3196 ] }, { "type": "function", "id": "lower_mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3141, 3154 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3155, 3162 ] }, { "type": "function", "id": "not_vec", "file": "model/prelude.sail", "loc": [ 997, 1004 ] }, { "type": "register", "id": "tselect", "file": "model/riscv_insts_zicsr.sail", "loc": [ 3029, 3036 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2976, 2981 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2946, 2951 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2924, 2926 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2882, 2893 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2894, 2898 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2845, 2856 ] }, { "type": "register", "id": "vxrm", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2857, 2861 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2807, 2818 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2819, 2824 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2768, 2779 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2780, 2786 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2712, 2720 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2675, 2681 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2621, 2629 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2569, 2575 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2479, 2493 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2494, 2502 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2407, 2421 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2422, 2430 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2335, 2349 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2350, 2358 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2263, 2277 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2278, 2286 ] }, { "type": "function", "id": "pmpReadCfgReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2107, 2120 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2121, 2129 ] }, { "type": "register", "id": "mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 2005, 2008 ] }, { "type": "register", "id": "mtval", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1979, 1984 ] }, { "type": "register", "id": "mcause", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1947, 1953 ] }, { "type": "function", "id": "pc_alignment_mask", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1907, 1924 ] }, { "type": "function", "id": "get_xret_target", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1880, 1895 ] }, { "type": "register", "id": "mscratch", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1851, 1859 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1798, 1809 ] }, { "type": "register", "id": "mcountinhibit", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1810, 1823 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1755, 1762 ] }, { "type": "register", "id": "mstatush", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1721, 1729 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1665, 1672 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1616, 1627 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1628, 1638 ] }, { "type": "function", "id": "get_mtvec", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1584, 1593 ] }, { "type": "register", "id": "mie", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1555, 1558 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1522, 1529 ] }, { "type": "register", "id": "medeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1489, 1496 ] }, { "type": "register", "id": "misa", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1459, 1463 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1426, 1433 ] }, { "type": "register", "id": "mhartid", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1398, 1405 ] }, { "type": "register", "id": "mimpid", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1371, 1377 ] }, { "type": "register", "id": "marchid", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1343, 1350 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1300, 1311 ] }, { "type": "register", "id": "mvendorid", "file": "model/riscv_insts_zicsr.sail", "loc": [ 1312, 1321 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4308, 4328 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4338, 4347 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "csr_name", "file": "model/riscv_csr_map.sail", "loc": [ 8753, 8761 ] } ] }, "read_kind_of_flags": { "function": { "number": 0, "source": "function read_kind_of_flags (aq : bool, rl : bool, res : bool) -> option(read_kind) =\n match (aq, rl, res) {\n (false, false, false) => Some(Read_plain),\n (true, false, false) => Some(Read_RISCV_acquire),\n (true, true, false) => Some(Read_RISCV_strong_acquire),\n (false, false, true) => Some(Read_RISCV_reserved),\n (true, false, true) => Some(Read_RISCV_reserved_acquire),\n (true, true, true) => Some(Read_RISCV_reserved_strong_acquire),\n (false, true, false) => None(), /* should these be instead throwing error_not_implemented as below? */\n (false, true, true) => None()\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "res" } ] }, "body": "match (aq, rl, res) {\n (false, false, false) => Some(Read_plain),\n (true, false, false) => Some(Read_RISCV_acquire),\n (true, true, false) => Some(Read_RISCV_strong_acquire),\n (false, false, true) => Some(Read_RISCV_reserved),\n (true, false, true) => Some(Read_RISCV_reserved_acquire),\n (true, true, true) => Some(Read_RISCV_reserved_strong_acquire),\n (false, true, false) => None(), /* should these be instead throwing error_not_implemented as below? */\n (false, true, true) => None()\n }" }, "links": [ { "type": "function", "id": "None", "file": "model/riscv_mem.sail", "loc": [ 2366, 2370 ] }, { "type": "function", "id": "None", "file": "model/riscv_mem.sail", "loc": [ 2258, 2262 ] }, { "type": "function", "id": "Some", "file": "model/riscv_mem.sail", "loc": [ 2187, 2191 ] }, { "type": "function", "id": "Some", "file": "model/riscv_mem.sail", "loc": [ 2123, 2127 ] }, { "type": "function", "id": "Some", "file": "model/riscv_mem.sail", "loc": [ 2067, 2071 ] }, { "type": "function", "id": "Some", "file": "model/riscv_mem.sail", "loc": [ 2005, 2009 ] }, { "type": "function", "id": "Some", "file": "model/riscv_mem.sail", "loc": [ 1950, 1954 ] }, { "type": "function", "id": "Some", "file": "model/riscv_mem.sail", "loc": [ 1903, 1907 ] } ] }, "read_kind_of_num": { "function": { "number": 0, "source": "read_kind_of_num arg# = $[complete] match arg# {\n 0 => Read_plain,\n 1 => Read_reserve,\n 2 => Read_acquire,\n 3 => Read_exclusive,\n 4 => Read_exclusive_acquire,\n 5 => Read_stream,\n 6 => Read_ifetch,\n 7 => Read_RISCV_acquire,\n 8 => Read_RISCV_strong_acquire,\n 9 => Read_RISCV_reserved,\n 10 => Read_RISCV_reserved_acquire,\n 11 => Read_RISCV_reserved_strong_acquire,\n _ => Read_X86_locked\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => Read_plain,\n 1 => Read_reserve,\n 2 => Read_acquire,\n 3 => Read_exclusive,\n 4 => Read_exclusive_acquire,\n 5 => Read_stream,\n 6 => Read_ifetch,\n 7 => Read_RISCV_acquire,\n 8 => Read_RISCV_strong_acquire,\n 9 => Read_RISCV_reserved,\n 10 => Read_RISCV_reserved_acquire,\n 11 => Read_RISCV_reserved_strong_acquire,\n _ => Read_X86_locked\n}" } }, "read_ram": { "function": { "number": 0, "source": "function read_ram(rk, addr, width, read_meta) =\n let meta = if read_meta then __ReadRAM_Meta(addr, width) else default_meta in\n (__read_mem(rk, sizeof(xlen), addr, width), meta)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rk" }, { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "read_meta" } ] }, "body": "let meta = if read_meta then __ReadRAM_Meta(addr, width) else default_meta in\n (__read_mem(rk, sizeof(xlen), addr, width), meta)" }, "links": [ { "type": "function", "id": "__ReadRAM_Meta", "file": "model/prelude_mem.sail", "loc": [ 2623, 2637 ] }, { "type": "function", "id": "__read_mem", "file": "model/prelude_mem.sail", "loc": [ 2675, 2685 ] } ] }, "read_seed_csr": { "function": { "number": 0, "source": "function read_seed_csr() -> xlenbits = {\n let reserved_bits : bits(6) = 0b000000;\n let custom_bits : bits(8) = 0x00;\n let seed : bits(16) = get_16_random_bits();\n zero_extend(opst_code(ES16) @ reserved_bits @ custom_bits @ seed)\n}", "pattern": { "type": "literal", "value": "()" }, "body": " let reserved_bits : bits(6) = 0b000000;\n let custom_bits : bits(8) = 0x00;\n let seed : bits(16) = get_16_random_bits();\n zero_extend(opst_code(ES16) @ reserved_bits @ custom_bits @ seed)" }, "links": [ { "type": "function", "id": "get_16_random_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 23973, 23991 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 23997, 24008 ] } ] }, "read_single_element": { "function": { "number": 0, "source": "function read_single_element(EEW, index, vrid) = {\n let VLEN = unsigned(vlenb) * 8;\n assert(VLEN >= EEW);\n let 'elem_per_reg : int = VLEN / EEW;\n assert('elem_per_reg >= 0);\n let real_vrid : regidx = vrid + to_bits(5, index / 'elem_per_reg);\n let real_index : int = index % 'elem_per_reg;\n let vrid_val : vector('elem_per_reg, dec, bits('m)) = read_single_vreg('elem_per_reg, EEW, real_vrid);\n assert(0 <= real_index & real_index < 'elem_per_reg);\n vrid_val[real_index]\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "EEW" }, { "type": "id", "id": "index" }, { "type": "id", "id": "vrid" } ] }, "body": " let VLEN = unsigned(vlenb) * 8;\n assert(VLEN >= EEW);\n let 'elem_per_reg : int = VLEN / EEW;\n assert('elem_per_reg >= 0);\n let real_vrid : regidx = vrid + to_bits(5, index / 'elem_per_reg);\n let real_index : int = index % 'elem_per_reg;\n let vrid_val : vector('elem_per_reg, dec, bits('m)) = read_single_vreg('elem_per_reg, EEW, real_vrid);\n assert(0 <= real_index & real_index < 'elem_per_reg);\n vrid_val[real_index]" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 8666, 8674 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 8675, 8680 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 8815, 8822 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "emod_int", "file": "model/prelude.sail", "loc": [ 2111, 2119 ] }, { "type": "function", "id": "read_single_vreg", "file": "model/riscv_vext_regs.sail", "loc": [ 8957, 8973 ] } ] }, "read_single_vreg": { "function": { "number": 0, "source": "function read_single_vreg(num_elem, SEW, vrid) = {\n let bv : vregtype = V(vrid);\n var result : vector('n, dec, bits('m)) = undefined;\n\n assert(8 <= SEW & SEW <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n let start_index = i * SEW;\n result[i] = slice(bv, start_index, SEW);\n };\n\n result\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "vrid" } ] }, "body": " let bv : vregtype = V(vrid);\n var result : vector('n, dec, bits('m)) = undefined;\n\n assert(8 <= SEW & SEW <= 64);\n foreach (i from 0 to (num_elem - 1)) {\n let start_index = i * SEW;\n result[i] = slice(bv, start_index, SEW);\n };\n\n result" }, "links": [ { "type": "function", "id": "rV_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 4435, 4442 ] }, { "type": "function", "id": "slice", "file": "model/riscv_vext_regs.sail", "loc": [ 6432, 6437 ] } ] }, "read_vmask": { "function": { "number": 0, "source": "function read_vmask(num_elem, vm, vrid) = {\n let VLEN = unsigned(vlenb) * 8;\n assert(num_elem <= sizeof(vlenmax));\n let vreg_val : vregtype = V(vrid);\n var result : vector('n, dec, bool) = undefined;\n\n foreach (i from 0 to (num_elem - 1)) {\n if vm == 0b1 then {\n result[i] = true\n } else {\n result[i] = bit_to_bool(vreg_val[i])\n }\n };\n\n result\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vrid" } ] }, "body": " let VLEN = unsigned(vlenb) * 8;\n assert(num_elem <= sizeof(vlenmax));\n let vreg_val : vregtype = V(vrid);\n var result : vector('n, dec, bool) = undefined;\n\n foreach (i from 0 to (num_elem - 1)) {\n if vm == 0b1 then {\n result[i] = true\n } else {\n result[i] = bit_to_bool(vreg_val[i])\n }\n };\n\n result" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 11100, 11108 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 11109, 11114 ] }, { "type": "function", "id": "rV_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 4435, 4442 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_vext_regs.sail", "loc": [ 11369, 11380 ] } ] }, "read_vmask_carry": { "function": { "number": 0, "source": "function read_vmask_carry(num_elem, vm, vrid) = {\n let VLEN = unsigned(vlenb) * 8;\n assert(0 < num_elem & num_elem <= sizeof(vlenmax));\n let vreg_val : vregtype = V(vrid);\n var result : vector('n, dec, bool) = undefined;\n\n foreach (i from 0 to (num_elem - 1)) {\n if vm == 0b1 then {\n result[i] = false\n } else {\n result[i] = bit_to_bool(vreg_val[i])\n }\n };\n\n result\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vrid" } ] }, "body": " let VLEN = unsigned(vlenb) * 8;\n assert(0 < num_elem & num_elem <= sizeof(vlenmax));\n let vreg_val : vregtype = V(vrid);\n var result : vector('n, dec, bool) = undefined;\n\n foreach (i from 0 to (num_elem - 1)) {\n if vm == 0b1 then {\n result[i] = false\n } else {\n result[i] = bit_to_bool(vreg_val[i])\n }\n };\n\n result" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 11679, 11687 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 11688, 11693 ] }, { "type": "function", "id": "rV_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 4435, 4442 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_vext_regs.sail", "loc": [ 11964, 11975 ] } ] }, "read_vreg": { "function": { "number": 0, "source": "function read_vreg(num_elem, SEW, LMUL_pow, vrid) = {\n var result : vector('n, dec, bits('m)) = undefined;\n let VLEN = unsigned(vlenb) * 8;\n let LMUL_pow_reg = if LMUL_pow < 0 then 0 else LMUL_pow;\n\n /* Check for valid vrid */\n if unsigned(vrid) + 2 ^ LMUL_pow_reg > 32 then {\n /* vrid would read past largest vreg (v31) */\n assert(false, \"invalid register group: vrid overflow the largest number\")\n } else if unsigned(vrid) % (2 ^ LMUL_pow_reg) != 0 then {\n /* vrid must be a multiple of emul */\n assert(false, \"invalid register group: vrid is not a multiple of EMUL\")\n } else {\n if LMUL_pow < 0 then {\n result = read_single_vreg('n, SEW, vrid);\n } else {\n let 'num_elem_single : int = VLEN / SEW;\n assert('num_elem_single >= 0);\n foreach (i_lmul from 0 to (2 ^ LMUL_pow_reg - 1)) {\n let r_start_i : int = i_lmul * 'num_elem_single;\n let r_end_i : int = r_start_i + 'num_elem_single - 1;\n let vrid_lmul : regidx = vrid + to_bits(5, i_lmul);\n let single_result : vector('num_elem_single, dec, bits('m)) = read_single_vreg('num_elem_single, SEW, vrid_lmul);\n foreach (r_i from r_start_i to r_end_i) {\n let s_i : int = r_i - r_start_i;\n assert(0 <= r_i & r_i < num_elem);\n assert(0 <= s_i & s_i < 'num_elem_single);\n result[r_i] = single_result[s_i];\n }\n }\n }\n };\n\n result\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "LMUL_pow" }, { "type": "id", "id": "vrid" } ] }, "body": " var result : vector('n, dec, bits('m)) = undefined;\n let VLEN = unsigned(vlenb) * 8;\n let LMUL_pow_reg = if LMUL_pow < 0 then 0 else LMUL_pow;\n\n /* Check for valid vrid */\n if unsigned(vrid) + 2 ^ LMUL_pow_reg > 32 then {\n /* vrid would read past largest vreg (v31) */\n assert(false, \"invalid register group: vrid overflow the largest number\")\n } else if unsigned(vrid) % (2 ^ LMUL_pow_reg) != 0 then {\n /* vrid must be a multiple of emul */\n assert(false, \"invalid register group: vrid is not a multiple of EMUL\")\n } else {\n if LMUL_pow < 0 then {\n result = read_single_vreg('n, SEW, vrid);\n } else {\n let 'num_elem_single : int = VLEN / SEW;\n assert('num_elem_single >= 0);\n foreach (i_lmul from 0 to (2 ^ LMUL_pow_reg - 1)) {\n let r_start_i : int = i_lmul * 'num_elem_single;\n let r_end_i : int = r_start_i + 'num_elem_single - 1;\n let vrid_lmul : regidx = vrid + to_bits(5, i_lmul);\n let single_result : vector('num_elem_single, dec, bits('m)) = read_single_vreg('num_elem_single, SEW, vrid_lmul);\n foreach (r_i from r_start_i to r_end_i) {\n let s_i : int = r_i - r_start_i;\n assert(0 <= r_i & r_i < num_elem);\n assert(0 <= s_i & s_i < 'num_elem_single);\n result[r_i] = single_result[s_i];\n }\n }\n }\n };\n\n result" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 7176, 7184 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 7185, 7190 ] }, { "type": "function", "id": "pow2", "file": "model/riscv_vext_regs.sail", "loc": [ 7308, 7311 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 7291, 7299 ] }, { "type": "function", "id": "emod_int", "file": "model/prelude.sail", "loc": [ 2111, 2119 ] }, { "type": "function", "id": "pow2", "file": "model/riscv_vext_regs.sail", "loc": [ 7495, 7498 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 7477, 7485 ] }, { "type": "function", "id": "read_single_vreg", "file": "model/riscv_vext_regs.sail", "loc": [ 7696, 7712 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "pow2", "file": "model/riscv_vext_regs.sail", "loc": [ 7859, 7862 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 8049, 8056 ] }, { "type": "function", "id": "read_single_vreg", "file": "model/riscv_vext_regs.sail", "loc": [ 8139, 8155 ] } ] }, "read_vreg_seg": { "function": { "number": 0, "source": "function read_vreg_seg(num_elem, SEW, LMUL_pow, nf, vrid) = {\n assert('q * 'm > 0);\n let LMUL_reg : int = if LMUL_pow <= 0 then 1 else int_power(2, LMUL_pow);\n vreg_list : vector('q, dec, vector('n, dec, bits('m))) = undefined;\n result : vector('n, dec, bits('q * 'm)) = undefined;\n foreach (j from 0 to (nf - 1)) {\n vreg_list[j] = read_vreg(num_elem, SEW, LMUL_pow, vrid + to_bits(5, j * LMUL_reg));\n };\n foreach (i from 0 to (num_elem - 1)) {\n result[i] = zeros('q * 'm);\n foreach (j from 0 to (nf - 1)) {\n result[i] = result[i] | (zero_extend(vreg_list[j][i]) << (j * 'm))\n }\n };\n result\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "LMUL_pow" }, { "type": "id", "id": "nf" }, { "type": "id", "id": "vrid" } ] }, "body": "function read_vreg_seg(num_elem, SEW, LMUL_pow, nf, vrid) = {\n assert('q * 'm > 0);\n let LMUL_reg : int = if LMUL_pow <= 0 then 1 else int_power(2, LMUL_pow);\n vreg_list : vector('q, dec, vector('n, dec, bits('m))) = undefined;\n result : vector('n, dec, bits('q * 'm)) = undefined;\n foreach (j from 0 to (nf - 1)) {\n vreg_list[j] = read_vreg(num_elem, SEW, LMUL_pow, vrid + to_bits(5, j * LMUL_reg));\n };\n foreach (i from 0 to (num_elem - 1)) {\n result[i] = zeros('q * 'm);\n foreach (j from 0 to (nf - 1)) {\n result[i] = result[i] | (zero_extend(vreg_list[j][i]) << (j * 'm))\n }\n };\n result" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 17397, 17406 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 17815, 17826 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "read_vreg", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 17600, 17609 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 17642, 17649 ] } ] }, "recip7": { "function": { "number": 0, "source": "function recip7 (v, rm_3b, sub) = {\n let (sig, exp, sign, e, s) : (bits(64), bits(64), bits(1), nat, nat) = match 'm {\n 16 => (zero_extend(64, v[9 .. 0]), zero_extend(64, v[14 .. 10]), [v[15]], 5, 10),\n 32 => (zero_extend(64, v[22 .. 0]), zero_extend(64, v[30 .. 23]), [v[31]], 8, 23),\n 64 => (zero_extend(64, v[51 .. 0]), zero_extend(64, v[62 .. 52]), [v[63]], 11, 52)\n };\n assert(s == 10 & e == 5 | s == 23 & e == 8 | s == 52 & e == 11);\n let table : vector(128, dec, int) = [\n 127, 125, 123, 121, 119, 117, 116, 114,\n 112, 110, 109, 107, 105, 104, 102, 100,\n 99, 97, 96, 94, 93, 91, 90, 88,\n 87, 85, 84, 83, 81, 80, 79, 77,\n 76, 75, 74, 72, 71, 70, 69, 68,\n 66, 65, 64, 63, 62, 61, 60, 59,\n 58, 57, 56, 55, 54, 53, 52, 51,\n 50, 49, 48, 47, 46, 45, 44, 43,\n 42, 41, 40, 40, 39, 38, 37, 36,\n 35, 35, 34, 33, 32, 31, 31, 30,\n 29, 28, 28, 27, 26, 25, 25, 24,\n 23, 23, 22, 21, 21, 20, 19, 19,\n 18, 17, 17, 16, 15, 15, 14, 14,\n 13, 12, 12, 11, 11, 10, 9, 9,\n 8, 8, 7, 7, 6, 5, 5, 4,\n 4, 3, 3, 2, 2, 1, 1, 0];\n\n let nr_leadingzeros = count_leadingzeros(sig, s);\n assert(nr_leadingzeros >= 0);\n let (normalized_exp, normalized_sig) =\n if sub then {\n (to_bits(64, (0 - nr_leadingzeros)), zero_extend(64, sig[(s - 1) .. 0] << (1 + nr_leadingzeros)))\n } else {\n (exp, sig)\n };\n\n let idx : nat = match 'm {\n 16 => unsigned(normalized_sig[9 .. 3]),\n 32 => unsigned(normalized_sig[22 .. 16]),\n 64 => unsigned(normalized_sig[51 .. 45])\n };\n assert(idx >= 0 & idx < 128);\n let mid_exp = to_bits(e, 2 * (2^(e - 1) - 1) - 1 - signed(normalized_exp));\n let mid_sig = to_bits(s, table[(127 - idx)]) << (s - 7);\n\n let (out_exp, out_sig)=\n if mid_exp == zeros(e) then {\n (mid_exp, mid_sig >> 1 | 0b1 @ zeros(s - 1))\n } else if mid_exp == ones(e) then {\n (zeros(e), mid_sig >> 2 | 0b01 @ zeros(s - 2))\n } else (mid_exp, mid_sig);\n\n if sub & nr_leadingzeros > 1 then {\n if (rm_3b == 0b001 | rm_3b == 0b010 & sign == 0b0 | rm_3b == 0b011 & sign == 0b1) then {\n (true, zero_extend(64, sign @ ones(e - 1) @ 0b0 @ ones(s)))\n }\n else (true, zero_extend(64, sign @ ones(e) @ zeros(s)))\n } else (false, zero_extend(64, sign @ out_exp @ out_sig))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v" }, { "type": "id", "id": "rm_3b" }, { "type": "id", "id": "sub" } ] }, "body": " let (sig, exp, sign, e, s) : (bits(64), bits(64), bits(1), nat, nat) = match 'm {\n 16 => (zero_extend(64, v[9 .. 0]), zero_extend(64, v[14 .. 10]), [v[15]], 5, 10),\n 32 => (zero_extend(64, v[22 .. 0]), zero_extend(64, v[30 .. 23]), [v[31]], 8, 23),\n 64 => (zero_extend(64, v[51 .. 0]), zero_extend(64, v[62 .. 52]), [v[63]], 11, 52)\n };\n assert(s == 10 & e == 5 | s == 23 & e == 8 | s == 52 & e == 11);\n let table : vector(128, dec, int) = [\n 127, 125, 123, 121, 119, 117, 116, 114,\n 112, 110, 109, 107, 105, 104, 102, 100,\n 99, 97, 96, 94, 93, 91, 90, 88,\n 87, 85, 84, 83, 81, 80, 79, 77,\n 76, 75, 74, 72, 71, 70, 69, 68,\n 66, 65, 64, 63, 62, 61, 60, 59,\n 58, 57, 56, 55, 54, 53, 52, 51,\n 50, 49, 48, 47, 46, 45, 44, 43,\n 42, 41, 40, 40, 39, 38, 37, 36,\n 35, 35, 34, 33, 32, 31, 31, 30,\n 29, 28, 28, 27, 26, 25, 25, 24,\n 23, 23, 22, 21, 21, 20, 19, 19,\n 18, 17, 17, 16, 15, 15, 14, 14,\n 13, 12, 12, 11, 11, 10, 9, 9,\n 8, 8, 7, 7, 6, 5, 5, 4,\n 4, 3, 3, 2, 2, 1, 1, 0];\n\n let nr_leadingzeros = count_leadingzeros(sig, s);\n assert(nr_leadingzeros >= 0);\n let (normalized_exp, normalized_sig) =\n if sub then {\n (to_bits(64, (0 - nr_leadingzeros)), zero_extend(64, sig[(s - 1) .. 0] << (1 + nr_leadingzeros)))\n } else {\n (exp, sig)\n };\n\n let idx : nat = match 'm {\n 16 => unsigned(normalized_sig[9 .. 3]),\n 32 => unsigned(normalized_sig[22 .. 16]),\n 64 => unsigned(normalized_sig[51 .. 45])\n };\n assert(idx >= 0 & idx < 128);\n let mid_exp = to_bits(e, 2 * (2^(e - 1) - 1) - 1 - signed(normalized_exp));\n let mid_sig = to_bits(s, table[(127 - idx)]) << (s - 7);\n\n let (out_exp, out_sig)=\n if mid_exp == zeros(e) then {\n (mid_exp, mid_sig >> 1 | 0b1 @ zeros(s - 1))\n } else if mid_exp == ones(e) then {\n (zeros(e), mid_sig >> 2 | 0b01 @ zeros(s - 2))\n } else (mid_exp, mid_sig);\n\n if sub & nr_leadingzeros > 1 then {\n if (rm_3b == 0b001 | rm_3b == 0b010 & sign == 0b0 | rm_3b == 0b011 & sign == 0b1) then {\n (true, zero_extend(64, sign @ ones(e - 1) @ 0b0 @ ones(s)))\n }\n else (true, zero_extend(64, sign @ ones(e) @ zeros(s)))\n } else (false, zero_extend(64, sign @ out_exp @ out_sig))" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 36469, 36480 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 36440, 36451 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 36382, 36393 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 36353, 36364 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 36295, 36306 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 36267, 36278 ] }, { "type": "function", "id": "count_leadingzeros", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37260, 37278 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37426, 37437 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37390, 37397 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37660, 37668 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37614, 37622 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37570, 37578 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37748, 37755 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37785, 37791 ] }, { "type": "function", "id": "int_power", "file": "model/prelude.sail", "loc": [ 1476, 1485 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 37826, 37833 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38012, 38016 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38264, 38275 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38307, 38311 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38287, 38291 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38343, 38354 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38366, 38370 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38406, 38417 ] } ] }, "reg_name_abi": { "function": { "number": 0, "source": "function reg_name_abi(r) = {\n match (r) {\n 0b00000 => \"zero\",\n 0b00001 => \"ra\",\n 0b00010 => \"sp\",\n 0b00011 => \"gp\",\n 0b00100 => \"tp\",\n 0b00101 => \"t0\",\n 0b00110 => \"t1\",\n 0b00111 => \"t2\",\n 0b01000 => \"fp\",\n 0b01001 => \"s1\",\n 0b01010 => \"a0\",\n 0b01011 => \"a1\",\n 0b01100 => \"a2\",\n 0b01101 => \"a3\",\n 0b01110 => \"a4\",\n 0b01111 => \"a5\",\n 0b10000 => \"a6\",\n 0b10001 => \"a7\",\n 0b10010 => \"s2\",\n 0b10011 => \"s3\",\n 0b10100 => \"s4\",\n 0b10101 => \"s5\",\n 0b10110 => \"s6\",\n 0b10111 => \"s7\",\n 0b11000 => \"s8\",\n 0b11001 => \"s9\",\n 0b11010 => \"s10\",\n 0b11011 => \"s11\",\n 0b11100 => \"t3\",\n 0b11101 => \"t4\",\n 0b11110 => \"t5\",\n 0b11111 => \"t6\"\n }\n}", "pattern": { "type": "id", "id": "r" }, "body": " match (r) {\n 0b00000 => \"zero\",\n 0b00001 => \"ra\",\n 0b00010 => \"sp\",\n 0b00011 => \"gp\",\n 0b00100 => \"tp\",\n 0b00101 => \"t0\",\n 0b00110 => \"t1\",\n 0b00111 => \"t2\",\n 0b01000 => \"fp\",\n 0b01001 => \"s1\",\n 0b01010 => \"a0\",\n 0b01011 => \"a1\",\n 0b01100 => \"a2\",\n 0b01101 => \"a3\",\n 0b01110 => \"a4\",\n 0b01111 => \"a5\",\n 0b10000 => \"a6\",\n 0b10001 => \"a7\",\n 0b10010 => \"s2\",\n 0b10011 => \"s3\",\n 0b10100 => \"s4\",\n 0b10101 => \"s5\",\n 0b10110 => \"s6\",\n 0b10111 => \"s7\",\n 0b11000 => \"s8\",\n 0b11001 => \"s9\",\n 0b11010 => \"s10\",\n 0b11011 => \"s11\",\n 0b11100 => \"t3\",\n 0b11101 => \"t4\",\n 0b11110 => \"t5\",\n 0b11111 => \"t6\"\n }" } }, "regidx_to_regno": { "function": { "number": 0, "source": "function regidx_to_regno b = let 'r = unsigned(b) in r", "pattern": { "type": "id", "id": "b" }, "body": "let 'r = unsigned(b) in r" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_types.sail", "loc": [ 1389, 1397 ] } ] }, "regval_from_reg": { "function": { "number": 0, "source": "function regval_from_reg(r) = r", "pattern": { "type": "id", "id": "r" }, "body": "r" } }, "regval_into_reg": { "function": { "number": 0, "source": "function regval_into_reg(v) = v", "pattern": { "type": "id", "id": "v" }, "body": "v" } }, "report_invalid_width": { "function": { "number": 0, "source": "function report_invalid_width(f , l, w, k) -> 'a = {\n /*\n * Ideally we would call internal_error here but this triggers a Sail bug,\n * https://github.com/rems-project/sail/issues/203 in versions < 0.15.1, so\n * we work around this by manually inlining.\n * TODO when we are happy to require Sail >= 0.15.1 uncomment the following\n * and remove the rest of the function.\n */\n // internal_error(f, l, \"Invalid width, \" ^ size_mnemonic(w) ^ \", for \" ^ k ^\n // \" with xlen=\" ^ dec_str(sizeof(xlen)));\n assert (false, f ^ \":\" ^ dec_str(l) ^ \": \" ^ \"Invalid width, \"\n ^ size_mnemonic(w) ^ \", for \" ^ k ^ \" with xlen=\"\n ^ dec_str(sizeof(xlen)));\n throw Error_internal_error()\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "f" }, { "type": "id", "id": "l" }, { "type": "id", "id": "w" }, { "type": "id", "id": "k" } ] }, "body": "function report_invalid_width(f , l, w, k) -> 'a = {\n /*\n * Ideally we would call internal_error here but this triggers a Sail bug,\n * https://github.com/rems-project/sail/issues/203 in versions < 0.15.1, so\n * we work around this by manually inlining.\n * TODO when we are happy to require Sail >= 0.15.1 uncomment the following\n * and remove the rest of the function.\n */\n // internal_error(f, l, \"Invalid width, \" ^ size_mnemonic(w) ^ \", for \" ^ k ^\n // \" with xlen=\" ^ dec_str(sizeof(xlen)));\n assert (false, f ^ \":\" ^ dec_str(l) ^ \": \" ^ \"Invalid width, \"\n ^ size_mnemonic(w) ^ \", for \" ^ k ^ \" with xlen=\"\n ^ dec_str(sizeof(xlen)));\n throw Error_internal_error()\n}" }, "links": [ { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_types.sail", "loc": [ 12230, 12237 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_types.sail", "loc": [ 12132, 12139 ] } ] }, "reset_htif": { "function": { "number": 0, "source": "function reset_htif () -> unit = {\n htif_cmd_write = bitzero;\n htif_payload_writes = 0x0;\n htif_tohost = zero_extend(0b0);\n}", "pattern": { "type": "literal", "value": "()" }, "body": " htif_cmd_write = bitzero;\n htif_payload_writes = 0x0;\n htif_tohost = zero_extend(0b0)" }, "links": [ { "type": "register", "id": "htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 13039, 13050 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 13053, 13064 ] }, { "type": "register", "id": "htif_payload_writes", "file": "model/riscv_platform.sail", "loc": [ 13010, 13029 ] }, { "type": "register", "id": "htif_cmd_write", "file": "model/riscv_platform.sail", "loc": [ 12982, 12996 ] } ] }, "retire_instruction": { "function": { "number": 0, "source": "function retire_instruction() -> unit = {\n if minstret_increment then minstret = minstret + 1;\n}", "pattern": { "type": "literal", "value": "()" }, "body": " if minstret_increment then minstret = minstret + 1" }, "links": [ { "type": "register", "id": "minstret_increment", "file": "model/riscv_sys_regs.sail", "loc": [ 16178, 16196 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_sys_regs.sail", "loc": [ 16202, 16210 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_sys_regs.sail", "loc": [ 16213, 16221 ] } ] }, "reverse_bits_in_byte": { "function": { "number": 0, "source": "function reverse_bits_in_byte (xs : bits(8)) -> bits(8) = {\n ys : bits(8) = zeros();\n foreach (i from 0 to 7)\n ys[i] = xs[7-i];\n ys\n}", "pattern": { "type": "id", "id": "xs" }, "body": "function reverse_bits_in_byte (xs : bits(8)) -> bits(8) = {\n ys : bits(8) = zeros();\n foreach (i from 0 to 7)\n ys[i] = xs[7-i];\n ys\n}" }, "links": [ { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "rfvvfunct6_of_num": { "function": { "number": 0, "source": "rfvvfunct6_of_num arg# = $[complete] match arg# {\n 0 => FVV_VFREDOSUM,\n 1 => FVV_VFREDUSUM,\n 2 => FVV_VFREDMAX,\n 3 => FVV_VFREDMIN,\n 4 => FVV_VFWREDOSUM,\n _ => FVV_VFWREDUSUM\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FVV_VFREDOSUM,\n 1 => FVV_VFREDUSUM,\n 2 => FVV_VFREDMAX,\n 3 => FVV_VFREDMIN,\n 4 => FVV_VFWREDOSUM,\n _ => FVV_VFWREDUSUM\n}" } }, "riscv_f16Add": { "function": { "number": 0, "source": "function riscv_f16Add (rm, v1, v2) = {\n extern_f16Add(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Add(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3017, 3029 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 2995, 3007 ] }, { "type": "function", "id": "extern_f16Add", "file": "model/riscv_softfloat_interface.sail", "loc": [ 2965, 2978 ] } ] }, "riscv_f16Div": { "function": { "number": 0, "source": "function riscv_f16Div (rm, v1, v2) = {\n extern_f16Div(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Div(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4013, 4025 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3991, 4003 ] }, { "type": "function", "id": "extern_f16Div", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3961, 3974 ] } ] }, "riscv_f16Eq": { "function": { "number": 0, "source": "function riscv_f16Eq (v1, v2) = {\n extern_f16Eq(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Eq(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20507, 20518 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20519, 20531 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20485, 20497 ] }, { "type": "function", "id": "extern_f16Eq", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20460, 20472 ] } ] }, "riscv_f16Le": { "function": { "number": 0, "source": "function riscv_f16Le (v1, v2) = {\n extern_f16Le(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Le(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19857, 19868 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19869, 19881 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19835, 19847 ] }, { "type": "function", "id": "extern_f16Le", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19810, 19822 ] } ] }, "riscv_f16Le_quiet": { "function": { "number": 0, "source": "function riscv_f16Le_quiet (v1, v2) = {\n extern_f16Le_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Le_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20203, 20214 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20215, 20227 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20181, 20193 ] }, { "type": "function", "id": "extern_f16Le_quiet", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20150, 20168 ] } ] }, "riscv_f16Lt": { "function": { "number": 0, "source": "function riscv_f16Lt (v1, v2) = {\n extern_f16Lt(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Lt(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19207, 19218 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19219, 19231 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19185, 19197 ] }, { "type": "function", "id": "extern_f16Lt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19160, 19172 ] } ] }, "riscv_f16Lt_quiet": { "function": { "number": 0, "source": "function riscv_f16Lt_quiet (v1, v2) = {\n extern_f16Lt_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Lt_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19553, 19564 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19565, 19577 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19531, 19543 ] }, { "type": "function", "id": "extern_f16Lt_quiet", "file": "model/riscv_softfloat_interface.sail", "loc": [ 19500, 19518 ] } ] }, "riscv_f16Mul": { "function": { "number": 0, "source": "function riscv_f16Mul (rm, v1, v2) = {\n extern_f16Mul(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Mul(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3681, 3693 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3659, 3671 ] }, { "type": "function", "id": "extern_f16Mul", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3629, 3642 ] } ] }, "riscv_f16MulAdd": { "function": { "number": 0, "source": "function riscv_f16MulAdd (rm, v1, v2, v3) = {\n extern_f16MulAdd(rm, v1, v2, v3);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" }, { "type": "id", "id": "v3" } ] }, "body": " extern_f16MulAdd(rm, v1, v2, v3);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7153, 7165 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7131, 7143 ] }, { "type": "function", "id": "extern_f16MulAdd", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7094, 7110 ] } ] }, "riscv_f16Recip7": { "function": { "number": 0, "source": "function riscv_f16Recip7 (rm, v) = {\n let (round_abnormal_true, res_true) = recip7(v, rm, true);\n let (round_abnormal_false, res_false) = recip7(v, rm, false);\n match fp_class(v) {\n 0x0001 => (zeros(5), 0x8000),\n 0x0080 => (zeros(5), 0x0000),\n 0x0008 => (dzFlag(), 0xfc00),\n 0x0010 => (dzFlag(), 0x7c00),\n 0x0100 => (nvFlag(), 0x7e00),\n 0x0200 => (zeros(5), 0x7e00),\n 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[15 .. 0]) else (zeros(5), res_true[15 .. 0]),\n 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[15 .. 0]) else (zeros(5), res_true[15 .. 0]),\n _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[15 .. 0]) else (zeros(5), res_false[15 .. 0])\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (round_abnormal_true, res_true) = recip7(v, rm, true);\n let (round_abnormal_false, res_false) = recip7(v, rm, false);\n match fp_class(v) {\n 0x0001 => (zeros(5), 0x8000),\n 0x0080 => (zeros(5), 0x0000),\n 0x0008 => (dzFlag(), 0xfc00),\n 0x0010 => (dzFlag(), 0x7c00),\n 0x0100 => (nvFlag(), 0x7e00),\n 0x0200 => (zeros(5), 0x7e00),\n 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[15 .. 0]) else (zeros(5), res_true[15 .. 0]),\n 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[15 .. 0]) else (zeros(5), res_true[15 .. 0]),\n _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[15 .. 0]) else (zeros(5), res_false[15 .. 0])\n }" }, "links": [ { "type": "function", "id": "recip7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38594, 38600 ] }, { "type": "function", "id": "recip7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38657, 38663 ] }, { "type": "function", "id": "fp_class", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38687, 38695 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39198, 39204 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39187, 39193 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39078, 39084 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39067, 39073 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38959, 38965 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38948, 38954 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38852, 38858 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38818, 38824 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 38784, 38790 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f16Rsqrte7": { "function": { "number": 0, "source": "function riscv_f16Rsqrte7 (rm, v) = {\n match fp_class(v) {\n 0x0001 => (nvFlag(), 0x7e00),\n 0x0002 => (nvFlag(), 0x7e00),\n 0x0004 => (nvFlag(), 0x7e00),\n 0x0100 => (nvFlag(), 0x7e00),\n 0x0200 => (zeros(5), 0x7e00),\n 0x0008 => (dzFlag(), 0xfc00),\n 0x0010 => (dzFlag(), 0x7c00),\n 0x0080 => (zeros(5), 0x0000),\n 0x0020 => (zeros(5), rsqrt7(v, true)[15 .. 0]),\n _ => (zeros(5), rsqrt7(v, false)[15 .. 0])\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " match fp_class(v) {\n 0x0001 => (nvFlag(), 0x7e00),\n 0x0002 => (nvFlag(), 0x7e00),\n 0x0004 => (nvFlag(), 0x7e00),\n 0x0100 => (nvFlag(), 0x7e00),\n 0x0200 => (zeros(5), 0x7e00),\n 0x0008 => (dzFlag(), 0xfc00),\n 0x0010 => (dzFlag(), 0x7c00),\n 0x0080 => (zeros(5), 0x0000),\n 0x0020 => (zeros(5), rsqrt7(v, true)[15 .. 0]),\n _ => (zeros(5), rsqrt7(v, false)[15 .. 0])\n }" }, "links": [ { "type": "function", "id": "fp_class", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34496, 34504 ] }, { "type": "function", "id": "rsqrt7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34859, 34865 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "rsqrt7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34807, 34813 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34729, 34735 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34695, 34701 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34627, 34633 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34593, 34599 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34559, 34565 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34525, 34531 ] } ] }, "riscv_f16Sqrt": { "function": { "number": 0, "source": "function riscv_f16Sqrt (rm, v) = {\n extern_f16Sqrt(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f16Sqrt(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8354, 8366 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8332, 8344 ] }, { "type": "function", "id": "extern_f16Sqrt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8306, 8320 ] } ] }, "riscv_f16Sub": { "function": { "number": 0, "source": "function riscv_f16Sub (rm, v1, v2) = {\n extern_f16Sub(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f16Sub(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3349, 3361 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3327, 3339 ] }, { "type": "function", "id": "extern_f16Sub", "file": "model/riscv_softfloat_interface.sail", "loc": [ 3297, 3310 ] } ] }, "riscv_f16ToF32": { "function": { "number": 0, "source": "function riscv_f16ToF32 (rm, v) = {\n extern_f16ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f16ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17175, 17187 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17153, 17165 ] }, { "type": "function", "id": "extern_f16ToF32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17126, 17141 ] } ] }, "riscv_f16ToF64": { "function": { "number": 0, "source": "function riscv_f16ToF64 (rm, v) = {\n extern_f16ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f16ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17497, 17509 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17475, 17487 ] }, { "type": "function", "id": "extern_f16ToF64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17448, 17463 ] } ] }, "riscv_f16ToI16": { "function": { "number": 0, "source": "function riscv_f16ToI16 (rm, v) = {\n let (_, sig32) = riscv_f16ToI32(rm, v);\n if signed(sig32) > signed(0b0 @ ones(15)) then (nvFlag(), 0b0 @ ones(15))\n else if signed(sig32) < signed(0b1 @ zeros(15)) then (nvFlag(), 0b1 @ zeros(15))\n else (zeros(5), sig32[15 .. 0]);\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (_, sig32) = riscv_f16ToI32(rm, v);\n if signed(sig32) > signed(0b0 @ ones(15)) then (nvFlag(), 0b0 @ ones(15))\n else if signed(sig32) < signed(0b1 @ zeros(15)) then (nvFlag(), 0b1 @ zeros(15))\n else (zeros(5), sig32[15 .. 0]);" }, "links": [ { "type": "function", "id": "riscv_f16ToI32", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30555, 30569 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30599, 30605 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30612, 30616 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30583, 30589 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30644, 30648 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30628, 30634 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30680, 30686 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30664, 30670 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30710, 30716 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f16ToI32": { "function": { "number": 0, "source": "function riscv_f16ToI32 (rm, v) = {\n extern_f16ToI32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f16ToI32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 9436, 9448 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 9414, 9426 ] }, { "type": "function", "id": "extern_f16ToI32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 9387, 9402 ] } ] }, "riscv_f16ToI64": { "function": { "number": 0, "source": "function riscv_f16ToI64 (rm, v) = {\n extern_f16ToI64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f16ToI64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10741, 10753 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10719, 10731 ] }, { "type": "function", "id": "extern_f16ToI64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10692, 10707 ] } ] }, "riscv_f16ToI8": { "function": { "number": 0, "source": "function riscv_f16ToI8 (rm, v) = {\n let (_, sig32) = riscv_f16ToI32(rm, v);\n if signed(sig32) > signed(0b0 @ ones(7)) then (nvFlag(), 0b0 @ ones(7))\n else if signed(sig32) < signed(0b1 @ zeros(7)) then (nvFlag(), 0b1 @ zeros(7))\n else (zeros(5), sig32[7 .. 0]);\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (_, sig32) = riscv_f16ToI32(rm, v);\n if signed(sig32) > signed(0b0 @ ones(7)) then (nvFlag(), 0b0 @ ones(7))\n else if signed(sig32) < signed(0b1 @ zeros(7)) then (nvFlag(), 0b1 @ zeros(7))\n else (zeros(5), sig32[7 .. 0]);" }, "links": [ { "type": "function", "id": "riscv_f16ToI32", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30893, 30907 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30937, 30943 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30950, 30954 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30921, 30927 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30981, 30985 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 30965, 30971 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31016, 31022 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31000, 31006 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31045, 31051 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f16ToUi16": { "function": { "number": 0, "source": "function riscv_f16ToUi16 (rm, v) = {\n let (_, sig32) = riscv_f16ToUi32(rm, v);\n if unsigned(sig32) > unsigned(ones(16)) then (nvFlag(), ones(16))\n else (zeros(5), sig32[15 .. 0]);\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (_, sig32) = riscv_f16ToUi32(rm, v);\n if unsigned(sig32) > unsigned(ones(16)) then (nvFlag(), ones(16))\n else (zeros(5), sig32[15 .. 0]);" }, "links": [ { "type": "function", "id": "riscv_f16ToUi32", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31572, 31587 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31619, 31627 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31628, 31632 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31601, 31609 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31654, 31658 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31644, 31650 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f16ToUi32": { "function": { "number": 0, "source": "function riscv_f16ToUi32 (rm, v) = {\n extern_f16ToUi32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f16ToUi32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 9766, 9778 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 9744, 9756 ] }, { "type": "function", "id": "extern_f16ToUi32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 9716, 9732 ] } ] }, "riscv_f16ToUi64": { "function": { "number": 0, "source": "function riscv_f16ToUi64 (rm, v) = {\n extern_f16ToUi64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f16ToUi64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11062, 11074 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11040, 11052 ] }, { "type": "function", "id": "extern_f16ToUi64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11012, 11028 ] } ] }, "riscv_f16ToUi8": { "function": { "number": 0, "source": "function riscv_f16ToUi8 (rm, v) = {\n let (_, sig32) = riscv_f16ToUi32(rm, v);\n if unsigned(sig32) > unsigned(ones(8)) then (nvFlag(), ones(8))\n else (zeros(5), sig32[7 .. 0]);\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (_, sig32) = riscv_f16ToUi32(rm, v);\n if unsigned(sig32) > unsigned(ones(8)) then (nvFlag(), ones(8))\n else (zeros(5), sig32[7 .. 0]);" }, "links": [ { "type": "function", "id": "riscv_f16ToUi32", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31822, 31837 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31869, 31877 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31878, 31882 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31851, 31859 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31903, 31907 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31893, 31899 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f16roundToInt": { "function": { "number": 0, "source": "function riscv_f16roundToInt (rm, v, exact) = {\n extern_f16roundToInt(rm, v, exact);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" }, { "type": "id", "id": "exact" } ] }, "body": " extern_f16roundToInt(rm, v, exact);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24107, 24119 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24085, 24097 ] }, { "type": "function", "id": "extern_f16roundToInt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24046, 24066 ] } ] }, "riscv_f32Add": { "function": { "number": 0, "source": "function riscv_f32Add (rm, v1, v2) = {\n extern_f32Add(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Add(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4345, 4357 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4323, 4335 ] }, { "type": "function", "id": "extern_f32Add", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4293, 4306 ] } ] }, "riscv_f32Div": { "function": { "number": 0, "source": "function riscv_f32Div (rm, v1, v2) = {\n extern_f32Div(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Div(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5341, 5353 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5319, 5331 ] }, { "type": "function", "id": "extern_f32Div", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5289, 5302 ] } ] }, "riscv_f32Eq": { "function": { "number": 0, "source": "function riscv_f32Eq (v1, v2) = {\n extern_f32Eq(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Eq(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22111, 22122 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22123, 22135 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22089, 22101 ] }, { "type": "function", "id": "extern_f32Eq", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22064, 22076 ] } ] }, "riscv_f32Le": { "function": { "number": 0, "source": "function riscv_f32Le (v1, v2) = {\n extern_f32Le(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Le(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21461, 21472 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21473, 21485 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21439, 21451 ] }, { "type": "function", "id": "extern_f32Le", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21414, 21426 ] } ] }, "riscv_f32Le_quiet": { "function": { "number": 0, "source": "function riscv_f32Le_quiet (v1, v2) = {\n extern_f32Le_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Le_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21807, 21818 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21819, 21831 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21785, 21797 ] }, { "type": "function", "id": "extern_f32Le_quiet", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21754, 21772 ] } ] }, "riscv_f32Lt": { "function": { "number": 0, "source": "function riscv_f32Lt (v1, v2) = {\n extern_f32Lt(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Lt(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20811, 20822 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20823, 20835 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20789, 20801 ] }, { "type": "function", "id": "extern_f32Lt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 20764, 20776 ] } ] }, "riscv_f32Lt_quiet": { "function": { "number": 0, "source": "function riscv_f32Lt_quiet (v1, v2) = {\n extern_f32Lt_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Lt_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21157, 21168 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21169, 21181 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21135, 21147 ] }, { "type": "function", "id": "extern_f32Lt_quiet", "file": "model/riscv_softfloat_interface.sail", "loc": [ 21104, 21122 ] } ] }, "riscv_f32Mul": { "function": { "number": 0, "source": "function riscv_f32Mul (rm, v1, v2) = {\n extern_f32Mul(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Mul(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5009, 5021 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4987, 4999 ] }, { "type": "function", "id": "extern_f32Mul", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4957, 4970 ] } ] }, "riscv_f32MulAdd": { "function": { "number": 0, "source": "function riscv_f32MulAdd (rm, v1, v2, v3) = {\n extern_f32MulAdd(rm, v1, v2, v3);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" }, { "type": "id", "id": "v3" } ] }, "body": " extern_f32MulAdd(rm, v1, v2, v3);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7530, 7542 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7508, 7520 ] }, { "type": "function", "id": "extern_f32MulAdd", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7471, 7487 ] } ] }, "riscv_f32Recip7": { "function": { "number": 0, "source": "function riscv_f32Recip7 (rm, v) = {\n let (round_abnormal_true, res_true) = recip7(v, rm, true);\n let (round_abnormal_false, res_false) = recip7(v, rm, false);\n match fp_class(v)[15 .. 0] {\n 0x0001 => (zeros(5), 0x80000000),\n 0x0080 => (zeros(5), 0x00000000),\n 0x0008 => (dzFlag(), 0xff800000),\n 0x0010 => (dzFlag(), 0x7f800000),\n 0x0100 => (nvFlag(), 0x7fc00000),\n 0x0200 => (zeros(5), 0x7fc00000),\n 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[31 .. 0]) else (zeros(5), res_true[31 .. 0]),\n 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[31 .. 0]) else (zeros(5), res_true[31 .. 0]),\n _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[31 .. 0]) else (zeros(5), res_false[31 .. 0])\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (round_abnormal_true, res_true) = recip7(v, rm, true);\n let (round_abnormal_false, res_false) = recip7(v, rm, false);\n match fp_class(v)[15 .. 0] {\n 0x0001 => (zeros(5), 0x80000000),\n 0x0080 => (zeros(5), 0x00000000),\n 0x0008 => (dzFlag(), 0xff800000),\n 0x0010 => (dzFlag(), 0x7f800000),\n 0x0100 => (nvFlag(), 0x7fc00000),\n 0x0200 => (zeros(5), 0x7fc00000),\n 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[31 .. 0]) else (zeros(5), res_true[31 .. 0]),\n 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[31 .. 0]) else (zeros(5), res_true[31 .. 0]),\n _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[31 .. 0]) else (zeros(5), res_false[31 .. 0])\n }" }, "links": [ { "type": "function", "id": "recip7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39413, 39419 ] }, { "type": "function", "id": "recip7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39476, 39482 ] }, { "type": "function", "id": "fp_class", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39506, 39514 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40050, 40056 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40039, 40045 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39930, 39936 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39919, 39925 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39811, 39817 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39800, 39806 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39696, 39702 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39658, 39664 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 39620, 39626 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f32Rsqrte7": { "function": { "number": 0, "source": "function riscv_f32Rsqrte7 (rm, v) = {\n match fp_class(v)[15 .. 0] {\n 0x0001 => (nvFlag(), 0x7fc00000),\n 0x0002 => (nvFlag(), 0x7fc00000),\n 0x0004 => (nvFlag(), 0x7fc00000),\n 0x0100 => (nvFlag(), 0x7fc00000),\n 0x0200 => (zeros(5), 0x7fc00000),\n 0x0008 => (dzFlag(), 0xff800000),\n 0x0010 => (dzFlag(), 0x7f800000),\n 0x0080 => (zeros(5), 0x00000000),\n 0x0020 => (zeros(5), rsqrt7(v, true)[31 .. 0]),\n _ => (zeros(5), rsqrt7(v, false)[31 .. 0])\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " match fp_class(v)[15 .. 0] {\n 0x0001 => (nvFlag(), 0x7fc00000),\n 0x0002 => (nvFlag(), 0x7fc00000),\n 0x0004 => (nvFlag(), 0x7fc00000),\n 0x0100 => (nvFlag(), 0x7fc00000),\n 0x0200 => (zeros(5), 0x7fc00000),\n 0x0008 => (dzFlag(), 0xff800000),\n 0x0010 => (dzFlag(), 0x7f800000),\n 0x0080 => (zeros(5), 0x00000000),\n 0x0020 => (zeros(5), rsqrt7(v, true)[31 .. 0]),\n _ => (zeros(5), rsqrt7(v, false)[31 .. 0])\n }" }, "links": [ { "type": "function", "id": "fp_class", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35005, 35013 ] }, { "type": "function", "id": "rsqrt7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35409, 35415 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "rsqrt7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35357, 35363 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35271, 35277 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35233, 35239 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35157, 35163 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35119, 35125 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35081, 35087 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35043, 35049 ] } ] }, "riscv_f32Sqrt": { "function": { "number": 0, "source": "function riscv_f32Sqrt (rm, v) = {\n extern_f32Sqrt(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f32Sqrt(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8667, 8679 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8645, 8657 ] }, { "type": "function", "id": "extern_f32Sqrt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8619, 8633 ] } ] }, "riscv_f32Sub": { "function": { "number": 0, "source": "function riscv_f32Sub (rm, v1, v2) = {\n extern_f32Sub(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f32Sub(rm, v1, v2);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4677, 4689 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4655, 4667 ] }, { "type": "function", "id": "extern_f32Sub", "file": "model/riscv_softfloat_interface.sail", "loc": [ 4625, 4638 ] } ] }, "riscv_f32ToF16": { "function": { "number": 0, "source": "function riscv_f32ToF16 (rm, v) = {\n extern_f32ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f32ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18123, 18135 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18101, 18113 ] }, { "type": "function", "id": "extern_f32ToF16", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18074, 18089 ] } ] }, "riscv_f32ToF64": { "function": { "number": 0, "source": "function riscv_f32ToF64 (rm, v) = {\n extern_f32ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f32ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17810, 17822 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17788, 17800 ] }, { "type": "function", "id": "extern_f32ToF64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 17761, 17776 ] } ] }, "riscv_f32ToI16": { "function": { "number": 0, "source": "function riscv_f32ToI16 (rm, v) = {\n let (_, sig32) = riscv_f32ToI32(rm, v);\n if signed(sig32) > signed(0b0 @ ones(15)) then (nvFlag(), 0b0 @ ones(15))\n else if signed(sig32) < signed(0b1 @ zeros(15)) then (nvFlag(), 0b1 @ zeros(15))\n else (zeros(5), sig32[15 .. 0]);\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (_, sig32) = riscv_f32ToI32(rm, v);\n if signed(sig32) > signed(0b0 @ ones(15)) then (nvFlag(), 0b0 @ ones(15))\n else if signed(sig32) < signed(0b1 @ zeros(15)) then (nvFlag(), 0b1 @ zeros(15))\n else (zeros(5), sig32[15 .. 0]);" }, "links": [ { "type": "function", "id": "riscv_f32ToI32", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31229, 31243 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31273, 31279 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31286, 31290 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31257, 31263 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31318, 31322 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31302, 31308 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31354, 31360 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31338, 31344 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 31384, 31390 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f32ToI32": { "function": { "number": 0, "source": "function riscv_f32ToI32 (rm, v) = {\n extern_f32ToI32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f32ToI32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12028, 12040 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12006, 12018 ] }, { "type": "function", "id": "extern_f32ToI32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11979, 11994 ] } ] }, "riscv_f32ToI64": { "function": { "number": 0, "source": "function riscv_f32ToI64 (rm, v) = {\n extern_f32ToI64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f32ToI64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13333, 13345 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13311, 13323 ] }, { "type": "function", "id": "extern_f32ToI64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13284, 13299 ] } ] }, "riscv_f32ToUi16": { "function": { "number": 0, "source": "function riscv_f32ToUi16 (rm, v) = {\n let (_, sig32) = riscv_f32ToUi32(rm, v);\n if unsigned(sig32) > unsigned(ones(16)) then (nvFlag(), ones(16))\n else (zeros(5), sig32[15 .. 0]);\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (_, sig32) = riscv_f32ToUi32(rm, v);\n if unsigned(sig32) > unsigned(ones(16)) then (nvFlag(), ones(16))\n else (zeros(5), sig32[15 .. 0]);" }, "links": [ { "type": "function", "id": "riscv_f32ToUi32", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32072, 32087 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32119, 32127 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32128, 32132 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32101, 32109 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32154, 32158 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32144, 32150 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f32ToUi32": { "function": { "number": 0, "source": "function riscv_f32ToUi32 (rm, v) = {\n extern_f32ToUi32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f32ToUi32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12358, 12370 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12336, 12348 ] }, { "type": "function", "id": "extern_f32ToUi32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12308, 12324 ] } ] }, "riscv_f32ToUi64": { "function": { "number": 0, "source": "function riscv_f32ToUi64 (rm, v) = {\n extern_f32ToUi64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f32ToUi64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13654, 13666 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13632, 13644 ] }, { "type": "function", "id": "extern_f32ToUi64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13604, 13620 ] } ] }, "riscv_f32roundToInt": { "function": { "number": 0, "source": "function riscv_f32roundToInt (rm, v, exact) = {\n extern_f32roundToInt(rm, v, exact);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" }, { "type": "id", "id": "exact" } ] }, "body": " extern_f32roundToInt(rm, v, exact);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24492, 24504 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24470, 24482 ] }, { "type": "function", "id": "extern_f32roundToInt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24431, 24451 ] } ] }, "riscv_f64Add": { "function": { "number": 0, "source": "function riscv_f64Add (rm, v1, v2) = {\n extern_f64Add(rm, v1, v2);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Add(rm, v1, v2);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5673, 5685 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5651, 5663 ] }, { "type": "function", "id": "extern_f64Add", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5621, 5634 ] } ] }, "riscv_f64Div": { "function": { "number": 0, "source": "function riscv_f64Div (rm, v1, v2) = {\n extern_f64Div(rm, v1, v2);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Div(rm, v1, v2);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 6642, 6654 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 6620, 6632 ] }, { "type": "function", "id": "extern_f64Div", "file": "model/riscv_softfloat_interface.sail", "loc": [ 6590, 6603 ] } ] }, "riscv_f64Eq": { "function": { "number": 0, "source": "function riscv_f64Eq (v1, v2) = {\n extern_f64Eq(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Eq(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23715, 23726 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23727, 23739 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23693, 23705 ] }, { "type": "function", "id": "extern_f64Eq", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23668, 23680 ] } ] }, "riscv_f64Le": { "function": { "number": 0, "source": "function riscv_f64Le (v1, v2) = {\n extern_f64Le(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Le(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23065, 23076 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23077, 23089 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23043, 23055 ] }, { "type": "function", "id": "extern_f64Le", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23018, 23030 ] } ] }, "riscv_f64Le_quiet": { "function": { "number": 0, "source": "function riscv_f64Le_quiet (v1, v2) = {\n extern_f64Le_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Le_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23411, 23422 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23423, 23435 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23389, 23401 ] }, { "type": "function", "id": "extern_f64Le_quiet", "file": "model/riscv_softfloat_interface.sail", "loc": [ 23358, 23376 ] } ] }, "riscv_f64Lt": { "function": { "number": 0, "source": "function riscv_f64Lt (v1, v2) = {\n extern_f64Lt(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Lt(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22415, 22426 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22427, 22439 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22393, 22405 ] }, { "type": "function", "id": "extern_f64Lt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22368, 22380 ] } ] }, "riscv_f64Lt_quiet": { "function": { "number": 0, "source": "function riscv_f64Lt_quiet (v1, v2) = {\n extern_f64Lt_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Lt_quiet(v1, v2);\n (float_fflags[4 .. 0], bit_to_bool(float_result[0]))" }, "links": [ { "type": "function", "id": "bit_to_bool", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22761, 22772 ] }, { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22773, 22785 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22739, 22751 ] }, { "type": "function", "id": "extern_f64Lt_quiet", "file": "model/riscv_softfloat_interface.sail", "loc": [ 22708, 22726 ] } ] }, "riscv_f64Mul": { "function": { "number": 0, "source": "function riscv_f64Mul (rm, v1, v2) = {\n extern_f64Mul(rm, v1, v2);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Mul(rm, v1, v2);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 6319, 6331 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 6297, 6309 ] }, { "type": "function", "id": "extern_f64Mul", "file": "model/riscv_softfloat_interface.sail", "loc": [ 6267, 6280 ] } ] }, "riscv_f64MulAdd": { "function": { "number": 0, "source": "function riscv_f64MulAdd (rm, v1, v2, v3) = {\n extern_f64MulAdd(rm, v1, v2, v3);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" }, { "type": "id", "id": "v3" } ] }, "body": " extern_f64MulAdd(rm, v1, v2, v3);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7907, 7919 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7885, 7897 ] }, { "type": "function", "id": "extern_f64MulAdd", "file": "model/riscv_softfloat_interface.sail", "loc": [ 7848, 7864 ] } ] }, "riscv_f64Recip7": { "function": { "number": 0, "source": "function riscv_f64Recip7 (rm, v) = {\n let (round_abnormal_true, res_true) = recip7(v, rm, true);\n let (round_abnormal_false, res_false) = recip7(v, rm, false);\n match fp_class(v)[15 .. 0] {\n 0x0001 => (zeros(5), 0x8000000000000000),\n 0x0080 => (zeros(5), 0x0000000000000000),\n 0x0008 => (dzFlag(), 0xfff0000000000000),\n 0x0010 => (dzFlag(), 0x7ff0000000000000),\n 0x0100 => (nvFlag(), 0x7ff8000000000000),\n 0x0200 => (zeros(5), 0x7ff8000000000000),\n 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[63 .. 0]) else (zeros(5), res_true[63 .. 0]),\n 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[63 .. 0]) else (zeros(5), res_true[63 .. 0]),\n _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[63 .. 0]) else (zeros(5), res_false[63 .. 0])\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " let (round_abnormal_true, res_true) = recip7(v, rm, true);\n let (round_abnormal_false, res_false) = recip7(v, rm, false);\n match fp_class(v)[15 .. 0] {\n 0x0001 => (zeros(5), 0x8000000000000000),\n 0x0080 => (zeros(5), 0x0000000000000000),\n 0x0008 => (dzFlag(), 0xfff0000000000000),\n 0x0010 => (dzFlag(), 0x7ff0000000000000),\n 0x0100 => (nvFlag(), 0x7ff8000000000000),\n 0x0200 => (zeros(5), 0x7ff8000000000000),\n 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[63 .. 0]) else (zeros(5), res_true[63 .. 0]),\n 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[63 .. 0]) else (zeros(5), res_true[63 .. 0]),\n _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[63 .. 0]) else (zeros(5), res_false[63 .. 0])\n }" }, "links": [ { "type": "function", "id": "recip7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40265, 40271 ] }, { "type": "function", "id": "recip7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40328, 40334 ] }, { "type": "function", "id": "fp_class", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40358, 40366 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40950, 40956 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40939, 40945 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40830, 40836 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40819, 40825 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "ofFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40711, 40717 ] }, { "type": "function", "id": "nxFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40700, 40706 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40580, 40586 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40534, 40540 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 40488, 40494 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] } ] }, "riscv_f64Rsqrte7": { "function": { "number": 0, "source": "function riscv_f64Rsqrte7 (rm, v) = {\n match fp_class(v)[15 .. 0] {\n 0x0001 => (nvFlag(), 0x7ff8000000000000),\n 0x0002 => (nvFlag(), 0x7ff8000000000000),\n 0x0004 => (nvFlag(), 0x7ff8000000000000),\n 0x0100 => (nvFlag(), 0x7ff8000000000000),\n 0x0200 => (zeros(5), 0x7ff8000000000000),\n 0x0008 => (dzFlag(), 0xfff0000000000000),\n 0x0010 => (dzFlag(), 0x7ff0000000000000),\n 0x0080 => (zeros(5), zeros(64)),\n 0x0020 => (zeros(5), rsqrt7(v, true)[63 .. 0]),\n _ => (zeros(5), rsqrt7(v, false)[63 .. 0])\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " match fp_class(v)[15 .. 0] {\n 0x0001 => (nvFlag(), 0x7ff8000000000000),\n 0x0002 => (nvFlag(), 0x7ff8000000000000),\n 0x0004 => (nvFlag(), 0x7ff8000000000000),\n 0x0100 => (nvFlag(), 0x7ff8000000000000),\n 0x0200 => (zeros(5), 0x7ff8000000000000),\n 0x0008 => (dzFlag(), 0xfff0000000000000),\n 0x0010 => (dzFlag(), 0x7ff0000000000000),\n 0x0080 => (zeros(5), zeros(64)),\n 0x0020 => (zeros(5), rsqrt7(v, true)[63 .. 0]),\n _ => (zeros(5), rsqrt7(v, false)[63 .. 0])\n }" }, "links": [ { "type": "function", "id": "fp_class", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35555, 35563 ] }, { "type": "function", "id": "rsqrt7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 36014, 36020 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "rsqrt7", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35962, 35968 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35869, 35875 ] }, { "type": "function", "id": "dzFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35823, 35829 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35731, 35737 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35685, 35691 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35639, 35645 ] }, { "type": "function", "id": "nvFlag", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 35593, 35599 ] } ] }, "riscv_f64Sqrt": { "function": { "number": 0, "source": "function riscv_f64Sqrt (rm, v) = {\n extern_f64Sqrt(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f64Sqrt(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8980, 8992 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8958, 8970 ] }, { "type": "function", "id": "extern_f64Sqrt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 8932, 8946 ] } ] }, "riscv_f64Sub": { "function": { "number": 0, "source": "function riscv_f64Sub (rm, v1, v2) = {\n extern_f64Sub(rm, v1, v2);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v1" }, { "type": "id", "id": "v2" } ] }, "body": " extern_f64Sub(rm, v1, v2);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5996, 6008 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5974, 5986 ] }, { "type": "function", "id": "extern_f64Sub", "file": "model/riscv_softfloat_interface.sail", "loc": [ 5944, 5957 ] } ] }, "riscv_f64ToF16": { "function": { "number": 0, "source": "function riscv_f64ToF16 (rm, v) = {\n extern_f64ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f64ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18445, 18457 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18423, 18435 ] }, { "type": "function", "id": "extern_f64ToF16", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18396, 18411 ] } ] }, "riscv_f64ToF32": { "function": { "number": 0, "source": "function riscv_f64ToF32 (rm, v) = {\n extern_f64ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f64ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18767, 18779 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18745, 18757 ] }, { "type": "function", "id": "extern_f64ToF32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 18718, 18733 ] } ] }, "riscv_f64ToI32": { "function": { "number": 0, "source": "function riscv_f64ToI32 (rm, v) = {\n extern_f64ToI32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f64ToI32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14619, 14631 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14597, 14609 ] }, { "type": "function", "id": "extern_f64ToI32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14570, 14585 ] } ] }, "riscv_f64ToI64": { "function": { "number": 0, "source": "function riscv_f64ToI64 (rm, v) = {\n extern_f64ToI64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f64ToI64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15906, 15918 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15884, 15896 ] }, { "type": "function", "id": "extern_f64ToI64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15857, 15872 ] } ] }, "riscv_f64ToUi32": { "function": { "number": 0, "source": "function riscv_f64ToUi32 (rm, v) = {\n extern_f64ToUi32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f64ToUi32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14949, 14961 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14927, 14939 ] }, { "type": "function", "id": "extern_f64ToUi32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14899, 14915 ] } ] }, "riscv_f64ToUi64": { "function": { "number": 0, "source": "function riscv_f64ToUi64 (rm, v) = {\n extern_f64ToUi64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_f64ToUi64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16227, 16239 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16205, 16217 ] }, { "type": "function", "id": "extern_f64ToUi64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16177, 16193 ] } ] }, "riscv_f64roundToInt": { "function": { "number": 0, "source": "function riscv_f64roundToInt (rm, v, exact) = {\n extern_f64roundToInt(rm, v, exact);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" }, { "type": "id", "id": "exact" } ] }, "body": " extern_f64roundToInt(rm, v, exact);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24877, 24889 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24855, 24867 ] }, { "type": "function", "id": "extern_f64roundToInt", "file": "model/riscv_softfloat_interface.sail", "loc": [ 24816, 24836 ] } ] }, "riscv_i32ToF16": { "function": { "number": 0, "source": "function riscv_i32ToF16 (rm, v) = {\n extern_i32ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_i32ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10088, 10100 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10066, 10078 ] }, { "type": "function", "id": "extern_i32ToF16", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10039, 10054 ] } ] }, "riscv_i32ToF32": { "function": { "number": 0, "source": "function riscv_i32ToF32 (rm, v) = {\n extern_i32ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_i32ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12680, 12692 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12658, 12670 ] }, { "type": "function", "id": "extern_i32ToF32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12631, 12646 ] } ] }, "riscv_i32ToF64": { "function": { "number": 0, "source": "function riscv_i32ToF64 (rm, v) = {\n extern_i32ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_i32ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15271, 15283 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15249, 15261 ] }, { "type": "function", "id": "extern_i32ToF64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15222, 15237 ] } ] }, "riscv_i64ToF16": { "function": { "number": 0, "source": "function riscv_i64ToF16 (rm, v) = {\n extern_i64ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_i64ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11375, 11387 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11353, 11365 ] }, { "type": "function", "id": "extern_i64ToF16", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11326, 11341 ] } ] }, "riscv_i64ToF32": { "function": { "number": 0, "source": "function riscv_i64ToF32 (rm, v) = {\n extern_i64ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_i64ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13967, 13979 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13945, 13957 ] }, { "type": "function", "id": "extern_i64ToF32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13918, 13933 ] } ] }, "riscv_i64ToF64": { "function": { "number": 0, "source": "function riscv_i64ToF64 (rm, v) = {\n extern_i64ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_i64ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16540, 16552 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16518, 16530 ] }, { "type": "function", "id": "extern_i64ToF64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16491, 16506 ] } ] }, "riscv_ui32ToF16": { "function": { "number": 0, "source": "function riscv_ui32ToF16 (rm, v) = {\n extern_ui32ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_ui32ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10419, 10431 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10397, 10409 ] }, { "type": "function", "id": "extern_ui32ToF16", "file": "model/riscv_softfloat_interface.sail", "loc": [ 10369, 10385 ] } ] }, "riscv_ui32ToF32": { "function": { "number": 0, "source": "function riscv_ui32ToF32 (rm, v) = {\n extern_ui32ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_ui32ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 13011, 13023 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12989, 13001 ] }, { "type": "function", "id": "extern_ui32ToF32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 12961, 12977 ] } ] }, "riscv_ui32ToF64": { "function": { "number": 0, "source": "function riscv_ui32ToF64 (rm, v) = {\n extern_ui32ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_ui32ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15593, 15605 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15571, 15583 ] }, { "type": "function", "id": "extern_ui32ToF64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 15543, 15559 ] } ] }, "riscv_ui64ToF16": { "function": { "number": 0, "source": "function riscv_ui64ToF16 (rm, v) = {\n extern_ui64ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_ui64ToF16(rm, v);\n (float_fflags[4 .. 0], float_result[15 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11705, 11717 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11683, 11695 ] }, { "type": "function", "id": "extern_ui64ToF16", "file": "model/riscv_softfloat_interface.sail", "loc": [ 11655, 11671 ] } ] }, "riscv_ui64ToF32": { "function": { "number": 0, "source": "function riscv_ui64ToF32 (rm, v) = {\n extern_ui64ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_ui64ToF32(rm, v);\n (float_fflags[4 .. 0], float_result[31 .. 0])" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14297, 14309 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14275, 14287 ] }, { "type": "function", "id": "extern_ui64ToF32", "file": "model/riscv_softfloat_interface.sail", "loc": [ 14247, 14263 ] } ] }, "riscv_ui64ToF64": { "function": { "number": 0, "source": "function riscv_ui64ToF64 (rm, v) = {\n extern_ui64ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rm" }, { "type": "id", "id": "v" } ] }, "body": " extern_ui64ToF64(rm, v);\n (float_fflags[4 .. 0], float_result)" }, "links": [ { "type": "register", "id": "float_result", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16862, 16874 ] }, { "type": "register", "id": "float_fflags", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16840, 16852 ] }, { "type": "function", "id": "extern_ui64ToF64", "file": "model/riscv_softfloat_interface.sail", "loc": [ 16812, 16828 ] } ] }, "rivvfunct6_of_num": { "function": { "number": 0, "source": "rivvfunct6_of_num arg# = $[complete] match arg# {\n 0 => IVV_VWREDSUMU,\n _ => IVV_VWREDSUM\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => IVV_VWREDSUMU,\n _ => IVV_VWREDSUM\n}" } }, "rmvvfunct6_of_num": { "function": { "number": 0, "source": "rmvvfunct6_of_num arg# = $[complete] match arg# {\n 0 => MVV_VREDSUM,\n 1 => MVV_VREDAND,\n 2 => MVV_VREDOR,\n 3 => MVV_VREDXOR,\n 4 => MVV_VREDMINU,\n 5 => MVV_VREDMIN,\n 6 => MVV_VREDMAXU,\n _ => MVV_VREDMAX\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => MVV_VREDSUM,\n 1 => MVV_VREDAND,\n 2 => MVV_VREDOR,\n 3 => MVV_VREDXOR,\n 4 => MVV_VREDMINU,\n 5 => MVV_VREDMIN,\n 6 => MVV_VREDMAXU,\n _ => MVV_VREDMAX\n}" } }, "rop_of_num": { "function": { "number": 0, "source": "rop_of_num arg# = $[complete] match arg# {\n 0 => RISCV_ADD,\n 1 => RISCV_SUB,\n 2 => RISCV_SLL,\n 3 => RISCV_SLT,\n 4 => RISCV_SLTU,\n 5 => RISCV_XOR,\n 6 => RISCV_SRL,\n 7 => RISCV_SRA,\n 8 => RISCV_OR,\n _ => RISCV_AND\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_ADD,\n 1 => RISCV_SUB,\n 2 => RISCV_SLL,\n 3 => RISCV_SLT,\n 4 => RISCV_SLTU,\n 5 => RISCV_XOR,\n 6 => RISCV_SRL,\n 7 => RISCV_SRA,\n 8 => RISCV_OR,\n _ => RISCV_AND\n}" } }, "ropw_of_num": { "function": { "number": 0, "source": "ropw_of_num arg# = $[complete] match arg# {\n 0 => RISCV_ADDW,\n 1 => RISCV_SUBW,\n 2 => RISCV_SLLW,\n 3 => RISCV_SRLW,\n _ => RISCV_SRAW\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_ADDW,\n 1 => RISCV_SUBW,\n 2 => RISCV_SLLW,\n 3 => RISCV_SRLW,\n _ => RISCV_SRAW\n}" } }, "rotate_bits_left": { "function": { "number": 0, "source": "function rotate_bits_left (v, n) =\n (v << n) | (v >> (to_bits(length(n), length(v)) - n))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v" }, { "type": "id", "id": "n" } ] }, "body": "(v << n) | (v >> (to_bits(length(n), length(v)) - n))" }, "links": [ { "type": "function", "id": "shift_bits_right", "file": "model/prelude.sail", "loc": [ 6319, 6335 ] }, { "type": "function", "id": "sub_vec", "file": "model/prelude.sail", "loc": [ 1712, 1719 ] }, { "type": "function", "id": "to_bits", "file": "model/prelude.sail", "loc": [ 7067, 7074 ] }, { "type": "function", "id": "shift_bits_left", "file": "model/prelude.sail", "loc": [ 6369, 6384 ] } ] }, "rotate_bits_right": { "function": { "number": 0, "source": "function rotate_bits_right (v, n) =\n (v >> n) | (v << (to_bits(length(n), length(v)) - n))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v" }, { "type": "id", "id": "n" } ] }, "body": "(v >> n) | (v << (to_bits(length(n), length(v)) - n))" }, "links": [ { "type": "function", "id": "shift_bits_left", "file": "model/prelude.sail", "loc": [ 6369, 6384 ] }, { "type": "function", "id": "sub_vec", "file": "model/prelude.sail", "loc": [ 1712, 1719 ] }, { "type": "function", "id": "to_bits", "file": "model/prelude.sail", "loc": [ 6894, 6901 ] }, { "type": "function", "id": "shift_bits_right", "file": "model/prelude.sail", "loc": [ 6319, 6335 ] } ] }, "rotatel": { "function": { "number": 0, "source": "function rotatel (v, n) =\n (v << n) | (v >> (length(v) - n))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v" }, { "type": "id", "id": "n" } ] }, "body": "(v << n) | (v >> (length(v) - n))" }, "links": [ { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] } ] }, "rotater": { "function": { "number": 0, "source": "function rotater (v, n) =\n (v >> n) | (v << (length(v) - n))", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v" }, { "type": "id", "id": "n" } ] }, "body": "(v >> n) | (v << (length(v) - n))" }, "links": [ { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] } ] }, "rounding_mode_of_num": { "function": { "number": 0, "source": "rounding_mode_of_num arg# = $[complete] match arg# {\n 0 => RM_RNE,\n 1 => RM_RTZ,\n 2 => RM_RDN,\n 3 => RM_RUP,\n 4 => RM_RMM,\n _ => RM_DYN\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RM_RNE,\n 1 => RM_RTZ,\n 2 => RM_RDN,\n 3 => RM_RUP,\n 4 => RM_RMM,\n _ => RM_DYN\n}" } }, "rsqrt7": { "function": { "number": 0, "source": "function rsqrt7 (v, sub) = {\n let (sig, exp, sign, e, s) : (bits(64), bits(64), bits(1), nat, nat) = match 'm {\n 16 => (zero_extend(64, v[9 .. 0]), zero_extend(64, v[14 .. 10]), [v[15]], 5, 10),\n 32 => (zero_extend(64, v[22 .. 0]), zero_extend(64, v[30 .. 23]), [v[31]], 8, 23),\n 64 => (zero_extend(64, v[51 .. 0]), zero_extend(64, v[62 .. 52]), [v[63]], 11, 52)\n };\n assert(s == 10 & e == 5 | s == 23 & e == 8 | s == 52 & e == 11);\n let table : vector(128, dec, int) = [\n 52, 51, 50, 48, 47, 46, 44, 43,\n 42, 41, 40, 39, 38, 36, 35, 34,\n 33, 32, 31, 30, 30, 29, 28, 27,\n 26, 25, 24, 23, 23, 22, 21, 20,\n 19, 19, 18, 17, 16, 16, 15, 14,\n 14, 13, 12, 12, 11, 10, 10, 9,\n 9, 8, 7, 7, 6, 6, 5, 4,\n 4, 3, 3, 2, 2, 1, 1, 0,\n 127, 125, 123, 121, 119, 118, 116, 114,\n 113, 111, 109, 108, 106, 105, 103, 102,\n 100, 99, 97, 96, 95, 93, 92, 91,\n 90, 88, 87, 86, 85, 84, 83, 82,\n 80, 79, 78, 77, 76, 75, 74, 73,\n 72, 71, 70, 70, 69, 68, 67, 66,\n 65, 64, 63, 63, 62, 61, 60, 59,\n 59, 58, 57, 56, 56, 55, 54, 53];\n\n let (normalized_exp, normalized_sig) =\n if sub then {\n let nr_leadingzeros = count_leadingzeros(sig, s);\n assert(nr_leadingzeros >= 0);\n (to_bits(64, (0 - nr_leadingzeros)), zero_extend(64, sig[(s - 1) .. 0] << (1 + nr_leadingzeros)))\n } else {\n (exp, sig)\n };\n\n let idx : nat = match 'm {\n 16 => unsigned([normalized_exp[0]] @ normalized_sig[9 .. 4]),\n 32 => unsigned([normalized_exp[0]] @ normalized_sig[22 .. 17]),\n 64 => unsigned([normalized_exp[0]] @ normalized_sig[51 .. 46])\n };\n assert(idx >= 0 & idx < 128);\n let out_sig = to_bits(s, table[(127 - idx)]) << (s - 7);\n let out_exp = to_bits(e, (3 * (2^(e - 1) - 1) - 1 - signed(normalized_exp)) / 2);\n zero_extend(64, sign @ out_exp @ out_sig)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v" }, { "type": "id", "id": "sub" } ] }, "body": " let (sig, exp, sign, e, s) : (bits(64), bits(64), bits(1), nat, nat) = match 'm {\n 16 => (zero_extend(64, v[9 .. 0]), zero_extend(64, v[14 .. 10]), [v[15]], 5, 10),\n 32 => (zero_extend(64, v[22 .. 0]), zero_extend(64, v[30 .. 23]), [v[31]], 8, 23),\n 64 => (zero_extend(64, v[51 .. 0]), zero_extend(64, v[62 .. 52]), [v[63]], 11, 52)\n };\n assert(s == 10 & e == 5 | s == 23 & e == 8 | s == 52 & e == 11);\n let table : vector(128, dec, int) = [\n 52, 51, 50, 48, 47, 46, 44, 43,\n 42, 41, 40, 39, 38, 36, 35, 34,\n 33, 32, 31, 30, 30, 29, 28, 27,\n 26, 25, 24, 23, 23, 22, 21, 20,\n 19, 19, 18, 17, 16, 16, 15, 14,\n 14, 13, 12, 12, 11, 10, 10, 9,\n 9, 8, 7, 7, 6, 6, 5, 4,\n 4, 3, 3, 2, 2, 1, 1, 0,\n 127, 125, 123, 121, 119, 118, 116, 114,\n 113, 111, 109, 108, 106, 105, 103, 102,\n 100, 99, 97, 96, 95, 93, 92, 91,\n 90, 88, 87, 86, 85, 84, 83, 82,\n 80, 79, 78, 77, 76, 75, 74, 73,\n 72, 71, 70, 70, 69, 68, 67, 66,\n 65, 64, 63, 63, 62, 61, 60, 59,\n 59, 58, 57, 56, 56, 55, 54, 53];\n\n let (normalized_exp, normalized_sig) =\n if sub then {\n let nr_leadingzeros = count_leadingzeros(sig, s);\n assert(nr_leadingzeros >= 0);\n (to_bits(64, (0 - nr_leadingzeros)), zero_extend(64, sig[(s - 1) .. 0] << (1 + nr_leadingzeros)))\n } else {\n (exp, sig)\n };\n\n let idx : nat = match 'm {\n 16 => unsigned([normalized_exp[0]] @ normalized_sig[9 .. 4]),\n 32 => unsigned([normalized_exp[0]] @ normalized_sig[22 .. 17]),\n 64 => unsigned([normalized_exp[0]] @ normalized_sig[51 .. 46])\n };\n assert(idx >= 0 & idx < 128);\n let out_sig = to_bits(s, table[(127 - idx)]) << (s - 7);\n let out_exp = to_bits(e, (3 * (2^(e - 1) - 1) - 1 - signed(normalized_exp)) / 2);\n zero_extend(64, sign @ out_exp @ out_sig)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32851, 32862 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32822, 32833 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32764, 32775 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32735, 32746 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32677, 32688 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 32649, 32660 ] }, { "type": "function", "id": "count_leadingzeros", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 33711, 33729 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 33822, 33833 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 33786, 33793 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34100, 34108 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34032, 34040 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 33966, 33974 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34210, 34217 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34269, 34276 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34307, 34313 ] }, { "type": "function", "id": "int_power", "file": "model/prelude.sail", "loc": [ 1476, 1485 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 34339, 34350 ] } ] }, "rvfi_read": { "function": { "number": 0, "source": "function rvfi_read (addr, width, result) = ()", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "result" } ] }, "body": "()" } }, "rvfi_trap": { "function": { "number": 0, "source": "function rvfi_trap () = ()", "pattern": { "type": "literal", "value": "()" }, "body": "()" } }, "rvfi_wX": { "function": { "number": 0, "source": "function rvfi_wX (r,v) = ()", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "r" }, { "type": "id", "id": "v" } ] }, "body": "()" } }, "rvfi_write": { "function": { "number": 0, "source": "function rvfi_write (addr, width, value, meta, result) = ()", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "value" }, { "type": "id", "id": "meta" }, { "type": "id", "id": "result" } ] }, "body": "()" } }, "sail_mask": { "function": { "number": 0, "source": "sail_mask (len, v) = if lteq_int(len, bitvector_length(v)) then truncate(v, len) else sail_zero_extend(v, len)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "len" }, { "type": "id", "id": "v" } ] }, "body": "if lteq_int(len, bitvector_length(v)) then truncate(v, len) else sail_zero_extend(v, len)" } }, "sail_ones": { "function": { "number": 0, "source": "sail_ones n = not_vec(sail_zeros(n))", "pattern": { "type": "id", "id": "n" }, "body": "not_vec(sail_zeros(n))" } }, "satp64Mode_of_bits": { "function": { "number": 0, "source": "function satp64Mode_of_bits(a : Architecture, m : satp_mode) -> option(SATPMode) =\n match (a, m) {\n (_, 0x0) => Some(Sbare),\n (RV32, 0x1) => Some(Sv32),\n (RV64, 0x8) => Some(Sv39),\n (RV64, 0x9) => Some(Sv48),\n (_, _) => None()\n }", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "a" }, { "type": "id", "id": "m" } ] }, "body": "match (a, m) {\n (_, 0x0) => Some(Sbare),\n (RV32, 0x1) => Some(Sv32),\n (RV64, 0x8) => Some(Sv39),\n (RV64, 0x9) => Some(Sv48),\n (_, _) => None()\n }" }, "links": [ { "type": "function", "id": "None", "file": "model/riscv_types.sail", "loc": [ 8684, 8688 ] }, { "type": "function", "id": "Some", "file": "model/riscv_types.sail", "loc": [ 8653, 8657 ] }, { "type": "function", "id": "Some", "file": "model/riscv_types.sail", "loc": [ 8622, 8626 ] }, { "type": "function", "id": "Some", "file": "model/riscv_types.sail", "loc": [ 8591, 8595 ] }, { "type": "function", "id": "Some", "file": "model/riscv_types.sail", "loc": [ 8559, 8563 ] } ] }, "satp_to_PT_base": { "function": { "number": 0, "source": "function satp_to_PT_base(satp_val : xlenbits) -> bits(64) = {\n let ppn = if sizeof(xlen) == 32 then zero_extend (64, Mk_Satp32(satp_val)[PPN])\n else if sizeof(xlen) == 64 then zero_extend (64, Mk_Satp64(satp_val)[PPN])\n else internal_error(__FILE__, __LINE__,\n \"Unsupported xlen\" ^ dec_str(sizeof(xlen)));\n ppn << pagesize_bits\n}", "pattern": { "type": "id", "id": "satp_val" }, "body": " let ppn = if sizeof(xlen) == 32 then zero_extend (64, Mk_Satp32(satp_val)[PPN])\n else if sizeof(xlen) == 64 then zero_extend (64, Mk_Satp64(satp_val)[PPN])\n else internal_error(__FILE__, __LINE__,\n \"Unsupported xlen\" ^ dec_str(sizeof(xlen)));\n ppn << pagesize_bits" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 9607, 9618 ] }, { "type": "function", "id": "Mk_Satp32", "file": "model/riscv_vmem.sail", "loc": [ 9624, 9633 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 9694, 9705 ] }, { "type": "function", "id": "Mk_Satp64", "file": "model/riscv_vmem.sail", "loc": [ 9711, 9720 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_vmem.sail", "loc": [ 9754, 9768 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_vmem.sail", "loc": [ 9842, 9849 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] } ] }, "satp_to_asid": { "function": { "number": 0, "source": "function satp_to_asid(satp_val : xlenbits) -> asidbits =\n if sizeof(xlen) == 32 then zero_extend(Mk_Satp32(satp_val)[Asid])\n else if sizeof(xlen) == 64 then Mk_Satp64(satp_val)[Asid]\n else internal_error(__FILE__, __LINE__,\n \"Unsupported xlen\" ^ dec_str(sizeof(xlen)))", "pattern": { "type": "id", "id": "satp_val" }, "body": "if sizeof(xlen) == 32 then zero_extend(Mk_Satp32(satp_val)[Asid])\n else if sizeof(xlen) == 64 then Mk_Satp64(satp_val)[Asid]\n else internal_error(__FILE__, __LINE__,\n \"Unsupported xlen\" ^ dec_str(sizeof(xlen)))" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 9228, 9239 ] }, { "type": "function", "id": "Mk_Satp32", "file": "model/riscv_vmem.sail", "loc": [ 9240, 9249 ] }, { "type": "function", "id": "Mk_Satp64", "file": "model/riscv_vmem.sail", "loc": [ 9302, 9311 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_vmem.sail", "loc": [ 9336, 9350 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_vmem.sail", "loc": [ 9415, 9422 ] } ] }, "sbox_lookup": { "function": { "number": 0, "source": "function sbox_lookup(x, table) = {\n table[255 - unsigned(x)]\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "table" } ] }, "body": " table[255 - unsigned(x)]" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_types_kext.sail", "loc": [ 9119, 9127 ] } ] }, "seed_opst_of_num": { "function": { "number": 0, "source": "seed_opst_of_num arg# = $[complete] match arg# {\n 0 => BIST,\n 1 => ES16,\n 2 => WAIT,\n _ => DEAD\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => BIST,\n 1 => ES16,\n 2 => WAIT,\n _ => DEAD\n}" } }, "select_instr_or_fcsr_rm": { "function": { "number": 0, "source": "function select_instr_or_fcsr_rm instr_rm =\n if (instr_rm == RM_DYN)\n then {\n let fcsr_rm = fcsr[FRM];\n if (valid_rounding_mode(fcsr_rm) & fcsr_rm != encdec_rounding_mode(RM_DYN))\n then Some(encdec_rounding_mode(fcsr_rm)) else None()\n }\n else Some(instr_rm)", "pattern": { "type": "id", "id": "instr_rm" }, "body": "if (instr_rm == RM_DYN)\n then {\n let fcsr_rm = fcsr[FRM];\n if (valid_rounding_mode(fcsr_rm) & fcsr_rm != encdec_rounding_mode(RM_DYN))\n then Some(encdec_rounding_mode(fcsr_rm)) else None()\n }\n else Some(instr_rm)" }, "links": [ { "type": "register", "id": "fcsr", "file": "model/riscv_insts_fext.sail", "loc": [ 2282, 2286 ] }, { "type": "function", "id": "valid_rounding_mode", "file": "model/riscv_insts_fext.sail", "loc": [ 2301, 2320 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_fext.sail", "loc": [ 2384, 2388 ] }, { "type": "function", "id": "None", "file": "model/riscv_insts_fext.sail", "loc": [ 2425, 2429 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_fext.sail", "loc": [ 2443, 2447 ] } ] }, "set_mstatus_SXL": { "function": { "number": 0, "source": "function set_mstatus_SXL(m : Mstatus, a : arch_xlen) -> Mstatus = {\n if sizeof(xlen) == 32\n then m\n else {\n let m = vector_update_subrange(m.bits, 35, 34, a);\n Mk_Mstatus(m)\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "a" } ] }, "body": " if sizeof(xlen) == 32\n then m\n else {\n let m = vector_update_subrange(m.bits, 35, 34, a);\n Mk_Mstatus(m)\n }" }, "links": [ { "type": "function", "id": "Mk_Mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 7793, 7803 ] } ] }, "set_mstatus_UXL": { "function": { "number": 0, "source": "function set_mstatus_UXL(m : Mstatus, a : arch_xlen) -> Mstatus = {\n if sizeof(xlen) == 32\n then m\n else {\n let m = vector_update_subrange(m.bits, 33, 32, a);\n Mk_Mstatus(m)\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "a" } ] }, "body": " if sizeof(xlen) == 32\n then m\n else {\n let m = vector_update_subrange(m.bits, 33, 32, a);\n Mk_Mstatus(m)\n }" }, "links": [ { "type": "function", "id": "Mk_Mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 8120, 8130 ] } ] }, "set_mtvec": { "function": { "number": 0, "source": "function set_mtvec(value : xlenbits) -> xlenbits = {\n mtvec = legalize_tvec(mtvec, value);\n mtvec.bits\n}", "pattern": { "type": "id", "id": "value" }, "body": " mtvec = legalize_tvec(mtvec, value);\n mtvec.bits" }, "links": [ { "type": "register", "id": "mtvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2560, 2565 ] }, { "type": "register", "id": "mtvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2521, 2526 ] }, { "type": "function", "id": "legalize_tvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2529, 2542 ] }, { "type": "register", "id": "mtvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2543, 2548 ] } ] }, "set_next_pc": { "function": { "number": 0, "source": "function set_next_pc(pc) = {\n nextPC = pc\n}", "pattern": { "type": "id", "id": "pc" }, "body": " nextPC = pc" }, "links": [ { "type": "register", "id": "nextPC", "file": "model/riscv_pc_access.sail", "loc": [ 1185, 1191 ] } ] }, "set_sstatus_UXL": { "function": { "number": 0, "source": "function set_sstatus_UXL(s : Sstatus, a : arch_xlen) -> Sstatus = {\n let m = Mk_Mstatus(s.bits);\n let m = set_mstatus_UXL(m, a);\n Mk_Sstatus(m.bits)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "s" }, { "type": "id", "id": "a" } ] }, "body": " let m = Mk_Mstatus(s.bits);\n let m = set_mstatus_UXL(m, a);\n Mk_Sstatus(m.bits)" }, "links": [ { "type": "function", "id": "Mk_Mstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 17069, 17079 ] }, { "type": "function", "id": "set_mstatus_UXL", "file": "model/riscv_sys_regs.sail", "loc": [ 17099, 17114 ] }, { "type": "function", "id": "Mk_Sstatus", "file": "model/riscv_sys_regs.sail", "loc": [ 17124, 17134 ] } ] }, "set_stvec": { "function": { "number": 0, "source": "function set_stvec(value : xlenbits) -> xlenbits = {\n stvec = legalize_tvec(stvec, value);\n stvec.bits\n}", "pattern": { "type": "id", "id": "value" }, "body": " stvec = legalize_tvec(stvec, value);\n stvec.bits" }, "links": [ { "type": "register", "id": "stvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2668, 2673 ] }, { "type": "register", "id": "stvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2629, 2634 ] }, { "type": "function", "id": "legalize_tvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2637, 2650 ] }, { "type": "register", "id": "stvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2651, 2656 ] } ] }, "set_utvec": { "function": { "number": 0, "source": "function set_utvec(value : xlenbits) -> xlenbits = {\n utvec = legalize_tvec(utvec, value);\n utvec.bits\n}", "pattern": { "type": "id", "id": "value" }, "body": " utvec = legalize_tvec(utvec, value);\n utvec.bits" }, "links": [ { "type": "register", "id": "utvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2776, 2781 ] }, { "type": "register", "id": "utvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2737, 2742 ] }, { "type": "function", "id": "legalize_tvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2745, 2758 ] }, { "type": "register", "id": "utvec", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2759, 2764 ] } ] }, "set_xret_target": { "function": { "number": 0, "source": "function set_xret_target(p, value) = {\n let target = legalize_xepc(value);\n match p {\n Machine => mepc = target,\n Supervisor => sepc = target,\n User => uepc = target\n };\n target\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "p" }, { "type": "id", "id": "value" } ] }, "body": " let target = legalize_xepc(value);\n match p {\n Machine => mepc = target,\n Supervisor => sepc = target,\n User => uepc = target\n };\n target" }, "links": [ { "type": "function", "id": "legalize_xepc", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2033, 2046 ] }, { "type": "register", "id": "uepc", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2151, 2155 ] }, { "type": "register", "id": "sepc", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2118, 2122 ] }, { "type": "register", "id": "mepc", "file": "model/riscv_sys_exceptions.sail", "loc": [ 2085, 2089 ] } ] }, "shift_right_arith32": { "function": { "number": 0, "source": "function shift_right_arith32 (v : bits(32), shift : bits(5)) -> bits(32) =\n let v64 : bits(64) = sign_extend(v) in\n (v64 >> shift)[31..0]", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v" }, { "type": "id", "id": "shift" } ] }, "body": "let v64 : bits(64) = sign_extend(v) in\n (v64 >> shift)[31..0]" }, "links": [ { "type": "function", "id": "sign_extend", "file": "model/prelude.sail", "loc": [ 6686, 6697 ] }, { "type": "function", "id": "shift_bits_right", "file": "model/prelude.sail", "loc": [ 6319, 6335 ] } ] }, "shift_right_arith64": { "function": { "number": 0, "source": "function shift_right_arith64 (v : bits(64), shift : bits(6)) -> bits(64) =\n let v128 : bits(128) = sign_extend(v) in\n (v128 >> shift)[63..0]", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "v" }, { "type": "id", "id": "shift" } ] }, "body": "let v128 : bits(128) = sign_extend(v) in\n (v128 >> shift)[63..0]" }, "links": [ { "type": "function", "id": "sign_extend", "file": "model/prelude.sail", "loc": [ 6540, 6551 ] }, { "type": "function", "id": "shift_bits_right", "file": "model/prelude.sail", "loc": [ 6319, 6335 ] } ] }, "sign_extend": { "function": { "number": 0, "source": "function sign_extend(m, v) = sail_sign_extend(v, m)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "v" } ] }, "body": "sail_sign_extend(v, m)" }, "links": [ { "type": "function", "id": "sail_sign_extend", "file": "model/prelude.sail", "loc": [ 4224, 4240 ] } ] }, "signed_saturation": { "function": { "number": 0, "source": "function signed_saturation(len, elem) = {\n if signed(elem) > signed(0b0 @ ones('m - 1)) then {\n vxsat = 0b1;\n 0b0 @ ones('m - 1)\n } else if signed(elem) < signed(0b1 @ zeros('m - 1)) then {\n vxsat = 0b1;\n 0b1 @ zeros('m - 1)\n } else {\n vxsat = 0b0;\n elem['m - 1 .. 0]\n };\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "len" }, { "type": "id", "id": "elem" } ] }, "body": " if signed(elem) > signed(0b0 @ ones('m - 1)) then {\n vxsat = 0b1;\n 0b0 @ ones('m - 1)\n } else if signed(elem) < signed(0b1 @ zeros('m - 1)) then {\n vxsat = 0b1;\n 0b1 @ zeros('m - 1)\n } else {\n vxsat = 0b0;\n elem['m - 1 .. 0]\n }" }, "links": [ { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22311, 22317 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22324, 22328 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22296, 22302 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22372, 22376 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22349, 22354 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22412, 22418 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "signed", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22397, 22403 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22451, 22456 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22503, 22508 ] } ] }, "slice_mask": { "function": { "number": 0, "source": "slice_mask (n, i, l) = if gteq_int(l, n) then {\n sail_shiftleft(sail_ones(n), i)\n} else {\n let one : bits('n) = sail_mask(n, [bitone] : bits(1));\n sail_shiftleft(sub_bits(sail_shiftleft(one, l), one), i)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "i" }, { "type": "id", "id": "l" } ] }, "body": "if gteq_int(l, n) then {\n sail_shiftleft(sail_ones(n), i)\n} else {\n let one : bits('n) = sail_mask(n, [bitone] : bits(1));\n sail_shiftleft(sub_bits(sail_shiftleft(one, l), one), i)\n}" } }, "sm4_sbox": { "function": { "number": 0, "source": "function sm4_sbox(x) = sbox_lookup(x, sm4_sbox_table)", "pattern": { "type": "id", "id": "x" }, "body": "sbox_lookup(x, sm4_sbox_table)" }, "links": [ { "type": "function", "id": "sbox_lookup", "file": "model/riscv_types_kext.sail", "loc": [ 10192, 10203 ] } ] }, "sop_of_num": { "function": { "number": 0, "source": "sop_of_num arg# = $[complete] match arg# {\n 0 => RISCV_SLLI,\n 1 => RISCV_SRLI,\n _ => RISCV_SRAI\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_SLLI,\n 1 => RISCV_SRLI,\n _ => RISCV_SRAI\n}" } }, "sopw_of_num": { "function": { "number": 0, "source": "sopw_of_num arg# = $[complete] match arg# {\n 0 => RISCV_SLLIW,\n 1 => RISCV_SRLIW,\n _ => RISCV_SRAIW\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_SLLIW,\n 1 => RISCV_SRLIW,\n _ => RISCV_SRAIW\n}" } }, "spc_backwards": { "function": { "number": 0, "source": "function spc_backwards _ = ()", "pattern": { "type": "wildcard" }, "body": "()" } }, "spc_backwards_matches": { "function": { "number": 0, "source": "function spc_backwards_matches s = {\n let len = string_length(s);\n n_leading_spaces(s) == len & len > 0\n}", "pattern": { "type": "id", "id": "s" }, "body": " let len = string_length(s);\n n_leading_spaces(s) == len & len > 0" }, "links": [ { "type": "function", "id": "string_length", "file": "model/mapping.sail", "loc": [ 6337, 6350 ] }, { "type": "function", "id": "n_leading_spaces", "file": "model/mapping.sail", "loc": [ 6357, 6373 ] } ] }, "spc_forwards": { "function": { "number": 0, "source": "function spc_forwards() = \" \"", "pattern": { "type": "literal", "value": "()" }, "body": "\" \"" } }, "spc_forwards_matches": { "function": { "number": 0, "source": "function spc_forwards_matches() = true", "pattern": { "type": "literal", "value": "()" }, "body": "true" } }, "step": { "function": { "number": 0, "source": "function step(step_no : int) -> bool = {\n /* for step extensions */\n ext_pre_step_hook();\n\n /*\n * This records whether or not minstret should be incremented when\n * the instruction is retired. Since retirement occurs before CSR\n * writes we initialise it based on mcountinhibit here, before it is\n * potentially changed. This is also set to false if minstret is\n * written. See the note near the minstret declaration for more\n * information.\n */\n minstret_increment = mcountinhibit[IR] == 0b0;\n\n let (retired, stepped) : (Retired, bool) =\n match dispatchInterrupt(cur_privilege) {\n Some(intr, priv) => {\n if get_config_print_instr()\n then print_bits(\"Handling interrupt: \", interruptType_to_bits(intr));\n handle_interrupt(intr, priv);\n (RETIRE_FAIL, false)\n },\n None() => {\n /* the extension hook interposes on the fetch result */\n let f : FetchResult = ext_fetch_hook(fetch());\n match f {\n /* extension error */\n F_Ext_Error(e) => {\n ext_handle_fetch_check_error(e);\n (RETIRE_FAIL, false)\n },\n /* standard error */\n F_Error(e, addr) => {\n handle_mem_exception(addr, e);\n (RETIRE_FAIL, false)\n },\n /* non-error cases: */\n F_RVC(h) => {\n instbits = zero_extend(h);\n let ast = ext_decode_compressed(h);\n if get_config_print_instr()\n then {\n print_instr(\"[\" ^ dec_str(step_no) ^ \"] [\" ^ to_str(cur_privilege) ^ \"]: \" ^ BitStr(PC) ^ \" (\" ^ BitStr(h) ^ \") \" ^ to_str(ast));\n };\n /* check for RVC once here instead of every RVC execute clause. */\n if haveRVC() then {\n nextPC = PC + 2;\n (execute(ast), true)\n } else {\n handle_illegal();\n (RETIRE_FAIL, true)\n }\n },\n F_Base(w) => {\n instbits = zero_extend(w);\n let ast = ext_decode(w);\n if get_config_print_instr()\n then {\n print_instr(\"[\" ^ dec_str(step_no) ^ \"] [\" ^ to_str(cur_privilege) ^ \"]: \" ^ BitStr(PC) ^ \" (\" ^ BitStr(w) ^ \") \" ^ to_str(ast));\n };\n nextPC = PC + 4;\n (execute(ast), true)\n }\n }\n }\n };\n\n tick_pc();\n\n /* update minstret */\n match retired {\n RETIRE_SUCCESS => retire_instruction(),\n RETIRE_FAIL => ()\n };\n\n /* for step extensions */\n ext_post_step_hook();\n\n stepped\n}", "pattern": { "type": "id", "id": "step_no" }, "body": " ext_pre_step_hook();\n\n /*\n * This records whether or not minstret should be incremented when\n * the instruction is retired. Since retirement occurs before CSR\n * writes we initialise it based on mcountinhibit here, before it is\n * potentially changed. This is also set to false if minstret is\n * written. See the note near the minstret declaration for more\n * information.\n */\n minstret_increment = mcountinhibit[IR] == 0b0;\n\n let (retired, stepped) : (Retired, bool) =\n match dispatchInterrupt(cur_privilege) {\n Some(intr, priv) => {\n if get_config_print_instr()\n then print_bits(\"Handling interrupt: \", interruptType_to_bits(intr));\n handle_interrupt(intr, priv);\n (RETIRE_FAIL, false)\n },\n None() => {\n /* the extension hook interposes on the fetch result */\n let f : FetchResult = ext_fetch_hook(fetch());\n match f {\n /* extension error */\n F_Ext_Error(e) => {\n ext_handle_fetch_check_error(e);\n (RETIRE_FAIL, false)\n },\n /* standard error */\n F_Error(e, addr) => {\n handle_mem_exception(addr, e);\n (RETIRE_FAIL, false)\n },\n /* non-error cases: */\n F_RVC(h) => {\n instbits = zero_extend(h);\n let ast = ext_decode_compressed(h);\n if get_config_print_instr()\n then {\n print_instr(\"[\" ^ dec_str(step_no) ^ \"] [\" ^ to_str(cur_privilege) ^ \"]: \" ^ BitStr(PC) ^ \" (\" ^ BitStr(h) ^ \") \" ^ to_str(ast));\n };\n /* check for RVC once here instead of every RVC execute clause. */\n if haveRVC() then {\n nextPC = PC + 2;\n (execute(ast), true)\n } else {\n handle_illegal();\n (RETIRE_FAIL, true)\n }\n },\n F_Base(w) => {\n instbits = zero_extend(w);\n let ast = ext_decode(w);\n if get_config_print_instr()\n then {\n print_instr(\"[\" ^ dec_str(step_no) ^ \"] [\" ^ to_str(cur_privilege) ^ \"]: \" ^ BitStr(PC) ^ \" (\" ^ BitStr(w) ^ \") \" ^ to_str(ast));\n };\n nextPC = PC + 4;\n (execute(ast), true)\n }\n }\n }\n };\n\n tick_pc();\n\n /* update minstret */\n match retired {\n RETIRE_SUCCESS => retire_instruction(),\n RETIRE_FAIL => ()\n };\n\n /* for step extensions */\n ext_post_step_hook();\n\n stepped" }, "links": [ { "type": "function", "id": "dispatchInterrupt", "file": "model/riscv_step.sail", "loc": [ 1336, 1353 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_step.sail", "loc": [ 1354, 1367 ] }, { "type": "function", "id": "ext_fetch_hook", "file": "model/riscv_step.sail", "loc": [ 1703, 1717 ] }, { "type": "function", "id": "fetch", "file": "model/riscv_step.sail", "loc": [ 1718, 1723 ] }, { "type": "function", "id": "ext_decode", "file": "model/riscv_step.sail", "loc": [ 2796, 2806 ] }, { "type": "function", "id": "execute", "file": "model/riscv_step.sail", "loc": [ 3073, 3080 ] }, { "type": "register", "id": "nextPC", "file": "model/riscv_step.sail", "loc": [ 3043, 3049 ] }, { "type": "register", "id": "PC", "file": "model/riscv_step.sail", "loc": [ 3052, 3054 ] }, { "type": "function", "id": "get_config_print_instr", "file": "model/riscv_step.sail", "loc": [ 2828, 2850 ] }, { "type": "function", "id": "print_instr", "file": "model/riscv_step.sail", "loc": [ 2886, 2897 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "print_insn", "file": "model/riscv_insts_end.sail", "loc": [ 1522, 1532 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "PC", "file": "model/riscv_step.sail", "loc": [ 2970, 2972 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_step.sail", "loc": [ 2938, 2951 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_step.sail", "loc": [ 2904, 2911 ] }, { "type": "register", "id": "instbits", "file": "model/riscv_step.sail", "loc": [ 2747, 2755 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_step.sail", "loc": [ 2758, 2769 ] }, { "type": "function", "id": "ext_decode_compressed", "file": "model/riscv_step.sail", "loc": [ 2171, 2192 ] }, { "type": "function", "id": "haveRVC", "file": "model/riscv_step.sail", "loc": [ 2511, 2518 ] }, { "type": "function", "id": "execute", "file": "model/riscv_step.sail", "loc": [ 2574, 2581 ] }, { "type": "register", "id": "nextPC", "file": "model/riscv_step.sail", "loc": [ 2542, 2548 ] }, { "type": "register", "id": "PC", "file": "model/riscv_step.sail", "loc": [ 2551, 2553 ] }, { "type": "function", "id": "handle_illegal", "file": "model/riscv_step.sail", "loc": [ 2630, 2644 ] }, { "type": "function", "id": "get_config_print_instr", "file": "model/riscv_step.sail", "loc": [ 2214, 2236 ] }, { "type": "function", "id": "print_instr", "file": "model/riscv_step.sail", "loc": [ 2272, 2283 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "print_insn", "file": "model/riscv_insts_end.sail", "loc": [ 1522, 1532 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "PC", "file": "model/riscv_step.sail", "loc": [ 2356, 2358 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_step.sail", "loc": [ 2324, 2337 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_step.sail", "loc": [ 2290, 2297 ] }, { "type": "register", "id": "instbits", "file": "model/riscv_step.sail", "loc": [ 2122, 2130 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_step.sail", "loc": [ 2133, 2144 ] }, { "type": "function", "id": "handle_mem_exception", "file": "model/riscv_step.sail", "loc": [ 1976, 1996 ] }, { "type": "function", "id": "ext_handle_fetch_check_error", "file": "model/riscv_step.sail", "loc": [ 1822, 1850 ] }, { "type": "function", "id": "handle_interrupt", "file": "model/riscv_step.sail", "loc": [ 1523, 1539 ] }, { "type": "function", "id": "get_config_print_instr", "file": "model/riscv_step.sail", "loc": [ 1412, 1434 ] }, { "type": "function", "id": "print_bits", "file": "model/riscv_step.sail", "loc": [ 1450, 1460 ] }, { "type": "function", "id": "interruptType_to_bits", "file": "model/riscv_step.sail", "loc": [ 1485, 1506 ] }, { "type": "function", "id": "ext_post_step_hook", "file": "model/riscv_step.sail", "loc": [ 3292, 3310 ] }, { "type": "function", "id": "retire_instruction", "file": "model/riscv_step.sail", "loc": [ 3209, 3227 ] }, { "type": "function", "id": "tick_pc", "file": "model/riscv_step.sail", "loc": [ 3133, 3140 ] }, { "type": "register", "id": "minstret_increment", "file": "model/riscv_step.sail", "loc": [ 1233, 1251 ] }, { "type": "register", "id": "mcountinhibit", "file": "model/riscv_step.sail", "loc": [ 1254, 1267 ] }, { "type": "function", "id": "ext_pre_step_hook", "file": "model/riscv_step.sail", "loc": [ 838, 855 ] } ] }, "tick_clock": { "function": { "number": 0, "source": "function tick_clock() = {\n if mcountinhibit[CY] == 0b0\n then mcycle = mcycle + 1;\n\n mtime = mtime + 1;\n clint_dispatch()\n}", "pattern": { "type": "literal", "value": "()" }, "body": " if mcountinhibit[CY] == 0b0\n then mcycle = mcycle + 1;\n\n mtime = mtime + 1;\n clint_dispatch()" }, "links": [ { "type": "function", "id": "clint_dispatch", "file": "model/riscv_platform.sail", "loc": [ 11813, 11827 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 11790, 11795 ] }, { "type": "register", "id": "mtime", "file": "model/riscv_platform.sail", "loc": [ 11799, 11804 ] }, { "type": "register", "id": "mcountinhibit", "file": "model/riscv_platform.sail", "loc": [ 11734, 11747 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_platform.sail", "loc": [ 11766, 11772 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_platform.sail", "loc": [ 11775, 11781 ] } ] }, "tick_pc": { "function": { "number": 0, "source": "function tick_pc() = {\n PC = nextPC\n}", "pattern": { "type": "literal", "value": "()" }, "body": " PC = nextPC" }, "links": [ { "type": "register", "id": "PC", "file": "model/riscv_pc_access.sail", "loc": [ 1252, 1254 ] }, { "type": "register", "id": "nextPC", "file": "model/riscv_pc_access.sail", "loc": [ 1257, 1263 ] } ] }, "tick_platform": { "function": { "number": 0, "source": "function tick_platform() -> unit = {\n htif_tick();\n}", "pattern": { "type": "literal", "value": "()" }, "body": " htif_tick()" }, "links": [ { "type": "function", "id": "htif_tick", "file": "model/riscv_platform.sail", "loc": [ 18874, 18883 ] } ] }, "to_bits": { "function": { "number": 0, "source": "function to_bits (l, n) = get_slice_int(l, n, 0)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "l" }, { "type": "id", "id": "n" } ] }, "body": "get_slice_int(l, n, 0)" }, "links": [ { "type": "function", "id": "get_slice_int", "file": "model/prelude.sail", "loc": [ 4895, 4908 ] } ] }, "trans_kind_of_num": { "function": { "number": 0, "source": "trans_kind_of_num arg# = $[complete] match arg# {\n 0 => Transaction_start,\n 1 => Transaction_commit,\n _ => Transaction_abort\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => Transaction_start,\n 1 => Transaction_commit,\n _ => Transaction_abort\n}" } }, "translate": { "function": { "number": 0, "source": "function translate(sv_params : SV_Params,\n asid : asidbits,\n ptb : bits(64),\n vAddr_arg : bits(64),\n ac : AccessType(ext_access_type),\n priv : Privilege,\n mxr : bool,\n do_sum : bool,\n ext_ptw : ext_ptw)\n -> TR_Result(bits(64), PTW_Error) = {\n let va_mask : bits(64) = zero_extend(ones(sv_params.va_size_bits));\n let vAddr = (vAddr_arg & va_mask);\n\n // On first reading, assume lookup_TLB returns None(), since TLBs\n // are not part of RISC-V archticture spec (see TLB_NOTE above)\n match lookup_TLB(asid, vAddr) {\n Some(index, ent) => translate_TLB_hit(sv_params, asid, ptb, vAddr, ac, priv,\n mxr, do_sum, ext_ptw, index, ent),\n None() => translate_TLB_miss(sv_params, asid, ptb, vAddr, ac, priv,\n mxr, do_sum, ext_ptw)\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "asid" }, { "type": "id", "id": "ptb" }, { "type": "id", "id": "vAddr_arg" }, { "type": "id", "id": "ac" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "mxr" }, { "type": "id", "id": "do_sum" }, { "type": "id", "id": "ext_ptw" } ] }, "body": " let va_mask : bits(64) = zero_extend(ones(sv_params.va_size_bits));\n let vAddr = (vAddr_arg & va_mask);\n\n // On first reading, assume lookup_TLB returns None(), since TLBs\n // are not part of RISC-V archticture spec (see TLB_NOTE above)\n match lookup_TLB(asid, vAddr) {\n Some(index, ent) => translate_TLB_hit(sv_params, asid, ptb, vAddr, ac, priv,\n mxr, do_sum, ext_ptw, index, ent),\n None() => translate_TLB_miss(sv_params, asid, ptb, vAddr, ac, priv,\n mxr, do_sum, ext_ptw)\n }" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 16938, 16949 ] }, { "type": "function", "id": "ones", "file": "model/riscv_vmem.sail", "loc": [ 16950, 16954 ] }, { "type": "function", "id": "lookup_TLB", "file": "model/riscv_vmem.sail", "loc": [ 17174, 17184 ] }, { "type": "function", "id": "translate_TLB_miss", "file": "model/riscv_vmem.sail", "loc": [ 17382, 17400 ] }, { "type": "function", "id": "translate_TLB_hit", "file": "model/riscv_vmem.sail", "loc": [ 17224, 17241 ] } ] }, "translateAddr": { "function": { "number": 0, "source": "function translateAddr(vAddr : xlenbits,\n ac : AccessType(ext_access_type))\n -> TR_Result(xlenbits, ExceptionType) = {\n // Internally the vmem code works with 64-bit values, whether xlen==32 or xlen==64\n // This 'extend' is a no-op when xlen==64 and extends when xlen==32\n let vAddr_64b : bits(64) = zero_extend(vAddr);\n // Effective privilege takes into account mstatus.PRV, mstatus.MPP\n // See riscv_sys_regs.sail for effectivePrivilege() and cur_privilege\n let effPriv : Privilege = effectivePrivilege(ac, mstatus, cur_privilege);\n let mode : SATPMode = translationMode(effPriv);\n let (valid_va, sv_params) : (bool, SV_Params) = match mode {\n Sbare => return TR_Address(vAddr, init_ext_ptw),\n Sv32 => (true, sv32_params),\n Sv39 => (is_valid_vAddr(sv39_params, vAddr_64b), sv39_params),\n Sv48 => (is_valid_vAddr(sv48_params, vAddr_64b), sv48_params),\n // Sv57 => (is_valid_vAddr(sv57_params, vAddr_64b), sv57_params), // TODO\n };\n if not(valid_va) then\n TR_Failure(translationException(ac, PTW_Invalid_Addr()), init_ext_ptw)\n else {\n let mxr = mstatus.MXR() == 0b1;\n let do_sum = mstatus.SUM() == 0b1;\n let asid : asidbits = satp_to_asid(satp);\n let ptb : bits(64) = satp_to_PT_base(satp);\n let tr_result1 = translate(sv_params,\n asid,\n ptb,\n vAddr_64b,\n ac, effPriv, mxr, do_sum,\n init_ext_ptw);\n // Fixup result PA or exception\n match tr_result1 {\n TR_Address(pa, ext_ptw) => TR_Address(truncate(pa, sizeof(xlen)), ext_ptw),\n TR_Failure(f, ext_ptw) => TR_Failure(translationException(ac, f), ext_ptw)\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "vAddr" }, { "type": "id", "id": "ac" } ] }, "body": " let vAddr_64b : bits(64) = zero_extend(vAddr);\n // Effective privilege takes into account mstatus.PRV, mstatus.MPP\n // See riscv_sys_regs.sail for effectivePrivilege() and cur_privilege\n let effPriv : Privilege = effectivePrivilege(ac, mstatus, cur_privilege);\n let mode : SATPMode = translationMode(effPriv);\n let (valid_va, sv_params) : (bool, SV_Params) = match mode {\n Sbare => return TR_Address(vAddr, init_ext_ptw),\n Sv32 => (true, sv32_params),\n Sv39 => (is_valid_vAddr(sv39_params, vAddr_64b), sv39_params),\n Sv48 => (is_valid_vAddr(sv48_params, vAddr_64b), sv48_params),\n // Sv57 => (is_valid_vAddr(sv57_params, vAddr_64b), sv57_params), // TODO\n };\n if not(valid_va) then\n TR_Failure(translationException(ac, PTW_Invalid_Addr()), init_ext_ptw)\n else {\n let mxr = mstatus.MXR() == 0b1;\n let do_sum = mstatus.SUM() == 0b1;\n let asid : asidbits = satp_to_asid(satp);\n let ptb : bits(64) = satp_to_PT_base(satp);\n let tr_result1 = translate(sv_params,\n asid,\n ptb,\n vAddr_64b,\n ac, effPriv, mxr, do_sum,\n init_ext_ptw);\n // Fixup result PA or exception\n match tr_result1 {\n TR_Address(pa, ext_ptw) => TR_Address(truncate(pa, sizeof(xlen)), ext_ptw),\n TR_Failure(f, ext_ptw) => TR_Failure(translationException(ac, f), ext_ptw)\n }\n }" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 17959, 17970 ] }, { "type": "function", "id": "effectivePrivilege", "file": "model/riscv_vmem.sail", "loc": [ 18150, 18168 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_vmem.sail", "loc": [ 18182, 18195 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_vmem.sail", "loc": [ 18173, 18180 ] }, { "type": "function", "id": "translationMode", "file": "model/riscv_vmem.sail", "loc": [ 18228, 18243 ] }, { "type": "function", "id": "is_valid_vAddr", "file": "model/riscv_vmem.sail", "loc": [ 18518, 18532 ] }, { "type": "function", "id": "is_valid_vAddr", "file": "model/riscv_vmem.sail", "loc": [ 18450, 18464 ] }, { "type": "function", "id": "TR_Address", "file": "model/riscv_vmem.sail", "loc": [ 18337, 18347 ] }, { "type": "function", "id": "not", "file": "model/riscv_vmem.sail", "loc": [ 18663, 18666 ] }, { "type": "function", "id": "TR_Failure", "file": "model/riscv_vmem.sail", "loc": [ 18686, 18696 ] }, { "type": "function", "id": "translationException", "file": "model/riscv_vmem.sail", "loc": [ 18697, 18717 ] }, { "type": "function", "id": "PTW_Invalid_Addr", "file": "model/riscv_vmem.sail", "loc": [ 18722, 18738 ] }, { "type": "function", "id": "_get_Mstatus_MXR", "file": "", "loc": [ 21, 37 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_vmem.sail", "loc": [ 18794, 18801 ] }, { "type": "function", "id": "_get_Mstatus_SUM", "file": "", "loc": [ 21, 37 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_vmem.sail", "loc": [ 18844, 18851 ] }, { "type": "function", "id": "satp_to_asid", "file": "model/riscv_vmem.sail", "loc": [ 18894, 18906 ] }, { "type": "register", "id": "satp", "file": "model/riscv_vmem.sail", "loc": [ 18907, 18911 ] }, { "type": "function", "id": "satp_to_PT_base", "file": "model/riscv_vmem.sail", "loc": [ 18942, 18957 ] }, { "type": "register", "id": "satp", "file": "model/riscv_vmem.sail", "loc": [ 18958, 18962 ] }, { "type": "function", "id": "translate", "file": "model/riscv_vmem.sail", "loc": [ 18986, 18995 ] }, { "type": "function", "id": "TR_Failure", "file": "model/riscv_vmem.sail", "loc": [ 19399, 19409 ] }, { "type": "function", "id": "translationException", "file": "model/riscv_vmem.sail", "loc": [ 19410, 19430 ] }, { "type": "function", "id": "TR_Address", "file": "model/riscv_vmem.sail", "loc": [ 19317, 19327 ] }, { "type": "function", "id": "truncate", "file": "model/riscv_vmem.sail", "loc": [ 19328, 19336 ] } ] }, "translate_TLB_hit": { "function": { "number": 0, "source": "function translate_TLB_hit(sv_params : SV_Params,\n asid : asidbits,\n ptb : bits(64),\n vAddr : bits(64),\n ac : AccessType(ext_access_type),\n priv : Privilege,\n mxr : bool,\n do_sum : bool,\n ext_ptw : ext_ptw,\n tlb_index : nat,\n ent : TLB_Entry)\n -> TR_Result(bits(64), PTW_Error) = {\n let pte = ent.pte;\n let ext_pte = msbs_of_PTE(sv_params, pte);\n let pte_flags = Mk_PTE_Flags(pte[7 .. 0]);\n let pte_check = check_PTE_permission(ac, priv, mxr, do_sum, pte_flags,\n ext_pte,\n ext_ptw);\n match pte_check {\n PTE_Check_Failure(ext_ptw, ext_ptw_fail) =>\n TR_Failure(ext_get_ptw_error(ext_ptw_fail), ext_ptw),\n PTE_Check_Success(ext_ptw) =>\n match update_PTE_Bits(sv_params, pte, ac) {\n None() => TR_Address(ent.pAddr | (vAddr & ent.vAddrMask), ext_ptw),\n Some(pte') =>\n // See riscv_platform.sail\n if not(plat_enable_dirty_update()) then\n // pte needs dirty/accessed update but that is not enabled\n TR_Failure(PTW_PTE_Update(), ext_ptw)\n else {\n // Writeback the PTE (which has new A/D bits)\n let n_ent = {ent with pte=pte'};\n write_TLB(tlb_index, n_ent);\n let pte_phys_addr = ent.pteAddr[(sizeof(xlen) - 1) .. 0];\n let mv = mem_write_value_priv(pte_phys_addr,\n 8,\n pte',\n Supervisor,\n false,\n false,\n false);\n match mv {\n MemValue(_) => (),\n MemException(e) => internal_error(__FILE__, __LINE__,\n \"invalid physical address in TLB\")\n };\n TR_Address(ent.pAddr | (vAddr & ent.vAddrMask), ext_ptw)\n }\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "asid" }, { "type": "id", "id": "ptb" }, { "type": "id", "id": "vAddr" }, { "type": "id", "id": "ac" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "mxr" }, { "type": "id", "id": "do_sum" }, { "type": "id", "id": "ext_ptw" }, { "type": "id", "id": "tlb_index" }, { "type": "id", "id": "ent" } ] }, "body": " let pte = ent.pte;\n let ext_pte = msbs_of_PTE(sv_params, pte);\n let pte_flags = Mk_PTE_Flags(pte[7 .. 0]);\n let pte_check = check_PTE_permission(ac, priv, mxr, do_sum, pte_flags,\n ext_pte,\n ext_ptw);\n match pte_check {\n PTE_Check_Failure(ext_ptw, ext_ptw_fail) =>\n TR_Failure(ext_get_ptw_error(ext_ptw_fail), ext_ptw),\n PTE_Check_Success(ext_ptw) =>\n match update_PTE_Bits(sv_params, pte, ac) {\n None() => TR_Address(ent.pAddr | (vAddr & ent.vAddrMask), ext_ptw),\n Some(pte') =>\n // See riscv_platform.sail\n if not(plat_enable_dirty_update()) then\n // pte needs dirty/accessed update but that is not enabled\n TR_Failure(PTW_PTE_Update(), ext_ptw)\n else {\n // Writeback the PTE (which has new A/D bits)\n let n_ent = {ent with pte=pte'};\n write_TLB(tlb_index, n_ent);\n let pte_phys_addr = ent.pteAddr[(sizeof(xlen) - 1) .. 0];\n let mv = mem_write_value_priv(pte_phys_addr,\n 8,\n pte',\n Supervisor,\n false,\n false,\n false);\n match mv {\n MemValue(_) => (),\n MemException(e) => internal_error(__FILE__, __LINE__,\n \"invalid physical address in TLB\")\n };\n TR_Address(ent.pAddr | (vAddr & ent.vAddrMask), ext_ptw)\n }\n }\n }" }, "links": [ { "type": "function", "id": "msbs_of_PTE", "file": "model/riscv_vmem.sail", "loc": [ 12296, 12307 ] }, { "type": "function", "id": "Mk_PTE_Flags", "file": "model/riscv_vmem.sail", "loc": [ 12343, 12355 ] }, { "type": "function", "id": "check_PTE_permission", "file": "model/riscv_vmem.sail", "loc": [ 12388, 12408 ] }, { "type": "function", "id": "update_PTE_Bits", "file": "model/riscv_vmem.sail", "loc": [ 12714, 12729 ] }, { "type": "function", "id": "not", "file": "model/riscv_vmem.sail", "loc": [ 12904, 12907 ] }, { "type": "function", "id": "plat_enable_dirty_update", "file": "model/riscv_vmem.sail", "loc": [ 12908, 12932 ] }, { "type": "function", "id": "TR_Failure", "file": "model/riscv_vmem.sail", "loc": [ 13024, 13034 ] }, { "type": "function", "id": "PTW_PTE_Update", "file": "model/riscv_vmem.sail", "loc": [ 13035, 13049 ] }, { "type": "function", "id": "mem_write_value_priv", "file": "model/riscv_vmem.sail", "loc": [ 13314, 13334 ] }, { "type": "function", "id": "TR_Address", "file": "model/riscv_vmem.sail", "loc": [ 13883, 13893 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_vmem.sail", "loc": [ 13738, 13752 ] }, { "type": "function", "id": "write_TLB", "file": "model/riscv_vmem.sail", "loc": [ 13194, 13203 ] }, { "type": "function", "id": "TR_Address", "file": "model/riscv_vmem.sail", "loc": [ 12774, 12784 ] }, { "type": "function", "id": "TR_Failure", "file": "model/riscv_vmem.sail", "loc": [ 12614, 12624 ] }, { "type": "function", "id": "ext_get_ptw_error", "file": "model/riscv_vmem.sail", "loc": [ 12625, 12642 ] } ] }, "translate_TLB_miss": { "function": { "number": 0, "source": "function translate_TLB_miss(sv_params : SV_Params,\n asid : asidbits,\n ptb : bits(64),\n vAddr : bits(64),\n ac : AccessType(ext_access_type),\n priv : Privilege,\n mxr : bool,\n do_sum : bool,\n ext_ptw : ext_ptw) -> TR_Result(bits(64), PTW_Error) = {\n let initial_level = sv_params.levels - 1;\n let ptw_result = pt_walk(sv_params, vAddr, ac, priv, mxr, do_sum,\n ptb, initial_level, false, ext_ptw);\n match ptw_result {\n PTW_Failure(f, ext_ptw) => TR_Failure(f, ext_ptw),\n PTW_Success(pAddr, pte, pteAddr, level, global, ext_ptw) => {\n let ext_pte = msbs_of_PTE(sv_params, pte);\n // Without TLBs, this 'match' expression can be replaced simply\n // by: 'TR_Address(pAddr, ext_ptw)' (see TLB_NOTE above)\n match update_PTE_Bits(sv_params, pte, ac) {\n None() => {\n add_to_TLB(asid, vAddr, pAddr, pte, pteAddr, level, global,\n sv_params.vpn_size_bits,\n pagesize_bits);\n TR_Address(pAddr, ext_ptw)\n },\n Some(pte') =>\n // See riscv_platform.sail\n if not(plat_enable_dirty_update()) then\n // pte needs dirty/accessed update but that is not enabled\n TR_Failure(PTW_PTE_Update(), ext_ptw)\n else {\n // Writeback the PTE (which has new A/D bits)\n let pte_phys_addr = pteAddr[(sizeof(xlen) - 1) .. 0];\n let mv = mem_write_value_priv(pte_phys_addr, // pteAddr,\n 8,\n pte',\n Supervisor,\n false,\n false,\n false);\n match mv {\n MemValue(_) => {\n add_to_TLB(asid, vAddr, pAddr, pte', pteAddr, level, global,\n sv_params.vpn_size_bits,\n pagesize_bits);\n TR_Address(pAddr, ext_ptw)\n },\n MemException(e) =>\n TR_Failure(PTW_Access(), ext_ptw)\n }\n }\n }\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "asid" }, { "type": "id", "id": "ptb" }, { "type": "id", "id": "vAddr" }, { "type": "id", "id": "ac" }, { "type": "id", "id": "priv" }, { "type": "id", "id": "mxr" }, { "type": "id", "id": "do_sum" }, { "type": "id", "id": "ext_ptw" } ] }, "body": " let initial_level = sv_params.levels - 1;\n let ptw_result = pt_walk(sv_params, vAddr, ac, priv, mxr, do_sum,\n ptb, initial_level, false, ext_ptw);\n match ptw_result {\n PTW_Failure(f, ext_ptw) => TR_Failure(f, ext_ptw),\n PTW_Success(pAddr, pte, pteAddr, level, global, ext_ptw) => {\n let ext_pte = msbs_of_PTE(sv_params, pte);\n // Without TLBs, this 'match' expression can be replaced simply\n // by: 'TR_Address(pAddr, ext_ptw)' (see TLB_NOTE above)\n match update_PTE_Bits(sv_params, pte, ac) {\n None() => {\n add_to_TLB(asid, vAddr, pAddr, pte, pteAddr, level, global,\n sv_params.vpn_size_bits,\n pagesize_bits);\n TR_Address(pAddr, ext_ptw)\n },\n Some(pte') =>\n // See riscv_platform.sail\n if not(plat_enable_dirty_update()) then\n // pte needs dirty/accessed update but that is not enabled\n TR_Failure(PTW_PTE_Update(), ext_ptw)\n else {\n // Writeback the PTE (which has new A/D bits)\n let pte_phys_addr = pteAddr[(sizeof(xlen) - 1) .. 0];\n let mv = mem_write_value_priv(pte_phys_addr, // pteAddr,\n 8,\n pte',\n Supervisor,\n false,\n false,\n false);\n match mv {\n MemValue(_) => {\n add_to_TLB(asid, vAddr, pAddr, pte', pteAddr, level, global,\n sv_params.vpn_size_bits,\n pagesize_bits);\n TR_Address(pAddr, ext_ptw)\n },\n MemException(e) =>\n TR_Failure(PTW_Access(), ext_ptw)\n }\n }\n }\n }\n }" }, "links": [ { "type": "function", "id": "pt_walk", "file": "model/riscv_vmem.sail", "loc": [ 14590, 14597 ] }, { "type": "function", "id": "msbs_of_PTE", "file": "model/riscv_vmem.sail", "loc": [ 14870, 14881 ] }, { "type": "function", "id": "update_PTE_Bits", "file": "model/riscv_vmem.sail", "loc": [ 15047, 15062 ] }, { "type": "function", "id": "not", "file": "model/riscv_vmem.sail", "loc": [ 15378, 15381 ] }, { "type": "function", "id": "plat_enable_dirty_update", "file": "model/riscv_vmem.sail", "loc": [ 15382, 15406 ] }, { "type": "function", "id": "TR_Failure", "file": "model/riscv_vmem.sail", "loc": [ 15498, 15508 ] }, { "type": "function", "id": "PTW_PTE_Update", "file": "model/riscv_vmem.sail", "loc": [ 15509, 15523 ] }, { "type": "function", "id": "mem_write_value_priv", "file": "model/riscv_vmem.sail", "loc": [ 15698, 15718 ] }, { "type": "function", "id": "TR_Failure", "file": "model/riscv_vmem.sail", "loc": [ 16376, 16386 ] }, { "type": "function", "id": "PTW_Access", "file": "model/riscv_vmem.sail", "loc": [ 16387, 16397 ] }, { "type": "function", "id": "TR_Address", "file": "model/riscv_vmem.sail", "loc": [ 16283, 16293 ] }, { "type": "function", "id": "add_to_TLB", "file": "model/riscv_vmem.sail", "loc": [ 16111, 16121 ] }, { "type": "function", "id": "TR_Address", "file": "model/riscv_vmem.sail", "loc": [ 15268, 15278 ] }, { "type": "function", "id": "add_to_TLB", "file": "model/riscv_vmem.sail", "loc": [ 15115, 15125 ] }, { "type": "function", "id": "TR_Failure", "file": "model/riscv_vmem.sail", "loc": [ 14758, 14768 ] } ] }, "translationException": { "function": { "number": 0, "source": "function translationException(a : AccessType(ext_access_type),\n f : PTW_Error)\n -> ExceptionType = {\n match (a, f) {\n (_, PTW_Ext_Error(e)) => E_Extension(ext_translate_exception(e)),\n (ReadWrite(_), PTW_Access()) => E_SAMO_Access_Fault(),\n (ReadWrite(_), _) => E_SAMO_Page_Fault(),\n (Read(_), PTW_Access()) => E_Load_Access_Fault(),\n (Read(_), _) => E_Load_Page_Fault(),\n (Write(_), PTW_Access()) => E_SAMO_Access_Fault(),\n (Write(_), _) => E_SAMO_Page_Fault(),\n (Execute(), PTW_Access()) => E_Fetch_Access_Fault(),\n (Execute(), _) => E_Fetch_Page_Fault()\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "a" }, { "type": "id", "id": "f" } ] }, "body": " match (a, f) {\n (_, PTW_Ext_Error(e)) => E_Extension(ext_translate_exception(e)),\n (ReadWrite(_), PTW_Access()) => E_SAMO_Access_Fault(),\n (ReadWrite(_), _) => E_SAMO_Page_Fault(),\n (Read(_), PTW_Access()) => E_Load_Access_Fault(),\n (Read(_), _) => E_Load_Page_Fault(),\n (Write(_), PTW_Access()) => E_SAMO_Access_Fault(),\n (Write(_), _) => E_SAMO_Page_Fault(),\n (Execute(), PTW_Access()) => E_Fetch_Access_Fault(),\n (Execute(), _) => E_Fetch_Page_Fault()\n }" }, "links": [ { "type": "function", "id": "E_Fetch_Page_Fault", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2940, 2958 ] }, { "type": "function", "id": "E_Fetch_Access_Fault", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2880, 2900 ] }, { "type": "function", "id": "E_SAMO_Page_Fault", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2823, 2840 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2764, 2783 ] }, { "type": "function", "id": "E_Load_Page_Fault", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2707, 2724 ] }, { "type": "function", "id": "E_Load_Access_Fault", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2648, 2667 ] }, { "type": "function", "id": "E_SAMO_Page_Fault", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2591, 2608 ] }, { "type": "function", "id": "E_SAMO_Access_Fault", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2532, 2551 ] }, { "type": "function", "id": "E_Extension", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2455, 2466 ] }, { "type": "function", "id": "ext_translate_exception", "file": "model/riscv_vmem_ptw.sail", "loc": [ 2467, 2490 ] } ] }, "translationMode": { "function": { "number": 0, "source": "function translationMode(priv : Privilege) -> SATPMode = {\n if priv == Machine then\n Sbare\n else if sizeof(xlen) == 32 then\n match Mk_Satp32(satp)[Mode] {\n 0b0 => Sbare,\n 0b1 => Sv32\n }\n else if sizeof(xlen) == 64 then {\n // Translation mode is based on mstatus.SXL, which could be RV32 when xlen==64\n let arch = architecture(get_mstatus_SXL(mstatus));\n match arch {\n Some(RV64) => { let mbits : bits(4) = satp[63 .. 60];\n match satp64Mode_of_bits(RV64, mbits) { // see riscv_types.sail\n Some(m) => m,\n None() => internal_error(__FILE__, __LINE__,\n \"invalid RV64 translation mode in satp\")\n }\n },\n Some(RV32) => match Mk_Satp32(satp[31 .. 0])[Mode] { // Note: satp is 64bits here\n // When xlen is 64, mstatus.SXL (for S privilege) can be RV32\n 0b0 => Sbare,\n 0b1 => Sv32\n },\n _ => internal_error(__FILE__, __LINE__, \"unsupported address translation arch\")\n }\n }\n else\n internal_error(__FILE__, __LINE__, \"unsupported xlen\")\n}", "pattern": { "type": "id", "id": "priv" }, "body": " if priv == Machine then\n Sbare\n else if sizeof(xlen) == 32 then\n match Mk_Satp32(satp)[Mode] {\n 0b0 => Sbare,\n 0b1 => Sv32\n }\n else if sizeof(xlen) == 64 then {\n // Translation mode is based on mstatus.SXL, which could be RV32 when xlen==64\n let arch = architecture(get_mstatus_SXL(mstatus));\n match arch {\n Some(RV64) => { let mbits : bits(4) = satp[63 .. 60];\n match satp64Mode_of_bits(RV64, mbits) { // see riscv_types.sail\n Some(m) => m,\n None() => internal_error(__FILE__, __LINE__,\n \"invalid RV64 translation mode in satp\")\n }\n },\n Some(RV32) => match Mk_Satp32(satp[31 .. 0])[Mode] { // Note: satp is 64bits here\n // When xlen is 64, mstatus.SXL (for S privilege) can be RV32\n 0b0 => Sbare,\n 0b1 => Sv32\n },\n _ => internal_error(__FILE__, __LINE__, \"unsupported address translation arch\")\n }\n }\n else\n internal_error(__FILE__, __LINE__, \"unsupported xlen\")" }, "links": [ { "type": "function", "id": "Mk_Satp32", "file": "model/riscv_vmem.sail", "loc": [ 10097, 10106 ] }, { "type": "register", "id": "satp", "file": "model/riscv_vmem.sail", "loc": [ 10107, 10111 ] }, { "type": "function", "id": "architecture", "file": "model/riscv_vmem.sail", "loc": [ 10300, 10312 ] }, { "type": "function", "id": "get_mstatus_SXL", "file": "model/riscv_vmem.sail", "loc": [ 10313, 10328 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_vmem.sail", "loc": [ 10329, 10336 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_vmem.sail", "loc": [ 11035, 11049 ] }, { "type": "function", "id": "Mk_Satp32", "file": "model/riscv_vmem.sail", "loc": [ 10778, 10787 ] }, { "type": "register", "id": "satp", "file": "model/riscv_vmem.sail", "loc": [ 10788, 10792 ] }, { "type": "register", "id": "satp", "file": "model/riscv_vmem.sail", "loc": [ 10401, 10405 ] }, { "type": "function", "id": "satp64Mode_of_bits", "file": "model/riscv_vmem.sail", "loc": [ 10445, 10463 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_vmem.sail", "loc": [ 10579, 10593 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_vmem.sail", "loc": [ 11131, 11145 ] } ] }, "trapVectorMode_of_bits": { "function": { "number": 0, "source": "function trapVectorMode_of_bits (m) =\n match (m) {\n 0b00 => TV_Direct,\n 0b01 => TV_Vector,\n _ => TV_Reserved\n }", "pattern": { "type": "id", "id": "m" }, "body": "match (m) {\n 0b00 => TV_Direct,\n 0b01 => TV_Vector,\n _ => TV_Reserved\n }" } }, "trap_handler": { "function": { "number": 0, "source": "function trap_handler(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenbits, info : option(xlenbits), ext : option(ext_exception))\n -> xlenbits = {\n rvfi_trap();\n if get_config_print_platform()\n then print_platform(\"handling \" ^ (if intr then \"int#\" else \"exc#\")\n ^ BitStr(c) ^ \" at priv \" ^ to_str(del_priv)\n ^ \" with tval \" ^ BitStr(tval(info)));\n\n cancel_reservation();\n\n match (del_priv) {\n Machine => {\n mcause[IsInterrupt] = bool_to_bits(intr);\n mcause[Cause] = zero_extend(c);\n\n mstatus[MPIE] = mstatus[MIE];\n mstatus[MIE] = 0b0;\n mstatus[MPP] = privLevel_to_bits(cur_privilege);\n mtval = tval(info);\n mepc = pc;\n\n cur_privilege = del_priv;\n\n handle_trap_extension(del_priv, pc, ext);\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n\n prepare_trap_vector(del_priv, mcause)\n },\n Supervisor => {\n assert (haveSupMode(), \"no supervisor mode present for delegation\");\n\n scause[IsInterrupt] = bool_to_bits(intr);\n scause[Cause] = zero_extend(c);\n\n mstatus[SPIE] = mstatus[SIE];\n mstatus[SIE] = 0b0;\n mstatus[SPP] = match cur_privilege {\n User => 0b0,\n Supervisor => 0b1,\n Machine => internal_error(__FILE__, __LINE__, \"invalid privilege for s-mode trap\")\n };\n stval = tval(info);\n sepc = pc;\n\n cur_privilege = del_priv;\n\n handle_trap_extension(del_priv, pc, ext);\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n\n prepare_trap_vector(del_priv, scause)\n },\n User => {\n assert(haveUsrMode(), \"no user mode present for delegation\");\n\n ucause[IsInterrupt] = bool_to_bits(intr);\n ucause[Cause] = zero_extend(c);\n\n mstatus[UPIE] = mstatus[UIE];\n mstatus[UIE] = 0b0;\n utval = tval(info);\n uepc = pc;\n\n cur_privilege = del_priv;\n\n handle_trap_extension(del_priv, pc, ext);\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n\n prepare_trap_vector(del_priv, ucause)\n }\n };\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "del_priv" }, { "type": "id", "id": "intr" }, { "type": "id", "id": "c" }, { "type": "id", "id": "pc" }, { "type": "id", "id": "info" }, { "type": "id", "id": "ext" } ] }, "body": " rvfi_trap();\n if get_config_print_platform()\n then print_platform(\"handling \" ^ (if intr then \"int#\" else \"exc#\")\n ^ BitStr(c) ^ \" at priv \" ^ to_str(del_priv)\n ^ \" with tval \" ^ BitStr(tval(info)));\n\n cancel_reservation();\n\n match (del_priv) {\n Machine => {\n mcause[IsInterrupt] = bool_to_bits(intr);\n mcause[Cause] = zero_extend(c);\n\n mstatus[MPIE] = mstatus[MIE];\n mstatus[MIE] = 0b0;\n mstatus[MPP] = privLevel_to_bits(cur_privilege);\n mtval = tval(info);\n mepc = pc;\n\n cur_privilege = del_priv;\n\n handle_trap_extension(del_priv, pc, ext);\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n\n prepare_trap_vector(del_priv, mcause)\n },\n Supervisor => {\n assert (haveSupMode(), \"no supervisor mode present for delegation\");\n\n scause[IsInterrupt] = bool_to_bits(intr);\n scause[Cause] = zero_extend(c);\n\n mstatus[SPIE] = mstatus[SIE];\n mstatus[SIE] = 0b0;\n mstatus[SPP] = match cur_privilege {\n User => 0b0,\n Supervisor => 0b1,\n Machine => internal_error(__FILE__, __LINE__, \"invalid privilege for s-mode trap\")\n };\n stval = tval(info);\n sepc = pc;\n\n cur_privilege = del_priv;\n\n handle_trap_extension(del_priv, pc, ext);\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n\n prepare_trap_vector(del_priv, scause)\n },\n User => {\n assert(haveUsrMode(), \"no user mode present for delegation\");\n\n ucause[IsInterrupt] = bool_to_bits(intr);\n ucause[Cause] = zero_extend(c);\n\n mstatus[UPIE] = mstatus[UIE];\n mstatus[UIE] = 0b0;\n utval = tval(info);\n uepc = pc;\n\n cur_privilege = del_priv;\n\n handle_trap_extension(del_priv, pc, ext);\n\n if get_config_print_reg()\n then print_reg(\"CSR mstatus <- \" ^ BitStr(mstatus.bits));\n\n prepare_trap_vector(del_priv, ucause)\n }\n }" }, "links": [ { "type": "function", "id": "prepare_trap_vector", "file": "model/riscv_sys_control.sail", "loc": [ 15466, 15485 ] }, { "type": "register", "id": "ucause", "file": "model/riscv_sys_control.sail", "loc": [ 15496, 15502 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 15370, 15390 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 15405, 15414 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 15442, 15449 ] }, { "type": "function", "id": "handle_trap_extension", "file": "model/riscv_sys_control.sail", "loc": [ 15315, 15336 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 15279, 15292 ] }, { "type": "register", "id": "uepc", "file": "model/riscv_sys_control.sail", "loc": [ 15249, 15253 ] }, { "type": "register", "id": "utval", "file": "model/riscv_sys_control.sail", "loc": [ 15212, 15217 ] }, { "type": "function", "id": "tval", "file": "model/riscv_sys_control.sail", "loc": [ 15230, 15234 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 15184, 15191 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 15147, 15154 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 15163, 15170 ] }, { "type": "register", "id": "ucause", "file": "model/riscv_sys_control.sail", "loc": [ 15101, 15107 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 15123, 15134 ] }, { "type": "register", "id": "ucause", "file": "model/riscv_sys_control.sail", "loc": [ 15052, 15058 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 15074, 15086 ] }, { "type": "function", "id": "haveUsrMode", "file": "model/riscv_sys_control.sail", "loc": [ 14989, 15000 ] }, { "type": "function", "id": "prepare_trap_vector", "file": "model/riscv_sys_control.sail", "loc": [ 14916, 14935 ] }, { "type": "register", "id": "scause", "file": "model/riscv_sys_control.sail", "loc": [ 14946, 14952 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 14820, 14840 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 14855, 14864 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 14892, 14899 ] }, { "type": "function", "id": "handle_trap_extension", "file": "model/riscv_sys_control.sail", "loc": [ 14765, 14786 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 14729, 14742 ] }, { "type": "register", "id": "sepc", "file": "model/riscv_sys_control.sail", "loc": [ 14699, 14703 ] }, { "type": "register", "id": "stval", "file": "model/riscv_sys_control.sail", "loc": [ 14662, 14667 ] }, { "type": "function", "id": "tval", "file": "model/riscv_sys_control.sail", "loc": [ 14680, 14684 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 14393, 14400 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 14415, 14428 ] }, { "type": "function", "id": "internal_error", "file": "model/riscv_sys_control.sail", "loc": [ 14555, 14569 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 14365, 14372 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 14328, 14335 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 14344, 14351 ] }, { "type": "register", "id": "scause", "file": "model/riscv_sys_control.sail", "loc": [ 14282, 14288 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 14304, 14315 ] }, { "type": "register", "id": "scause", "file": "model/riscv_sys_control.sail", "loc": [ 14233, 14239 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 14255, 14267 ] }, { "type": "function", "id": "haveSupMode", "file": "model/riscv_sys_control.sail", "loc": [ 14164, 14175 ] }, { "type": "function", "id": "prepare_trap_vector", "file": "model/riscv_sys_control.sail", "loc": [ 14084, 14103 ] }, { "type": "register", "id": "mcause", "file": "model/riscv_sys_control.sail", "loc": [ 14114, 14120 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 13988, 14008 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_sys_control.sail", "loc": [ 14023, 14032 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 14060, 14067 ] }, { "type": "function", "id": "handle_trap_extension", "file": "model/riscv_sys_control.sail", "loc": [ 13933, 13954 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 13897, 13910 ] }, { "type": "register", "id": "mepc", "file": "model/riscv_sys_control.sail", "loc": [ 13867, 13871 ] }, { "type": "register", "id": "mtval", "file": "model/riscv_sys_control.sail", "loc": [ 13830, 13835 ] }, { "type": "function", "id": "tval", "file": "model/riscv_sys_control.sail", "loc": [ 13848, 13852 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 13773, 13780 ] }, { "type": "function", "id": "privLevel_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 13789, 13806 ] }, { "type": "register", "id": "cur_privilege", "file": "model/riscv_sys_control.sail", "loc": [ 13807, 13820 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 13745, 13752 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 13708, 13715 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_sys_control.sail", "loc": [ 13724, 13731 ] }, { "type": "register", "id": "mcause", "file": "model/riscv_sys_control.sail", "loc": [ 13662, 13668 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 13684, 13695 ] }, { "type": "register", "id": "mcause", "file": "model/riscv_sys_control.sail", "loc": [ 13613, 13619 ] }, { "type": "function", "id": "bool_to_bits", "file": "model/riscv_sys_control.sail", "loc": [ 13635, 13647 ] }, { "type": "function", "id": "cancel_reservation", "file": "model/riscv_sys_control.sail", "loc": [ 13545, 13563 ] }, { "type": "function", "id": "get_config_print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 13316, 13341 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_sys_control.sail", "loc": [ 13351, 13365 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "tval", "file": "model/riscv_sys_control.sail", "loc": [ 13528, 13532 ] }, { "type": "function", "id": "privLevel_to_str", "file": "model/riscv_types.sail", "loc": [ 3620, 3636 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "rvfi_trap", "file": "model/riscv_sys_control.sail", "loc": [ 13296, 13305 ] } ] }, "tval": { "function": { "number": 0, "source": "function tval(excinfo : option(xlenbits)) -> xlenbits = {\n match (excinfo) {\n Some(e) => e,\n None() => zero_extend(0b0)\n }\n}", "pattern": { "type": "id", "id": "excinfo" }, "body": " match (excinfo) {\n Some(e) => e,\n None() => zero_extend(0b0)\n }" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_control.sail", "loc": [ 12810, 12821 ] } ] }, "tvec_addr": { "function": { "number": 0, "source": "function tvec_addr(m : Mtvec, c : Mcause) -> option(xlenbits) = {\n let base : xlenbits = m[Base] @ 0b00;\n match (trapVectorMode_of_bits(m[Mode])) {\n TV_Direct => Some(base),\n TV_Vector => if c[IsInterrupt] == 0b1\n then Some(base + (zero_extend(c[Cause]) << 2))\n else Some(base),\n TV_Reserved => None()\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "c" } ] }, "body": " let base : xlenbits = m[Base] @ 0b00;\n match (trapVectorMode_of_bits(m[Mode])) {\n TV_Direct => Some(base),\n TV_Vector => if c[IsInterrupt] == 0b1\n then Some(base + (zero_extend(c[Cause]) << 2))\n else Some(base),\n TV_Reserved => None()\n }" }, "links": [ { "type": "function", "id": "trapVectorMode_of_bits", "file": "model/riscv_sys_regs.sail", "loc": [ 13735, 13757 ] }, { "type": "function", "id": "None", "file": "model/riscv_sys_regs.sail", "loc": [ 13960, 13964 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_regs.sail", "loc": [ 13865, 13869 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_sys_regs.sail", "loc": [ 13878, 13889 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_regs.sail", "loc": [ 13929, 13933 ] }, { "type": "function", "id": "Some", "file": "model/riscv_sys_regs.sail", "loc": [ 13787, 13791 ] } ] }, "ufFlag": { "function": { "number": 0, "source": "function ufFlag() -> bits(5) = 0b_00010", "pattern": { "type": "literal", "value": "()" }, "body": "0b_00010" } }, "undefined_SV_Params": { "function": { "number": 0, "source": "function undefined_SV_Params() = sv32_params", "pattern": { "type": "literal", "value": "()" }, "body": "sv32_params" } }, "unsigned_saturation": { "function": { "number": 0, "source": "function unsigned_saturation(len, elem) = {\n if unsigned(elem) > unsigned(ones('m)) then {\n vxsat = 0b1;\n ones('m)\n } else {\n vxsat = 0b0;\n elem['m - 1 .. 0]\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "len" }, { "type": "id", "id": "elem" } ] }, "body": " if unsigned(elem) > unsigned(ones('m)) then {\n vxsat = 0b1;\n ones('m)\n } else {\n vxsat = 0b0;\n elem['m - 1 .. 0]\n }" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22007, 22015 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22016, 22020 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 21990, 21998 ] }, { "type": "function", "id": "ones", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22054, 22058 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22037, 22042 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 22078, 22083 ] } ] }, "uop_of_num": { "function": { "number": 0, "source": "uop_of_num arg# = $[complete] match arg# {\n 0 => RISCV_LUI,\n _ => RISCV_AUIPC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_LUI,\n _ => RISCV_AUIPC\n}" } }, "update_PTE_Bits": { "function": { "number": 0, "source": "function update_PTE_Bits(sv_params : SV_Params,\n pte : bits(64),\n a : AccessType(ext_access_type))\n -> option(bits(64)) = {\n let pte_flags = Mk_PTE_Flags(pte [7 .. 0]);\n\n // Update 'dirty' bit?\n let update_d : bool = (pte_flags[D] == 0b0)\n & (match a {\n Execute() => false,\n Read() => false,\n Write(_) => true,\n ReadWrite(_, _) => true\n });\n // Update 'accessed'-bit?\n let update_a = (pte_flags[A] == 0b0);\n\n if update_d | update_a then {\n let pte_flags = [pte_flags with\n A = 0b1,\n D = (if update_d then 0b1 else pte_flags[D])];\n Some(pte[63 .. 8] @ pte_flags.bits())\n }\n else\n None()\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "pte" }, { "type": "id", "id": "a" } ] }, "body": " let pte_flags = Mk_PTE_Flags(pte [7 .. 0]);\n\n // Update 'dirty' bit?\n let update_d : bool = (pte_flags[D] == 0b0)\n & (match a {\n Execute() => false,\n Read() => false,\n Write(_) => true,\n ReadWrite(_, _) => true\n });\n // Update 'accessed'-bit?\n let update_a = (pte_flags[A] == 0b0);\n\n if update_d | update_a then {\n let pte_flags = [pte_flags with\n A = 0b1,\n D = (if update_d then 0b1 else pte_flags[D])];\n Some(pte[63 .. 8] @ pte_flags.bits())\n }\n else\n None()" }, "links": [ { "type": "function", "id": "Mk_PTE_Flags", "file": "model/riscv_vmem_pte.sail", "loc": [ 5132, 5144 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vmem_pte.sail", "loc": [ 5758, 5762 ] }, { "type": "function", "id": "_get_PTE_Flags_bits", "file": "", "loc": [ 22, 41 ] }, { "type": "function", "id": "None", "file": "model/riscv_vmem_pte.sail", "loc": [ 5811, 5815 ] } ] }, "validDoubleRegs": { "function": { "number": 0, "source": "function validDoubleRegs(n, regs) = {\n if haveZdinx() & sizeof(xlen) == 32 then\n foreach (i from 0 to (n - 1))\n if (regs[i][0] == bitone) then return false;\n true\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "n" }, { "type": "id", "id": "regs" } ] }, "body": " if haveZdinx() & sizeof(xlen) == 32 then\n foreach (i from 0 to (n - 1))\n if (regs[i][0] == bitone) then return false;\n true" }, "links": [ { "type": "function", "id": "haveZdinx", "file": "model/riscv_insts_dext.sail", "loc": [ 7748, 7757 ] } ] }, "valid_eew_emul": { "function": { "number": 0, "source": "function valid_eew_emul(EEW, EMUL_pow) = {\n let ELEN = int_power(2, get_elen_pow());\n EEW >= 8 & EEW <= ELEN & EMUL_pow >= -3 & EMUL_pow <= 3\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "EEW" }, { "type": "id", "id": "EMUL_pow" } ] }, "body": " let ELEN = int_power(2, get_elen_pow());\n EEW >= 8 & EEW <= ELEN & EMUL_pow >= -3 & EMUL_pow <= 3" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 1284, 1293 ] }, { "type": "function", "id": "get_elen_pow", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 1297, 1309 ] } ] }, "valid_fp_op": { "function": { "number": 0, "source": "function valid_fp_op(SEW, rm_3b) = {\n /* 128-bit floating-point values will be supported in future extensions */\n let valid_sew = (SEW >= 16 & SEW <= 128);\n let valid_rm = not(rm_3b == 0b101 | rm_3b == 0b110 | rm_3b == 0b111);\n valid_sew & valid_rm\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "SEW" }, { "type": "id", "id": "rm_3b" } ] }, "body": " let valid_sew = (SEW >= 16 & SEW <= 128);\n let valid_rm = not(rm_3b == 0b101 | rm_3b == 0b110 | rm_3b == 0b111);\n valid_sew & valid_rm" }, "links": [ { "type": "function", "id": "not", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 2230, 2233 ] } ] }, "valid_rd_mask": { "function": { "number": 0, "source": "function valid_rd_mask(rd, vm) = {\n vm != 0b0 | rd != 0b00000\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "vm" } ] }, "body": " vm != 0b0 | rd != 0b00000" } }, "valid_reg_overlap": { "function": { "number": 0, "source": "function valid_reg_overlap(rs, rd, EMUL_pow_rs, EMUL_pow_rd) = {\n let rs_group = if EMUL_pow_rs > 0 then int_power(2, EMUL_pow_rs) else 1;\n let rd_group = if EMUL_pow_rd > 0 then int_power(2, EMUL_pow_rd) else 1;\n let rs_int = unsigned(rs);\n let rd_int = unsigned(rd);\n if EMUL_pow_rs < EMUL_pow_rd then {\n (rs_int + rs_group <= rd_int) | (rs_int >= rd_int + rd_group) |\n ((rs_int + rs_group == rd_int + rd_group) & (EMUL_pow_rs >= 0))\n } else if EMUL_pow_rs > EMUL_pow_rd then {\n (rd_int <= rs_int) | (rd_int >= rs_int + rs_group)\n } else true;\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "rs" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "EMUL_pow_rs" }, { "type": "id", "id": "EMUL_pow_rd" } ] }, "body": " let rs_group = if EMUL_pow_rs > 0 then int_power(2, EMUL_pow_rs) else 1;\n let rd_group = if EMUL_pow_rd > 0 then int_power(2, EMUL_pow_rd) else 1;\n let rs_int = unsigned(rs);\n let rd_int = unsigned(rd);\n if EMUL_pow_rs < EMUL_pow_rd then {\n (rs_int + rs_group <= rd_int) | (rs_int >= rd_int + rd_group) |\n ((rs_int + rs_group == rd_int + rd_group) & (EMUL_pow_rs >= 0))\n } else if EMUL_pow_rs > EMUL_pow_rd then {\n (rd_int <= rs_int) | (rd_int >= rs_int + rs_group)\n } else true;" }, "links": [ { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 3287, 3296 ] }, { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 3362, 3371 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 3411, 3419 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 3440, 3448 ] } ] }, "valid_rounding_mode": { "function": { "number": 0, "source": "function valid_rounding_mode rm = (rm != 0b101 & rm != 0b110)", "pattern": { "type": "id", "id": "rm" }, "body": "rm != 0b101 & rm != 0b110" } }, "valid_segment": { "function": { "number": 0, "source": "function valid_segment(nf, EMUL_pow) = {\n if EMUL_pow < 0 then nf / int_power(2, 0 - EMUL_pow) <= 8\n else nf * int_power(2, EMUL_pow) <= 8\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "EMUL_pow" } ] }, "body": " if EMUL_pow < 0 then nf / int_power(2, 0 - EMUL_pow) <= 8\n else nf * int_power(2, EMUL_pow) <= 8" }, "links": [ { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 4067, 4076 ] }, { "type": "function", "id": "int_power", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 4111, 4120 ] } ] }, "valid_vtype": { "function": { "number": 0, "source": "function valid_vtype() = {\n vtype[vill] == 0b0\n}", "pattern": { "type": "literal", "value": "()" }, "body": " vtype[vill] == 0b0" }, "links": [ { "type": "register", "id": "vtype", "file": "model/riscv_insts_vext_utils.sail", "loc": [ 1711, 1716 ] } ] }, "vext2funct6_of_num": { "function": { "number": 0, "source": "vext2funct6_of_num arg# = $[complete] match arg# {\n 0 => VEXT2_ZVF2,\n _ => VEXT2_SVF2\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VEXT2_ZVF2,\n _ => VEXT2_SVF2\n}" } }, "vext4funct6_of_num": { "function": { "number": 0, "source": "vext4funct6_of_num arg# = $[complete] match arg# {\n 0 => VEXT4_ZVF4,\n _ => VEXT4_SVF4\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VEXT4_ZVF4,\n _ => VEXT4_SVF4\n}" } }, "vext8funct6_of_num": { "function": { "number": 0, "source": "vext8funct6_of_num arg# = $[complete] match arg# {\n 0 => VEXT8_ZVF8,\n _ => VEXT8_SVF8\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VEXT8_ZVF8,\n _ => VEXT8_SVF8\n}" } }, "vfnunary0_of_num": { "function": { "number": 0, "source": "vfnunary0_of_num arg# = $[complete] match arg# {\n 0 => FNV_CVT_XU_F,\n 1 => FNV_CVT_X_F,\n 2 => FNV_CVT_F_XU,\n 3 => FNV_CVT_F_X,\n 4 => FNV_CVT_F_F,\n 5 => FNV_CVT_ROD_F_F,\n 6 => FNV_CVT_RTZ_XU_F,\n _ => FNV_CVT_RTZ_X_F\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FNV_CVT_XU_F,\n 1 => FNV_CVT_X_F,\n 2 => FNV_CVT_F_XU,\n 3 => FNV_CVT_F_X,\n 4 => FNV_CVT_F_F,\n 5 => FNV_CVT_ROD_F_F,\n 6 => FNV_CVT_RTZ_XU_F,\n _ => FNV_CVT_RTZ_X_F\n}" } }, "vfunary0_of_num": { "function": { "number": 0, "source": "vfunary0_of_num arg# = $[complete] match arg# {\n 0 => FV_CVT_XU_F,\n 1 => FV_CVT_X_F,\n 2 => FV_CVT_F_XU,\n 3 => FV_CVT_F_X,\n 4 => FV_CVT_RTZ_XU_F,\n _ => FV_CVT_RTZ_X_F\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FV_CVT_XU_F,\n 1 => FV_CVT_X_F,\n 2 => FV_CVT_F_XU,\n 3 => FV_CVT_F_X,\n 4 => FV_CVT_RTZ_XU_F,\n _ => FV_CVT_RTZ_X_F\n}" } }, "vfunary1_of_num": { "function": { "number": 0, "source": "vfunary1_of_num arg# = $[complete] match arg# {\n 0 => FVV_VSQRT,\n 1 => FVV_VRSQRT7,\n 2 => FVV_VREC7,\n _ => FVV_VCLASS\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FVV_VSQRT,\n 1 => FVV_VRSQRT7,\n 2 => FVV_VREC7,\n _ => FVV_VCLASS\n}" } }, "vfwunary0_of_num": { "function": { "number": 0, "source": "vfwunary0_of_num arg# = $[complete] match arg# {\n 0 => FWV_CVT_XU_F,\n 1 => FWV_CVT_X_F,\n 2 => FWV_CVT_F_XU,\n 3 => FWV_CVT_F_X,\n 4 => FWV_CVT_F_F,\n 5 => FWV_CVT_RTZ_XU_F,\n _ => FWV_CVT_RTZ_X_F\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => FWV_CVT_XU_F,\n 1 => FWV_CVT_X_F,\n 2 => FWV_CVT_F_XU,\n 3 => FWV_CVT_F_X,\n 4 => FWV_CVT_F_F,\n 5 => FWV_CVT_RTZ_XU_F,\n _ => FWV_CVT_RTZ_X_F\n}" } }, "vicmpfunct6_of_num": { "function": { "number": 0, "source": "vicmpfunct6_of_num arg# = $[complete] match arg# {\n 0 => VICMP_VMSEQ,\n 1 => VICMP_VMSNE,\n 2 => VICMP_VMSLEU,\n 3 => VICMP_VMSLE,\n 4 => VICMP_VMSGTU,\n _ => VICMP_VMSGT\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VICMP_VMSEQ,\n 1 => VICMP_VMSNE,\n 2 => VICMP_VMSLEU,\n 3 => VICMP_VMSLE,\n 4 => VICMP_VMSGTU,\n _ => VICMP_VMSGT\n}" } }, "vifunct6_of_num": { "function": { "number": 0, "source": "vifunct6_of_num arg# = $[complete] match arg# {\n 0 => VI_VADD,\n 1 => VI_VRSUB,\n 2 => VI_VAND,\n 3 => VI_VOR,\n 4 => VI_VXOR,\n 5 => VI_VSADDU,\n 6 => VI_VSADD,\n 7 => VI_VSLL,\n 8 => VI_VSRL,\n 9 => VI_VSRA,\n 10 => VI_VSSRL,\n _ => VI_VSSRA\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VI_VADD,\n 1 => VI_VRSUB,\n 2 => VI_VAND,\n 3 => VI_VOR,\n 4 => VI_VXOR,\n 5 => VI_VSADDU,\n 6 => VI_VSADD,\n 7 => VI_VSLL,\n 8 => VI_VSRL,\n 9 => VI_VSRA,\n 10 => VI_VSSRL,\n _ => VI_VSSRA\n}" } }, "vimcfunct6_of_num": { "function": { "number": 0, "source": "vimcfunct6_of_num arg# = $[complete] match arg# {_ => VIMC_VMADC}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {_ => VIMC_VMADC}" } }, "vimfunct6_of_num": { "function": { "number": 0, "source": "vimfunct6_of_num arg# = $[complete] match arg# {_ => VIM_VMADC}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {_ => VIM_VMADC}" } }, "vimsfunct6_of_num": { "function": { "number": 0, "source": "vimsfunct6_of_num arg# = $[complete] match arg# {_ => VIMS_VADC}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {_ => VIMS_VADC}" } }, "visgfunct6_of_num": { "function": { "number": 0, "source": "visgfunct6_of_num arg# = $[complete] match arg# {\n 0 => VI_VSLIDEUP,\n 1 => VI_VSLIDEDOWN,\n _ => VI_VRGATHER\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VI_VSLIDEUP,\n 1 => VI_VSLIDEDOWN,\n _ => VI_VRGATHER\n}" } }, "vlewidth_of_num": { "function": { "number": 0, "source": "vlewidth_of_num arg# = $[complete] match arg# {\n 0 => VLE8,\n 1 => VLE16,\n 2 => VLE32,\n _ => VLE64\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VLE8,\n 1 => VLE16,\n 2 => VLE32,\n _ => VLE64\n}" } }, "vmlsop_of_num": { "function": { "number": 0, "source": "vmlsop_of_num arg# = $[complete] match arg# {\n 0 => VLM,\n _ => VSM\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VLM,\n _ => VSM\n}" } }, "vpn_j_of_va": { "function": { "number": 0, "source": "function vpn_j_of_va(sv_params : SV_Params,\n va : bits(64),\n level : PTW_Level) -> bits(64) = {\n let lsb : range(0,63) = pagesize_bits + level * sv_params.vpn_size_bits;\n assert (lsb < sizeof(xlen));\n let mask : bits(64) = zero_extend(ones(sv_params.vpn_size_bits));\n ((va >> lsb) & mask)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "va" }, { "type": "id", "id": "level" } ] }, "body": " let lsb : range(0,63) = pagesize_bits + level * sv_params.vpn_size_bits;\n assert (lsb < sizeof(xlen));\n let mask : bits(64) = zero_extend(ones(sv_params.vpn_size_bits));\n ((va >> lsb) & mask)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 2195, 2206 ] }, { "type": "function", "id": "ones", "file": "model/riscv_vmem.sail", "loc": [ 2207, 2211 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] } ] }, "vpns_of_va": { "function": { "number": 0, "source": "function vpns_of_va(sv_params : SV_Params,\n va : bits(64)) -> bits(64) = {\n let mask : bits(64) = zero_extend(ones(sv_params.va_size_bits));\n (va & mask) >> pagesize_bits\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "sv_params" }, { "type": "id", "id": "va" } ] }, "body": " let mask : bits(64) = zero_extend(ones(sv_params.va_size_bits));\n (va & mask) >> pagesize_bits" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_vmem.sail", "loc": [ 1800, 1811 ] }, { "type": "function", "id": "ones", "file": "model/riscv_vmem.sail", "loc": [ 1812, 1816 ] }, { "type": "function", "id": "shiftr", "file": "model/prelude.sail", "loc": [ 6337, 6343 ] } ] }, "vsetop_of_num": { "function": { "number": 0, "source": "vsetop_of_num arg# = $[complete] match arg# {\n 0 => VSETVLI,\n _ => VSETVL\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VSETVLI,\n _ => VSETVL\n}" } }, "vvcmpfunct6_of_num": { "function": { "number": 0, "source": "vvcmpfunct6_of_num arg# = $[complete] match arg# {\n 0 => VVCMP_VMSEQ,\n 1 => VVCMP_VMSNE,\n 2 => VVCMP_VMSLTU,\n 3 => VVCMP_VMSLT,\n 4 => VVCMP_VMSLEU,\n _ => VVCMP_VMSLE\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VVCMP_VMSEQ,\n 1 => VVCMP_VMSNE,\n 2 => VVCMP_VMSLTU,\n 3 => VVCMP_VMSLT,\n 4 => VVCMP_VMSLEU,\n _ => VVCMP_VMSLE\n}" } }, "vvfunct6_of_num": { "function": { "number": 0, "source": "vvfunct6_of_num arg# = $[complete] match arg# {\n 0 => VV_VADD,\n 1 => VV_VSUB,\n 2 => VV_VMINU,\n 3 => VV_VMIN,\n 4 => VV_VMAXU,\n 5 => VV_VMAX,\n 6 => VV_VAND,\n 7 => VV_VOR,\n 8 => VV_VXOR,\n 9 => VV_VRGATHER,\n 10 => VV_VRGATHEREI16,\n 11 => VV_VSADDU,\n 12 => VV_VSADD,\n 13 => VV_VSSUBU,\n 14 => VV_VSSUB,\n 15 => VV_VSLL,\n 16 => VV_VSMUL,\n 17 => VV_VSRL,\n 18 => VV_VSRA,\n 19 => VV_VSSRL,\n _ => VV_VSSRA\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VV_VADD,\n 1 => VV_VSUB,\n 2 => VV_VMINU,\n 3 => VV_VMIN,\n 4 => VV_VMAXU,\n 5 => VV_VMAX,\n 6 => VV_VAND,\n 7 => VV_VOR,\n 8 => VV_VXOR,\n 9 => VV_VRGATHER,\n 10 => VV_VRGATHEREI16,\n 11 => VV_VSADDU,\n 12 => VV_VSADD,\n 13 => VV_VSSUBU,\n 14 => VV_VSSUB,\n 15 => VV_VSLL,\n 16 => VV_VSMUL,\n 17 => VV_VSRL,\n 18 => VV_VSRA,\n 19 => VV_VSSRL,\n _ => VV_VSSRA\n}" } }, "vvmcfunct6_of_num": { "function": { "number": 0, "source": "vvmcfunct6_of_num arg# = $[complete] match arg# {\n 0 => VVMC_VMADC,\n _ => VVMC_VMSBC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VVMC_VMADC,\n _ => VVMC_VMSBC\n}" } }, "vvmfunct6_of_num": { "function": { "number": 0, "source": "vvmfunct6_of_num arg# = $[complete] match arg# {\n 0 => VVM_VMADC,\n _ => VVM_VMSBC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VVM_VMADC,\n _ => VVM_VMSBC\n}" } }, "vvmsfunct6_of_num": { "function": { "number": 0, "source": "vvmsfunct6_of_num arg# = $[complete] match arg# {\n 0 => VVMS_VADC,\n _ => VVMS_VSBC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VVMS_VADC,\n _ => VVMS_VSBC\n}" } }, "vxcmpfunct6_of_num": { "function": { "number": 0, "source": "vxcmpfunct6_of_num arg# = $[complete] match arg# {\n 0 => VXCMP_VMSEQ,\n 1 => VXCMP_VMSNE,\n 2 => VXCMP_VMSLTU,\n 3 => VXCMP_VMSLT,\n 4 => VXCMP_VMSLEU,\n 5 => VXCMP_VMSLE,\n 6 => VXCMP_VMSGTU,\n _ => VXCMP_VMSGT\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VXCMP_VMSEQ,\n 1 => VXCMP_VMSNE,\n 2 => VXCMP_VMSLTU,\n 3 => VXCMP_VMSLT,\n 4 => VXCMP_VMSLEU,\n 5 => VXCMP_VMSLE,\n 6 => VXCMP_VMSGTU,\n _ => VXCMP_VMSGT\n}" } }, "vxfunct6_of_num": { "function": { "number": 0, "source": "vxfunct6_of_num arg# = $[complete] match arg# {\n 0 => VX_VADD,\n 1 => VX_VSUB,\n 2 => VX_VRSUB,\n 3 => VX_VMINU,\n 4 => VX_VMIN,\n 5 => VX_VMAXU,\n 6 => VX_VMAX,\n 7 => VX_VAND,\n 8 => VX_VOR,\n 9 => VX_VXOR,\n 10 => VX_VSADDU,\n 11 => VX_VSADD,\n 12 => VX_VSSUBU,\n 13 => VX_VSSUB,\n 14 => VX_VSLL,\n 15 => VX_VSMUL,\n 16 => VX_VSRL,\n 17 => VX_VSRA,\n 18 => VX_VSSRL,\n _ => VX_VSSRA\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VX_VADD,\n 1 => VX_VSUB,\n 2 => VX_VRSUB,\n 3 => VX_VMINU,\n 4 => VX_VMIN,\n 5 => VX_VMAXU,\n 6 => VX_VMAX,\n 7 => VX_VAND,\n 8 => VX_VOR,\n 9 => VX_VXOR,\n 10 => VX_VSADDU,\n 11 => VX_VSADD,\n 12 => VX_VSSUBU,\n 13 => VX_VSSUB,\n 14 => VX_VSLL,\n 15 => VX_VSMUL,\n 16 => VX_VSRL,\n 17 => VX_VSRA,\n 18 => VX_VSSRL,\n _ => VX_VSSRA\n}" } }, "vxmcfunct6_of_num": { "function": { "number": 0, "source": "vxmcfunct6_of_num arg# = $[complete] match arg# {\n 0 => VXMC_VMADC,\n _ => VXMC_VMSBC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VXMC_VMADC,\n _ => VXMC_VMSBC\n}" } }, "vxmfunct6_of_num": { "function": { "number": 0, "source": "vxmfunct6_of_num arg# = $[complete] match arg# {\n 0 => VXM_VMADC,\n _ => VXM_VMSBC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VXM_VMADC,\n _ => VXM_VMSBC\n}" } }, "vxmsfunct6_of_num": { "function": { "number": 0, "source": "vxmsfunct6_of_num arg# = $[complete] match arg# {\n 0 => VXMS_VADC,\n _ => VXMS_VSBC\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VXMS_VADC,\n _ => VXMS_VSBC\n}" } }, "vxsgfunct6_of_num": { "function": { "number": 0, "source": "vxsgfunct6_of_num arg# = $[complete] match arg# {\n 0 => VX_VSLIDEUP,\n 1 => VX_VSLIDEDOWN,\n _ => VX_VRGATHER\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => VX_VSLIDEUP,\n 1 => VX_VSLIDEDOWN,\n _ => VX_VRGATHER\n}" } }, "wF": { "function": { "number": 0, "source": "function wF (r, in_v) = {\n assert(sys_enable_fdext());\n let v = fregval_into_freg(in_v);\n match r {\n 0 => f0 = v,\n 1 => f1 = v,\n 2 => f2 = v,\n 3 => f3 = v,\n 4 => f4 = v,\n 5 => f5 = v,\n 6 => f6 = v,\n 7 => f7 = v,\n 8 => f8 = v,\n 9 => f9 = v,\n 10 => f10 = v,\n 11 => f11 = v,\n 12 => f12 = v,\n 13 => f13 = v,\n 14 => f14 = v,\n 15 => f15 = v,\n 16 => f16 = v,\n 17 => f17 = v,\n 18 => f18 = v,\n 19 => f19 = v,\n 20 => f20 = v,\n 21 => f21 = v,\n 22 => f22 = v,\n 23 => f23 = v,\n 24 => f24 = v,\n 25 => f25 = v,\n 26 => f26 = v,\n 27 => f27 = v,\n 28 => f28 = v,\n 29 => f29 = v,\n 30 => f30 = v,\n 31 => f31 = v,\n _ => assert(false, \"invalid floating point register number\")\n };\n\n dirty_fd_context();\n\n if get_config_print_reg()\n then\n /* TODO: will only print bits; should we print in floating point format? */\n print_reg(\"f\" ^ dec_str(r) ^ \" <- \" ^ FRegStr(v));\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "r" }, { "type": "id", "id": "in_v" } ] }, "body": "function wF (r, in_v) = {\n assert(sys_enable_fdext());\n let v = fregval_into_freg(in_v);\n match r {\n 0 => f0 = v,\n 1 => f1 = v,\n 2 => f2 = v,\n 3 => f3 = v,\n 4 => f4 = v,\n 5 => f5 = v,\n 6 => f6 = v,\n 7 => f7 = v,\n 8 => f8 = v,\n 9 => f9 = v,\n 10 => f10 = v,\n 11 => f11 = v,\n 12 => f12 = v,\n 13 => f13 = v,\n 14 => f14 = v,\n 15 => f15 = v,\n 16 => f16 = v,\n 17 => f17 = v,\n 18 => f18 = v,\n 19 => f19 = v,\n 20 => f20 = v,\n 21 => f21 = v,\n 22 => f22 = v,\n 23 => f23 = v,\n 24 => f24 = v,\n 25 => f25 = v,\n 26 => f26 = v,\n 27 => f27 = v,\n 28 => f28 = v,\n 29 => f29 = v,\n 30 => f30 = v,\n 31 => f31 = v,\n _ => assert(false, \"invalid floating point register number\")\n };\n\n dirty_fd_context();\n\n if get_config_print_reg()\n then\n /* TODO: will only print bits; should we print in floating point format? */\n print_reg(\"f\" ^ dec_str(r) ^ \" <- \" ^ FRegStr(v));" }, "links": [ { "type": "function", "id": "fregval_into_freg", "file": "model/riscv_fdext_regs.sail", "loc": [ 4964, 4981 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_fdext_regs.sail", "loc": [ 5701, 5721 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_fdext_regs.sail", "loc": [ 5819, 5828 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "FRegStr", "file": "model/riscv_fdext_regs.sail", "loc": [ 5857, 5864 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_fdext_regs.sail", "loc": [ 5835, 5842 ] }, { "type": "function", "id": "dirty_fd_context", "file": "model/riscv_fdext_regs.sail", "loc": [ 5673, 5689 ] }, { "type": "register", "id": "f31", "file": "model/riscv_fdext_regs.sail", "loc": [ 5590, 5593 ] }, { "type": "register", "id": "f30", "file": "model/riscv_fdext_regs.sail", "loc": [ 5571, 5574 ] }, { "type": "register", "id": "f29", "file": "model/riscv_fdext_regs.sail", "loc": [ 5552, 5555 ] }, { "type": "register", "id": "f28", "file": "model/riscv_fdext_regs.sail", "loc": [ 5533, 5536 ] }, { "type": "register", "id": "f27", "file": "model/riscv_fdext_regs.sail", "loc": [ 5514, 5517 ] }, { "type": "register", "id": "f26", "file": "model/riscv_fdext_regs.sail", "loc": [ 5495, 5498 ] }, { "type": "register", "id": "f25", "file": "model/riscv_fdext_regs.sail", "loc": [ 5476, 5479 ] }, { "type": "register", "id": "f24", "file": "model/riscv_fdext_regs.sail", "loc": [ 5457, 5460 ] }, { "type": "register", "id": "f23", "file": "model/riscv_fdext_regs.sail", "loc": [ 5438, 5441 ] }, { "type": "register", "id": "f22", "file": "model/riscv_fdext_regs.sail", "loc": [ 5419, 5422 ] }, { "type": "register", "id": "f21", "file": "model/riscv_fdext_regs.sail", "loc": [ 5400, 5403 ] }, { "type": "register", "id": "f20", "file": "model/riscv_fdext_regs.sail", "loc": [ 5381, 5384 ] }, { "type": "register", "id": "f19", "file": "model/riscv_fdext_regs.sail", "loc": [ 5362, 5365 ] }, { "type": "register", "id": "f18", "file": "model/riscv_fdext_regs.sail", "loc": [ 5343, 5346 ] }, { "type": "register", "id": "f17", "file": "model/riscv_fdext_regs.sail", "loc": [ 5324, 5327 ] }, { "type": "register", "id": "f16", "file": "model/riscv_fdext_regs.sail", "loc": [ 5305, 5308 ] }, { "type": "register", "id": "f15", "file": "model/riscv_fdext_regs.sail", "loc": [ 5286, 5289 ] }, { "type": "register", "id": "f14", "file": "model/riscv_fdext_regs.sail", "loc": [ 5267, 5270 ] }, { "type": "register", "id": "f13", "file": "model/riscv_fdext_regs.sail", "loc": [ 5248, 5251 ] }, { "type": "register", "id": "f12", "file": "model/riscv_fdext_regs.sail", "loc": [ 5229, 5232 ] }, { "type": "register", "id": "f11", "file": "model/riscv_fdext_regs.sail", "loc": [ 5210, 5213 ] }, { "type": "register", "id": "f10", "file": "model/riscv_fdext_regs.sail", "loc": [ 5191, 5194 ] }, { "type": "register", "id": "f9", "file": "model/riscv_fdext_regs.sail", "loc": [ 5173, 5175 ] }, { "type": "register", "id": "f8", "file": "model/riscv_fdext_regs.sail", "loc": [ 5155, 5157 ] }, { "type": "register", "id": "f7", "file": "model/riscv_fdext_regs.sail", "loc": [ 5137, 5139 ] }, { "type": "register", "id": "f6", "file": "model/riscv_fdext_regs.sail", "loc": [ 5119, 5121 ] }, { "type": "register", "id": "f5", "file": "model/riscv_fdext_regs.sail", "loc": [ 5101, 5103 ] }, { "type": "register", "id": "f4", "file": "model/riscv_fdext_regs.sail", "loc": [ 5083, 5085 ] }, { "type": "register", "id": "f3", "file": "model/riscv_fdext_regs.sail", "loc": [ 5065, 5067 ] }, { "type": "register", "id": "f2", "file": "model/riscv_fdext_regs.sail", "loc": [ 5047, 5049 ] }, { "type": "register", "id": "f1", "file": "model/riscv_fdext_regs.sail", "loc": [ 5029, 5031 ] }, { "type": "register", "id": "f0", "file": "model/riscv_fdext_regs.sail", "loc": [ 5011, 5013 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 4933, 4949 ] } ] }, "wF_D": { "function": { "number": 0, "source": "function wF_D(i, data) = {\n assert(sizeof(flen) >= 64);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n F(i) = data\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": "function wF_D(i, data) = {\n assert(sizeof(flen) >= 64);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n F(i)" }, "links": [ { "type": "function", "id": "wF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6041, 6048 ] }, { "type": "function", "id": "not", "file": "model/riscv_fdext_regs.sail", "loc": [ 7007, 7010 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 7011, 7027 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 6986, 7002 ] } ] }, "wF_H": { "function": { "number": 0, "source": "function wF_H(i, data) = {\n assert(sizeof(flen) >= 16);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n F(i) = nan_box(data)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": "function wF_H(i, data) = {\n assert(sizeof(flen) >= 16);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n F(i)" }, "links": [ { "type": "function", "id": "wF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6041, 6048 ] }, { "type": "function", "id": "nan_box_H", "file": "model/riscv_fdext_regs.sail", "loc": [ 2782, 2791 ] }, { "type": "function", "id": "not", "file": "model/riscv_fdext_regs.sail", "loc": [ 6344, 6347 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 6348, 6364 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 6323, 6339 ] } ] }, "wF_S": { "function": { "number": 0, "source": "function wF_S(i, data) = {\n assert(sizeof(flen) >= 32);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n F(i) = nan_box(data)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": "function wF_S(i, data) = {\n assert(sizeof(flen) >= 32);\n assert(sys_enable_fdext() & not(sys_enable_zfinx()));\n F(i)" }, "links": [ { "type": "function", "id": "wF_bits", "file": "model/riscv_fdext_regs.sail", "loc": [ 6041, 6048 ] }, { "type": "function", "id": "nan_box_S", "file": "model/riscv_fdext_regs.sail", "loc": [ 2793, 2802 ] }, { "type": "function", "id": "not", "file": "model/riscv_fdext_regs.sail", "loc": [ 6681, 6684 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 6685, 6701 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 6660, 6676 ] } ] }, "wF_bits": { "function": { "number": 0, "source": "function wF_bits(i: bits(5), data: flenbits) -> unit = {\n wF(unsigned(i)) = data\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": " wF(unsigned(i))" }, "links": [ { "type": "function", "id": "wF", "file": "model/riscv_fdext_regs.sail", "loc": [ 5992, 5994 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_fdext_regs.sail", "loc": [ 5995, 6003 ] } ] }, "wF_or_X_D": { "function": { "number": 0, "source": "function wF_or_X_D(i, data) = {\n assert (sizeof(flen) >= 64);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_D(i) = data\n else if sizeof(xlen) >= 64\n then X(i) = sign_extend(data)\n else {\n assert (i[0] == bitzero);\n if i != zeros() then {\n X(i) = data[31..0];\n X(i + 1) = data[63..32];\n }\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": "function wF_or_X_D(i, data) = {\n assert (sizeof(flen) >= 64);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_D(i) = data\n else if sizeof(xlen) >= 64\n then X(i) = sign_extend(data)\n else {\n assert (i[0] == bitzero);\n if i != zeros() then {\n X(i) = data[31..0];\n X(i + 1) = data[63..32];\n }\n }" }, "links": [ { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 8530, 8546 ] }, { "type": "function", "id": "wF_D", "file": "model/riscv_fdext_regs.sail", "loc": [ 7133, 7137 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_fdext_regs.sail", "loc": [ 8613, 8624 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 8502, 8518 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 8480, 8496 ] } ] }, "wF_or_X_H": { "function": { "number": 0, "source": "function wF_or_X_H(i, data) = {\n assert(sizeof(flen) >= 16);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_H(i) = data\n else X(i) = sign_extend(data)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": "function wF_or_X_H(i, data) = {\n assert(sizeof(flen) >= 16);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_H(i) = data\n else X(i) = sign_extend(data)" }, "links": [ { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 8049, 8065 ] }, { "type": "function", "id": "wF_H", "file": "model/riscv_fdext_regs.sail", "loc": [ 7073, 7077 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_fdext_regs.sail", "loc": [ 8103, 8114 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 8021, 8037 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 7999, 8015 ] } ] }, "wF_or_X_S": { "function": { "number": 0, "source": "function wF_or_X_S(i, data) = {\n assert(sizeof(flen) >= 32);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_S(i) = data\n else X(i) = sign_extend(data)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": "function wF_or_X_S(i, data) = {\n assert(sizeof(flen) >= 32);\n assert(sys_enable_fdext() != sys_enable_zfinx());\n if sys_enable_fdext()\n then F_S(i) = data\n else X(i) = sign_extend(data)" }, "links": [ { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 8289, 8305 ] }, { "type": "function", "id": "wF_S", "file": "model/riscv_fdext_regs.sail", "loc": [ 7103, 7107 ] }, { "type": "function", "id": "wX_bits", "file": "model/riscv_regs.sail", "loc": [ 3761, 3768 ] }, { "type": "function", "id": "sign_extend", "file": "model/riscv_fdext_regs.sail", "loc": [ 8343, 8354 ] }, { "type": "function", "id": "sys_enable_zfinx", "file": "model/riscv_fdext_regs.sail", "loc": [ 8261, 8277 ] }, { "type": "function", "id": "sys_enable_fdext", "file": "model/riscv_fdext_regs.sail", "loc": [ 8239, 8255 ] } ] }, "wV": { "function": { "number": 0, "source": "function wV (r, in_v) = {\n let v = in_v;\n match r {\n 0 => vr0 = v,\n 1 => vr1 = v,\n 2 => vr2 = v,\n 3 => vr3 = v,\n 4 => vr4 = v,\n 5 => vr5 = v,\n 6 => vr6 = v,\n 7 => vr7 = v,\n 8 => vr8 = v,\n 9 => vr9 = v,\n 10 => vr10 = v,\n 11 => vr11 = v,\n 12 => vr12 = v,\n 13 => vr13 = v,\n 14 => vr14 = v,\n 15 => vr15 = v,\n 16 => vr16 = v,\n 17 => vr17 = v,\n 18 => vr18 = v,\n 19 => vr19 = v,\n 20 => vr20 = v,\n 21 => vr21 = v,\n 22 => vr22 = v,\n 23 => vr23 = v,\n 24 => vr24 = v,\n 25 => vr25 = v,\n 26 => vr26 = v,\n 27 => vr27 = v,\n 28 => vr28 = v,\n 29 => vr29 = v,\n 30 => vr30 = v,\n 31 => vr31 = v,\n _ => assert(false, \"invalid vector register number\")\n };\n\n dirty_v_context();\n\n let VLEN = unsigned(vlenb) * 8;\n assert(0 < VLEN & VLEN <= sizeof(vlenmax));\n if get_config_print_reg()\n then print_reg(\"v\" ^ dec_str(r) ^ \" <- \" ^ BitStr(v[VLEN - 1 .. 0]));\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "r" }, { "type": "id", "id": "in_v" } ] }, "body": " let v = in_v;\n match r {\n 0 => vr0 = v,\n 1 => vr1 = v,\n 2 => vr2 = v,\n 3 => vr3 = v,\n 4 => vr4 = v,\n 5 => vr5 = v,\n 6 => vr6 = v,\n 7 => vr7 = v,\n 8 => vr8 = v,\n 9 => vr9 = v,\n 10 => vr10 = v,\n 11 => vr11 = v,\n 12 => vr12 = v,\n 13 => vr13 = v,\n 14 => vr14 = v,\n 15 => vr15 = v,\n 16 => vr16 = v,\n 17 => vr17 = v,\n 18 => vr18 = v,\n 19 => vr19 = v,\n 20 => vr20 = v,\n 21 => vr21 = v,\n 22 => vr22 = v,\n 23 => vr23 = v,\n 24 => vr24 = v,\n 25 => vr25 = v,\n 26 => vr26 = v,\n 27 => vr27 = v,\n 28 => vr28 = v,\n 29 => vr29 = v,\n 30 => vr30 = v,\n 31 => vr31 = v,\n _ => assert(false, \"invalid vector register number\")\n };\n\n dirty_v_context();\n\n let VLEN = unsigned(vlenb) * 8;\n assert(0 < VLEN & VLEN <= sizeof(vlenmax));\n if get_config_print_reg()\n then print_reg(\"v\" ^ dec_str(r) ^ \" <- \" ^ BitStr(v[VLEN - 1 .. 0]));" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 4104, 4112 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 4113, 4118 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_vext_regs.sail", "loc": [ 4178, 4198 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_vext_regs.sail", "loc": [ 4208, 4217 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_vext_regs.sail", "loc": [ 4224, 4231 ] }, { "type": "function", "id": "dirty_v_context", "file": "model/riscv_vext_regs.sail", "loc": [ 4071, 4086 ] }, { "type": "register", "id": "vr31", "file": "model/riscv_vext_regs.sail", "loc": [ 3996, 4000 ] }, { "type": "register", "id": "vr30", "file": "model/riscv_vext_regs.sail", "loc": [ 3976, 3980 ] }, { "type": "register", "id": "vr29", "file": "model/riscv_vext_regs.sail", "loc": [ 3956, 3960 ] }, { "type": "register", "id": "vr28", "file": "model/riscv_vext_regs.sail", "loc": [ 3936, 3940 ] }, { "type": "register", "id": "vr27", "file": "model/riscv_vext_regs.sail", "loc": [ 3916, 3920 ] }, { "type": "register", "id": "vr26", "file": "model/riscv_vext_regs.sail", "loc": [ 3896, 3900 ] }, { "type": "register", "id": "vr25", "file": "model/riscv_vext_regs.sail", "loc": [ 3876, 3880 ] }, { "type": "register", "id": "vr24", "file": "model/riscv_vext_regs.sail", "loc": [ 3856, 3860 ] }, { "type": "register", "id": "vr23", "file": "model/riscv_vext_regs.sail", "loc": [ 3836, 3840 ] }, { "type": "register", "id": "vr22", "file": "model/riscv_vext_regs.sail", "loc": [ 3816, 3820 ] }, { "type": "register", "id": "vr21", "file": "model/riscv_vext_regs.sail", "loc": [ 3796, 3800 ] }, { "type": "register", "id": "vr20", "file": "model/riscv_vext_regs.sail", "loc": [ 3776, 3780 ] }, { "type": "register", "id": "vr19", "file": "model/riscv_vext_regs.sail", "loc": [ 3756, 3760 ] }, { "type": "register", "id": "vr18", "file": "model/riscv_vext_regs.sail", "loc": [ 3736, 3740 ] }, { "type": "register", "id": "vr17", "file": "model/riscv_vext_regs.sail", "loc": [ 3716, 3720 ] }, { "type": "register", "id": "vr16", "file": "model/riscv_vext_regs.sail", "loc": [ 3696, 3700 ] }, { "type": "register", "id": "vr15", "file": "model/riscv_vext_regs.sail", "loc": [ 3676, 3680 ] }, { "type": "register", "id": "vr14", "file": "model/riscv_vext_regs.sail", "loc": [ 3656, 3660 ] }, { "type": "register", "id": "vr13", "file": "model/riscv_vext_regs.sail", "loc": [ 3636, 3640 ] }, { "type": "register", "id": "vr12", "file": "model/riscv_vext_regs.sail", "loc": [ 3616, 3620 ] }, { "type": "register", "id": "vr11", "file": "model/riscv_vext_regs.sail", "loc": [ 3596, 3600 ] }, { "type": "register", "id": "vr10", "file": "model/riscv_vext_regs.sail", "loc": [ 3576, 3580 ] }, { "type": "register", "id": "vr9", "file": "model/riscv_vext_regs.sail", "loc": [ 3557, 3560 ] }, { "type": "register", "id": "vr8", "file": "model/riscv_vext_regs.sail", "loc": [ 3539, 3542 ] }, { "type": "register", "id": "vr7", "file": "model/riscv_vext_regs.sail", "loc": [ 3521, 3524 ] }, { "type": "register", "id": "vr6", "file": "model/riscv_vext_regs.sail", "loc": [ 3503, 3506 ] }, { "type": "register", "id": "vr5", "file": "model/riscv_vext_regs.sail", "loc": [ 3485, 3488 ] }, { "type": "register", "id": "vr4", "file": "model/riscv_vext_regs.sail", "loc": [ 3467, 3470 ] }, { "type": "register", "id": "vr3", "file": "model/riscv_vext_regs.sail", "loc": [ 3449, 3452 ] }, { "type": "register", "id": "vr2", "file": "model/riscv_vext_regs.sail", "loc": [ 3431, 3434 ] }, { "type": "register", "id": "vr1", "file": "model/riscv_vext_regs.sail", "loc": [ 3413, 3416 ] }, { "type": "register", "id": "vr0", "file": "model/riscv_vext_regs.sail", "loc": [ 3395, 3398 ] } ] }, "wV_bits": { "function": { "number": 0, "source": "function wV_bits(i: bits(5), data: vregtype) -> unit = {\n wV(unsigned(i)) = data\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": " wV(unsigned(i))" }, "links": [ { "type": "function", "id": "wV", "file": "model/riscv_vext_regs.sail", "loc": [ 4395, 4397 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 4398, 4406 ] } ] }, "wX": { "function": { "number": 0, "source": "function wX (r, in_v) = {\n let v = regval_into_reg(in_v);\n match r {\n 0 => (),\n 1 => x1 = v,\n 2 => x2 = v,\n 3 => x3 = v,\n 4 => x4 = v,\n 5 => x5 = v,\n 6 => x6 = v,\n 7 => x7 = v,\n 8 => x8 = v,\n 9 => x9 = v,\n 10 => x10 = v,\n 11 => x11 = v,\n 12 => x12 = v,\n 13 => x13 = v,\n 14 => x14 = v,\n 15 => x15 = v,\n 16 => x16 = v,\n 17 => x17 = v,\n 18 => x18 = v,\n 19 => x19 = v,\n 20 => x20 = v,\n 21 => x21 = v,\n 22 => x22 = v,\n 23 => x23 = v,\n 24 => x24 = v,\n 25 => x25 = v,\n 26 => x26 = v,\n 27 => x27 = v,\n 28 => x28 = v,\n 29 => x29 = v,\n 30 => x30 = v,\n 31 => x31 = v,\n _ => assert(false, \"invalid register number\")\n };\n if (r != 0) then {\n rvfi_wX(r, in_v);\n if get_config_print_reg()\n then print_reg(\"x\" ^ dec_str(r) ^ \" <- \" ^ RegStr(v));\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "r" }, { "type": "id", "id": "in_v" } ] }, "body": " let v = regval_into_reg(in_v);\n match r {\n 0 => (),\n 1 => x1 = v,\n 2 => x2 = v,\n 3 => x3 = v,\n 4 => x4 = v,\n 5 => x5 = v,\n 6 => x6 = v,\n 7 => x7 = v,\n 8 => x8 = v,\n 9 => x9 = v,\n 10 => x10 = v,\n 11 => x11 = v,\n 12 => x12 = v,\n 13 => x13 = v,\n 14 => x14 = v,\n 15 => x15 = v,\n 16 => x16 = v,\n 17 => x17 = v,\n 18 => x18 = v,\n 19 => x19 = v,\n 20 => x20 = v,\n 21 => x21 = v,\n 22 => x22 = v,\n 23 => x23 = v,\n 24 => x24 = v,\n 25 => x25 = v,\n 26 => x26 = v,\n 27 => x27 = v,\n 28 => x28 = v,\n 29 => x29 = v,\n 30 => x30 = v,\n 31 => x31 = v,\n _ => assert(false, \"invalid register number\")\n };\n if (r != 0) then {\n rvfi_wX(r, in_v);\n if get_config_print_reg()\n then print_reg(\"x\" ^ dec_str(r) ^ \" <- \" ^ RegStr(v));\n }" }, "links": [ { "type": "function", "id": "regval_into_reg", "file": "model/riscv_regs.sail", "loc": [ 2764, 2779 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_regs.sail", "loc": [ 3503, 3523 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_regs.sail", "loc": [ 3536, 3545 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "RegStr", "file": "model/riscv_regs.sail", "loc": [ 3574, 3580 ] }, { "type": "function", "id": "dec_str", "file": "model/riscv_regs.sail", "loc": [ 3552, 3559 ] }, { "type": "function", "id": "rvfi_wX", "file": "model/riscv_regs.sail", "loc": [ 3475, 3482 ] }, { "type": "register", "id": "x31", "file": "model/riscv_regs.sail", "loc": [ 3384, 3387 ] }, { "type": "register", "id": "x30", "file": "model/riscv_regs.sail", "loc": [ 3365, 3368 ] }, { "type": "register", "id": "x29", "file": "model/riscv_regs.sail", "loc": [ 3346, 3349 ] }, { "type": "register", "id": "x28", "file": "model/riscv_regs.sail", "loc": [ 3327, 3330 ] }, { "type": "register", "id": "x27", "file": "model/riscv_regs.sail", "loc": [ 3308, 3311 ] }, { "type": "register", "id": "x26", "file": "model/riscv_regs.sail", "loc": [ 3289, 3292 ] }, { "type": "register", "id": "x25", "file": "model/riscv_regs.sail", "loc": [ 3270, 3273 ] }, { "type": "register", "id": "x24", "file": "model/riscv_regs.sail", "loc": [ 3251, 3254 ] }, { "type": "register", "id": "x23", "file": "model/riscv_regs.sail", "loc": [ 3232, 3235 ] }, { "type": "register", "id": "x22", "file": "model/riscv_regs.sail", "loc": [ 3213, 3216 ] }, { "type": "register", "id": "x21", "file": "model/riscv_regs.sail", "loc": [ 3194, 3197 ] }, { "type": "register", "id": "x20", "file": "model/riscv_regs.sail", "loc": [ 3175, 3178 ] }, { "type": "register", "id": "x19", "file": "model/riscv_regs.sail", "loc": [ 3156, 3159 ] }, { "type": "register", "id": "x18", "file": "model/riscv_regs.sail", "loc": [ 3137, 3140 ] }, { "type": "register", "id": "x17", "file": "model/riscv_regs.sail", "loc": [ 3118, 3121 ] }, { "type": "register", "id": "x16", "file": "model/riscv_regs.sail", "loc": [ 3099, 3102 ] }, { "type": "register", "id": "x15", "file": "model/riscv_regs.sail", "loc": [ 3080, 3083 ] }, { "type": "register", "id": "x14", "file": "model/riscv_regs.sail", "loc": [ 3061, 3064 ] }, { "type": "register", "id": "x13", "file": "model/riscv_regs.sail", "loc": [ 3042, 3045 ] }, { "type": "register", "id": "x12", "file": "model/riscv_regs.sail", "loc": [ 3023, 3026 ] }, { "type": "register", "id": "x11", "file": "model/riscv_regs.sail", "loc": [ 3004, 3007 ] }, { "type": "register", "id": "x10", "file": "model/riscv_regs.sail", "loc": [ 2985, 2988 ] }, { "type": "register", "id": "x9", "file": "model/riscv_regs.sail", "loc": [ 2967, 2969 ] }, { "type": "register", "id": "x8", "file": "model/riscv_regs.sail", "loc": [ 2949, 2951 ] }, { "type": "register", "id": "x7", "file": "model/riscv_regs.sail", "loc": [ 2931, 2933 ] }, { "type": "register", "id": "x6", "file": "model/riscv_regs.sail", "loc": [ 2913, 2915 ] }, { "type": "register", "id": "x5", "file": "model/riscv_regs.sail", "loc": [ 2895, 2897 ] }, { "type": "register", "id": "x4", "file": "model/riscv_regs.sail", "loc": [ 2877, 2879 ] }, { "type": "register", "id": "x3", "file": "model/riscv_regs.sail", "loc": [ 2859, 2861 ] }, { "type": "register", "id": "x2", "file": "model/riscv_regs.sail", "loc": [ 2841, 2843 ] }, { "type": "register", "id": "x1", "file": "model/riscv_regs.sail", "loc": [ 2823, 2825 ] } ] }, "wX_bits": { "function": { "number": 0, "source": "function wX_bits(i: bits(5), data: xlenbits) -> unit = {\n wX(unsigned(i)) = data\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "data" } ] }, "body": " wX(unsigned(i))" }, "links": [ { "type": "function", "id": "wX", "file": "model/riscv_regs.sail", "loc": [ 3712, 3714 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_regs.sail", "loc": [ 3715, 3723 ] } ] }, "within_clint": { "function": { "number": 0, "source": "function within_clint forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : int('n)) -> bool = {\n /* To avoid overflow issues when physical memory extends to the end\n * of the addressable range, we need to perform address bound checks\n * on unsigned unbounded integers.\n */\n let addr_int = unsigned(addr);\n let clint_base_int = unsigned(plat_clint_base ());\n let clint_size_int = unsigned(plat_clint_size ());\n clint_base_int <= addr_int\n & (addr_int + sizeof('n)) <= (clint_base_int + clint_size_int)\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": " let addr_int = unsigned(addr);\n let clint_base_int = unsigned(plat_clint_base ());\n let clint_size_int = unsigned(plat_clint_size ());\n clint_base_int <= addr_int\n & (addr_int + sizeof('n)) <= (clint_base_int + clint_size_int)" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 5571, 5579 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 5610, 5618 ] }, { "type": "function", "id": "plat_clint_base", "file": "model/riscv_platform.sail", "loc": [ 5619, 5634 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 5663, 5671 ] }, { "type": "function", "id": "plat_clint_size", "file": "model/riscv_platform.sail", "loc": [ 5672, 5687 ] } ] }, "within_htif_readable": { "function": { "number": 0, "source": "function within_htif_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : int('n)) -> bool =\n plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": "plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4)" }, "links": [ { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 6132, 6148 ] }, { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 6102, 6118 ] } ] }, "within_htif_writable": { "function": { "number": 0, "source": "function within_htif_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : int('n)) -> bool =\n plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": "plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4)" }, "links": [ { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 5939, 5955 ] }, { "type": "function", "id": "plat_htif_tohost", "file": "model/riscv_platform.sail", "loc": [ 5909, 5925 ] } ] }, "within_mmio_readable": { "function": { "number": 0, "source": "function within_mmio_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : int('n)) -> bool =\n within_clint(addr, width) | (within_htif_readable(addr, width) & 1 <= 'n)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": "within_clint(addr, width) | (within_htif_readable(addr, width) & 1 <= 'n)" }, "links": [ { "type": "function", "id": "within_htif_readable", "file": "model/riscv_platform.sail", "loc": [ 17214, 17234 ] }, { "type": "function", "id": "within_clint", "file": "model/riscv_platform.sail", "loc": [ 17185, 17197 ] } ] }, "within_mmio_writable": { "function": { "number": 0, "source": "function within_mmio_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : int('n)) -> bool =\n within_clint(addr, width) | (within_htif_writable(addr, width) & 'n <= 8)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": "within_clint(addr, width) | (within_htif_writable(addr, width) & 'n <= 8)" }, "links": [ { "type": "function", "id": "within_htif_writable", "file": "model/riscv_platform.sail", "loc": [ 17553, 17573 ] }, { "type": "function", "id": "within_clint", "file": "model/riscv_platform.sail", "loc": [ 17524, 17536 ] } ] }, "within_phys_mem": { "function": { "number": 0, "source": "function within_phys_mem forall 'n, 'n <= max_mem_access. (addr : xlenbits, width : int('n)) -> bool = {\n /* To avoid overflow issues when physical memory extends to the end\n * of the addressable range, we need to perform address bound checks\n * on unsigned unbounded integers.\n */\n let addr_int = unsigned(addr);\n let ram_base_int = unsigned(plat_ram_base ());\n let rom_base_int = unsigned(plat_rom_base ());\n let ram_size_int = unsigned(plat_ram_size ());\n let rom_size_int = unsigned(plat_rom_size ());\n\n /* todo: iterate over segment list */\n if ( ram_base_int <= addr_int\n & (addr_int + sizeof('n)) <= (ram_base_int + ram_size_int))\n then true\n else if ( rom_base_int <= addr_int\n & (addr_int + sizeof('n)) <= (rom_base_int + rom_size_int))\n then true\n else {\n print_platform(\"within_phys_mem: \" ^ BitStr(addr) ^ \" not within phys-mem:\");\n print_platform(\" plat_rom_base: \" ^ BitStr(plat_rom_base ()));\n print_platform(\" plat_rom_size: \" ^ BitStr(plat_rom_size ()));\n print_platform(\" plat_ram_base: \" ^ BitStr(plat_ram_base ()));\n print_platform(\" plat_ram_size: \" ^ BitStr(plat_ram_size ()));\n false\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": " let addr_int = unsigned(addr);\n let ram_base_int = unsigned(plat_ram_base ());\n let rom_base_int = unsigned(plat_rom_base ());\n let ram_size_int = unsigned(plat_ram_size ());\n let rom_size_int = unsigned(plat_rom_size ());\n\n /* todo: iterate over segment list */\n if ( ram_base_int <= addr_int\n & (addr_int + sizeof('n)) <= (ram_base_int + ram_size_int))\n then true\n else if ( rom_base_int <= addr_int\n & (addr_int + sizeof('n)) <= (rom_base_int + rom_size_int))\n then true\n else {\n print_platform(\"within_phys_mem: \" ^ BitStr(addr) ^ \" not within phys-mem:\");\n print_platform(\" plat_rom_base: \" ^ BitStr(plat_rom_base ()));\n print_platform(\" plat_rom_size: \" ^ BitStr(plat_rom_size ()));\n print_platform(\" plat_ram_base: \" ^ BitStr(plat_ram_base ()));\n print_platform(\" plat_ram_size: \" ^ BitStr(plat_ram_size ()));\n false\n }" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 4376, 4384 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 4413, 4421 ] }, { "type": "function", "id": "plat_ram_base", "file": "model/riscv_platform.sail", "loc": [ 4422, 4435 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 4462, 4470 ] }, { "type": "function", "id": "plat_rom_base", "file": "model/riscv_platform.sail", "loc": [ 4471, 4484 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 4511, 4519 ] }, { "type": "function", "id": "plat_ram_size", "file": "model/riscv_platform.sail", "loc": [ 4520, 4533 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_platform.sail", "loc": [ 4560, 4568 ] }, { "type": "function", "id": "plat_rom_size", "file": "model/riscv_platform.sail", "loc": [ 4569, 4582 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 5176, 5190 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "plat_ram_size", "file": "model/riscv_platform.sail", "loc": [ 5220, 5233 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 5108, 5122 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "plat_ram_base", "file": "model/riscv_platform.sail", "loc": [ 5152, 5165 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 5040, 5054 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "plat_rom_size", "file": "model/riscv_platform.sail", "loc": [ 5084, 5097 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 4972, 4986 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "plat_rom_base", "file": "model/riscv_platform.sail", "loc": [ 5016, 5029 ] }, { "type": "function", "id": "print_platform", "file": "model/riscv_platform.sail", "loc": [ 4890, 4904 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] } ] }, "wmvvfunct6_of_num": { "function": { "number": 0, "source": "wmvvfunct6_of_num arg# = $[complete] match arg# {\n 0 => WMVV_VWMACCU,\n 1 => WMVV_VWMACC,\n _ => WMVV_VWMACCSU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => WMVV_VWMACCU,\n 1 => WMVV_VWMACC,\n _ => WMVV_VWMACCSU\n}" } }, "wmvxfunct6_of_num": { "function": { "number": 0, "source": "wmvxfunct6_of_num arg# = $[complete] match arg# {\n 0 => WMVX_VWMACCU,\n 1 => WMVX_VWMACC,\n 2 => WMVX_VWMACCUS,\n _ => WMVX_VWMACCSU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => WMVX_VWMACCU,\n 1 => WMVX_VWMACC,\n 2 => WMVX_VWMACCUS,\n _ => WMVX_VWMACCSU\n}" } }, "word_width_bytes": { "function": { "number": 0, "source": "function word_width_bytes width = match width {\n BYTE => 1,\n HALF => 2,\n WORD => 4,\n DOUBLE => 8\n}", "pattern": { "type": "id", "id": "width" }, "body": "match width {\n BYTE => 1,\n HALF => 2,\n WORD => 4,\n DOUBLE => 8\n}" } }, "word_width_of_num": { "function": { "number": 0, "source": "word_width_of_num arg# = $[complete] match arg# {\n 0 => BYTE,\n 1 => HALF,\n 2 => WORD,\n _ => DOUBLE\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => BYTE,\n 1 => HALF,\n 2 => WORD,\n _ => DOUBLE\n}" } }, "writeCSR": { "function": { "number": 0, "source": "function writeCSR (csr : csreg, value : xlenbits) -> unit = {\n let res : option(xlenbits) =\n match (csr, sizeof(xlen)) {\n /* machine mode */\n (0x300, _) => { mstatus = legalize_mstatus(mstatus, value); Some(mstatus.bits) },\n (0x301, _) => { misa = legalize_misa(misa, value); Some(misa.bits) },\n (0x302, _) => { medeleg = legalize_medeleg(medeleg, value); Some(medeleg.bits) },\n (0x303, _) => { mideleg = legalize_mideleg(mideleg, value); Some(mideleg.bits) },\n (0x304, _) => { mie = legalize_mie(mie, value); Some(mie.bits) },\n (0x305, _) => { Some(set_mtvec(value)) },\n (0x306, _) => { mcounteren = legalize_mcounteren(mcounteren, value); Some(zero_extend(mcounteren.bits)) },\n (0x30A, 32) => { menvcfg = legalize_menvcfg(menvcfg, menvcfg.bits[63 .. 32] @ value); Some(menvcfg.bits[31 .. 0]) },\n (0x30A, 64) => { menvcfg = legalize_menvcfg(menvcfg, value); Some(menvcfg.bits) },\n (0x310, 32) => { Some(mstatush.bits) }, // ignore writes for now\n (0x31A, 32) => { menvcfg = legalize_menvcfg(menvcfg, value @ menvcfg.bits[31 .. 0]); Some(menvcfg.bits[63 .. 32]) },\n (0x320, _) => { mcountinhibit = legalize_mcountinhibit(mcountinhibit, value); Some(zero_extend(mcountinhibit.bits)) },\n (0x340, _) => { mscratch = value; Some(mscratch) },\n (0x341, _) => { Some(set_xret_target(Machine, value)) },\n (0x342, _) => { mcause.bits = value; Some(mcause.bits) },\n (0x343, _) => { mtval = value; Some(mtval) },\n (0x344, _) => { mip = legalize_mip(mip, value); Some(mip.bits) },\n\n // pmpcfgN\n (0x3A @ idx : bits(4), _) if idx[0] == bitzero | sizeof(xlen) == 32 => {\n let idx = unsigned(idx);\n pmpWriteCfgReg(idx, value); Some(pmpReadCfgReg(idx))\n },\n\n // pmpaddrN. Unfortunately the PMP index does not nicely align with the CSR index bits.\n (0x3B @ idx : bits(4), _) => { let idx = unsigned(0b00 @ idx); pmpWriteAddrReg(idx, value); Some(pmpReadAddrReg(idx)) },\n (0x3C @ idx : bits(4), _) => { let idx = unsigned(0b01 @ idx); pmpWriteAddrReg(idx, value); Some(pmpReadAddrReg(idx)) },\n (0x3D @ idx : bits(4), _) => { let idx = unsigned(0b10 @ idx); pmpWriteAddrReg(idx, value); Some(pmpReadAddrReg(idx)) },\n (0x3E @ idx : bits(4), _) => { let idx = unsigned(0b11 @ idx); pmpWriteAddrReg(idx, value); Some(pmpReadAddrReg(idx)) },\n\n /* machine mode counters */\n (0xB00, _) => { mcycle[(sizeof(xlen) - 1) .. 0] = value; Some(value) },\n (0xB02, _) => { minstret[(sizeof(xlen) - 1) .. 0] = value; minstret_increment = false; Some(value) },\n (0xB80, 32) => { mcycle[63 .. 32] = value; Some(value) },\n (0xB82, 32) => { minstret[63 .. 32] = value; minstret_increment = false; Some(value) },\n\n /* trigger/debug */\n (0x7a0, _) => { tselect = value; Some(tselect) },\n\n /* supervisor mode */\n (0x100, _) => { mstatus = legalize_sstatus(mstatus, value); Some(mstatus.bits) },\n (0x102, _) => { sedeleg = legalize_sedeleg(sedeleg, value); Some(sedeleg.bits) },\n (0x103, _) => { sideleg.bits = value; Some(sideleg.bits) }, /* TODO: does this need legalization? */\n (0x104, _) => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits) },\n (0x105, _) => { Some(set_stvec(value)) },\n (0x106, _) => { scounteren = legalize_scounteren(scounteren, value); Some(zero_extend(scounteren.bits)) },\n (0x10A, _) => { senvcfg = legalize_senvcfg(senvcfg, zero_extend(value)); Some(senvcfg.bits[sizeof(xlen) - 1 .. 0]) },\n (0x140, _) => { sscratch = value; Some(sscratch) },\n (0x141, _) => { Some(set_xret_target(Supervisor, value)) },\n (0x142, _) => { scause.bits = value; Some(scause.bits) },\n (0x143, _) => { stval = value; Some(stval) },\n (0x144, _) => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits) },\n (0x180, _) => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) },\n\n /* user mode: seed (entropy source). writes are ignored */\n (0x015, _) => write_seed_csr(),\n\n /* vector */\n (0x008, _) => { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); Some(zero_extend(vstart)) },\n (0x009, _) => { vxsat = value[0 .. 0]; Some(zero_extend(vxsat)) },\n (0x00A, _) => { vxrm = value[1 .. 0]; Some(zero_extend(vxrm)) },\n (0x00F, _) => { vcsr.bits = value[2 ..0]; Some(zero_extend(vcsr.bits)) },\n (0xC20, _) => { vl = value; Some(vl) },\n (0xC21, _) => { vtype.bits = value; Some(vtype.bits) },\n (0xC22, _) => { vlenb = value; Some(vlenb) },\n\n _ => ext_write_CSR(csr, value)\n };\n match res {\n Some(v) => if get_config_print_reg()\n then print_reg(\"CSR \" ^ to_str(csr) ^ \" <- \" ^ BitStr(v) ^ \" (input: \" ^ BitStr(value) ^ \")\"),\n None() => print_bits(\"unhandled write to CSR \", csr)\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "value" } ] }, "body": " let res : option(xlenbits) =\n match (csr, sizeof(xlen)) {\n /* machine mode */\n (0x300, _) => { mstatus = legalize_mstatus(mstatus, value); Some(mstatus.bits) },\n (0x301, _) => { misa = legalize_misa(misa, value); Some(misa.bits) },\n (0x302, _) => { medeleg = legalize_medeleg(medeleg, value); Some(medeleg.bits) },\n (0x303, _) => { mideleg = legalize_mideleg(mideleg, value); Some(mideleg.bits) },\n (0x304, _) => { mie = legalize_mie(mie, value); Some(mie.bits) },\n (0x305, _) => { Some(set_mtvec(value)) },\n (0x306, _) => { mcounteren = legalize_mcounteren(mcounteren, value); Some(zero_extend(mcounteren.bits)) },\n (0x30A, 32) => { menvcfg = legalize_menvcfg(menvcfg, menvcfg.bits[63 .. 32] @ value); Some(menvcfg.bits[31 .. 0]) },\n (0x30A, 64) => { menvcfg = legalize_menvcfg(menvcfg, value); Some(menvcfg.bits) },\n (0x310, 32) => { Some(mstatush.bits) }, // ignore writes for now\n (0x31A, 32) => { menvcfg = legalize_menvcfg(menvcfg, value @ menvcfg.bits[31 .. 0]); Some(menvcfg.bits[63 .. 32]) },\n (0x320, _) => { mcountinhibit = legalize_mcountinhibit(mcountinhibit, value); Some(zero_extend(mcountinhibit.bits)) },\n (0x340, _) => { mscratch = value; Some(mscratch) },\n (0x341, _) => { Some(set_xret_target(Machine, value)) },\n (0x342, _) => { mcause.bits = value; Some(mcause.bits) },\n (0x343, _) => { mtval = value; Some(mtval) },\n (0x344, _) => { mip = legalize_mip(mip, value); Some(mip.bits) },\n\n // pmpcfgN\n (0x3A @ idx : bits(4), _) if idx[0] == bitzero | sizeof(xlen) == 32 => {\n let idx = unsigned(idx);\n pmpWriteCfgReg(idx, value); Some(pmpReadCfgReg(idx))\n },\n\n // pmpaddrN. Unfortunately the PMP index does not nicely align with the CSR index bits.\n (0x3B @ idx : bits(4), _) => { let idx = unsigned(0b00 @ idx); pmpWriteAddrReg(idx, value); Some(pmpReadAddrReg(idx)) },\n (0x3C @ idx : bits(4), _) => { let idx = unsigned(0b01 @ idx); pmpWriteAddrReg(idx, value); Some(pmpReadAddrReg(idx)) },\n (0x3D @ idx : bits(4), _) => { let idx = unsigned(0b10 @ idx); pmpWriteAddrReg(idx, value); Some(pmpReadAddrReg(idx)) },\n (0x3E @ idx : bits(4), _) => { let idx = unsigned(0b11 @ idx); pmpWriteAddrReg(idx, value); Some(pmpReadAddrReg(idx)) },\n\n /* machine mode counters */\n (0xB00, _) => { mcycle[(sizeof(xlen) - 1) .. 0] = value; Some(value) },\n (0xB02, _) => { minstret[(sizeof(xlen) - 1) .. 0] = value; minstret_increment = false; Some(value) },\n (0xB80, 32) => { mcycle[63 .. 32] = value; Some(value) },\n (0xB82, 32) => { minstret[63 .. 32] = value; minstret_increment = false; Some(value) },\n\n /* trigger/debug */\n (0x7a0, _) => { tselect = value; Some(tselect) },\n\n /* supervisor mode */\n (0x100, _) => { mstatus = legalize_sstatus(mstatus, value); Some(mstatus.bits) },\n (0x102, _) => { sedeleg = legalize_sedeleg(sedeleg, value); Some(sedeleg.bits) },\n (0x103, _) => { sideleg.bits = value; Some(sideleg.bits) }, /* TODO: does this need legalization? */\n (0x104, _) => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits) },\n (0x105, _) => { Some(set_stvec(value)) },\n (0x106, _) => { scounteren = legalize_scounteren(scounteren, value); Some(zero_extend(scounteren.bits)) },\n (0x10A, _) => { senvcfg = legalize_senvcfg(senvcfg, zero_extend(value)); Some(senvcfg.bits[sizeof(xlen) - 1 .. 0]) },\n (0x140, _) => { sscratch = value; Some(sscratch) },\n (0x141, _) => { Some(set_xret_target(Supervisor, value)) },\n (0x142, _) => { scause.bits = value; Some(scause.bits) },\n (0x143, _) => { stval = value; Some(stval) },\n (0x144, _) => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits) },\n (0x180, _) => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) },\n\n /* user mode: seed (entropy source). writes are ignored */\n (0x015, _) => write_seed_csr(),\n\n /* vector */\n (0x008, _) => { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); Some(zero_extend(vstart)) },\n (0x009, _) => { vxsat = value[0 .. 0]; Some(zero_extend(vxsat)) },\n (0x00A, _) => { vxrm = value[1 .. 0]; Some(zero_extend(vxrm)) },\n (0x00F, _) => { vcsr.bits = value[2 ..0]; Some(zero_extend(vcsr.bits)) },\n (0xC20, _) => { vl = value; Some(vl) },\n (0xC21, _) => { vtype.bits = value; Some(vtype.bits) },\n (0xC22, _) => { vlenb = value; Some(vlenb) },\n\n _ => ext_write_CSR(csr, value)\n };\n match res {\n Some(v) => if get_config_print_reg()\n then print_reg(\"CSR \" ^ to_str(csr) ^ \" <- \" ^ BitStr(v) ^ \" (input: \" ^ BitStr(value) ^ \")\"),\n None() => print_bits(\"unhandled write to CSR \", csr)\n }" }, "links": [ { "type": "function", "id": "ext_write_CSR", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8910, 8923 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8875, 8879 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8880, 8885 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8860, 8865 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8820, 8824 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8825, 8830 ] }, { "type": "register", "id": "vtype", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8800, 8805 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8768, 8772 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8773, 8775 ] }, { "type": "register", "id": "vl", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8756, 8758 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8704, 8708 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8709, 8720 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8721, 8725 ] }, { "type": "register", "id": "vcsr", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8678, 8682 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8631, 8635 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8636, 8647 ] }, { "type": "register", "id": "vxrm", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8648, 8652 ] }, { "type": "register", "id": "vxrm", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8609, 8613 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8561, 8565 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8566, 8577 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8578, 8583 ] }, { "type": "register", "id": "vxsat", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8538, 8543 ] }, { "type": "function", "id": "get_vlen_pow", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8414, 8426 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8489, 8493 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8494, 8505 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8506, 8512 ] }, { "type": "register", "id": "vstart", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8430, 8436 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8439, 8450 ] }, { "type": "function", "id": "write_seed_csr", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8338, 8352 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8241, 8245 ] }, { "type": "register", "id": "satp", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8246, 8250 ] }, { "type": "register", "id": "satp", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8186, 8190 ] }, { "type": "function", "id": "legalize_satp", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8193, 8206 ] }, { "type": "register", "id": "satp", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8227, 8231 ] }, { "type": "function", "id": "cur_Architecture", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8207, 8223 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8147, 8151 ] }, { "type": "register", "id": "mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8152, 8155 ] }, { "type": "register", "id": "mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8106, 8109 ] }, { "type": "function", "id": "legalize_sip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8112, 8124 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8130, 8137 ] }, { "type": "register", "id": "mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8125, 8128 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8070, 8074 ] }, { "type": "register", "id": "stval", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8075, 8080 ] }, { "type": "register", "id": "stval", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8055, 8060 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8013, 8017 ] }, { "type": "register", "id": "scause", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8018, 8024 ] }, { "type": "register", "id": "scause", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7992, 7998 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7927, 7931 ] }, { "type": "function", "id": "set_xret_target", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7932, 7947 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7888, 7892 ] }, { "type": "register", "id": "sscratch", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7893, 7901 ] }, { "type": "register", "id": "sscratch", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7870, 7878 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7804, 7808 ] }, { "type": "register", "id": "senvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7809, 7816 ] }, { "type": "register", "id": "senvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7747, 7754 ] }, { "type": "function", "id": "legalize_senvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7757, 7773 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7783, 7794 ] }, { "type": "register", "id": "senvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7774, 7781 ] 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"register", "id": "sedeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7315, 7322 ] }, { "type": "function", "id": "legalize_sedeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7325, 7341 ] }, { "type": "register", "id": "sedeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7342, 7349 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7272, 7276 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7277, 7284 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7228, 7235 ] }, { "type": "function", "id": "legalize_sstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7238, 7254 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7255, 7262 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7163, 7167 ] }, { "type": "register", "id": "tselect", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7168, 7175 ] }, { "type": "register", "id": "tselect", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7146, 7153 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7085, 7089 ] }, { "type": "register", "id": "minstret_increment", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7057, 7075 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_insts_zicsr.sail", "loc": [ 7029, 7037 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6993, 6997 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6967, 6973 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6931, 6935 ] }, { "type": "register", "id": "minstret_increment", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6903, 6921 ] }, { "type": "register", "id": "minstret", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6860, 6868 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6824, 6828 ] }, { "type": "register", "id": "mcycle", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6783, 6789 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6649, 6657 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6700, 6704 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6705, 6719 ] }, { "type": "function", "id": "pmpWriteAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6671, 6686 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6523, 6531 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6574, 6578 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6579, 6593 ] }, { "type": "function", "id": "pmpWriteAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6545, 6560 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6397, 6405 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6448, 6452 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6453, 6467 ] }, { "type": "function", "id": "pmpWriteAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6419, 6434 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6271, 6279 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6322, 6326 ] }, { "type": "function", "id": "pmpReadAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6327, 6341 ] }, { "type": "function", "id": "pmpWriteAddrReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6293, 6308 ] }, { "type": "function", "id": "unsigned", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6051, 6059 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6100, 6104 ] }, { "type": "function", "id": "pmpReadCfgReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6105, 6118 ] }, { "type": "function", "id": "pmpWriteCfgReg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 6072, 6086 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5923, 5927 ] }, { "type": "register", "id": "mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5928, 5931 ] }, { "type": "register", "id": "mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5891, 5894 ] }, { "type": "function", "id": "legalize_mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5897, 5909 ] }, { "type": "register", "id": "mip", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5910, 5913 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5855, 5859 ] }, { "type": "register", "id": "mtval", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5860, 5865 ] }, { "type": "register", "id": "mtval", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5840, 5845 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5798, 5802 ] }, { "type": "register", "id": "mcause", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5803, 5809 ] }, { "type": "register", "id": "mcause", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5777, 5783 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5715, 5719 ] }, { "type": "function", "id": "set_xret_target", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5720, 5735 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5676, 5680 ] }, { "type": "register", "id": "mscratch", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5681, 5689 ] }, { "type": "register", "id": "mscratch", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5658, 5666 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5596, 5600 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5601, 5612 ] }, { "type": "register", "id": "mcountinhibit", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5613, 5626 ] }, { "type": "register", "id": "mcountinhibit", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5534, 5547 ] }, { "type": "function", "id": "legalize_mcountinhibit", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5550, 5572 ] }, { "type": "register", "id": "mcountinhibit", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5573, 5586 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5481, 5485 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5486, 5493 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5413, 5420 ] }, { "type": "function", "id": "legalize_menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5423, 5439 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5457, 5464 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5440, 5447 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5344, 5348 ] }, { "type": "register", "id": "mstatush", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5349, 5357 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5301, 5305 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5306, 5313 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5257, 5264 ] }, { "type": "function", "id": "legalize_menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5267, 5283 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5284, 5291 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5205, 5209 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5210, 5217 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5136, 5143 ] }, { "type": "function", "id": "legalize_menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5146, 5162 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5172, 5179 ] }, { "type": "register", "id": "menvcfg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5163, 5170 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5077, 5081 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5082, 5093 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5094, 5104 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5024, 5034 ] }, { "type": "function", "id": "legalize_mcounteren", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5037, 5056 ] }, { "type": "register", "id": "mcounteren", "file": "model/riscv_insts_zicsr.sail", "loc": [ 5057, 5067 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4977, 4981 ] }, { "type": "function", "id": "set_mtvec", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4982, 4991 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4938, 4942 ] }, { "type": "register", "id": "mie", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4943, 4946 ] }, { "type": "register", "id": "mie", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4906, 4909 ] }, { "type": "function", "id": "legalize_mie", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4912, 4924 ] }, { "type": "register", "id": "mie", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4925, 4928 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4863, 4867 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4868, 4875 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4819, 4826 ] }, { "type": "function", "id": "legalize_mideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4829, 4845 ] }, { "type": "register", "id": "mideleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4846, 4853 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4776, 4780 ] }, { "type": "register", "id": "medeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4781, 4788 ] }, { "type": "register", "id": "medeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4732, 4739 ] }, { "type": "function", "id": "legalize_medeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4742, 4758 ] }, { "type": "register", "id": "medeleg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4759, 4766 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4692, 4696 ] }, { "type": "register", "id": "misa", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4697, 4701 ] }, { "type": "register", "id": "misa", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4657, 4661 ] }, { "type": "function", "id": "legalize_misa", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4664, 4677 ] }, { "type": "register", "id": "misa", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4678, 4682 ] }, { "type": "function", "id": "Some", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4614, 4618 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4619, 4626 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4570, 4577 ] }, { "type": "function", "id": "legalize_mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4580, 4596 ] }, { "type": "register", "id": "mstatus", "file": "model/riscv_insts_zicsr.sail", "loc": [ 4597, 4604 ] }, { "type": "function", "id": "print_bits", "file": "model/riscv_insts_zicsr.sail", "loc": [ 9123, 9133 ] }, { "type": "function", "id": "get_config_print_reg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 8975, 8995 ] }, { "type": "function", "id": "print_reg", "file": "model/riscv_insts_zicsr.sail", "loc": [ 9018, 9027 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "concat_str", "file": "model/prelude.sail", "loc": [ 1487, 1497 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "bits_str", "file": "model/prelude.sail", "loc": [ 1302, 1310 ] }, { "type": "function", "id": "csr_name", "file": "model/riscv_csr_map.sail", "loc": [ 8753, 8761 ] } ] }, "write_TLB": { "function": { "number": 0, "source": "function write_TLB(idx : nat, ent : TLB_Entry) -> unit =\n tlb = Some(ent)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "idx" }, { "type": "id", "id": "ent" } ] }, "body": "tlb = Some(ent)" }, "links": [ { "type": "register", "id": "tlb", "file": "model/riscv_vmem_tlb.sail", "loc": [ 1787, 1790 ] }, { "type": "function", "id": "Some", "file": "model/riscv_vmem_tlb.sail", "loc": [ 1793, 1797 ] } ] }, "write_kind_of_num": { "function": { "number": 0, "source": "write_kind_of_num arg# = $[complete] match arg# {\n 0 => Write_plain,\n 1 => Write_conditional,\n 2 => Write_release,\n 3 => Write_exclusive,\n 4 => Write_exclusive_release,\n 5 => Write_RISCV_release,\n 6 => Write_RISCV_strong_release,\n 7 => Write_RISCV_conditional,\n 8 => Write_RISCV_conditional_release,\n 9 => Write_RISCV_conditional_strong_release,\n _ => Write_X86_locked\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => Write_plain,\n 1 => Write_conditional,\n 2 => Write_release,\n 3 => Write_exclusive,\n 4 => Write_exclusive_release,\n 5 => Write_RISCV_release,\n 6 => Write_RISCV_strong_release,\n 7 => Write_RISCV_conditional,\n 8 => Write_RISCV_conditional_release,\n 9 => Write_RISCV_conditional_strong_release,\n _ => Write_X86_locked\n}" } }, "write_ram": { "function": { "number": 0, "source": "function write_ram(wk, addr, width, data, meta) = {\n /* Write out metadata only if the value write succeeds.\n * It is assumed for now that this write always succeeds;\n * there is currently no return value.\n * FIXME: We should convert the external API for all backends\n * (not just for Lem) to consume the value along with the\n * metadata to ensure atomicity.\n */\n let ret : bool = __write_mem(wk, sizeof(xlen), addr, width, data);\n if ret then __WriteRAM_Meta(addr, width, meta);\n ret\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "wk" }, { "type": "id", "id": "addr" }, { "type": "id", "id": "width" }, { "type": "id", "id": "data" }, { "type": "id", "id": "meta" } ] }, "body": " let ret : bool = __write_mem(wk, sizeof(xlen), addr, width, data);\n if ret then __WriteRAM_Meta(addr, width, meta);\n ret" }, "links": [ { "type": "function", "id": "__write_mem", "file": "model/prelude_mem.sail", "loc": [ 2092, 2103 ] }, { "type": "function", "id": "__WriteRAM_Meta", "file": "model/prelude_mem.sail", "loc": [ 2156, 2171 ] } ] }, "write_ram_ea": { "function": { "number": 0, "source": "function write_ram_ea(wk, addr, width) =\n __write_mem_ea(wk, sizeof(xlen), addr, width)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "wk" }, { "type": "id", "id": "addr" }, { "type": "id", "id": "width" } ] }, "body": "__write_mem_ea(wk, sizeof(xlen), addr, width)" }, "links": [ { "type": "function", "id": "__write_mem_ea", "file": "model/prelude_mem.sail", "loc": [ 2341, 2355 ] } ] }, "write_seed_csr": { "function": { "number": 0, "source": "function write_seed_csr () -> option(xlenbits) = None()", "pattern": { "type": "literal", "value": "()" }, "body": "None()" }, "links": [ { "type": "function", "id": "None", "file": "model/riscv_sys_regs.sail", "loc": [ 24156, 24160 ] } ] }, "write_single_element": { "function": { "number": 0, "source": "function write_single_element(EEW, index, vrid, value) = {\n let VLEN = unsigned(vlenb) * 8;\n let 'elem_per_reg : int = VLEN / EEW;\n assert('elem_per_reg >= 0);\n let real_vrid : regidx = vrid + to_bits(5, index / 'elem_per_reg);\n let real_index : int = index % 'elem_per_reg;\n\n let vrid_val : vector('elem_per_reg, dec, bits('m)) = read_single_vreg('elem_per_reg, EEW, real_vrid);\n r : vregtype = zeros();\n foreach (i from ('elem_per_reg - 1) downto 0) {\n r = r << EEW;\n if i == real_index then {\n r = r | zero_extend(value);\n } else {\n r = r | zero_extend(vrid_val[i]);\n }\n };\n V(real_vrid) = r;\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "EEW" }, { "type": "id", "id": "index" }, { "type": "id", "id": "vrid" }, { "type": "id", "id": "value" } ] }, "body": " let VLEN = unsigned(vlenb) * 8;\n let 'elem_per_reg : int = VLEN / EEW;\n assert('elem_per_reg >= 0);\n let real_vrid : regidx = vrid + to_bits(5, index / 'elem_per_reg);\n let real_index : int = index % 'elem_per_reg;\n\n let vrid_val : vector('elem_per_reg, dec, bits('m)) = read_single_vreg('elem_per_reg, EEW, real_vrid);\n r : vregtype = zeros();\n foreach (i from ('elem_per_reg - 1) downto 0) {\n r = r << EEW;\n if i == real_index then {\n r = r | zero_extend(value);\n } else {\n r = r | zero_extend(vrid_val[i]);\n }\n };\n V(real_vrid) = r;" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 10315, 10323 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 10324, 10329 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 10441, 10448 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "emod_int", "file": "model/prelude.sail", "loc": [ 2111, 2119 ] }, { "type": "function", "id": "read_single_vreg", "file": "model/riscv_vext_regs.sail", "loc": [ 10584, 10600 ] }, { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "wV_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 4444, 4451 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_regs.sail", "loc": [ 10771, 10782 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_regs.sail", "loc": [ 10818, 10829 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] } ] }, "write_single_vreg": { "function": { "number": 0, "source": "function write_single_vreg(num_elem, SEW, vrid, v) = {\n r : vregtype = zeros();\n\n assert(8 <= SEW & SEW <= 64);\n foreach (i from (num_elem - 1) downto 0) {\n r = r << SEW;\n r = r | zero_extend(v[i]);\n };\n\n V(vrid) = r\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "vrid" }, { "type": "id", "id": "v" } ] }, "body": "function write_single_vreg(num_elem, SEW, vrid, v) = {\n r : vregtype = zeros();\n\n assert(8 <= SEW & SEW <= 64);\n foreach (i from (num_elem - 1) downto 0) {\n r = r << SEW;\n r = r | zero_extend(v[i]);\n };\n\n V(vrid) = r\n}" }, "links": [ { "type": "function", "id": "zeros_implicit", "file": "model/prelude.sail", "loc": [ 4429, 4443 ] }, { "type": "function", "id": "wV_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 4444, 4451 ] }, { "type": "function", "id": "zero_extend", "file": "model/riscv_vext_regs.sail", "loc": [ 6827, 6838 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] } ] }, "write_vmask": { "function": { "number": 0, "source": "function write_vmask(num_elem, vrid, v) = {\n let VLEN = unsigned(vlenb) * 8;\n assert(0 < VLEN & VLEN <= sizeof(vlenmax));\n assert(0 < num_elem & num_elem <= VLEN);\n let vreg_val : vregtype = V(vrid);\n var result : vregtype = undefined;\n\n foreach (i from 0 to (num_elem - 1)) {\n result[i] = bool_to_bit(v[i])\n };\n foreach (i from num_elem to (VLEN - 1)) {\n /* Mask tail is always agnostic */\n result[i] = vreg_val[i] /* TODO: configuration support */\n };\n\n V(vrid) = result\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "vrid" }, { "type": "id", "id": "v" } ] }, "body": " let VLEN = unsigned(vlenb) * 8;\n assert(0 < VLEN & VLEN <= sizeof(vlenmax));\n assert(0 < num_elem & num_elem <= VLEN);\n let vreg_val : vregtype = V(vrid);\n var result : vregtype = undefined;\n\n foreach (i from 0 to (num_elem - 1)) {\n result[i] = bool_to_bit(v[i])\n };\n foreach (i from num_elem to (VLEN - 1)) {\n /* Mask tail is always agnostic */\n result[i] = vreg_val[i] /* TODO: configuration support */\n };\n\n V(vrid) = result" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 12233, 12241 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 12242, 12247 ] }, { "type": "function", "id": "rV_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 4435, 4442 ] }, { "type": "function", "id": "wV_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 4444, 4451 ] }, { "type": "function", "id": "bool_to_bit", "file": "model/riscv_vext_regs.sail", "loc": [ 12477, 12488 ] } ] }, "write_vreg": { "function": { "number": 0, "source": "function write_vreg(num_elem, SEW, LMUL_pow, vrid, vec) = {\n let VLEN = unsigned(vlenb) * 8;\n let LMUL_pow_reg = if LMUL_pow < 0 then 0 else LMUL_pow;\n\n let 'num_elem_single : int = VLEN / SEW;\n assert('num_elem_single >= 0);\n foreach (i_lmul from 0 to (2 ^ LMUL_pow_reg - 1)) {\n var single_vec : vector('num_elem_single, dec, bits('m)) = undefined;\n let vrid_lmul : regidx = vrid + to_bits(5, i_lmul);\n let r_start_i : int = i_lmul * 'num_elem_single;\n let r_end_i : int = r_start_i + 'num_elem_single - 1;\n foreach (r_i from r_start_i to r_end_i) {\n let s_i : int = r_i - r_start_i;\n assert(0 <= r_i & r_i < num_elem);\n assert(0 <= s_i & s_i < 'num_elem_single);\n single_vec[s_i] = vec[r_i]\n };\n write_single_vreg('num_elem_single, SEW, vrid_lmul, single_vec)\n }\n}", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "num_elem" }, { "type": "id", "id": "SEW" }, { "type": "id", "id": "LMUL_pow" }, { "type": "id", "id": "vrid" }, { "type": "id", "id": "vec" } ] }, "body": " let VLEN = unsigned(vlenb) * 8;\n let LMUL_pow_reg = if LMUL_pow < 0 then 0 else LMUL_pow;\n\n let 'num_elem_single : int = VLEN / SEW;\n assert('num_elem_single >= 0);\n foreach (i_lmul from 0 to (2 ^ LMUL_pow_reg - 1)) {\n var single_vec : vector('num_elem_single, dec, bits('m)) = undefined;\n let vrid_lmul : regidx = vrid + to_bits(5, i_lmul);\n let r_start_i : int = i_lmul * 'num_elem_single;\n let r_end_i : int = r_start_i + 'num_elem_single - 1;\n foreach (r_i from r_start_i to r_end_i) {\n let s_i : int = r_i - r_start_i;\n assert(0 <= r_i & r_i < num_elem);\n assert(0 <= s_i & s_i < 'num_elem_single);\n single_vec[s_i] = vec[r_i]\n };\n write_single_vreg('num_elem_single, SEW, vrid_lmul, single_vec)\n }" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/riscv_vext_regs.sail", "loc": [ 9354, 9362 ] }, { "type": "register", "id": "vlenb", "file": "model/riscv_vext_regs.sail", "loc": [ 9363, 9368 ] }, { "type": "function", "id": "quot_round_zero", "file": "model/prelude.sail", "loc": [ 7697, 7712 ] }, { "type": "function", "id": "pow2", "file": "model/riscv_vext_regs.sail", "loc": [ 9541, 9544 ] }, { "type": "function", "id": "to_bits", "file": "model/riscv_vext_regs.sail", "loc": [ 9677, 9684 ] }, { "type": "function", "id": "write_single_vreg", "file": "model/riscv_vext_regs.sail", "loc": [ 10031, 10048 ] } ] }, "wvfunct6_of_num": { "function": { "number": 0, "source": "wvfunct6_of_num arg# = $[complete] match arg# {\n 0 => WV_VADD,\n 1 => WV_VSUB,\n 2 => WV_VADDU,\n _ => WV_VSUBU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => WV_VADD,\n 1 => WV_VSUB,\n 2 => WV_VADDU,\n _ => WV_VSUBU\n}" } }, "wvvfunct6_of_num": { "function": { "number": 0, "source": "wvvfunct6_of_num arg# = $[complete] match arg# {\n 0 => WVV_VADD,\n 1 => WVV_VSUB,\n 2 => WVV_VADDU,\n 3 => WVV_VSUBU,\n 4 => WVV_VWMUL,\n 5 => WVV_VWMULU,\n _ => WVV_VWMULSU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => WVV_VADD,\n 1 => WVV_VSUB,\n 2 => WVV_VADDU,\n 3 => WVV_VSUBU,\n 4 => WVV_VWMUL,\n 5 => WVV_VWMULU,\n _ => WVV_VWMULSU\n}" } }, "wvxfunct6_of_num": { "function": { "number": 0, "source": "wvxfunct6_of_num arg# = $[complete] match arg# {\n 0 => WVX_VADD,\n 1 => WVX_VSUB,\n 2 => WVX_VADDU,\n 3 => WVX_VSUBU,\n 4 => WVX_VWMUL,\n 5 => WVX_VWMULU,\n _ => WVX_VWMULSU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => WVX_VADD,\n 1 => WVX_VSUB,\n 2 => WVX_VADDU,\n 3 => WVX_VSUBU,\n 4 => WVX_VWMUL,\n 5 => WVX_VWMULU,\n _ => WVX_VWMULSU\n}" } }, "wxfunct6_of_num": { "function": { "number": 0, "source": "wxfunct6_of_num arg# = $[complete] match arg# {\n 0 => WX_VADD,\n 1 => WX_VSUB,\n 2 => WX_VADDU,\n _ => WX_VSUBU\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => WX_VADD,\n 1 => WX_VSUB,\n 2 => WX_VADDU,\n _ => WX_VSUBU\n}" } }, "xt2": { "function": { "number": 0, "source": "function xt2(x) = {\n (x << 1) ^ (if bit_to_bool(x[7]) then 0x1b else 0x00)\n}", "pattern": { "type": "id", "id": "x" }, "body": " (x << 1) ^ (if bit_to_bool(x[7]) then 0x1b else 0x00)" }, "links": [ { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "bit_to_bool", "file": "model/riscv_types_kext.sail", "loc": [ 1100, 1111 ] }, { "type": "function", "id": "shiftl", "file": "model/prelude.sail", "loc": [ 6386, 6392 ] } ] }, "xt3": { "function": { "number": 0, "source": "function xt3(x) = x ^ xt2(x)", "pattern": { "type": "id", "id": "x" }, "body": "x ^ xt2(x)" }, "links": [ { "type": "function", "id": "xor_vec", "file": "model/prelude.sail", "loc": [ 1467, 1474 ] }, { "type": "function", "id": "xt2", "file": "model/riscv_types_kext.sail", "loc": [ 1193, 1196 ] } ] }, "zero_extend": { "function": { "number": 0, "source": "function zero_extend(m, v) = sail_zero_extend(v, m)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "m" }, { "type": "id", "id": "v" } ] }, "body": "sail_zero_extend(v, m)" }, "links": [ { "type": "function", "id": "sail_zero_extend", "file": "model/prelude.sail", "loc": [ 4276, 4292 ] } ] }, "zeros_implicit": { "function": { "number": 0, "source": "function zeros_implicit (n) = sail_zeros(n)", "pattern": { "type": "id", "id": "n" }, "body": "sail_zeros(n)" }, "links": [ { "type": "function", "id": "sail_zeros", "file": "model/prelude.sail", "loc": [ 4397, 4407 ] } ] }, "zicondop_of_num": { "function": { "number": 0, "source": "zicondop_of_num arg# = $[complete] match arg# {\n 0 => RISCV_CZERO_EQZ,\n _ => RISCV_CZERO_NEZ\n}", "pattern": { "type": "id", "id": "arg#" }, "body": "$[complete] match arg# {\n 0 => RISCV_CZERO_EQZ,\n _ => RISCV_CZERO_NEZ\n}" } }, "(operator <=_s)": { "function": { "number": 0, "source": "function operator <=_s (x, y) = signed(x) <= signed(y)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "signed(x) <= signed(y)" }, "links": [ { "type": "function", "id": "signed", "file": "model/prelude.sail", "loc": [ 5686, 5692 ] }, { "type": "function", "id": "signed", "file": "model/prelude.sail", "loc": [ 5673, 5679 ] } ] }, "(operator <=_u)": { "function": { "number": 0, "source": "function operator <=_u (x, y) = unsigned(x) <= unsigned(y)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "unsigned(x) <= unsigned(y)" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/prelude.sail", "loc": [ 5914, 5922 ] }, { "type": "function", "id": "unsigned", "file": "model/prelude.sail", "loc": [ 5899, 5907 ] } ] }, "(operator <_s)": { "function": { "number": 0, "source": "function operator <_s (x, y) = signed(x) < signed(y)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "signed(x) < signed(y)" }, "links": [ { "type": "function", "id": "signed", "file": "model/prelude.sail", "loc": [ 5577, 5583 ] }, { "type": "function", "id": "signed", "file": "model/prelude.sail", "loc": [ 5565, 5571 ] } ] }, "(operator <_u)": { "function": { "number": 0, "source": "function operator <_u (x, y) = unsigned(x) < unsigned(y)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "unsigned(x) < unsigned(y)" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/prelude.sail", "loc": [ 5797, 5805 ] }, { "type": "function", "id": "unsigned", "file": "model/prelude.sail", "loc": [ 5783, 5791 ] } ] }, "(operator >=_s)": { "function": { "number": 0, "source": "function operator >=_s (x, y) = signed(x) >= signed(y)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "signed(x) >= signed(y)" }, "links": [ { "type": "function", "id": "signed", "file": "model/prelude.sail", "loc": [ 5741, 5747 ] }, { "type": "function", "id": "signed", "file": "model/prelude.sail", "loc": [ 5728, 5734 ] } ] }, "(operator >=_u)": { "function": { "number": 0, "source": "function operator >=_u (x, y) = unsigned(x) >= unsigned(y)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "unsigned(x) >= unsigned(y)" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/prelude.sail", "loc": [ 5973, 5981 ] }, { "type": "function", "id": "unsigned", "file": "model/prelude.sail", "loc": [ 5958, 5966 ] } ] }, "(operator >_s)": { "function": { "number": 0, "source": "function operator >_s (x, y) = signed(x) > signed(y)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "signed(x) > signed(y)" }, "links": [ { "type": "function", "id": "signed", "file": "model/prelude.sail", "loc": [ 5631, 5637 ] }, { "type": "function", "id": "signed", "file": "model/prelude.sail", "loc": [ 5619, 5625 ] } ] }, "(operator >_u)": { "function": { "number": 0, "source": "function operator >_u (x, y) = unsigned(x) > unsigned(y)", "pattern": { "type": "tuple", "patterns": [ { "type": "id", "id": "x" }, { "type": "id", "id": "y" } ] }, "body": "unsigned(x) > unsigned(y)" }, "links": [ { "type": "function", "id": "unsigned", "file": "model/prelude.sail", "loc": [ 5855, 5863 ] }, { "type": "function", "id": "unsigned", "file": "model/prelude.sail", "loc": [ 5841, 5849 ] } ] } }, "mappings": { "amo_mnemonic": { "mapping": [ { "number": 0, "source": "AMOSWAP <-> \"amoswap\"", "left": { "type": "id", "id": "AMOSWAP" }, "right": { "type": "literal", "value": "\"amoswap\"" } }, { "number": 1, "source": "AMOADD <-> \"amoadd\"", "left": { "type": "id", "id": "AMOADD" }, "right": { "type": "literal", "value": "\"amoadd\"" } }, { "number": 2, "source": "AMOXOR <-> \"amoxor\"", "left": { "type": "id", "id": "AMOXOR" }, "right": { "type": "literal", "value": "\"amoxor\"" } }, { "number": 3, "source": "AMOAND <-> \"amoand\"", "left": { "type": "id", "id": "AMOAND" }, "right": { "type": "literal", "value": "\"amoand\"" } }, { "number": 4, "source": "AMOOR <-> \"amoor\"", "left": { "type": "id", "id": "AMOOR" }, "right": { "type": "literal", "value": "\"amoor\"" } }, { "number": 5, "source": "AMOMIN <-> \"amomin\"", "left": { "type": "id", "id": "AMOMIN" }, "right": { "type": "literal", "value": "\"amomin\"" } }, { "number": 6, "source": "AMOMAX <-> \"amomax\"", "left": { "type": "id", "id": "AMOMAX" }, "right": { "type": "literal", "value": "\"amomax\"" } }, { "number": 7, "source": "AMOMINU <-> \"amominu\"", "left": { "type": "id", "id": "AMOMINU" }, "right": { "type": "literal", "value": "\"amominu\"" } }, { "number": 8, "source": "AMOMAXU <-> \"amomaxu\"", "left": { "type": "id", "id": "AMOMAXU" }, "right": { "type": "literal", "value": "\"amomaxu\"" } } ] }, "assembly": { "mapping": [ { "number": 0, "source": "mapping clause assembly = UTYPE(imm, rd, op)\n <-> utype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_20(imm)", "left": { "type": "app", "id": "UTYPE", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "utype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_20", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 1, "source": "mapping clause assembly = RISCV_JAL(imm, rd)\n <-> \"jal\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_21(imm)", "left": { "type": "app", "id": "RISCV_JAL", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"jal\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_21", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 2, "source": "mapping clause assembly = RISCV_JALR(imm, rs1, rd)\n <-> \"jalr\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_12(imm) ^ \"(\" ^ reg_name(rs1) ^ \")\"", "left": { "type": "app", "id": "RISCV_JALR", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"jalr\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "imm" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 3, "source": "mapping clause assembly = BTYPE(imm, rs2, rs1, op)\n <-> btype_mnemonic(op) ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_13(imm)", "left": { "type": "app", "id": "BTYPE", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "btype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_13", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 4, "source": "mapping clause assembly = ITYPE(imm, rs1, rd, op)\n <-> itype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)", "left": { "type": "app", "id": "ITYPE", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "itype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 5, "source": "mapping clause assembly = SHIFTIOP(shamt, rs1, rd, op)\n <-> shiftiop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_6(shamt)", "left": { "type": "app", "id": "SHIFTIOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "shiftiop_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 6, "source": "mapping clause assembly = RTYPE(rs2, rs1, rd, op)\n <-> rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "rtype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 7, "source": "mapping clause assembly = LOAD(imm, rs1, rd, is_unsigned, size, aq, rl)\n <-> \"l\" ^ size_mnemonic(size) ^ maybe_u(is_unsigned) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_12(imm) ^ \"(\" ^ reg_name(rs1) ^ \")\"", "left": { "type": "app", "id": "LOAD", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "is_unsigned" }, { "type": "id", "id": "size" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"l\"" }, { "type": "app", "id": "size_mnemonic", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "app", "id": "maybe_u", "patterns": [ { "type": "id", "id": "is_unsigned" } ] }, { "type": "app", "id": "maybe_aq", "patterns": [ { "type": "id", "id": "aq" } ] }, { "type": "app", "id": "maybe_rl", "patterns": [ { "type": "id", "id": "rl" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "imm" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 8, "source": "mapping clause assembly = STORE(imm, rs2, rs1, size, aq, rl)\n <-> \"s\" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_12(imm) ^ opt_spc() ^ \"(\" ^ opt_spc() ^ reg_name(rs1) ^ opt_spc() ^ \")\"", "left": { "type": "app", "id": "STORE", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "size" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"s\"" }, { "type": "app", "id": "size_mnemonic", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "app", "id": "maybe_aq", "patterns": [ { "type": "id", "id": "aq" } ] }, { "type": "app", "id": "maybe_rl", "patterns": [ { "type": "id", "id": "rl" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "imm" } ] }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 9, "source": "mapping clause assembly = ADDIW(imm, rs1, rd)\n if sizeof(xlen) == 64\n <-> \"addiw\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "ADDIW", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"addiw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 10, "source": "mapping clause assembly = RTYPEW(rs2, rs1, rd, op)\n if sizeof(xlen) == 64\n <-> rtypew_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "rtypew_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 11, "source": "mapping clause assembly = SHIFTIWOP(shamt, rs1, rd, op)\n if sizeof(xlen) == 64\n <-> shiftiwop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "SHIFTIWOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "shiftiwop_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 12, "source": "mapping clause assembly = FENCE(pred, succ)\n <-> \"fence\" ^ spc() ^ fence_bits(pred) ^ sep() ^ fence_bits(succ)", "left": { "type": "app", "id": "FENCE", "patterns": [ { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fence\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "fence_bits", "patterns": [ { "type": "id", "id": "pred" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "fence_bits", "patterns": [ { "type": "id", "id": "succ" } ] } ] } }, { "number": 13, "source": "mapping clause assembly = FENCE_TSO(pred, succ)\n <-> \"fence.tso\" ^ spc() ^ fence_bits(pred) ^ sep() ^ fence_bits(succ)", "left": { "type": "app", "id": "FENCE_TSO", "patterns": [ { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fence.tso\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "fence_bits", "patterns": [ { "type": "id", "id": "pred" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "fence_bits", "patterns": [ { "type": "id", "id": "succ" } ] } ] } }, { "number": 14, "source": "mapping clause assembly = FENCEI() <-> \"fence.i\"", "left": { "type": "app", "id": "FENCEI", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"fence.i\"" } }, { "number": 15, "source": "mapping clause assembly = ECALL() <-> \"ecall\"", "left": { "type": "app", "id": "ECALL", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"ecall\"" } }, { "number": 16, "source": "mapping clause assembly = MRET() <-> \"mret\"", "left": { "type": "app", "id": "MRET", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"mret\"" } }, { "number": 17, "source": "mapping clause assembly = SRET() <-> \"sret\"", "left": { "type": "app", "id": "SRET", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"sret\"" } }, { "number": 18, "source": "mapping clause assembly = EBREAK() <-> \"ebreak\"", "left": { "type": "app", "id": "EBREAK", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"ebreak\"" } }, { "number": 19, "source": "mapping clause assembly = WFI() <-> \"wfi\"", "left": { "type": "app", "id": "WFI", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"wfi\"" } }, { "number": 20, "source": "mapping clause assembly = SFENCE_VMA(rs1, rs2)\n <-> \"sfence.vma\" ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "SFENCE_VMA", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sfence.vma\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 21, "source": "mapping clause assembly = LOADRES(aq, rl, rs1, size, rd)\n <-> \"lr.\" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\"", "left": { "type": "app", "id": "LOADRES", "patterns": [ { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "size" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"lr.\"" }, { "type": "app", "id": "size_mnemonic", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "app", "id": "maybe_aq", "patterns": [ { "type": "id", "id": "aq" } ] }, { "type": "app", "id": "maybe_rl", "patterns": [ { "type": "id", "id": "rl" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 22, "source": "mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd)\n <-> \"sc.\" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs2) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\"", "left": { "type": "app", "id": "STORECON", "patterns": [ { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "size" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sc.\"" }, { "type": "app", "id": "size_mnemonic", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "app", "id": "maybe_aq", "patterns": [ { "type": "id", "id": "aq" } ] }, { "type": "app", "id": "maybe_rl", "patterns": [ { "type": "id", "id": "rl" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 23, "source": "mapping clause assembly = AMO(op, aq, rl, rs2, rs1, width, rd)\n <-> amo_mnemonic(op) ^ \".\" ^ size_mnemonic(width) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs2) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\"", "left": { "type": "app", "id": "AMO", "patterns": [ { "type": "id", "id": "op" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "amo_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "literal", "value": "\".\"" }, { "type": "app", "id": "size_mnemonic", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "app", "id": "maybe_aq", "patterns": [ { "type": "id", "id": "aq" } ] }, { "type": "app", "id": "maybe_rl", "patterns": [ { "type": "id", "id": "rl" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 24, "source": "mapping clause assembly = C_NOP() <-> \"c.nop\"", "left": { "type": "app", "id": "C_NOP", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"c.nop\"" } }, { "number": 25, "source": "mapping clause assembly = C_ADDI4SPN(rdc, nzimm)\n if nzimm != 0b00000000\n <-> \"c.addi4spn\" ^ spc() ^ creg_name(rdc) ^ sep() ^ hex_bits_10(nzimm @ 0b00)\n if nzimm != 0b00000000", "left": { "type": "app", "id": "C_ADDI4SPN", "patterns": [ { "type": "id", "id": "rdc" }, { "type": "id", "id": "nzimm" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.addi4spn\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rdc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_10", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nzimm" }, { "type": "literal", "value": "0b00" } ] } ] } ] } }, { "number": 26, "source": "mapping clause assembly = C_LW(uimm, rsc, rdc)\n <-> \"c.lw\" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_7(uimm @ 0b00)", "left": { "type": "app", "id": "C_LW", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc" }, { "type": "id", "id": "rdc" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.lw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rdc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_7", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b00" } ] } ] } ] } }, { "number": 27, "source": "mapping clause assembly = C_LD(uimm, rsc, rdc)\n if sizeof(xlen) == 64\n <-> \"c.ld\" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_8(uimm @ 0b000)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_LD", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc" }, { "type": "id", "id": "rdc" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.ld\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rdc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_8", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b000" } ] } ] } ] } }, { "number": 28, "source": "mapping clause assembly = C_SW(uimm, rsc1, rsc2)\n <-> \"c.sw\" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_7(uimm @ 0b00)", "left": { "type": "app", "id": "C_SW", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc1" }, { "type": "id", "id": "rsc2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.sw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_7", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b00" } ] } ] } ] } }, { "number": 29, "source": "mapping clause assembly = C_SD(uimm, rsc1, rsc2)\n if sizeof(xlen) == 64\n <-> \"c.sd\" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm @ 0b000)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_SD", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc1" }, { "type": "id", "id": "rsc2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.sd\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_8", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b000" } ] } ] } ] } }, { "number": 30, "source": "mapping clause assembly = C_ADDI(nzi, rsd)\n if nzi != 0b000000 & rsd != zreg\n <-> \"c.addi\" ^ spc() ^ reg_name(rsd) ^ sep() ^ hex_bits_6(nzi)\n if nzi != 0b000000 & rsd != zreg", "left": { "type": "app", "id": "C_ADDI", "patterns": [ { "type": "id", "id": "nzi" }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.addi\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "nzi" } ] } ] } }, { "number": 31, "source": "mapping clause assembly = C_JAL(imm)\n if sizeof(xlen) == 32\n <-> \"c.jal\" ^ spc() ^ hex_bits_12(imm @ 0b0)\n if sizeof(xlen) == 32", "left": { "type": "app", "id": "C_JAL", "patterns": [ { "type": "id", "id": "imm" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.jal\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "literal", "value": "0b0" } ] } ] } ] } }, { "number": 32, "source": "mapping clause assembly = C_ADDIW(imm, rsd)\n if sizeof(xlen) == 64\n <-> \"c.addiw\" ^ spc() ^ reg_name(rsd) ^ sep() ^ hex_bits_6(imm)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_ADDIW", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.addiw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 33, "source": "mapping clause assembly = C_LI(imm, rd)\n if rd != zreg\n <-> \"c.li\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(imm)\n if rd != zreg", "left": { "type": "app", "id": "C_LI", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.li\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 34, "source": "mapping clause assembly = C_ADDI16SP(imm)\n if imm != 0b000000\n <-> \"c.addi16sp\" ^ spc() ^ hex_bits_6(imm)\n if imm != 0b000000", "left": { "type": "app", "id": "C_ADDI16SP", "patterns": [ { "type": "id", "id": "imm" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.addi16sp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 35, "source": "mapping clause assembly = C_LUI(imm, rd)\n if rd != zreg & rd != sp & imm != 0b000000\n <-> \"c.lui\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(imm)\n if rd != zreg & rd != sp & imm != 0b000000", "left": { "type": "app", "id": "C_LUI", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.lui\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 36, "source": "mapping clause assembly = C_SRLI(shamt, rsd)\n if shamt != 0b000000\n <-> \"c.srli\" ^ spc() ^ creg_name(rsd) ^ sep() ^ hex_bits_6(shamt)\n if shamt != 0b000000", "left": { "type": "app", "id": "C_SRLI", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.srli\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 37, "source": "mapping clause assembly = C_SRAI(shamt, rsd)\n if shamt != 0b000000\n <-> \"c.srai\" ^ spc() ^ creg_name(rsd) ^ sep() ^ hex_bits_6(shamt)\n if shamt != 0b000000", "left": { "type": "app", "id": "C_SRAI", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.srai\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 38, "source": "mapping clause assembly = C_ANDI(imm, rsd)\n <-> \"c.andi\" ^ spc() ^ creg_name(rsd) ^ sep() ^ hex_bits_6(imm)", "left": { "type": "app", "id": "C_ANDI", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.andi\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 39, "source": "mapping clause assembly = C_SUB(rsd, rs2)\n <-> \"c.sub\" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2)", "left": { "type": "app", "id": "C_SUB", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.sub\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 40, "source": "mapping clause assembly = C_XOR(rsd, rs2)\n <-> \"c.xor\" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2)", "left": { "type": "app", "id": "C_XOR", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.xor\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 41, "source": "mapping clause assembly = C_OR(rsd, rs2)\n <-> \"c.or\" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2)", "left": { "type": "app", "id": "C_OR", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.or\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 42, "source": "mapping clause assembly = C_AND(rsd, rs2)\n <-> \"c.and\" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2)", "left": { "type": "app", "id": "C_AND", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.and\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 43, "source": "mapping clause assembly = C_SUBW(rsd, rs2)\n if sizeof(xlen) == 64\n <-> \"c.subw\" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_SUBW", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.subw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 44, "source": "mapping clause assembly = C_ADDW(rsd, rs2)\n if sizeof(xlen) == 64\n <-> \"c.addw\" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_ADDW", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.addw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 45, "source": "mapping clause assembly = C_J(imm)\n <-> \"c.j\" ^ spc() ^ hex_bits_11(imm)", "left": { "type": "app", "id": "C_J", "patterns": [ { "type": "id", "id": "imm" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.j\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_11", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 46, "source": "mapping clause assembly = C_BEQZ(imm, rs)\n <-> \"c.beqz\" ^ spc() ^ creg_name(rs) ^ sep() ^ hex_bits_8(imm)", "left": { "type": "app", "id": "C_BEQZ", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.beqz\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rs" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_8", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 47, "source": "mapping clause assembly = C_BNEZ(imm, rs)\n <-> \"c.bnez\" ^ spc() ^ creg_name(rs) ^ sep() ^ hex_bits_8(imm)", "left": { "type": "app", "id": "C_BNEZ", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.bnez\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rs" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_8", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 48, "source": "mapping clause assembly = C_SLLI(shamt, rsd)\n if shamt != 0b000000 & rsd != zreg\n <-> \"c.slli\" ^ spc() ^ reg_name(rsd) ^ sep() ^ hex_bits_6(shamt)\n if shamt != 0b000000 & rsd != zreg", "left": { "type": "app", "id": "C_SLLI", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.slli\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 49, "source": "mapping clause assembly = C_LWSP(uimm, rd)\n if rd != zreg\n <-> \"c.lwsp\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm)\n if rd != zreg", "left": { "type": "app", "id": "C_LWSP", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.lwsp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "uimm" } ] } ] } }, { "number": 50, "source": "mapping clause assembly = C_LDSP(uimm, rd)\n if rd != zreg & sizeof(xlen) == 64\n <-> \"c.ldsp\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm)\n if rd != zreg & sizeof(xlen) == 64", "left": { "type": "app", "id": "C_LDSP", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.ldsp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "uimm" } ] } ] } }, { "number": 51, "source": "mapping clause assembly = C_SWSP(uimm, rs2)\n <-> \"c.swsp\" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_6(uimm)", "left": { "type": "app", "id": "C_SWSP", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.swsp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "uimm" } ] } ] } }, { "number": 52, "source": "mapping clause assembly = C_SDSP(uimm, rs2)\n if sizeof(xlen) == 64\n <-> \"c.sdsp\" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_6(uimm)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_SDSP", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.sdsp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "uimm" } ] } ] } }, { "number": 53, "source": "mapping clause assembly = C_JR(rs1)\n if rs1 != zreg\n <-> \"c.jr\" ^ spc() ^ reg_name(rs1)\n if rs1 != zreg", "left": { "type": "app", "id": "C_JR", "patterns": [ { "type": "id", "id": "rs1" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.jr\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 54, "source": "mapping clause assembly = C_JALR(rs1)\n if rs1 != zreg\n <-> \"c.jalr\" ^ spc() ^ reg_name(rs1)\n if rs1 != zreg", "left": { "type": "app", "id": "C_JALR", "patterns": [ { "type": "id", "id": "rs1" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.jalr\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 55, "source": "mapping clause assembly = C_MV(rd, rs2)\n if rd != zreg & rs2 != zreg\n <-> \"c.mv\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs2)\n if rd != zreg & rs2 != zreg", "left": { "type": "app", "id": "C_MV", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.mv\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 56, "source": "mapping clause assembly = C_EBREAK() <-> \"c.ebreak\"", "left": { "type": "app", "id": "C_EBREAK", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"c.ebreak\"" } }, { "number": 57, "source": "mapping clause assembly = C_ADD(rsd, rs2)\n if rsd != zreg & rs2 != zreg\n <-> \"c.add\" ^ spc() ^ reg_name(rsd) ^ sep() ^ reg_name(rs2)\n if rsd != zreg & rs2 != zreg", "left": { "type": "app", "id": "C_ADD", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.add\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 58, "source": "mapping clause assembly = MUL(rs2, rs1, rd, high, signed1, signed2)\n <-> mul_mnemonic(high, signed1, signed2) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "MUL", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "high" }, { "type": "id", "id": "signed1" }, { "type": "id", "id": "signed2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "mul_mnemonic", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "high" }, { "type": "id", "id": "signed1" }, { "type": "id", "id": "signed2" } ] } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 59, "source": "mapping clause assembly = DIV(rs2, rs1, rd, s)\n <-> \"div\" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "DIV", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"div\"" }, { "type": "app", "id": "maybe_not_u", "patterns": [ { "type": "id", "id": "s" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 60, "source": "mapping clause assembly = REM(rs2, rs1, rd, s)\n <-> \"rem\" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "REM", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"rem\"" }, { "type": "app", "id": "maybe_not_u", "patterns": [ { "type": "id", "id": "s" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 61, "source": "mapping clause assembly = MULW(rs2, rs1, rd)\n if sizeof(xlen) == 64\n <-> \"mulw\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "MULW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"mulw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 62, "source": "mapping clause assembly = DIVW(rs2, rs1, rd, s)\n if sizeof(xlen) == 64\n <-> \"div\" ^ maybe_not_u(s) ^ \"w\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "DIVW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"div\"" }, { "type": "app", "id": "maybe_not_u", "patterns": [ { "type": "id", "id": "s" } ] }, { "type": "literal", "value": "\"w\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 63, "source": "mapping clause assembly = REMW(rs2, rs1, rd, s)\n if sizeof(xlen) == 64\n <-> \"rem\" ^ maybe_not_u(s) ^ \"w\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "REMW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"rem\"" }, { "type": "app", "id": "maybe_not_u", "patterns": [ { "type": "id", "id": "s" } ] }, { "type": "literal", "value": "\"w\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 64, "source": "mapping clause assembly = CSR(csr, rs1, rd, true, op)\n <-> csr_mnemonic(op) ^ \"i\" ^ spc() ^ reg_name(rd) ^ sep() ^ csr_name_map(csr) ^ sep() ^ hex_bits_5(rs1)", "left": { "type": "app", "id": "CSR", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "true" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "csr_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "literal", "value": "\"i\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "csr_name_map", "patterns": [ { "type": "id", "id": "csr" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 65, "source": "mapping clause assembly = CSR(csr, rs1, rd, false, op)\n <-> csr_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ csr_name_map(csr) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "CSR", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "false" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "csr_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "csr_name_map", "patterns": [ { "type": "id", "id": "csr" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 66, "source": "mapping clause assembly = URET() <-> \"uret\"", "left": { "type": "app", "id": "URET", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "literal", "value": "\"uret\"" } }, { "number": 67, "source": "mapping clause assembly = C_NOP_HINT(imm) <-> \"c.nop.hint.\" ^ hex_bits_6(imm)", "left": { "type": "app", "id": "C_NOP_HINT", "patterns": [ { "type": "id", "id": "imm" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.nop.hint.\"" }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 68, "source": "mapping clause assembly = C_ADDI_HINT(rsd)\n if rsd != zreg\n <-> \"c.addi.hint.\" ^ reg_name(rsd)\n if rsd != zreg", "left": { "type": "app", "id": "C_ADDI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.addi.hint.\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rsd" } ] } ] } }, { "number": 69, "source": "mapping clause assembly = C_LI_HINT(imm)\n <-> \"c.li.hint.\" ^ hex_bits_6(imm)", "left": { "type": "app", "id": "C_LI_HINT", "patterns": [ { "type": "id", "id": "imm" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.li.hint.\"" }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 70, "source": "mapping clause assembly = C_LUI_HINT(imm)\n if imm != 0b000000\n <-> \"c.lui.hint.\" ^ hex_bits_6(imm)\n if imm != 0b000000", "left": { "type": "app", "id": "C_LUI_HINT", "patterns": [ { "type": "id", "id": "imm" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.lui.hint.\"" }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 71, "source": "mapping clause assembly = C_MV_HINT(rs2)\n if rs2 != zreg\n <-> \"c.mv.hint.\" ^ reg_name(rs2)\n if rs2 != zreg", "left": { "type": "app", "id": "C_MV_HINT", "patterns": [ { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.mv.hint.\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 72, "source": "mapping clause assembly = C_ADD_HINT(rs2)\n if rs2 != zreg\n <-> \"c.add.hint.\" ^ reg_name(rs2)\n if rs2 != zreg", "left": { "type": "app", "id": "C_ADD_HINT", "patterns": [ { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.add.hint.\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 73, "source": "mapping clause assembly = C_SLLI_HINT(shamt, rsd)\n if shamt == 0b000000 | rsd == zreg\n <-> \"c.slli.hint.\" ^ reg_name(rsd) ^ \".\" ^ hex_bits_6(shamt)\n if shamt == 0b000000 | rsd == zreg", "left": { "type": "app", "id": "C_SLLI_HINT", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.slli.hint.\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rsd" } ] }, { "type": "literal", "value": "\".\"" }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 74, "source": "mapping clause assembly = C_SRLI_HINT(rsd)\n <-> \"c.srli.hint.\" ^ creg_name(rsd)", "left": { "type": "app", "id": "C_SRLI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.srli.hint.\"" }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] } ] } }, { "number": 75, "source": "mapping clause assembly = C_SRAI_HINT(rsd)\n <-> \"c.srai.hint.\" ^ creg_name(rsd)", "left": { "type": "app", "id": "C_SRAI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.srai.hint.\"" }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsd" } ] } ] } }, { "number": 76, "source": "mapping clause assembly = FENCE_RESERVED(fm, pred, succ, rs, rd)\n if (fm != 0b0000 & fm != 0b1000) | rs != 0b00000 | rd != 0b00000\n <-> \"fence.reserved.\" ^ fence_bits(pred) ^ \".\" ^ fence_bits(succ) ^ \".\"\n ^ reg_name(rs) ^ \".\" ^ reg_name(rd) ^ \".\" ^ hex_bits_4(fm)\n if (fm != 0b0000 & fm != 0b1000) | rs != 0b00000 | rd != 0b00000", "left": { "type": "app", "id": "FENCE_RESERVED", "patterns": [ { "type": "id", "id": "fm" }, { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" }, { "type": "id", "id": "rs" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fence.reserved.\"" }, { "type": "app", "id": "fence_bits", "patterns": [ { "type": "id", "id": "pred" } ] }, { "type": "literal", "value": "\".\"" }, { "type": "app", "id": "fence_bits", "patterns": [ { "type": "id", "id": "succ" } ] }, { "type": "literal", "value": "\".\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs" } ] }, { "type": "literal", "value": "\".\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "literal", "value": "\".\"" }, { "type": "app", "id": "hex_bits_4", "patterns": [ { "type": "id", "id": "fm" } ] } ] } }, { "number": 77, "source": "mapping clause assembly = FENCEI_RESERVED(imm, rs, rd)\n if imm != 0b000000000000 | rs != zreg | rd != zreg\n <-> \"fence.i.reserved.\" ^ reg_name(rd) ^ \".\" ^ reg_name(rs) ^ \".\" ^ hex_bits_12(imm)\n if imm != 0b000000000000 | rs != zreg | rd != zreg", "left": { "type": "app", "id": "FENCEI_RESERVED", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fence.i.reserved.\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "literal", "value": "\".\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs" } ] }, { "type": "literal", "value": "\".\"" }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 78, "source": "mapping clause assembly = LOAD_FP(imm, rs1, rd, width)\n <-> \"fl\" ^ size_mnemonic(width)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ hex_bits_12(imm)\n ^ opt_spc() ^ \"(\" ^ opt_spc() ^ reg_name(rs1) ^ opt_spc() ^ \")\"", "left": { "type": "app", "id": "LOAD_FP", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "width" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fl\"" }, { "type": "app", "id": "size_mnemonic", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "imm" } ] }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 79, "source": "mapping clause assembly = STORE_FP(imm, rs2, rs1, width)\n <-> \"fs\" ^ size_mnemonic(width)\n ^ spc() ^ freg_name(rs2)\n ^ sep() ^ hex_bits_12(imm)\n ^ opt_spc() ^ \"(\" ^ opt_spc() ^ reg_name(rs1) ^ opt_spc() ^ \")\"", "left": { "type": "app", "id": "STORE_FP", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fs\"" }, { "type": "app", "id": "size_mnemonic", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "imm" } ] }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "opt_spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 80, "source": "mapping clause assembly = F_MADD_TYPE_S(rs3, rs2, rs1, rm, rd, op)\n <-> f_madd_type_mnemonic_S(op)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)\n ^ sep() ^ freg_or_reg_name(rs3)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_MADD_TYPE_S", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_madd_type_mnemonic_S", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 81, "source": "mapping clause assembly = F_BIN_RM_TYPE_S(rs2, rs1, rm, rd, op)\n <-> f_bin_rm_type_mnemonic_S(op)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_BIN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 82, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FSQRT_S)\n <-> f_un_rm_type_mnemonic_S(FSQRT_S)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FSQRT_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 83, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_W_S)\n <-> f_un_rm_type_mnemonic_S(FCVT_W_S)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCVT_W_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 84, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_WU_S)\n <-> f_un_rm_type_mnemonic_S(FCVT_WU_S)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCVT_WU_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 85, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_W)\n <-> f_un_rm_type_mnemonic_S(FCVT_S_W)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_W" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCVT_S_W" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 86, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_WU)\n <-> f_un_rm_type_mnemonic_S(FCVT_S_WU)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_WU" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCVT_S_WU" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 87, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S)\n <-> f_un_rm_type_mnemonic_S(FCVT_L_S)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCVT_L_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 88, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S)\n <-> f_un_rm_type_mnemonic_S(FCVT_LU_S)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCVT_LU_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 89, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L)\n <-> f_un_rm_type_mnemonic_S(FCVT_S_L)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_L" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCVT_S_L" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 90, "source": "mapping clause assembly = F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_LU)\n <-> f_un_rm_type_mnemonic_S(FCVT_S_LU)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_LU" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCVT_S_LU" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 91, "source": "mapping clause assembly = F_BIN_TYPE_S(rs2, rs1, rd, FSGNJ_S)\n <-> f_bin_type_mnemonic_S(FSGNJ_S)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FSGNJ_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 92, "source": "mapping clause assembly = F_BIN_TYPE_S(rs2, rs1, rd, FSGNJN_S)\n <-> f_bin_type_mnemonic_S(FSGNJN_S)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FSGNJN_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 93, "source": "mapping clause assembly = F_BIN_TYPE_S(rs2, rs1, rd, FSGNJX_S)\n <-> f_bin_type_mnemonic_S(FSGNJX_S)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FSGNJX_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 94, "source": "mapping clause assembly = F_BIN_TYPE_S(rs2, rs1, rd, FMIN_S)\n <-> f_bin_type_mnemonic_S(FMIN_S)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FMIN_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 95, "source": "mapping clause assembly = F_BIN_TYPE_S(rs2, rs1, rd, FMAX_S)\n <-> f_bin_type_mnemonic_S(FMAX_S)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FMAX_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 96, "source": "mapping clause assembly = F_BIN_TYPE_S(rs2, rs1, rd, FEQ_S)\n <-> f_bin_type_mnemonic_S(FEQ_S)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FEQ_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 97, "source": "mapping clause assembly = F_BIN_TYPE_S(rs2, rs1, rd, FLT_S)\n <-> f_bin_type_mnemonic_S(FLT_S)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FLT_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 98, "source": "mapping clause assembly = F_BIN_TYPE_S(rs2, rs1, rd, FLE_S)\n <-> f_bin_type_mnemonic_S(FLE_S)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FLE_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 99, "source": "mapping clause assembly = F_UN_TYPE_S(rs1, rd, FMV_X_W)\n <-> f_un_type_mnemonic_S(FMV_X_W)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_W" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FMV_X_W" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 100, "source": "mapping clause assembly = F_UN_TYPE_S(rs1, rd, FMV_W_X)\n <-> f_un_type_mnemonic_S(FMV_W_X)\n ^ spc() ^ freg_name(rd)\n ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_W_X" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FMV_W_X" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 101, "source": "mapping clause assembly = F_UN_TYPE_S(rs1, rd, FCLASS_S)\n <-> f_un_type_mnemonic_S(FCLASS_S)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_S", "patterns": [ { "type": "id", "id": "FCLASS_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 102, "source": "mapping clause assembly = C_FLWSP(imm, rd)\n if sizeof(xlen) == 32\n <-> \"c.flwsp\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(imm)\n if sizeof(xlen) == 32", "left": { "type": "app", "id": "C_FLWSP", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.flwsp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "imm" } ] } ] } }, { "number": 103, "source": "mapping clause assembly = C_FSWSP(uimm, rs2)\n if sizeof(xlen) == 32\n <-> \"c.fswsp\" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_6(uimm)\n if sizeof(xlen) == 32", "left": { "type": "app", "id": "C_FSWSP", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.fswsp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "uimm" } ] } ] } }, { "number": 104, "source": "mapping clause assembly = C_FLW(uimm, rsc, rdc)\n if sizeof(xlen) == 32\n <-> \"c.flw\" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_7(uimm @ 0b00)\n if sizeof(xlen) == 32", "left": { "type": "app", "id": "C_FLW", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc" }, { "type": "id", "id": "rdc" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.flw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rdc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_7", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b00" } ] } ] } ] } }, { "number": 105, "source": "mapping clause assembly = C_FSW(uimm, rsc1, rsc2)\n if sizeof(xlen) == 32\n <-> \"c.fsw\" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_7(uimm @ 0b00)\n if sizeof(xlen) == 32", "left": { "type": "app", "id": "C_FSW", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc1" }, { "type": "id", "id": "rsc2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.fsw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_7", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b00" } ] } ] } ] } }, { "number": 106, "source": "mapping clause assembly = F_MADD_TYPE_D(rs3, rs2, rs1, rm, rd, op)\n <-> f_madd_type_mnemonic_D(op)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)\n ^ sep() ^ freg_or_reg_name(rs3)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_MADD_TYPE_D", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_madd_type_mnemonic_D", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 107, "source": "mapping clause assembly = F_BIN_RM_TYPE_D(rs2, rs1, rm, rd, op)\n <-> f_bin_rm_type_mnemonic_D(op)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_BIN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 108, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FSQRT_D)\n <-> f_un_rm_type_mnemonic_D(FSQRT_D)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FSQRT_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 109, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_W_D)\n <-> f_un_rm_type_mnemonic_D(FCVT_W_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_W_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 110, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_WU_D)\n <-> f_un_rm_type_mnemonic_D(FCVT_WU_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_WU_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 111, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_W)\n <-> f_un_rm_type_mnemonic_D(FCVT_D_W)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_W" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_D_W" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 112, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_WU)\n <-> f_un_rm_type_mnemonic_D(FCVT_D_WU)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_WU" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_D_WU" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 113, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D)\n <-> f_un_rm_type_mnemonic_D(FCVT_L_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_L_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 114, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D)\n <-> f_un_rm_type_mnemonic_D(FCVT_LU_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_LU_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 115, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L)\n <-> f_un_rm_type_mnemonic_D(FCVT_D_L)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_L" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_D_L" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 116, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU)\n <-> f_un_rm_type_mnemonic_D(FCVT_D_LU)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_LU" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_D_LU" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 117, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_S_D)\n <-> f_un_rm_type_mnemonic_D(FCVT_S_D)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_S_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 118, "source": "mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_S)\n <-> f_un_rm_type_mnemonic_D(FCVT_D_S)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCVT_D_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 119, "source": "mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJ_D)\n <-> f_bin_type_mnemonic_D(FSGNJ_D)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FSGNJ_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 120, "source": "mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJN_D)\n <-> f_bin_type_mnemonic_D(FSGNJN_D)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FSGNJN_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 121, "source": "mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJX_D)\n <-> f_bin_type_mnemonic_D(FSGNJX_D)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FSGNJX_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 122, "source": "mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FMIN_D)\n <-> f_bin_type_mnemonic_D(FMIN_D)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FMIN_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 123, "source": "mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FMAX_D)\n <-> f_bin_type_mnemonic_D(FMAX_D)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FMAX_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 124, "source": "mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FEQ_D)\n <-> f_bin_type_mnemonic_D(FEQ_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FEQ_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 125, "source": "mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FLT_D)\n <-> f_bin_type_mnemonic_D(FLT_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FLT_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 126, "source": "mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FLE_D)\n <-> f_bin_type_mnemonic_D(FLE_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FLE_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 127, "source": "mapping clause assembly = F_UN_TYPE_D(rs1, rd, FMV_X_D)\n <-> f_un_type_mnemonic_D(FMV_X_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FMV_X_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 128, "source": "mapping clause assembly = F_UN_TYPE_D(rs1, rd, FMV_D_X)\n <-> f_un_type_mnemonic_D(FMV_D_X)\n ^ spc() ^ freg_name(rd)\n ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_D_X" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FMV_D_X" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 129, "source": "mapping clause assembly = F_UN_TYPE_D(rs1, rd, FCLASS_D)\n <-> f_un_type_mnemonic_D(FCLASS_D)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_D", "patterns": [ { "type": "id", "id": "FCLASS_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 130, "source": "mapping clause assembly = C_FLDSP(uimm, rd)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64)\n <-> \"c.fldsp\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64)", "left": { "type": "app", "id": "C_FLDSP", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.fldsp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "uimm" } ] } ] } }, { "number": 131, "source": "mapping clause assembly = C_FSDSP(uimm, rs2)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64)\n <-> \"c.fsdsp\" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_6(uimm)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64)", "left": { "type": "app", "id": "C_FSDSP", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.fsdsp\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "uimm" } ] } ] } }, { "number": 132, "source": "mapping clause assembly = C_FLD(uimm, rsc, rdc)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64)\n <-> \"c.fld\" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_8(uimm @ 0b000)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64)", "left": { "type": "app", "id": "C_FLD", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc" }, { "type": "id", "id": "rdc" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.fld\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rdc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_8", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b000" } ] } ] } ] } }, { "number": 133, "source": "mapping clause assembly = C_FSD(uimm, rsc1, rsc2)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64)\n <-> \"c.fsd\" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm @ 0b000)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64)", "left": { "type": "app", "id": "C_FSD", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "id", "id": "rsc1" }, { "type": "id", "id": "rsc2" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.fsd\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "creg_name", "patterns": [ { "type": "id", "id": "rsc2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_8", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b000" } ] } ] } ] } }, { "number": 134, "source": "mapping clause assembly = RISCV_SLLIUW(shamt, rs1, rd)\n <-> \"slli.uw\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_6(shamt)", "left": { "type": "app", "id": "RISCV_SLLIUW", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"slli.uw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 135, "source": "mapping clause assembly = ZBA_RTYPEUW(rs2, rs1, rd, op)\n <-> zba_rtypeuw_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "ZBA_RTYPEUW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zba_rtypeuw_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 136, "source": "mapping clause assembly = ZBA_RTYPE(rs2, rs1, rd, op)\n <-> zba_rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "ZBA_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zba_rtype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 137, "source": "mapping clause assembly = RISCV_RORIW(shamt, rs1, rd)\n <-> \"roriw\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt)", "left": { "type": "app", "id": "RISCV_RORIW", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"roriw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 138, "source": "mapping clause assembly = RISCV_RORI(shamt, rs1, rd)\n <-> \"rori\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_6(shamt)", "left": { "type": "app", "id": "RISCV_RORI", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"rori\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 139, "source": "mapping clause assembly = ZBB_RTYPEW(rs2, rs1, rd, op)\n <-> zbb_rtypew_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "ZBB_RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zbb_rtypew_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 140, "source": "mapping clause assembly = ZBB_RTYPE(rs2, rs1, rd, op)\n <-> zbb_rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zbb_rtype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 141, "source": "mapping clause assembly = ZBB_EXTOP(rs1, rd, op)\n <-> zbb_extop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "ZBB_EXTOP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zbb_extop_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 142, "source": "mapping clause assembly = RISCV_REV8(rs1, rd)\n <-> \"rev8\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_REV8", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"rev8\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 143, "source": "mapping clause assembly = RISCV_ORCB(rs1, rd)\n <-> \"orc.b\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_ORCB", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"orc.b\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 144, "source": "mapping clause assembly = RISCV_CPOP(rs1, rd)\n <-> \"cpop\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_CPOP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"cpop\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 145, "source": "mapping clause assembly = RISCV_CPOPW(rs1, rd)\n <-> \"cpopw\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_CPOPW", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"cpopw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 146, "source": "mapping clause assembly = RISCV_CLZ(rs1, rd)\n <-> \"clz\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_CLZ", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"clz\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 147, "source": "mapping clause assembly = RISCV_CLZW(rs1, rd)\n <-> \"clzw\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_CLZW", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"clzw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 148, "source": "mapping clause assembly = RISCV_CTZ(rs1, rd)\n <-> \"ctz\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_CTZ", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"ctz\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 149, "source": "mapping clause assembly = RISCV_CTZW(rs1, rd)\n <-> \"ctzw\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_CTZW", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"ctzw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 150, "source": "mapping clause assembly = RISCV_CLMUL(rs2, rs1, rd)\n <-> \"clmul\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "RISCV_CLMUL", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"clmul\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 151, "source": "mapping clause assembly = RISCV_CLMULH(rs2, rs1, rd)\n <-> \"clmulh\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "RISCV_CLMULH", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"clmulh\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 152, "source": "mapping clause assembly = RISCV_CLMULR(rs2, rs1, rd)\n <-> \"clmulr\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "RISCV_CLMULR", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"clmulr\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 153, "source": "mapping clause assembly = ZBS_IOP(shamt, rs1, rd, op)\n <-> zbs_iop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_6(shamt)", "left": { "type": "app", "id": "ZBS_IOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zbs_iop_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_6", "patterns": [ { "type": "id", "id": "shamt" } ] } ] } }, { "number": 154, "source": "mapping clause assembly = ZBS_RTYPE(rs2, rs1, rd, op)\n <-> zbs_rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "ZBS_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zbs_rtype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 155, "source": "mapping clause assembly = F_BIN_RM_TYPE_H(rs2, rs1, rm, rd, op)\n <-> f_bin_rm_type_mnemonic_H(op)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_BIN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 156, "source": "mapping clause assembly = F_MADD_TYPE_H(rs3, rs2, rs1, rm, rd, op)\n <-> f_madd_type_mnemonic_H(op)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)\n ^ sep() ^ freg_or_reg_name(rs3)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_MADD_TYPE_H", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_madd_type_mnemonic_H", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 157, "source": "mapping clause assembly = F_BIN_TYPE_H(rs2, rs1, rd, FSGNJ_H)\n <-> f_bin_type_mnemonic_H(FSGNJ_H)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FSGNJ_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 158, "source": "mapping clause assembly = F_BIN_TYPE_H(rs2, rs1, rd, FSGNJN_H)\n <-> f_bin_type_mnemonic_H(FSGNJN_H)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FSGNJN_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 159, "source": "mapping clause assembly = F_BIN_TYPE_H(rs2, rs1, rd, FSGNJX_H)\n <-> f_bin_type_mnemonic_H(FSGNJX_H)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FSGNJX_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 160, "source": "mapping clause assembly = F_BIN_TYPE_H(rs2, rs1, rd, FMIN_H)\n <-> f_bin_type_mnemonic_H(FMIN_H)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FMIN_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 161, "source": "mapping clause assembly = F_BIN_TYPE_H(rs2, rs1, rd, FMAX_H)\n <-> f_bin_type_mnemonic_H(FMAX_H)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FMAX_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 162, "source": "mapping clause assembly = F_BIN_TYPE_H(rs2, rs1, rd, FEQ_H)\n <-> f_bin_type_mnemonic_H(FEQ_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FEQ_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 163, "source": "mapping clause assembly = F_BIN_TYPE_H(rs2, rs1, rd, FLT_H)\n <-> f_bin_type_mnemonic_H(FLT_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FLT_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 164, "source": "mapping clause assembly = F_BIN_TYPE_H(rs2, rs1, rd, FLE_H)\n <-> f_bin_type_mnemonic_H(FLE_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ freg_or_reg_name(rs2)", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_bin_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FLE_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 165, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FSQRT_H)\n <-> f_un_rm_type_mnemonic_H(FSQRT_H)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FSQRT_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 166, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_W_H)\n <-> f_un_rm_type_mnemonic_H(FCVT_W_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_W_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 167, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_WU_H)\n <-> f_un_rm_type_mnemonic_H(FCVT_WU_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_WU_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 168, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_W)\n <-> f_un_rm_type_mnemonic_H(FCVT_H_W)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_W" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_H_W" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 169, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_WU)\n <-> f_un_rm_type_mnemonic_H(FCVT_H_WU)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_WU" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_H_WU" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 170, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_L_H)\n <-> f_un_rm_type_mnemonic_H(FCVT_L_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_L_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 171, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_LU_H)\n <-> f_un_rm_type_mnemonic_H(FCVT_LU_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_LU_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 172, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_L)\n <-> f_un_rm_type_mnemonic_H(FCVT_H_L)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_L" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_H_L" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 173, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_LU)\n <-> f_un_rm_type_mnemonic_H(FCVT_H_LU)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_LU" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_H_LU" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 174, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_S)\n <-> f_un_rm_type_mnemonic_H(FCVT_H_S)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_S" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_H_S" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 175, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_D)\n <-> f_un_rm_type_mnemonic_H(FCVT_H_D)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_D" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_H_D" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 176, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_S_H)\n <-> f_un_rm_type_mnemonic_H(FCVT_S_H)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_S_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 177, "source": "mapping clause assembly = F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_D_H)\n <-> f_un_rm_type_mnemonic_H(FCVT_D_H)\n ^ spc() ^ freg_or_reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_rm_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCVT_D_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 178, "source": "mapping clause assembly = F_UN_TYPE_H(rs1, rd, FMV_X_H)\n <-> f_un_type_mnemonic_H(FMV_X_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FMV_X_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 179, "source": "mapping clause assembly = F_UN_TYPE_H(rs1, rd, FMV_H_X)\n <-> f_un_type_mnemonic_H(FMV_H_X)\n ^ spc() ^ freg_name(rd)\n ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_H_X" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FMV_H_X" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 180, "source": "mapping clause assembly = F_UN_TYPE_H(rs1, rd, FCLASS_H)\n <-> f_un_type_mnemonic_H(FCLASS_H)\n ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_or_reg_name(rs1)", "left": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_H" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "f_un_type_mnemonic_H", "patterns": [ { "type": "id", "id": "FCLASS_H" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_or_reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 181, "source": "mapping clause assembly = RISCV_FLI_H(constantidx, rd)\n <-> \"fli.h\" ^ spc() ^ freg_name(rd) ^ sep() ^ hex_bits_5(constantidx)", "left": { "type": "app", "id": "RISCV_FLI_H", "patterns": [ { "type": "id", "id": "constantidx" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fli.h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "constantidx" } ] } ] } }, { "number": 182, "source": "mapping clause assembly = RISCV_FLI_S(constantidx, rd)\n <-> \"fli.s\" ^ spc() ^ freg_name(rd) ^ sep() ^ hex_bits_5(constantidx)", "left": { "type": "app", "id": "RISCV_FLI_S", "patterns": [ { "type": "id", "id": "constantidx" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fli.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "constantidx" } ] } ] } }, { "number": 183, "source": "mapping clause assembly = RISCV_FLI_D(constantidx, rd)\n <-> \"fli.d\" ^ spc() ^ freg_name(rd) ^ sep() ^ hex_bits_5(constantidx)", "left": { "type": "app", "id": "RISCV_FLI_D", "patterns": [ { "type": "id", "id": "constantidx" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fli.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "constantidx" } ] } ] } }, { "number": 184, "source": "mapping clause assembly = RISCV_FMINM_H(rs2, rs1, rd)\n <-> \"fminm.h\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FMINM_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fminm.h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 185, "source": "mapping clause assembly = RISCV_FMAXM_H(rs2, rs1, rd)\n <-> \"fmaxm.h\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FMAXM_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fmaxm.h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 186, "source": "mapping clause assembly = RISCV_FMINM_S(rs2, rs1, rd)\n <-> \"fminm.s\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FMINM_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fminm.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 187, "source": "mapping clause assembly = RISCV_FMAXM_S(rs2, rs1, rd)\n <-> \"fmaxm.s\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FMAXM_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fmaxm.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 188, "source": "mapping clause assembly = RISCV_FMINM_D(rs2, rs1, rd)\n <-> \"fminm.d\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FMINM_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fminm.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 189, "source": "mapping clause assembly = RISCV_FMAXM_D(rs2, rs1, rd)\n <-> \"fmaxm.d\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FMAXM_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fmaxm.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 190, "source": "mapping clause assembly = RISCV_FROUND_H(rs1, rm, rd)\n <-> \"fround.h\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "RISCV_FROUND_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fround.h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 191, "source": "mapping clause assembly = RISCV_FROUNDNX_H(rs1, rm, rd)\n <-> \"froundnx.h\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "RISCV_FROUNDNX_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"froundnx.h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 192, "source": "mapping clause assembly = RISCV_FROUND_S(rs1, rm, rd)\n <-> \"fround.s\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "RISCV_FROUND_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fround.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 193, "source": "mapping clause assembly = RISCV_FROUNDNX_S(rs1, rm, rd)\n <-> \"froundnx.s\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "RISCV_FROUNDNX_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"froundnx.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 194, "source": "mapping clause assembly = RISCV_FROUND_D(rs1, rm, rd)\n <-> \"fround.d\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "RISCV_FROUND_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fround.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 195, "source": "mapping clause assembly = RISCV_FROUNDNX_D(rs1, rm, rd)\n <-> \"froundnx.d\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ frm_mnemonic(rm)", "left": { "type": "app", "id": "RISCV_FROUNDNX_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"froundnx.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "frm_mnemonic", "patterns": [ { "type": "id", "id": "rm" } ] } ] } }, { "number": 196, "source": "mapping clause assembly = RISCV_FMVH_X_D(rs1, rd)\n <-> \"fmvh.x.d\" ^ spc() ^ reg_name(rd)\n ^ sep() ^ freg_name(rs1)", "left": { "type": "app", "id": "RISCV_FMVH_X_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fmvh.x.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 197, "source": "mapping clause assembly = RISCV_FMVP_D_X(rs2, rs1, rd)\n <-> \"fmvp.d.x\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ reg_name(rs1)\n ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "RISCV_FMVP_D_X", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fmvp.d.x\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 198, "source": "mapping clause assembly = RISCV_FLEQ_H(rs2, rs1, rd)\n <-> \"fleq.h\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FLEQ_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fleq.h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 199, "source": "mapping clause assembly = RISCV_FLTQ_H(rs2, rs1, rd)\n <-> \"fltq.h\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FLTQ_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fltq.h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 200, "source": "mapping clause assembly = RISCV_FLEQ_S(rs2, rs1, rd)\n <-> \"fleq.s\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FLEQ_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fleq.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 201, "source": "mapping clause assembly = RISCV_FLTQ_S(rs2, rs1, rd)\n <-> \"fltq.s\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FLTQ_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fltq.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 202, "source": "mapping clause assembly = RISCV_FLEQ_D(rs2, rs1, rd)\n <-> \"fleq.d\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FLEQ_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fleq.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 203, "source": "mapping clause assembly = RISCV_FLTQ_D(rs2, rs1, rd)\n <-> \"fltq.d\" ^ spc() ^ freg_name(rd)\n ^ sep() ^ freg_name(rs1)\n ^ sep() ^ freg_name(rs2)", "left": { "type": "app", "id": "RISCV_FLTQ_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fltq.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 204, "source": "mapping clause assembly = RISCV_FCVTMOD_W_D(rs1, rd)\n <-> \"fcvtmod.w.d\" ^ spc() ^ reg_name(rd)\n\t\t ^ sep() ^ freg_name(rs1)", "left": { "type": "app", "id": "RISCV_FCVTMOD_W_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"fcvtmod.w.d\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 205, "source": "mapping clause assembly = SHA256SIG0 (rs1, rd)\n <-> \"sha256sig0\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SHA256SIG0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha256sig0\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 206, "source": "mapping clause assembly = SHA256SIG1 (rs1, rd)\n <-> \"sha256sig1\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SHA256SIG1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha256sig1\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 207, "source": "mapping clause assembly = SHA256SUM0 (rs1, rd)\n <-> \"sha256sum0\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SHA256SUM0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha256sum0\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 208, "source": "mapping clause assembly = SHA256SUM1 (rs1, rd)\n <-> \"sha256sum1\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SHA256SUM1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha256sum1\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 209, "source": "mapping clause assembly = AES32ESMI (bs, rs2, rs1, rd) <->\n \"aes32esmi\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_2(bs)", "left": { "type": "app", "id": "AES32ESMI", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes32esmi\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_2", "patterns": [ { "type": "id", "id": "bs" } ] } ] } }, { "number": 210, "source": "mapping clause assembly = AES32ESI (bs, rs2, rs1, rd) <->\n \"aes32esi\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_2(bs)", "left": { "type": "app", "id": "AES32ESI", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes32esi\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_2", "patterns": [ { "type": "id", "id": "bs" } ] } ] } }, { "number": 211, "source": "mapping clause assembly = AES32DSMI (bs, rs2, rs1, rd) <->\n \"aes32dsmi\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_2(bs)", "left": { "type": "app", "id": "AES32DSMI", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes32dsmi\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_2", "patterns": [ { "type": "id", "id": "bs" } ] } ] } }, { "number": 212, "source": "mapping clause assembly = AES32DSI (bs, rs2, rs1, rd) <->\n \"aes32dsi\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_2(bs)", "left": { "type": "app", "id": "AES32DSI", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes32dsi\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_2", "patterns": [ { "type": "id", "id": "bs" } ] } ] } }, { "number": 213, "source": "mapping clause assembly = SHA512SIG0L (rs2, rs1, rd)\n <-> \"sha512sig0l\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "SHA512SIG0L", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sig0l\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 214, "source": "mapping clause assembly = SHA512SIG0H (rs2, rs1, rd)\n <-> \"sha512sig0h\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "SHA512SIG0H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sig0h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 215, "source": "mapping clause assembly = SHA512SIG1L (rs2, rs1, rd)\n <-> \"sha512sig1l\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "SHA512SIG1L", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sig1l\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 216, "source": "mapping clause assembly = SHA512SIG1H (rs2, rs1, rd)\n <-> \"sha512sig1h\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "SHA512SIG1H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sig1h\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 217, "source": "mapping clause assembly = SHA512SUM0R (rs2, rs1, rd)\n <-> \"sha512sum0r\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "SHA512SUM0R", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sum0r\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 218, "source": "mapping clause assembly = SHA512SUM1R (rs2, rs1, rd)\n <-> \"sha512sum1r\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "SHA512SUM1R", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sum1r\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 219, "source": "mapping clause assembly = AES64KS1I (rnum, rs1, rd)\n <-> \"aes64ks1i\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_4(rnum)", "left": { "type": "app", "id": "AES64KS1I", "patterns": [ { "type": "id", "id": "rnum" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes64ks1i\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_4", "patterns": [ { "type": "id", "id": "rnum" } ] } ] } }, { "number": 220, "source": "mapping clause assembly = AES64KS2 (rs2, rs1, rd)\n <-> \"aes64ks2\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "AES64KS2", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes64ks2\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 221, "source": "mapping clause assembly = AES64IM (rs1, rd)\n <-> \"aes64im\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "AES64IM", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes64im\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 222, "source": "mapping clause assembly = AES64ESM (rs2, rs1, rd)\n <-> \"aes64esm\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "AES64ESM", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes64esm\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 223, "source": "mapping clause assembly = AES64ES (rs2, rs1, rd)\n <-> \"aes64es\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "AES64ES", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes64es\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 224, "source": "mapping clause assembly = AES64DSM (rs2, rs1, rd)\n <-> \"aes64dsm\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "AES64DSM", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes64dsm\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 225, "source": "mapping clause assembly = AES64DS (rs2, rs1, rd)\n <-> \"aes64ds\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "AES64DS", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"aes64ds\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 226, "source": "mapping clause assembly = SHA512SIG0 (rs1, rd)\n <-> \"sha512sig0\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SHA512SIG0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sig0\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 227, "source": "mapping clause assembly = SHA512SIG1 (rs1, rd)\n <-> \"sha512sig1\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SHA512SIG1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sig1\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 228, "source": "mapping clause assembly = SHA512SUM0 (rs1, rd)\n <-> \"sha512sum0\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SHA512SUM0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sum0\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 229, "source": "mapping clause assembly = SHA512SUM1 (rs1, rd)\n <-> \"sha512sum1\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SHA512SUM1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sha512sum1\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 230, "source": "mapping clause assembly = SM3P0 (rs1, rd) <->\n \"sm3p0\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SM3P0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sm3p0\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 231, "source": "mapping clause assembly = SM3P1 (rs1, rd) <->\n \"sm3p1\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "SM3P1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sm3p1\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 232, "source": "mapping clause assembly = SM4ED (bs, rs2, rs1, rd) <->\n \"sm4ed\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_2(bs)", "left": { "type": "app", "id": "SM4ED", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sm4ed\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_2", "patterns": [ { "type": "id", "id": "bs" } ] } ] } }, { "number": 233, "source": "mapping clause assembly = SM4KS (bs, rs2, rs1, rd) <->\n \"sm4ks\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_2(bs)", "left": { "type": "app", "id": "SM4KS", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"sm4ks\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_2", "patterns": [ { "type": "id", "id": "bs" } ] } ] } }, { "number": 234, "source": "mapping clause assembly = ZBKB_RTYPE(rs2, rs1, rd, op)\n <-> zbkb_rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "ZBKB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zbkb_rtype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 235, "source": "mapping clause assembly = ZBKB_PACKW(rs2, rs1, rd)\n <-> \"packw\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "ZBKB_PACKW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"packw\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 236, "source": "mapping clause assembly = RISCV_ZIP(rs1, rd)\n <-> \"zip\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_ZIP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"zip\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 237, "source": "mapping clause assembly = RISCV_UNZIP(rs1, rd)\n <-> \"unzip\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_UNZIP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"unzip\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 238, "source": "mapping clause assembly = RISCV_BREV8(rs1, rd)\n <-> \"brev8\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "RISCV_BREV8", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"brev8\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 239, "source": "mapping clause assembly = RISCV_XPERM8(rs2, rs1, rd)\n <-> \"xperm8\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "RISCV_XPERM8", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"xperm8\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 240, "source": "mapping clause assembly = RISCV_XPERM4(rs2, rs1, rd)\n <-> \"xperm4\" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "RISCV_XPERM4", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"xperm4\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 241, "source": "mapping clause assembly = ZICOND_RTYPE(rs2, rs1, rd, op)\n <-> zicond_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)", "left": { "type": "app", "id": "ZICOND_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "zicond_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] } ] } }, { "number": 242, "source": "mapping clause assembly = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd)\n <-> vsettype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ sew_flag(sew) ^ maybe_lmul_flag(lmul) ^ maybe_ta_flag(ta) ^ maybe_ma_flag(ma)", "left": { "type": "app", "id": "VSET_TYPE", "patterns": [ { "type": "id", "id": "op" }, { "type": "id", "id": "ma" }, { "type": "id", "id": "ta" }, { "type": "id", "id": "sew" }, { "type": "id", "id": "lmul" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vsettype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "sew_flag", "patterns": [ { "type": "id", "id": "sew" } ] }, { "type": "app", "id": "maybe_lmul_flag", "patterns": [ { "type": "id", "id": "lmul" } ] }, { "type": "app", "id": "maybe_ta_flag", "patterns": [ { "type": "id", "id": "ta" } ] }, { "type": "app", "id": "maybe_ma_flag", "patterns": [ { "type": "id", "id": "ma" } ] } ] } }, { "number": 243, "source": "mapping clause assembly = VSETI_TYPE(ma, ta, sew, lmul, uimm, rd)\n <-> \"vsetivli\" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_5(uimm) ^ sep() ^ sew_flag(sew) ^ maybe_lmul_flag(lmul) ^ maybe_ta_flag(ta) ^ maybe_ma_flag(ma)", "left": { "type": "app", "id": "VSETI_TYPE", "patterns": [ { "type": "id", "id": "ma" }, { "type": "id", "id": "ta" }, { "type": "id", "id": "sew" }, { "type": "id", "id": "lmul" }, { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vsetivli\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "uimm" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "sew_flag", "patterns": [ { "type": "id", "id": "sew" } ] }, { "type": "app", "id": "maybe_lmul_flag", "patterns": [ { "type": "id", "id": "lmul" } ] }, { "type": "app", "id": "maybe_ta_flag", "patterns": [ { "type": "id", "id": "ta" } ] }, { "type": "app", "id": "maybe_ma_flag", "patterns": [ { "type": "id", "id": "ma" } ] } ] } }, { "number": 244, "source": "mapping clause assembly = VVTYPE(funct6, vm, vs2, vs1, vd)\n <-> vvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 245, "source": "mapping clause assembly = NVSTYPE(funct6, vm, vs2, vs1, vd)\n <-> nvstype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "NVSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "nvstype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 246, "source": "mapping clause assembly = NVTYPE(funct6, vm, vs2, vs1, vd)\n <-> nvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "NVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "nvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 247, "source": "mapping clause assembly = MASKTYPEV(vs2, vs1, vd)\n<-> \"vmerge.vvm\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "MASKTYPEV", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmerge.vvm\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 248, "source": "mapping clause assembly = MOVETYPEV(vs1, vd)\n <-> \"vmv.v.v\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs1)", "left": { "type": "app", "id": "MOVETYPEV", "patterns": [ { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmv.v.v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] } ] } }, { "number": 249, "source": "mapping clause assembly = VXTYPE(funct6, vm, vs2, rs1, vd)\n <-> vxtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vxtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 250, "source": "mapping clause assembly = NXSTYPE(funct6, vm, vs2, rs1, vd)\n <-> nxstype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "NXSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "nxstype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 251, "source": "mapping clause assembly = NXTYPE(funct6, vm, vs2, rs1, vd)\n <-> nxtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "NXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "nxtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 252, "source": "mapping clause assembly = VXSG(funct6, vm, vs2, rs1, vd)\n <-> vxsg_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VXSG", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vxsg_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 253, "source": "mapping clause assembly = MASKTYPEX(vs2, rs1, vd)\n <-> \"vmerge.vxm\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "MASKTYPEX", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmerge.vxm\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 254, "source": "mapping clause assembly = MOVETYPEX(rs1, vd)\n <-> \"vmv.v.x\" ^ spc() ^ vreg_name(vd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "MOVETYPEX", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmv.v.x\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 255, "source": "mapping clause assembly = VITYPE(funct6, vm, vs2, simm, vd)\n <-> vitype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VITYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vitype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 256, "source": "mapping clause assembly = NISTYPE(funct6, vm, vs2, simm, vd)\n <-> nistype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "NISTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "nistype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 257, "source": "mapping clause assembly = NITYPE(funct6, vm, vs2, simm, vd)\n <-> nitype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "NITYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "nitype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 258, "source": "mapping clause assembly = VISG(funct6, vm, vs2, simm, vd)\n <-> visg_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(simm) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VISG", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "visg_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 259, "source": "mapping clause assembly = MASKTYPEI(vs2, simm, vd)\n <-> \"vmerge.vim\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "MASKTYPEI", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmerge.vim\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 260, "source": "mapping clause assembly = MOVETYPEI(vd, simm)\n <-> \"vmv.v.i\" ^ spc() ^ vreg_name(vd) ^ sep() ^ hex_bits_5(simm)", "left": { "type": "app", "id": "MOVETYPEI", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "simm" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmv.v.i\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] } ] } }, { "number": 261, "source": "mapping clause assembly = VMVRTYPE(vs2, simm, vd)\n <-> \"vmv\" ^ simm_string(simm) ^ \"r.v\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2)", "left": { "type": "app", "id": "VMVRTYPE", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmv\"" }, { "type": "app", "id": "simm_string", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "literal", "value": "\"r.v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] } ] } }, { "number": 262, "source": "mapping clause assembly = MVVTYPE(funct6, vm, vs2, vs1, vd)\n <-> mvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "MVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "mvvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 263, "source": "mapping clause assembly = MVVMATYPE(funct6, vm, vs2, vs1, vd)\n <-> mvvmatype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs1) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "MVVMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "mvvmatype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 264, "source": "mapping clause assembly = WVVTYPE(funct6, vm, vs2, vs1, vd)\n <-> wvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "WVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "wvvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 265, "source": "mapping clause assembly = WVTYPE(funct6, vm, vs2, vs1, vd)\n <-> wvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "WVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "wvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 266, "source": "mapping clause assembly = WMVVTYPE(funct6, vm, vs2, vs1, vd)\n <-> wmvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs1) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "WMVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "wmvvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 267, "source": "mapping clause assembly = VEXT2TYPE(funct6, vm, vs2, vd)\n <-> vext2type_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VEXT2TYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vext2type_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 268, "source": "mapping clause assembly = VEXT4TYPE(funct6, vm, vs2, vd)\n <-> vext4type_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VEXT4TYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vext4type_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 269, "source": "mapping clause assembly = VEXT8TYPE(funct6, vm, vs2, vd)\n <-> vext8type_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VEXT8TYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vext8type_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 270, "source": "mapping clause assembly = VMVXS(vs2, rd)\n <-> \"vmv.x.s\" ^ spc() ^ reg_name(rd) ^ sep() ^ vreg_name(vs2)", "left": { "type": "app", "id": "VMVXS", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmv.x.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] } ] } }, { "number": 271, "source": "mapping clause assembly = MVVCOMPRESS(vs2, vs1, vd)\n <-> \"vcompress.vm\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1)", "left": { "type": "app", "id": "MVVCOMPRESS", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vcompress.vm\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] } ] } }, { "number": 272, "source": "mapping clause assembly = MVXTYPE(funct6, vm, vs2, rs1, vd)\n <-> mvxtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "MVXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "mvxtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 273, "source": "mapping clause assembly = MVXMATYPE(funct6, vm, vs2, rs1, vd)\n <-> mvxmatype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ reg_name(rs1) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "MVXMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "mvxmatype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 274, "source": "mapping clause assembly = WVXTYPE(funct6, vm, vs2, rs1, vd)\n <-> wvxtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "WVXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "wvxtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 275, "source": "mapping clause assembly = WXTYPE(funct6, vm, vs2, rs1, vd)\n <-> wxtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "WXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "wxtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 276, "source": "mapping clause assembly = WMVXTYPE(funct6, vm, vs2, rs1, vd)\n <-> wmvxtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ reg_name(rs1) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "WMVXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "wmvxtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 277, "source": "mapping clause assembly = VMVSX(rs1, vd)\n <-> \"vmv.s.x\" ^ spc() ^ vreg_name(vd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "VMVSX", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmv.s.x\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 278, "source": "mapping clause assembly = FVVTYPE(funct6, vm, vs2, vs1, vd)\n <-> fvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fvvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 279, "source": "mapping clause assembly = FVVMATYPE(funct6, vm, vs2, vs1, vd)\n <-> fvvmatype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs1) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FVVMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fvvmatype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 280, "source": "mapping clause assembly = FWVVTYPE(funct6, vm, vs2, vs1, vd)\n <-> fwvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FWVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fwvvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 281, "source": "mapping clause assembly = FWVVMATYPE(funct6, vm, vs1, vs2, vd)\n <-> fwvvmatype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs1) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FWVVMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fwvvmatype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 282, "source": "mapping clause assembly = FWVTYPE(funct6, vm, vs2, vs1, vd)\n <-> fwvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FWVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fwvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 283, "source": "mapping clause assembly = VFUNARY0(vm, vs2, vfunary0, vd)\n <-> vfunary0_mnemonic(vfunary0) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VFUNARY0", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfunary0" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vfunary0_mnemonic", "patterns": [ { "type": "id", "id": "vfunary0" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 284, "source": "mapping clause assembly = VFWUNARY0(vm, vs2, vfwunary0, vd)\n <-> vfwunary0_mnemonic(vfwunary0) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VFWUNARY0", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfwunary0" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vfwunary0_mnemonic", "patterns": [ { "type": "id", "id": "vfwunary0" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 285, "source": "mapping clause assembly = VFNUNARY0(vm, vs2, vfnunary0, vd)\n <-> vfnunary0_mnemonic(vfnunary0) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VFNUNARY0", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfnunary0" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vfnunary0_mnemonic", "patterns": [ { "type": "id", "id": "vfnunary0" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 286, "source": "mapping clause assembly = VFUNARY1(vm, vs2, vfunary1, vd)\n <-> vfunary1_mnemonic(vfunary1) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VFUNARY1", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfunary1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vfunary1_mnemonic", "patterns": [ { "type": "id", "id": "vfunary1" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 287, "source": "mapping clause assembly = VFMVFS(vs2, rd)\n <-> \"vfmv.f.s\" ^ spc() ^ freg_name(rd) ^ sep() ^ vreg_name(vs2)", "left": { "type": "app", "id": "VFMVFS", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vfmv.f.s\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] } ] } }, { "number": 288, "source": "mapping clause assembly = FVFTYPE(funct6, vm, vs2, rs1, vd)\n <-> fvftype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FVFTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fvftype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 289, "source": "mapping clause assembly = FVFMATYPE(funct6, vm, vs2, rs1, vd)\n <-> fvfmatype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ reg_name(rs1) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FVFMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fvfmatype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 290, "source": "mapping clause assembly = FWVFTYPE(funct6, vm, vs2, rs1, vd)\n <-> fwvftype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FWVFTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fwvftype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 291, "source": "mapping clause assembly = FWVFMATYPE(funct6, vm, rs1, vs2, vd)\n <-> fwvfmatype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ reg_name(rs1) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FWVFMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fwvfmatype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 292, "source": "mapping clause assembly = FWFTYPE(funct6, vm, vs2, rs1, vd)\n <-> fwftype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FWFTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fwftype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 293, "source": "mapping clause assembly = VFMERGE(vs2, rs1, vd)\n <-> \"vfmerge.vfm\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "VFMERGE", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vfmerge.vfm\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 294, "source": "mapping clause assembly = VFMV(rs1, vd)\n <-> \"vfmv.v.f\" ^ spc() ^ vreg_name(vd) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "VFMV", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vfmv.v.f\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 295, "source": "mapping clause assembly = VFMVSF(rs1, vd)\n <-> \"vfmv.s.f\" ^ spc() ^ vreg_name(vd) ^ sep() ^ freg_name(rs1)", "left": { "type": "app", "id": "VFMVSF", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vfmv.s.f\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 296, "source": "mapping clause assembly = VLSEGTYPE(nf, vm, rs1, width, vd)\n <-> \"vl\" ^ nfields_string(nf) ^ \"e\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vd) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VLSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vl\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"e\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 297, "source": "mapping clause assembly = VLSEGFFTYPE(nf, vm, rs1, width, vd)\n <-> \"vl\" ^ nfields_string(nf) ^ \"e\" ^ vlewidth_bitsnumberstr(width) ^ \"ff.v\" ^ spc() ^ vreg_name(vd) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VLSEGFFTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vl\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"e\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\"ff.v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 298, "source": "mapping clause assembly = VSSEGTYPE(nf, vm, rs1, width, vs3)\n <-> \"vs\" ^ nfields_string(nf) ^ \"e\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vs3) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VSSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vs\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"e\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 299, "source": "mapping clause assembly = VLSSEGTYPE(nf, vm, rs2, rs1, width, vd)\n <-> \"vls\" ^ nfields_string(nf) ^ \"e\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vd) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ sep() ^ reg_name(rs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VLSSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vls\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"e\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 300, "source": "mapping clause assembly = VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3)\n <-> \"vss\" ^ nfields_string(nf) ^ \"e\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vs3) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ sep() ^ reg_name(rs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VSSSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vss\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"e\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 301, "source": "mapping clause assembly = VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd)\n <-> \"vlux\" ^ nfields_string(nf) ^ \"ei\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vd) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VLUXSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vlux\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"ei\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 302, "source": "mapping clause assembly = VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd)\n <-> \"vlox\" ^ nfields_string(nf) ^ \"ei\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vd) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VLOXSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vlox\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"ei\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 303, "source": "mapping clause assembly = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3)\n <-> \"vsux\" ^ nfields_string(nf) ^ \"ei\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vs3) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VSUXSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vsux\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"ei\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 304, "source": "mapping clause assembly = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3)\n <-> \"vsox\" ^ nfields_string(nf) ^ \"ei\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vs3) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VSUXSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vsox\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"ei\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 305, "source": "mapping clause assembly = VLRETYPE(nf, rs1, width, vd)\n <-> \"vl\" ^ nfields_string(nf) ^ \"re\" ^ vlewidth_bitsnumberstr(width) ^ \".v\" ^ spc() ^ vreg_name(vd) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\"", "left": { "type": "app", "id": "VLRETYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vl\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"re\"" }, { "type": "app", "id": "vlewidth_bitsnumberstr", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "literal", "value": "\".v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 306, "source": "mapping clause assembly = VSRETYPE(nf, rs1, vs3)\n <-> \"vs\" ^ nfields_string(nf) ^ \"r.v\" ^ spc() ^ vreg_name(vs3) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\"", "left": { "type": "app", "id": "VSRETYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vs\"" }, { "type": "app", "id": "nfields_string", "patterns": [ { "type": "id", "id": "nf" } ] }, { "type": "literal", "value": "\"r.v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 307, "source": "mapping clause assembly = VMTYPE(rs1, vd_or_vs3, op)\n <-> vmtype_mnemonic(op) ^ spc() ^ vreg_name(vd_or_vs3) ^ sep() ^ \"(\" ^ reg_name(rs1) ^ \")\"", "left": { "type": "app", "id": "VMTYPE", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd_or_vs3" }, { "type": "id", "id": "op" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vmtype_mnemonic", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd_or_vs3" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"(\"" }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "literal", "value": "\")\"" } ] } }, { "number": 308, "source": "mapping clause assembly = MMTYPE(funct6, vs2, vs1, vd)\n <-> mmtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1)", "left": { "type": "app", "id": "MMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "mmtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] } ] } }, { "number": 309, "source": "mapping clause assembly = VCPOP_M(vm, vs2, rd)\n <-> \"vpopc.m\" ^ spc() ^ reg_name(rd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VCPOP_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vpopc.m\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 310, "source": "mapping clause assembly = VFIRST_M(vm, vs2, rd)\n <-> \"vfirst.m\" ^ spc() ^ reg_name(rd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VFIRST_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vfirst.m\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 311, "source": "mapping clause assembly = VMSBF_M(vm, vs2, vd)\n <-> \"vmsbf.m\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VMSBF_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmsbf.m\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 312, "source": "mapping clause assembly = VMSIF_M(vm, vs2, vd)\n <-> \"vmsif.m\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VMSIF_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmsif.m\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 313, "source": "mapping clause assembly = VMSOF_M(vm, vs2, vd)\n <-> \"vmsof.m\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VMSOF_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vmsof.m\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 314, "source": "mapping clause assembly = VIOTA_M(vm, vs2, vd)\n <-> \"viota.m\" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VIOTA_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"viota.m\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 315, "source": "mapping clause assembly = VID_V(vm, vd)\n <-> \"vid.v\" ^ spc() ^ vreg_name(vd) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VID_V", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"vid.v\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 316, "source": "mapping clause assembly = VVMTYPE(funct6, vs2, vs1, vd)\n <-> vvmtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "VVMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vvmtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 317, "source": "mapping clause assembly = VVMCTYPE(funct6, vs2, vs1, vd)\n <-> vvmctype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1)", "left": { "type": "app", "id": "VVMCTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vvmctype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] } ] } }, { "number": 318, "source": "mapping clause assembly = VVMSTYPE(funct6, vs2, vs1, vd)\n <-> vvmstype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "VVMSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vvmstype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 319, "source": "mapping clause assembly = VVCMPTYPE(funct6, vm, vs2, vs1, vd)\n <-> vvcmptype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VVCMPTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vvcmptype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 320, "source": "mapping clause assembly = VXMTYPE(funct6, vs2, rs1, vd)\n <-> vxmtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "VXMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vxmtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 321, "source": "mapping clause assembly = VXMCTYPE(funct6, vs2, rs1, vd)\n <-> vxmctype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1)", "left": { "type": "app", "id": "VXMCTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vxmctype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] } ] } }, { "number": 322, "source": "mapping clause assembly = VXMSTYPE(funct6, vs2, rs1, vd)\n <-> vxmstype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "VXMSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vxmstype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 323, "source": "mapping clause assembly = VXCMPTYPE(funct6, vm, vs2, rs1, vd)\n <-> vxcmptype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VXCMPTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vxcmptype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 324, "source": "mapping clause assembly = VIMTYPE(funct6, vs2, simm, vd)\n <-> vimtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "VIMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vimtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 325, "source": "mapping clause assembly = VIMCTYPE(funct6, vs2, simm, vd)\n <-> vimctype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm)", "left": { "type": "app", "id": "VIMCTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vimctype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] } ] } }, { "number": 326, "source": "mapping clause assembly = VIMSTYPE(funct6, vs2, simm, vd)\n <-> vimstype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ sep() ^ \"v0\"", "left": { "type": "app", "id": "VIMSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vimstype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0\"" } ] } }, { "number": 327, "source": "mapping clause assembly = VICMPTYPE(funct6, vm, vs2, simm, vd)\n <-> vicmptype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "VICMPTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "vicmptype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_5", "patterns": [ { "type": "id", "id": "simm" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 328, "source": "mapping clause assembly = FVVMTYPE(funct6, vm, vs2, vs1, vd)\n <-> fvvmtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FVVMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fvvmtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 329, "source": "mapping clause assembly = FVFMTYPE(funct6, vm, vs2, rs1, vd)\n <-> fvfmtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "FVFMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "fvfmtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "rs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 330, "source": "mapping clause assembly = RIVVTYPE(funct6, vm, vs2, vs1, vd)\n <-> rivvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "RIVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "rivvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 331, "source": "mapping clause assembly = RMVVTYPE(funct6, vm, vs2, vs1, vd)\n <-> rmvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "RMVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "rmvvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 332, "source": "mapping clause assembly = RFVVTYPE(funct6, vm, vs2, vs1, vd)\n <-> rfvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm)", "left": { "type": "app", "id": "RFVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "rfvvtype_mnemonic", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vd" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs2" } ] }, { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "vreg_name", "patterns": [ { "type": "id", "id": "vs1" } ] }, { "type": "app", "id": "maybe_vmask", "patterns": [ { "type": "id", "id": "vm" } ] } ] } }, { "number": 333, "source": "mapping clause assembly = ILLEGAL(s) <-> \"illegal\" ^ spc() ^ hex_bits_32(s)", "left": { "type": "app", "id": "ILLEGAL", "patterns": [ { "type": "id", "id": "s" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"illegal\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_32", "patterns": [ { "type": "id", "id": "s" } ] } ] } }, { "number": 334, "source": "mapping clause assembly = C_ILLEGAL(s) <-> \"c.illegal\" ^ spc() ^ hex_bits_16(s)", "left": { "type": "app", "id": "C_ILLEGAL", "patterns": [ { "type": "id", "id": "s" } ] }, "right": { "type": "string_append", "patterns": [ { "type": "literal", "value": "\"c.illegal\"" }, { "type": "app", "id": "spc", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "app", "id": "hex_bits_16", "patterns": [ { "type": "id", "id": "s" } ] } ] } } ] }, "bit_maybe_i": { "mapping": [ { "number": 0, "source": "0b1 <-> \"i\"", "left": { "type": "literal", "value": "0b1" }, "right": { "type": "literal", "value": "\"i\"" } }, { "number": 1, "source": "0b0 <-> \"\"", "left": { "type": "literal", "value": "0b0" }, "right": { "type": "literal", "value": "\"\"" } } ] }, "bit_maybe_o": { "mapping": [ { "number": 0, "source": "0b1 <-> \"o\"", "left": { "type": "literal", "value": "0b1" }, "right": { "type": "literal", "value": "\"o\"" } }, { "number": 1, "source": "0b0 <-> \"\"", "left": { "type": "literal", "value": "0b0" }, "right": { "type": "literal", "value": "\"\"" } } ] }, "bit_maybe_r": { "mapping": [ { "number": 0, "source": "0b1 <-> \"r\"", "left": { "type": "literal", "value": "0b1" }, "right": { "type": "literal", "value": "\"r\"" } }, { "number": 1, "source": "0b0 <-> \"\"", "left": { "type": "literal", "value": "0b0" }, "right": { "type": "literal", "value": "\"\"" } } ] }, "bit_maybe_w": { "mapping": [ { "number": 0, "source": "0b1 <-> \"w\"", "left": { "type": "literal", "value": "0b1" }, "right": { "type": "literal", "value": "\"w\"" } }, { "number": 1, "source": "0b0 <-> \"\"", "left": { "type": "literal", "value": "0b0" }, "right": { "type": "literal", "value": "\"\"" } } ] }, "bool_bits": { "mapping": [ { "number": 0, "source": "true <-> 0b1", "left": { "type": "literal", "value": "true" }, "right": { "type": "literal", "value": "0b1" } }, { "number": 1, "source": "false <-> 0b0", "left": { "type": "literal", "value": "false" }, "right": { "type": "literal", "value": "0b0" } } ] }, "bool_not_bits": { "mapping": [ { "number": 0, "source": "true <-> 0b0", "left": { "type": "literal", "value": "true" }, "right": { "type": "literal", "value": "0b0" } }, { "number": 1, "source": "false <-> 0b1", "left": { "type": "literal", "value": "false" }, "right": { "type": "literal", "value": "0b1" } } ] }, "btype_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_BEQ <-> \"beq\"", "left": { "type": "id", "id": "RISCV_BEQ" }, "right": { "type": "literal", "value": "\"beq\"" } }, { "number": 1, "source": "RISCV_BNE <-> \"bne\"", "left": { "type": "id", "id": "RISCV_BNE" }, "right": { "type": "literal", "value": "\"bne\"" } }, { "number": 2, "source": "RISCV_BLT <-> \"blt\"", "left": { "type": "id", "id": "RISCV_BLT" }, "right": { "type": "literal", "value": "\"blt\"" } }, { "number": 3, "source": "RISCV_BGE <-> \"bge\"", "left": { "type": "id", "id": "RISCV_BGE" }, "right": { "type": "literal", "value": "\"bge\"" } }, { "number": 4, "source": "RISCV_BLTU <-> \"bltu\"", "left": { "type": "id", "id": "RISCV_BLTU" }, "right": { "type": "literal", "value": "\"bltu\"" } }, { "number": 5, "source": "RISCV_BGEU <-> \"bgeu\"", "left": { "type": "id", "id": "RISCV_BGEU" }, "right": { "type": "literal", "value": "\"bgeu\"" } } ] }, "bytes_wordwidth": { "mapping": [ { "number": 0, "source": "1 <-> BYTE", "left": { "type": "literal", "value": "1" }, "right": { "type": "id", "id": "BYTE" } }, { "number": 1, "source": "2 <-> HALF", "left": { "type": "literal", "value": "2" }, "right": { "type": "id", "id": "HALF" } }, { "number": 2, "source": "4 <-> WORD", "left": { "type": "literal", "value": "4" }, "right": { "type": "id", "id": "WORD" } }, { "number": 3, "source": "8 <-> DOUBLE", "left": { "type": "literal", "value": "8" }, "right": { "type": "id", "id": "DOUBLE" } } ] }, "creg_name": { "mapping": [ { "number": 0, "source": "0b000 <-> \"s0\"", "left": { "type": "literal", "value": "0b000" }, "right": { "type": "literal", "value": "\"s0\"" } }, { "number": 1, "source": "0b001 <-> \"s1\"", "left": { "type": "literal", "value": "0b001" }, "right": { "type": "literal", "value": "\"s1\"" } }, { "number": 2, "source": "0b010 <-> \"a0\"", "left": { "type": "literal", "value": "0b010" }, "right": { "type": "literal", "value": "\"a0\"" } }, { "number": 3, "source": "0b011 <-> \"a1\"", "left": { "type": "literal", "value": "0b011" }, "right": { "type": "literal", "value": "\"a1\"" } }, { "number": 4, "source": "0b100 <-> \"a2\"", "left": { "type": "literal", "value": "0b100" }, "right": { "type": "literal", "value": "\"a2\"" } }, { "number": 5, "source": "0b101 <-> \"a3\"", "left": { "type": "literal", "value": "0b101" }, "right": { "type": "literal", "value": "\"a3\"" } }, { "number": 6, "source": "0b110 <-> \"a4\"", "left": { "type": "literal", "value": "0b110" }, "right": { "type": "literal", "value": "\"a4\"" } }, { "number": 7, "source": "0b111 <-> \"a5\"", "left": { "type": "literal", "value": "0b111" }, "right": { "type": "literal", "value": "\"a5\"" } } ] }, "csr_mnemonic": { "mapping": [ { "number": 0, "source": "CSRRW <-> \"csrrw\"", "left": { "type": "id", "id": "CSRRW" }, "right": { "type": "literal", "value": "\"csrrw\"" } }, { "number": 1, "source": "CSRRS <-> \"csrrs\"", "left": { "type": "id", "id": "CSRRS" }, "right": { "type": "literal", "value": "\"csrrs\"" } }, { "number": 2, "source": "CSRRC <-> \"csrrc\"", "left": { "type": "id", "id": "CSRRC" }, "right": { "type": "literal", "value": "\"csrrc\"" } } ] }, "csr_name_map": { "mapping": [ { "number": 0, "source": "mapping clause csr_name_map = 0x000 <-> \"ustatus\"", "left": { "type": "literal", "value": "0x000" }, "right": { "type": "literal", "value": "\"ustatus\"" } }, { "number": 1, "source": "mapping clause csr_name_map = 0x004 <-> \"uie\"", "left": { "type": "literal", "value": "0x004" }, "right": { "type": "literal", "value": "\"uie\"" } }, { "number": 2, "source": "mapping clause csr_name_map = 0x005 <-> \"utvec\"", "left": { "type": "literal", "value": "0x005" }, "right": { "type": "literal", "value": "\"utvec\"" } }, { "number": 3, "source": "mapping clause csr_name_map = 0x040 <-> \"uscratch\"", "left": { "type": "literal", "value": "0x040" }, "right": { "type": "literal", "value": "\"uscratch\"" } }, { "number": 4, "source": "mapping clause csr_name_map = 0x041 <-> \"uepc\"", "left": { "type": "literal", "value": "0x041" }, "right": { "type": "literal", "value": "\"uepc\"" } }, { "number": 5, "source": "mapping clause csr_name_map = 0x042 <-> \"ucause\"", "left": { "type": "literal", "value": "0x042" }, "right": { "type": "literal", "value": "\"ucause\"" } }, { "number": 6, "source": "mapping clause csr_name_map = 0x043 <-> \"utval\"", "left": { "type": "literal", "value": "0x043" }, "right": { "type": "literal", "value": "\"utval\"" } }, { "number": 7, "source": "mapping clause csr_name_map = 0x044 <-> \"uip\"", "left": { "type": "literal", "value": "0x044" }, "right": { "type": "literal", "value": "\"uip\"" } }, { "number": 8, "source": "mapping clause csr_name_map = 0x001 <-> \"fflags\"", "left": { "type": "literal", "value": "0x001" }, "right": { "type": "literal", "value": "\"fflags\"" } }, { "number": 9, "source": "mapping clause csr_name_map = 0x002 <-> \"frm\"", "left": { "type": "literal", "value": "0x002" }, "right": { "type": "literal", "value": "\"frm\"" } }, { "number": 10, "source": "mapping clause csr_name_map = 0x003 <-> \"fcsr\"", "left": { "type": "literal", "value": "0x003" }, "right": { "type": "literal", "value": "\"fcsr\"" } }, { "number": 11, "source": "mapping clause csr_name_map = 0x015 <-> \"seed\"", "left": { "type": "literal", "value": "0x015" }, "right": { "type": "literal", "value": "\"seed\"" } }, { "number": 12, "source": "mapping clause csr_name_map = 0xC00 <-> \"cycle\"", "left": { "type": "literal", "value": "0xC00" }, "right": { "type": "literal", "value": "\"cycle\"" } }, { "number": 13, "source": "mapping clause csr_name_map = 0xC01 <-> \"time\"", "left": { "type": "literal", "value": "0xC01" }, "right": { "type": "literal", "value": "\"time\"" } }, { "number": 14, "source": "mapping clause csr_name_map = 0xC02 <-> \"instret\"", "left": { "type": "literal", "value": "0xC02" }, "right": { "type": "literal", "value": "\"instret\"" } }, { "number": 15, "source": "mapping clause csr_name_map = 0xC80 <-> \"cycleh\"", "left": { "type": "literal", "value": "0xC80" }, "right": { "type": "literal", "value": "\"cycleh\"" } }, { "number": 16, "source": "mapping clause csr_name_map = 0xC81 <-> \"timeh\"", "left": { "type": "literal", "value": "0xC81" }, "right": { "type": "literal", "value": "\"timeh\"" } }, { "number": 17, "source": "mapping clause csr_name_map = 0xC82 <-> \"instreth\"", "left": { "type": "literal", "value": "0xC82" }, "right": { "type": "literal", "value": "\"instreth\"" } }, { "number": 18, "source": "mapping clause csr_name_map = 0x100 <-> \"sstatus\"", "left": { "type": "literal", "value": "0x100" }, "right": { "type": "literal", "value": "\"sstatus\"" } }, { "number": 19, "source": "mapping clause csr_name_map = 0x102 <-> \"sedeleg\"", "left": { "type": "literal", "value": "0x102" }, "right": { "type": "literal", "value": "\"sedeleg\"" } }, { "number": 20, "source": "mapping clause csr_name_map = 0x103 <-> \"sideleg\"", "left": { "type": "literal", "value": "0x103" }, "right": { "type": "literal", "value": "\"sideleg\"" } }, { "number": 21, "source": "mapping clause csr_name_map = 0x104 <-> \"sie\"", "left": { "type": "literal", "value": "0x104" }, "right": { "type": "literal", "value": "\"sie\"" } }, { "number": 22, "source": "mapping clause csr_name_map = 0x105 <-> \"stvec\"", "left": { "type": "literal", "value": "0x105" }, "right": { "type": "literal", "value": "\"stvec\"" } }, { "number": 23, "source": "mapping clause csr_name_map = 0x106 <-> \"scounteren\"", "left": { "type": "literal", "value": "0x106" }, "right": { "type": "literal", "value": "\"scounteren\"" } }, { "number": 24, "source": "mapping clause csr_name_map = 0x140 <-> \"sscratch\"", "left": { "type": "literal", "value": "0x140" }, "right": { "type": "literal", "value": "\"sscratch\"" } }, { "number": 25, "source": "mapping clause csr_name_map = 0x141 <-> \"sepc\"", "left": { "type": "literal", "value": "0x141" }, "right": { "type": "literal", "value": "\"sepc\"" } }, { "number": 26, "source": "mapping clause csr_name_map = 0x142 <-> \"scause\"", "left": { "type": "literal", "value": "0x142" }, "right": { "type": "literal", "value": "\"scause\"" } }, { "number": 27, "source": "mapping clause csr_name_map = 0x143 <-> \"stval\"", "left": { "type": "literal", "value": "0x143" }, "right": { "type": "literal", "value": "\"stval\"" } }, { "number": 28, "source": "mapping clause csr_name_map = 0x144 <-> \"sip\"", "left": { "type": "literal", "value": "0x144" }, "right": { "type": "literal", "value": "\"sip\"" } }, { "number": 29, "source": "mapping clause csr_name_map = 0x180 <-> \"satp\"", "left": { "type": "literal", "value": "0x180" }, "right": { "type": "literal", "value": "\"satp\"" } }, { "number": 30, "source": "mapping clause csr_name_map = 0x10A <-> \"senvcfg\"", "left": { "type": "literal", "value": "0x10A" }, "right": { "type": "literal", "value": "\"senvcfg\"" } }, { "number": 31, "source": "mapping clause csr_name_map = 0xF11 <-> \"mvendorid\"", "left": { "type": "literal", "value": "0xF11" }, "right": { "type": "literal", "value": "\"mvendorid\"" } }, { "number": 32, "source": "mapping clause csr_name_map = 0xF12 <-> \"marchid\"", "left": { "type": "literal", "value": "0xF12" }, "right": { "type": "literal", "value": "\"marchid\"" } }, { "number": 33, "source": "mapping clause csr_name_map = 0xF13 <-> \"mimpid\"", "left": { "type": "literal", "value": "0xF13" }, "right": { "type": "literal", "value": "\"mimpid\"" } }, { "number": 34, "source": "mapping clause csr_name_map = 0xF14 <-> \"mhartid\"", "left": { "type": "literal", "value": "0xF14" }, "right": { "type": "literal", "value": "\"mhartid\"" } }, { "number": 35, "source": "mapping clause csr_name_map = 0x300 <-> \"mstatus\"", "left": { "type": "literal", "value": "0x300" }, "right": { "type": "literal", "value": "\"mstatus\"" } }, { "number": 36, "source": "mapping clause csr_name_map = 0x301 <-> \"misa\"", "left": { "type": "literal", "value": "0x301" }, "right": { "type": "literal", "value": "\"misa\"" } }, { "number": 37, "source": "mapping clause csr_name_map = 0x302 <-> \"medeleg\"", "left": { "type": "literal", "value": "0x302" }, "right": { "type": "literal", "value": "\"medeleg\"" } }, { "number": 38, "source": "mapping clause csr_name_map = 0x303 <-> \"mideleg\"", "left": { "type": "literal", "value": "0x303" }, "right": { "type": "literal", "value": "\"mideleg\"" } }, { "number": 39, "source": "mapping clause csr_name_map = 0x304 <-> \"mie\"", "left": { "type": "literal", "value": "0x304" }, "right": { "type": "literal", "value": "\"mie\"" } }, { "number": 40, "source": "mapping clause csr_name_map = 0x305 <-> \"mtvec\"", "left": { "type": "literal", "value": "0x305" }, "right": { "type": "literal", "value": "\"mtvec\"" } }, { "number": 41, "source": "mapping clause csr_name_map = 0x306 <-> \"mcounteren\"", "left": { "type": "literal", "value": "0x306" }, "right": { "type": "literal", "value": "\"mcounteren\"" } }, { "number": 42, "source": "mapping clause csr_name_map = 0x320 <-> \"mcountinhibit\"", "left": { "type": "literal", "value": "0x320" }, "right": { "type": "literal", "value": "\"mcountinhibit\"" } }, { "number": 43, "source": "mapping clause csr_name_map = 0x30A <-> \"menvcfg\"", "left": { "type": "literal", "value": "0x30A" }, "right": { "type": "literal", "value": "\"menvcfg\"" } }, { "number": 44, "source": "mapping clause csr_name_map = 0x340 <-> \"mscratch\"", "left": { "type": "literal", "value": "0x340" }, "right": { "type": "literal", "value": "\"mscratch\"" } }, { "number": 45, "source": "mapping clause csr_name_map = 0x341 <-> \"mepc\"", "left": { "type": "literal", "value": "0x341" }, "right": { "type": "literal", "value": "\"mepc\"" } }, { "number": 46, "source": "mapping clause csr_name_map = 0x342 <-> \"mcause\"", "left": { "type": "literal", "value": "0x342" }, "right": { "type": "literal", "value": "\"mcause\"" } }, { "number": 47, "source": "mapping clause csr_name_map = 0x343 <-> \"mtval\"", "left": { "type": "literal", "value": "0x343" }, "right": { "type": "literal", "value": "\"mtval\"" } }, { "number": 48, "source": "mapping clause csr_name_map = 0x344 <-> \"mip\"", "left": { "type": "literal", "value": "0x344" }, "right": { "type": "literal", "value": "\"mip\"" } }, { "number": 49, "source": "mapping clause csr_name_map = 0x3A0 <-> \"pmpcfg0\"", "left": { "type": "literal", "value": "0x3A0" }, "right": { "type": "literal", "value": "\"pmpcfg0\"" } }, { "number": 50, "source": "mapping clause csr_name_map = 0x3A1 <-> \"pmpcfg1\"", "left": { "type": "literal", "value": "0x3A1" }, "right": { "type": "literal", "value": "\"pmpcfg1\"" } }, { "number": 51, "source": "mapping clause csr_name_map = 0x3A2 <-> \"pmpcfg2\"", "left": { "type": "literal", "value": "0x3A2" }, "right": { "type": "literal", "value": "\"pmpcfg2\"" } }, { "number": 52, "source": "mapping clause csr_name_map = 0x3A3 <-> \"pmpcfg3\"", "left": { "type": "literal", "value": "0x3A3" }, "right": { "type": "literal", "value": "\"pmpcfg3\"" } }, { "number": 53, "source": "mapping clause csr_name_map = 0x3A4 <-> \"pmpcfg4\"", "left": { "type": "literal", "value": "0x3A4" }, "right": { "type": "literal", "value": "\"pmpcfg4\"" } }, { "number": 54, "source": "mapping clause csr_name_map = 0x3A5 <-> \"pmpcfg5\"", "left": { "type": "literal", "value": "0x3A5" }, "right": { "type": "literal", "value": "\"pmpcfg5\"" } }, { "number": 55, "source": "mapping clause csr_name_map = 0x3A6 <-> \"pmpcfg6\"", "left": { "type": "literal", "value": "0x3A6" }, "right": { "type": "literal", "value": "\"pmpcfg6\"" } }, { "number": 56, "source": "mapping clause csr_name_map = 0x3A7 <-> \"pmpcfg7\"", "left": { "type": "literal", "value": "0x3A7" }, "right": { "type": "literal", "value": "\"pmpcfg7\"" } }, { "number": 57, "source": "mapping clause csr_name_map = 0x3A8 <-> \"pmpcfg8\"", "left": { "type": "literal", "value": "0x3A8" }, "right": { "type": "literal", "value": "\"pmpcfg8\"" } }, { "number": 58, "source": "mapping clause csr_name_map = 0x3A9 <-> \"pmpcfg9\"", "left": { "type": "literal", "value": "0x3A9" }, "right": { "type": "literal", "value": "\"pmpcfg9\"" } }, { "number": 59, "source": "mapping clause csr_name_map = 0x3AA <-> \"pmpcfg10\"", "left": { "type": "literal", "value": "0x3AA" }, "right": { "type": "literal", "value": "\"pmpcfg10\"" } }, { "number": 60, "source": "mapping clause csr_name_map = 0x3AB <-> \"pmpcfg11\"", "left": { "type": "literal", "value": "0x3AB" }, "right": { "type": "literal", "value": "\"pmpcfg11\"" } }, { "number": 61, "source": "mapping clause csr_name_map = 0x3AC <-> \"pmpcfg12\"", "left": { "type": "literal", "value": "0x3AC" }, "right": { "type": "literal", "value": "\"pmpcfg12\"" } }, { "number": 62, "source": "mapping clause csr_name_map = 0x3AD <-> \"pmpcfg13\"", "left": { "type": "literal", "value": "0x3AD" }, "right": { "type": "literal", "value": "\"pmpcfg13\"" } }, { "number": 63, "source": "mapping clause csr_name_map = 0x3AE <-> \"pmpcfg14\"", "left": { "type": "literal", "value": "0x3AE" }, "right": { "type": "literal", "value": "\"pmpcfg14\"" } }, { "number": 64, "source": "mapping clause csr_name_map = 0x3AF <-> \"pmpcfg15\"", "left": { "type": "literal", "value": "0x3AF" }, "right": { "type": "literal", "value": "\"pmpcfg15\"" } }, { "number": 65, "source": "mapping clause csr_name_map = 0x3B0 <-> \"pmpaddr0\"", "left": { "type": "literal", "value": "0x3B0" }, "right": { "type": "literal", "value": "\"pmpaddr0\"" } }, { "number": 66, "source": "mapping clause csr_name_map = 0x3B1 <-> \"pmpaddr1\"", "left": { "type": "literal", "value": "0x3B1" }, "right": { "type": "literal", "value": "\"pmpaddr1\"" } }, { "number": 67, "source": "mapping clause csr_name_map = 0x3B2 <-> \"pmpaddr2\"", "left": { "type": "literal", "value": "0x3B2" }, "right": { "type": "literal", "value": "\"pmpaddr2\"" } }, { "number": 68, "source": "mapping clause csr_name_map = 0x3B3 <-> \"pmpaddr3\"", "left": { "type": "literal", "value": "0x3B3" }, "right": { "type": "literal", "value": "\"pmpaddr3\"" } }, { "number": 69, "source": "mapping clause csr_name_map = 0x3B4 <-> \"pmpaddr4\"", "left": { "type": "literal", "value": "0x3B4" }, "right": { "type": "literal", "value": "\"pmpaddr4\"" } }, { "number": 70, "source": "mapping clause csr_name_map = 0x3B5 <-> \"pmpaddr5\"", "left": { "type": "literal", "value": "0x3B5" }, "right": { "type": "literal", "value": "\"pmpaddr5\"" } }, { "number": 71, "source": "mapping clause csr_name_map = 0x3B6 <-> \"pmpaddr6\"", "left": { "type": "literal", "value": "0x3B6" }, "right": { "type": "literal", "value": "\"pmpaddr6\"" } }, { "number": 72, "source": "mapping clause csr_name_map = 0x3B7 <-> \"pmpaddr7\"", "left": { "type": "literal", "value": "0x3B7" }, "right": { "type": "literal", "value": "\"pmpaddr7\"" } }, { "number": 73, "source": "mapping clause csr_name_map = 0x3B8 <-> \"pmpaddr8\"", "left": { "type": "literal", "value": "0x3B8" }, "right": { "type": "literal", "value": "\"pmpaddr8\"" } }, { "number": 74, "source": "mapping clause csr_name_map = 0x3B9 <-> \"pmpaddr9\"", "left": { "type": "literal", "value": "0x3B9" }, "right": { "type": "literal", "value": "\"pmpaddr9\"" } }, { "number": 75, "source": "mapping clause csr_name_map = 0x3BA <-> \"pmpaddr10\"", "left": { "type": "literal", "value": "0x3BA" }, "right": { "type": "literal", "value": "\"pmpaddr10\"" } }, { "number": 76, "source": "mapping clause csr_name_map = 0x3BB <-> \"pmpaddr11\"", "left": { "type": "literal", "value": "0x3BB" }, "right": { "type": "literal", "value": "\"pmpaddr11\"" } }, { "number": 77, "source": "mapping clause csr_name_map = 0x3BC <-> \"pmpaddr12\"", "left": { "type": "literal", "value": "0x3BC" }, "right": { "type": "literal", "value": "\"pmpaddr12\"" } }, { "number": 78, "source": "mapping clause csr_name_map = 0x3BD <-> \"pmpaddr13\"", "left": { "type": "literal", "value": "0x3BD" }, "right": { "type": "literal", "value": "\"pmpaddr13\"" } }, { "number": 79, "source": "mapping clause csr_name_map = 0x3BE <-> \"pmpaddr14\"", "left": { "type": "literal", "value": "0x3BE" }, "right": { "type": "literal", "value": "\"pmpaddr14\"" } }, { "number": 80, "source": "mapping clause csr_name_map = 0x3BF <-> \"pmpaddr15\"", "left": { "type": "literal", "value": "0x3BF" }, "right": { "type": "literal", "value": "\"pmpaddr15\"" } }, { "number": 81, "source": "mapping clause csr_name_map = 0x3C0 <-> \"pmpaddr16\"", "left": { "type": "literal", "value": "0x3C0" }, "right": { "type": "literal", "value": "\"pmpaddr16\"" } }, { "number": 82, "source": "mapping clause csr_name_map = 0x3C1 <-> \"pmpaddr17\"", "left": { "type": "literal", "value": "0x3C1" }, "right": { "type": "literal", "value": "\"pmpaddr17\"" } }, { "number": 83, "source": "mapping clause csr_name_map = 0x3C2 <-> \"pmpaddr18\"", "left": { "type": "literal", "value": "0x3C2" }, "right": { "type": "literal", "value": "\"pmpaddr18\"" } }, { "number": 84, "source": "mapping clause csr_name_map = 0x3C3 <-> \"pmpaddr19\"", "left": { "type": "literal", "value": "0x3C3" }, "right": { "type": "literal", "value": "\"pmpaddr19\"" } }, { "number": 85, "source": "mapping clause csr_name_map = 0x3C4 <-> \"pmpaddr20\"", "left": { "type": "literal", "value": "0x3C4" }, "right": { "type": "literal", "value": "\"pmpaddr20\"" } }, { "number": 86, "source": "mapping clause csr_name_map = 0x3C5 <-> \"pmpaddr21\"", "left": { "type": "literal", "value": "0x3C5" }, "right": { "type": "literal", "value": "\"pmpaddr21\"" } }, { "number": 87, "source": "mapping clause csr_name_map = 0x3C6 <-> \"pmpaddr22\"", "left": { "type": "literal", "value": "0x3C6" }, "right": { "type": "literal", "value": "\"pmpaddr22\"" } }, { "number": 88, "source": "mapping clause csr_name_map = 0x3C7 <-> \"pmpaddr23\"", "left": { "type": "literal", "value": "0x3C7" }, "right": { "type": "literal", "value": "\"pmpaddr23\"" } }, { "number": 89, "source": "mapping clause csr_name_map = 0x3C8 <-> \"pmpaddr24\"", "left": { "type": "literal", "value": "0x3C8" }, "right": { "type": "literal", "value": "\"pmpaddr24\"" } }, { "number": 90, "source": "mapping clause csr_name_map = 0x3C9 <-> \"pmpaddr25\"", "left": { "type": "literal", "value": "0x3C9" }, "right": { "type": "literal", "value": "\"pmpaddr25\"" } }, { "number": 91, "source": "mapping clause csr_name_map = 0x3CA <-> \"pmpaddr26\"", "left": { "type": "literal", "value": "0x3CA" }, "right": { "type": "literal", "value": "\"pmpaddr26\"" } }, { "number": 92, "source": "mapping clause csr_name_map = 0x3CB <-> \"pmpaddr27\"", "left": { "type": "literal", "value": "0x3CB" }, "right": { "type": "literal", "value": "\"pmpaddr27\"" } }, { "number": 93, "source": "mapping clause csr_name_map = 0x3CC <-> \"pmpaddr28\"", "left": { "type": "literal", "value": "0x3CC" }, "right": { "type": "literal", "value": "\"pmpaddr28\"" } }, { "number": 94, "source": "mapping clause csr_name_map = 0x3CD <-> \"pmpaddr29\"", "left": { "type": "literal", "value": "0x3CD" }, "right": { "type": "literal", "value": "\"pmpaddr29\"" } }, { "number": 95, "source": "mapping clause csr_name_map = 0x3CE <-> \"pmpaddr30\"", "left": { "type": "literal", "value": "0x3CE" }, "right": { "type": "literal", "value": "\"pmpaddr30\"" } }, { "number": 96, "source": "mapping clause csr_name_map = 0x3CF <-> \"pmpaddr31\"", "left": { "type": "literal", "value": "0x3CF" }, "right": { "type": "literal", "value": "\"pmpaddr31\"" } }, { "number": 97, "source": "mapping clause csr_name_map = 0x3D0 <-> \"pmpaddr32\"", "left": { "type": "literal", "value": "0x3D0" }, "right": { "type": "literal", "value": "\"pmpaddr32\"" } }, { "number": 98, "source": "mapping clause csr_name_map = 0x3D1 <-> \"pmpaddr33\"", "left": { "type": "literal", "value": "0x3D1" }, "right": { "type": "literal", "value": "\"pmpaddr33\"" } }, { "number": 99, "source": "mapping clause csr_name_map = 0x3D2 <-> \"pmpaddr34\"", "left": { "type": "literal", "value": "0x3D2" }, "right": { "type": "literal", "value": "\"pmpaddr34\"" } }, { "number": 100, "source": "mapping clause csr_name_map = 0x3D3 <-> \"pmpaddr35\"", "left": { "type": "literal", "value": "0x3D3" }, "right": { "type": "literal", "value": "\"pmpaddr35\"" } }, { "number": 101, "source": "mapping clause csr_name_map = 0x3D4 <-> \"pmpaddr36\"", "left": { "type": "literal", "value": "0x3D4" }, "right": { "type": "literal", "value": "\"pmpaddr36\"" } }, { "number": 102, "source": "mapping clause csr_name_map = 0x3D5 <-> \"pmpaddr37\"", "left": { "type": "literal", "value": "0x3D5" }, "right": { "type": "literal", "value": "\"pmpaddr37\"" } }, { "number": 103, "source": "mapping clause csr_name_map = 0x3D6 <-> \"pmpaddr38\"", "left": { "type": "literal", "value": "0x3D6" }, "right": { "type": "literal", "value": "\"pmpaddr38\"" } }, { "number": 104, "source": "mapping clause csr_name_map = 0x3D7 <-> \"pmpaddr39\"", "left": { "type": "literal", "value": "0x3D7" }, "right": { "type": "literal", "value": "\"pmpaddr39\"" } }, { "number": 105, "source": "mapping clause csr_name_map = 0x3D8 <-> \"pmpaddr40\"", "left": { "type": "literal", "value": "0x3D8" }, "right": { "type": "literal", "value": "\"pmpaddr40\"" } }, { "number": 106, "source": "mapping clause csr_name_map = 0x3D9 <-> \"pmpaddr41\"", "left": { "type": "literal", "value": "0x3D9" }, "right": { "type": "literal", "value": "\"pmpaddr41\"" } }, { "number": 107, "source": "mapping clause csr_name_map = 0x3DA <-> \"pmpaddr42\"", "left": { "type": "literal", "value": "0x3DA" }, "right": { "type": "literal", "value": "\"pmpaddr42\"" } }, { "number": 108, "source": "mapping clause csr_name_map = 0x3DB <-> \"pmpaddr43\"", "left": { "type": "literal", "value": "0x3DB" }, "right": { "type": "literal", "value": "\"pmpaddr43\"" } }, { "number": 109, "source": "mapping clause csr_name_map = 0x3DC <-> \"pmpaddr44\"", "left": { "type": "literal", "value": "0x3DC" }, "right": { "type": "literal", "value": "\"pmpaddr44\"" } }, { "number": 110, "source": "mapping clause csr_name_map = 0x3DD <-> \"pmpaddr45\"", "left": { "type": "literal", "value": "0x3DD" }, "right": { "type": "literal", "value": "\"pmpaddr45\"" } }, { "number": 111, "source": "mapping clause csr_name_map = 0x3DE <-> \"pmpaddr46\"", "left": { "type": "literal", "value": "0x3DE" }, "right": { "type": "literal", "value": "\"pmpaddr46\"" } }, { "number": 112, "source": "mapping clause csr_name_map = 0x3DF <-> \"pmpaddr47\"", "left": { "type": "literal", "value": "0x3DF" }, "right": { "type": "literal", "value": "\"pmpaddr47\"" } }, { "number": 113, "source": "mapping clause csr_name_map = 0x3E0 <-> \"pmpaddr48\"", "left": { "type": "literal", "value": "0x3E0" }, "right": { "type": "literal", "value": "\"pmpaddr48\"" } }, { "number": 114, "source": "mapping clause csr_name_map = 0x3E1 <-> \"pmpaddr49\"", "left": { "type": "literal", "value": "0x3E1" }, "right": { "type": "literal", "value": "\"pmpaddr49\"" } }, { "number": 115, "source": "mapping clause csr_name_map = 0x3E2 <-> \"pmpaddr50\"", "left": { "type": "literal", "value": "0x3E2" }, "right": { "type": "literal", "value": "\"pmpaddr50\"" } }, { "number": 116, "source": "mapping clause csr_name_map = 0x3E3 <-> \"pmpaddr51\"", "left": { "type": "literal", "value": "0x3E3" }, "right": { "type": "literal", "value": "\"pmpaddr51\"" } }, { "number": 117, "source": "mapping clause csr_name_map = 0x3E4 <-> \"pmpaddr52\"", "left": { "type": "literal", "value": "0x3E4" }, "right": { "type": "literal", "value": "\"pmpaddr52\"" } }, { "number": 118, "source": "mapping clause csr_name_map = 0x3E5 <-> \"pmpaddr53\"", "left": { "type": "literal", "value": "0x3E5" }, "right": { "type": "literal", "value": "\"pmpaddr53\"" } }, { "number": 119, "source": "mapping clause csr_name_map = 0x3E6 <-> \"pmpaddr54\"", "left": { "type": "literal", "value": "0x3E6" }, "right": { "type": "literal", "value": "\"pmpaddr54\"" } }, { "number": 120, "source": "mapping clause csr_name_map = 0x3E7 <-> \"pmpaddr55\"", "left": { "type": "literal", "value": "0x3E7" }, "right": { "type": "literal", "value": "\"pmpaddr55\"" } }, { "number": 121, "source": "mapping clause csr_name_map = 0x3E8 <-> \"pmpaddr56\"", "left": { "type": "literal", "value": "0x3E8" }, "right": { "type": "literal", "value": "\"pmpaddr56\"" } }, { "number": 122, "source": "mapping clause csr_name_map = 0x3E9 <-> \"pmpaddr57\"", "left": { "type": "literal", "value": "0x3E9" }, "right": { "type": "literal", "value": "\"pmpaddr57\"" } }, { "number": 123, "source": "mapping clause csr_name_map = 0x3EA <-> \"pmpaddr58\"", "left": { "type": "literal", "value": "0x3EA" }, "right": { "type": "literal", "value": "\"pmpaddr58\"" } }, { "number": 124, "source": "mapping clause csr_name_map = 0x3EB <-> \"pmpaddr59\"", "left": { "type": "literal", "value": "0x3EB" }, "right": { "type": "literal", "value": "\"pmpaddr59\"" } }, { "number": 125, "source": "mapping clause csr_name_map = 0x3EC <-> \"pmpaddr60\"", "left": { "type": "literal", "value": "0x3EC" }, "right": { "type": "literal", "value": "\"pmpaddr60\"" } }, { "number": 126, "source": "mapping clause csr_name_map = 0x3ED <-> \"pmpaddr61\"", "left": { "type": "literal", "value": "0x3ED" }, "right": { "type": "literal", "value": "\"pmpaddr61\"" } }, { "number": 127, "source": "mapping clause csr_name_map = 0x3EE <-> \"pmpaddr62\"", "left": { "type": "literal", "value": "0x3EE" }, "right": { "type": "literal", "value": "\"pmpaddr62\"" } }, { "number": 128, "source": "mapping clause csr_name_map = 0x3EF <-> \"pmpaddr63\"", "left": { "type": "literal", "value": "0x3EF" }, "right": { "type": "literal", "value": "\"pmpaddr63\"" } }, { "number": 129, "source": "mapping clause csr_name_map = 0xB00 <-> \"mcycle\"", "left": { "type": "literal", "value": "0xB00" }, "right": { "type": "literal", "value": "\"mcycle\"" } }, { "number": 130, "source": "mapping clause csr_name_map = 0xB02 <-> \"minstret\"", "left": { "type": "literal", "value": "0xB02" }, "right": { "type": "literal", "value": "\"minstret\"" } }, { "number": 131, "source": "mapping clause csr_name_map = 0xB80 <-> \"mcycleh\"", "left": { "type": "literal", "value": "0xB80" }, "right": { "type": "literal", "value": "\"mcycleh\"" } }, { "number": 132, "source": "mapping clause csr_name_map = 0xB82 <-> \"minstreth\"", "left": { "type": "literal", "value": "0xB82" }, "right": { "type": "literal", "value": "\"minstreth\"" } }, { "number": 133, "source": "mapping clause csr_name_map = 0x7a0 <-> \"tselect\"", "left": { "type": "literal", "value": "0x7a0" }, "right": { "type": "literal", "value": "\"tselect\"" } }, { "number": 134, "source": "mapping clause csr_name_map = 0x7a1 <-> \"tdata1\"", "left": { "type": "literal", "value": "0x7a1" }, "right": { "type": "literal", "value": "\"tdata1\"" } }, { "number": 135, "source": "mapping clause csr_name_map = 0x7a2 <-> \"tdata2\"", "left": { "type": "literal", "value": "0x7a2" }, "right": { "type": "literal", "value": "\"tdata2\"" } }, { "number": 136, "source": "mapping clause csr_name_map = 0x7a3 <-> \"tdata3\"", "left": { "type": "literal", "value": "0x7a3" }, "right": { "type": "literal", "value": "\"tdata3\"" } }, { "number": 137, "source": "mapping clause csr_name_map = 0x008 <-> \"vstart\"", "left": { "type": "literal", "value": "0x008" }, "right": { "type": "literal", "value": "\"vstart\"" } }, { "number": 138, "source": "mapping clause csr_name_map = 0x009 <-> \"vxsat\"", "left": { "type": "literal", "value": "0x009" }, "right": { "type": "literal", "value": "\"vxsat\"" } }, { "number": 139, "source": "mapping clause csr_name_map = 0x00A <-> \"vxrm\"", "left": { "type": "literal", "value": "0x00A" }, "right": { "type": "literal", "value": "\"vxrm\"" } }, { "number": 140, "source": "mapping clause csr_name_map = 0x00F <-> \"vcsr\"", "left": { "type": "literal", "value": "0x00F" }, "right": { "type": "literal", "value": "\"vcsr\"" } }, { "number": 141, "source": "mapping clause csr_name_map = 0xC20 <-> \"vl\"", "left": { "type": "literal", "value": "0xC20" }, "right": { "type": "literal", "value": "\"vl\"" } }, { "number": 142, "source": "mapping clause csr_name_map = 0xC21 <-> \"vtype\"", "left": { "type": "literal", "value": "0xC21" }, "right": { "type": "literal", "value": "\"vtype\"" } }, { "number": 143, "source": "mapping clause csr_name_map = 0xC22 <-> \"vlenb\"", "left": { "type": "literal", "value": "0xC22" }, "right": { "type": "literal", "value": "\"vlenb\"" } }, { "number": 144, "source": "mapping clause csr_name_map = reg <-> hex_bits_12(reg)", "left": { "type": "id", "id": "reg" }, "right": { "type": "app", "id": "hex_bits_12", "patterns": [ { "type": "id", "id": "reg" } ] } } ] }, "encdec": { "mapping": [ { "number": 0, "source": "mapping clause encdec = UTYPE(imm, rd, op)\n <-> imm @ rd @ encdec_uop(op)", "left": { "type": "app", "id": "UTYPE", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rd" }, { "type": "app", "id": "encdec_uop", "patterns": [ { "type": "id", "id": "op" } ] } ] } }, { "number": 1, "source": "mapping clause encdec = RISCV_JAL(imm_19 @ imm_7_0 @ imm_8 @ imm_18_13 @ imm_12_9 @ 0b0, rd)\n <-> imm_19 : bits(1) @ imm_18_13 : bits(6) @ imm_12_9 : bits(4) @ imm_8 : bits(1) @ imm_7_0 : bits(8) @ rd @ 0b1101111", "left": { "type": "app", "id": "RISCV_JAL", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm_19" }, { "type": "id", "id": "imm_7_0" }, { "type": "id", "id": "imm_8" }, { "type": "id", "id": "imm_18_13" }, { "type": "id", "id": "imm_12_9" }, { "type": "literal", "value": "0b0" } ] }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm_19" }, { "type": "id", "id": "imm_18_13" }, { "type": "id", "id": "imm_12_9" }, { "type": "id", "id": "imm_8" }, { "type": "id", "id": "imm_7_0" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1101111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x6F, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 8, name: 'imm_7_0', attr: '8', type: 2 },\n { bits: 1, name: 'imm_8', attr: '1', type: 2 },\n { bits: 4, name: 'imm_12_9', attr: '4', type: 2 },\n { bits: 6, name: 'imm_18_13', attr: '6', type: 2 },\n { bits: 1, name: 'imm_19', attr: '1', type: 2 }\n]}" }, { "number": 2, "source": "mapping clause encdec = RISCV_JALR(imm, rs1, rd)\n <-> imm @ rs1 @ 0b000 @ rd @ 0b1100111", "left": { "type": "app", "id": "RISCV_JALR", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1100111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x67, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 'imm', attr: '12', type: 2 }\n]}" }, { "number": 3, "source": "mapping clause encdec = BTYPE(imm7_6 @ imm5_0 @ imm7_5_0 @ imm5_4_1 @ 0b0, rs2, rs1, op)\n <-> imm7_6 : bits(1) @ imm7_5_0 : bits(6) @ rs2 @ rs1 @ encdec_bop(op) @ imm5_4_1 : bits(4) @ imm5_0 : bits(1) @ 0b1100011", "left": { "type": "app", "id": "BTYPE", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7_6" }, { "type": "id", "id": "imm5_0" }, { "type": "id", "id": "imm7_5_0" }, { "type": "id", "id": "imm5_4_1" }, { "type": "literal", "value": "0b0" } ] }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "op" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7_6" }, { "type": "id", "id": "imm7_5_0" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_bop", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "id", "id": "imm5_4_1" }, { "type": "id", "id": "imm5_0" }, { "type": "literal", "value": "0b1100011" } ] } }, { "number": 4, "source": "mapping clause encdec = ITYPE(imm, rs1, rd, op)\n <-> imm @ rs1 @ encdec_iop(op) @ rd @ 0b0010011", "left": { "type": "app", "id": "ITYPE", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "op" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_iop", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] } }, { "number": 5, "source": "mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SLLI) <-> 0b000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero", "left": { "type": "app", "id": "SHIFTIOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SLLI" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000000" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x00, attr: '6', type: 8 }\n]}" }, { "number": 6, "source": "mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRLI) <-> 0b000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero", "left": { "type": "app", "id": "SHIFTIOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SRLI" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000000" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x00, attr: '6', type: 8 }\n]}" }, { "number": 7, "source": "mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRAI) <-> 0b010000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero", "left": { "type": "app", "id": "SHIFTIOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SRAI" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010000" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x10, attr: '6', type: 8 }\n]}" }, { "number": 8, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_ADD) <-> 0b0000000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ADD" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 9, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SLT) <-> 0b0000000 @ rs2 @ rs1 @ 0b010 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SLT" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 10, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SLTU) <-> 0b0000000 @ rs2 @ rs1 @ 0b011 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SLTU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 11, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_AND) <-> 0b0000000 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_AND" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b111" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 12, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_OR) <-> 0b0000000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_OR" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 13, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_XOR) <-> 0b0000000 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_XOR" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 14, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SLL) <-> 0b0000000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SLL" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 15, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SRL) <-> 0b0000000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SRL" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 16, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SUB) <-> 0b0100000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SUB" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x20, attr: '7', type: 8 }\n]}" }, { "number": 17, "source": "mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SRA) <-> 0b0100000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011", "left": { "type": "app", "id": "RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SRA" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x20, attr: '7', type: 8 }\n]}" }, { "number": 18, "source": "mapping clause encdec = LOAD(imm, rs1, rd, is_unsigned, size, false, false) if (word_width_bytes(size) < sizeof(xlen_bytes)) | (not(is_unsigned) & word_width_bytes(size) <= sizeof(xlen_bytes))\n <-> imm @ rs1 @ bool_bits(is_unsigned) @ size_bits(size) @ rd @ 0b0000011 if (word_width_bytes(size) < sizeof(xlen_bytes)) | (not(is_unsigned) & word_width_bytes(size) <= sizeof(xlen_bytes))", "left": { "type": "app", "id": "LOAD", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "is_unsigned" }, { "type": "id", "id": "size" }, { "type": "literal", "value": "false" }, { "type": "literal", "value": "false" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "bool_bits", "patterns": [ { "type": "id", "id": "is_unsigned" } ] }, { "type": "app", "id": "size_bits", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0000011" } ] } }, { "number": 19, "source": "mapping clause encdec = STORE(imm7 @ imm5, rs2, rs1, size, false, false) if word_width_bytes(size) <= sizeof(xlen_bytes)\n <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ imm5 : bits(5) @ 0b0100011 if word_width_bytes(size) <= sizeof(xlen_bytes)", "left": { "type": "app", "id": "STORE", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7" }, { "type": "id", "id": "imm5" } ] }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "size" }, { "type": "literal", "value": "false" }, { "type": "literal", "value": "false" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b0" }, { "type": "app", "id": "size_bits", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "id", "id": "imm5" }, { "type": "literal", "value": "0b0100011" } ] } }, { "number": 20, "source": "mapping clause encdec = ADDIW(imm, rs1, rd)\n if sizeof(xlen) == 64\n <-> imm @ rs1 @ 0b000 @ rd @ 0b0011011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "ADDIW", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 'imm', attr: '12', type: 2 }\n]}" }, { "number": 21, "source": "mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_ADDW)\n if sizeof(xlen) == 64\n <-> 0b0000000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ADDW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 22, "source": "mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SUBW)\n if sizeof(xlen) == 64\n <-> 0b0100000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SUBW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x20, attr: '7', type: 8 }\n]}" }, { "number": 23, "source": "mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SLLW)\n if sizeof(xlen) == 64\n <-> 0b0000000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0111011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SLLW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 24, "source": "mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SRLW)\n if sizeof(xlen) == 64\n <-> 0b0000000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SRLW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 25, "source": "mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SRAW)\n if sizeof(xlen) == 64\n <-> 0b0100000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SRAW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x20, attr: '7', type: 8 }\n]}" }, { "number": 26, "source": "mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SLLIW)\n if sizeof(xlen) == 64\n <-> 0b0000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0011011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "SHIFTIWOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SLLIW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'shamt', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 27, "source": "mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRLIW)\n if sizeof(xlen) == 64\n <-> 0b0000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "SHIFTIWOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SRLIW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'shamt', attr: '5', type: 2 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 28, "source": "mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRAIW)\n if sizeof(xlen) == 64\n <-> 0b0100000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "SHIFTIWOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SRAIW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'shamt', attr: '5', type: 2 },\n { bits: 7, name: 0x20, attr: '7', type: 8 }\n]}" }, { "number": 29, "source": "mapping clause encdec = FENCE(pred, succ)\n <-> 0b0000 @ pred @ succ @ 0b00000 @ 0b000 @ 0b00000 @ 0b0001111", "left": { "type": "app", "id": "FENCE", "patterns": [ { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000" }, { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b0001111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x0F, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 4, name: 'succ', attr: '4', type: 2 },\n { bits: 4, name: 'pred', attr: '4', type: 2 },\n { bits: 4, name: 0x0, attr: '4', type: 8 }\n]}" }, { "number": 30, "source": "mapping clause encdec = FENCE_TSO(pred, succ)\n <-> 0b1000 @ pred @ succ @ 0b00000 @ 0b000 @ 0b00000 @ 0b0001111", "left": { "type": "app", "id": "FENCE_TSO", "patterns": [ { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1000" }, { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b0001111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x0F, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 4, name: 'succ', attr: '4', type: 2 },\n { bits: 4, name: 'pred', attr: '4', type: 2 },\n { bits: 4, name: 0x8, attr: '4', type: 8 }\n]}" }, { "number": 31, "source": "mapping clause encdec = FENCEI()\n <-> 0b000000000000 @ 0b00000 @ 0b001 @ 0b00000 @ 0b0001111", "left": { "type": "app", "id": "FENCEI", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000000000000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b001" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b0001111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x0F, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 12, name: 0x000, attr: '12', type: 8 }\n]}" }, { "number": 32, "source": "mapping clause encdec = ECALL()\n <-> 0b000000000000 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011", "left": { "type": "app", "id": "ECALL", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000000000000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b1110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x73, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 12, name: 0x000, attr: '12', type: 8 }\n]}" }, { "number": 33, "source": "mapping clause encdec = MRET()\n <-> 0b0011000 @ 0b00010 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011", "left": { "type": "app", "id": "MRET", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0011000" }, { "type": "literal", "value": "0b00010" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b1110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x73, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 0x02, attr: '5', type: 8 },\n { bits: 7, name: 0x18, attr: '7', type: 8 }\n]}" }, { "number": 34, "source": "mapping clause encdec = SRET()\n <-> 0b0001000 @ 0b00010 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011", "left": { "type": "app", "id": "SRET", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0001000" }, { "type": "literal", "value": "0b00010" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b1110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x73, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 0x02, attr: '5', type: 8 },\n { bits: 7, name: 0x08, attr: '7', type: 8 }\n]}" }, { "number": 35, "source": "mapping clause encdec = EBREAK()\n <-> 0b000000000001 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011", "left": { "type": "app", "id": "EBREAK", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000000000001" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b1110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x73, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 12, name: 0x001, attr: '12', type: 8 }\n]}" }, { "number": 36, "source": "mapping clause encdec = WFI()\n <-> 0b000100000101 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011", "left": { "type": "app", "id": "WFI", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000100000101" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b1110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x73, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 12, name: 0x105, attr: '12', type: 8 }\n]}" }, { "number": 37, "source": "mapping clause encdec = SFENCE_VMA(rs1, rs2)\n <-> 0b0001001 @ rs2 @ rs1 @ 0b000 @ 0b00000 @ 0b1110011", "left": { "type": "app", "id": "SFENCE_VMA", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0001001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b1110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x73, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x09, attr: '7', type: 8 }\n]}" }, { "number": 38, "source": "mapping clause encdec = LOADRES(aq, rl, rs1, size, rd) if amo_width_valid(size)\n <-> 0b00010 @ bool_bits(aq) @ bool_bits(rl) @ 0b00000 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111 if amo_width_valid(size)", "left": { "type": "app", "id": "LOADRES", "patterns": [ { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "size" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00010" }, { "type": "app", "id": "bool_bits", "patterns": [ { "type": "id", "id": "aq" } ] }, { "type": "app", "id": "bool_bits", "patterns": [ { "type": "id", "id": "rl" } ] }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b0" }, { "type": "app", "id": "size_bits", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0101111" } ] } }, { "number": 39, "source": "mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd) if amo_width_valid(size)\n <-> 0b00011 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111 if amo_width_valid(size)", "left": { "type": "app", "id": "STORECON", "patterns": [ { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "size" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00011" }, { "type": "app", "id": "bool_bits", "patterns": [ { "type": "id", "id": "aq" } ] }, { "type": "app", "id": "bool_bits", "patterns": [ { "type": "id", "id": "rl" } ] }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b0" }, { "type": "app", "id": "size_bits", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0101111" } ] } }, { "number": 40, "source": "mapping clause encdec = AMO(op, aq, rl, rs2, rs1, size, rd) if amo_width_valid(size)\n <-> encdec_amoop(op) @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111 if amo_width_valid(size)", "left": { "type": "app", "id": "AMO", "patterns": [ { "type": "id", "id": "op" }, { "type": "id", "id": "aq" }, { "type": "id", "id": "rl" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "size" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_amoop", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "app", "id": "bool_bits", "patterns": [ { "type": "id", "id": "aq" } ] }, { "type": "app", "id": "bool_bits", "patterns": [ { "type": "id", "id": "rl" } ] }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b0" }, { "type": "app", "id": "size_bits", "patterns": [ { "type": "id", "id": "size" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0101111" } ] } }, { "number": 41, "source": "mapping clause encdec = MUL(rs2, rs1, rd, high, signed1, signed2)\n <-> 0b0000001 @ rs2 @ rs1 @ encdec_mul_op(high, signed1, signed2) : bits(3) @ rd @ 0b0110011", "left": { "type": "app", "id": "MUL", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "high" }, { "type": "id", "id": "signed1" }, { "type": "id", "id": "signed2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_mul_op", "patterns": [ { "type": "tuple", "patterns": [ { "type": "id", "id": "high" }, { "type": "id", "id": "signed1" }, { "type": "id", "id": "signed2" } ] } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] } }, { "number": 42, "source": "mapping clause encdec = DIV(rs2, rs1, rd, s)\n <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0110011", "left": { "type": "app", "id": "DIV", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b10" }, { "type": "app", "id": "bool_not_bits", "patterns": [ { "type": "id", "id": "s" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] } }, { "number": 43, "source": "mapping clause encdec = REM(rs2, rs1, rd, s)\n <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0110011", "left": { "type": "app", "id": "REM", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b11" }, { "type": "app", "id": "bool_not_bits", "patterns": [ { "type": "id", "id": "s" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] } }, { "number": 44, "source": "mapping clause encdec = MULW(rs2, rs1, rd)\n if sizeof(xlen) == 64\n <-> 0b0000001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "MULW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x01, attr: '7', type: 8 }\n]}" }, { "number": 45, "source": "mapping clause encdec = DIVW(rs2, rs1, rd, s)\n if sizeof(xlen) == 64\n <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0111011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "DIVW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b10" }, { "type": "app", "id": "bool_not_bits", "patterns": [ { "type": "id", "id": "s" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] } }, { "number": 46, "source": "mapping clause encdec = REMW(rs2, rs1, rd, s)\n if sizeof(xlen) == 64\n <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0111011\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "REMW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "s" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b11" }, { "type": "app", "id": "bool_not_bits", "patterns": [ { "type": "id", "id": "s" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] } }, { "number": 47, "source": "mapping clause encdec = CSR(csr, rs1, rd, is_imm, op)\n <-> csr @ rs1 @ bool_bits(is_imm) @ encdec_csrop(op) @ rd @ 0b1110011", "left": { "type": "app", "id": "CSR", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "is_imm" }, { "type": "id", "id": "op" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "csr" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "bool_bits", "patterns": [ { "type": "id", "id": "is_imm" } ] }, { "type": "app", "id": "encdec_csrop", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1110011" } ] } }, { "number": 48, "source": "mapping clause encdec = URET()\n <-> 0b0000000 @ 0b00010 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011", "left": { "type": "app", "id": "URET", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "literal", "value": "0b00010" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b1110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x73, attr: '7', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 0x02, attr: '5', type: 8 },\n { bits: 7, name: 0x00, attr: '7', type: 8 }\n]}" }, { "number": 49, "source": "mapping clause encdec = FENCE_RESERVED(fm, pred, succ, rs, rd)\n if (fm != 0b0000 & fm != 0b1000) | rs != 0b00000 | rd != 0b00000\n <-> fm : bits(4) @ pred : bits(4) @ succ : bits(4) @ rs : regidx @ 0b000 @ rd : regidx @ 0b0001111\n if (fm != 0b0000 & fm != 0b1000) | rs != 0b00000 | rd != 0b00000", "left": { "type": "app", "id": "FENCE_RESERVED", "patterns": [ { "type": "id", "id": "fm" }, { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" }, { "type": "id", "id": "rs" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "fm" }, { "type": "id", "id": "pred" }, { "type": "id", "id": "succ" }, { "type": "id", "id": "rs" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0001111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x0F, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs', attr: '5', type: 2 },\n { bits: 4, name: 'succ', attr: '4', type: 2 },\n { bits: 4, name: 'pred', attr: '4', type: 2 },\n { bits: 4, name: 'fm', attr: '4', type: 2 }\n]}" }, { "number": 50, "source": "mapping clause encdec = FENCEI_RESERVED(imm, rs, rd)\n if imm != 0b000000000000 | rs != zreg | rd != zreg\n <-> imm : bits(12) @ rs : regidx @ 0b001 @ rd : regidx @ 0b0001111\n if imm != 0b000000000000 | rs != zreg | rd != zreg", "left": { "type": "app", "id": "FENCEI_RESERVED", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0001111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x0F, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs', attr: '5', type: 2 },\n { bits: 12, name: 'imm', attr: '12', type: 2 }\n]}" }, { "number": 51, "source": "mapping clause encdec = LOAD_FP(imm, rs1, rd, HALF) if haveZfh()\n <-> imm @ rs1 @ 0b001 @ rd @ 0b000_0111 if haveZfh()", "left": { "type": "app", "id": "LOAD_FP", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "HALF" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0000111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x07, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 'imm', attr: '12', type: 2 }\n]}" }, { "number": 52, "source": "mapping clause encdec = LOAD_FP(imm, rs1, rd, WORD) if haveFExt()\n <-> imm @ rs1 @ 0b010 @ rd @ 0b000_0111 if haveFExt()", "left": { "type": "app", "id": "LOAD_FP", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "WORD" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0000111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x07, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 'imm', attr: '12', type: 2 }\n]}" }, { "number": 53, "source": "mapping clause encdec = LOAD_FP(imm, rs1, rd, DOUBLE) if haveDExt()\n <-> imm @ rs1 @ 0b011 @ rd @ 0b000_0111 if haveDExt()", "left": { "type": "app", "id": "LOAD_FP", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "DOUBLE" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0000111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x07, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 'imm', attr: '12', type: 2 }\n]}" }, { "number": 54, "source": "mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, HALF) if haveZfh()\n <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b001 @ imm5 : bits(5) @ 0b010_0111 if haveZfh()", "left": { "type": "app", "id": "STORE_FP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7" }, { "type": "id", "id": "imm5" } ] }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "HALF" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "imm5" }, { "type": "literal", "value": "0b0100111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x27, attr: '7', type: 8 },\n { bits: 5, name: 'imm5', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 'imm7', attr: '7', type: 2 }\n]}" }, { "number": 55, "source": "mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, WORD) if haveFExt()\n <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b010 @ imm5 : bits(5) @ 0b010_0111 if haveFExt()", "left": { "type": "app", "id": "STORE_FP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7" }, { "type": "id", "id": "imm5" } ] }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "WORD" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "imm5" }, { "type": "literal", "value": "0b0100111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x27, attr: '7', type: 8 },\n { bits: 5, name: 'imm5', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 'imm7', attr: '7', type: 2 }\n]}" }, { "number": 56, "source": "mapping clause encdec = STORE_FP(imm7 @ imm5, rs2, rs1, DOUBLE) if haveDExt()\n <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b011 @ imm5 : bits(5) @ 0b010_0111 if haveDExt()", "left": { "type": "app", "id": "STORE_FP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7" }, { "type": "id", "id": "imm5" } ] }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "DOUBLE" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm7" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "imm5" }, { "type": "literal", "value": "0b0100111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x27, attr: '7', type: 8 },\n { bits: 5, name: 'imm5', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 'imm7', attr: '7', type: 2 }\n]}" }, { "number": 57, "source": "mapping clause encdec =\n F_MADD_TYPE_S(rs3, rs2, rs1, rm, rd, FMADD_S) if haveSingleFPU()\n<-> rs3 @ 0b00 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_MADD_TYPE_S", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMADD_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1000011" } ] } }, { "number": 58, "source": "mapping clause encdec =\n F_MADD_TYPE_S(rs3, rs2, rs1, rm, rd, FMSUB_S) if haveSingleFPU()\n<-> rs3 @ 0b00 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_0111 if haveSingleFPU()", "left": { "type": "app", "id": "F_MADD_TYPE_S", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMSUB_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1000111" } ] } }, { "number": 59, "source": "mapping clause encdec =\n F_MADD_TYPE_S(rs3, rs2, rs1, rm, rd, FNMSUB_S) if haveSingleFPU()\n<-> rs3 @ 0b00 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_1011 if haveSingleFPU()", "left": { "type": "app", "id": "F_MADD_TYPE_S", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FNMSUB_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1001011" } ] } }, { "number": 60, "source": "mapping clause encdec =\n F_MADD_TYPE_S(rs3, rs2, rs1, rm, rd, FNMADD_S) if haveSingleFPU()\n<-> rs3 @ 0b00 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_1111 if haveSingleFPU()", "left": { "type": "app", "id": "F_MADD_TYPE_S", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FNMADD_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1001111" } ] } }, { "number": 61, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_S(rs2, rs1, rm, rd, FADD_S) if haveSingleFPU()\n<-> 0b000_0000 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FADD_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 62, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_S(rs2, rs1, rm, rd, FSUB_S) if haveSingleFPU()\n<-> 0b000_0100 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSUB_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 63, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_S(rs2, rs1, rm, rd, FMUL_S) if haveSingleFPU()\n<-> 0b000_1000 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMUL_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0001000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 64, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_S(rs2, rs1, rm, rd, FDIV_S) if haveSingleFPU()\n<-> 0b000_1100 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FDIV_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0001100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 65, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FSQRT_S) if haveSingleFPU()\n<-> 0b010_1100 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0101100" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 66, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_W_S) if haveSingleFPU()\n<-> 0b110_0000 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100000" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 67, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_WU_S) if haveSingleFPU()\n<-> 0b110_0000 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100000" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 68, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_W) if haveSingleFPU()\n<-> 0b110_1000 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_W" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101000" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 69, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_WU) if haveSingleFPU()\n<-> 0b110_1000 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_WU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101000" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 70, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S) if haveSingleFPU() & sizeof(xlen) >= 64\n<-> 0b110_0000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100000" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 71, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S) if haveSingleFPU() & sizeof(xlen) >= 64\n<-> 0b110_0000 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100000" }, { "type": "literal", "value": "0b00011" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 72, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L) if haveSingleFPU() & sizeof(xlen) >= 64\n<-> 0b110_1000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_L" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101000" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 73, "source": "mapping clause encdec =\n F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_LU) if haveSingleFPU() & sizeof(xlen) >= 64\n<-> 0b110_1000 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_LU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101000" }, { "type": "literal", "value": "0b00011" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 74, "source": "mapping clause encdec = F_BIN_TYPE_S(rs2, rs1, rd, FSGNJ_S) if haveSingleFPU()\n <-> 0b001_0000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 75, "source": "mapping clause encdec = F_BIN_TYPE_S(rs2, rs1, rd, FSGNJN_S) if haveSingleFPU()\n <-> 0b001_0000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 76, "source": "mapping clause encdec = F_BIN_TYPE_S(rs2, rs1, rd, FSGNJX_S) if haveSingleFPU()\n <-> 0b001_0000 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 77, "source": "mapping clause encdec = F_BIN_TYPE_S(rs2, rs1, rd, FMIN_S) if haveSingleFPU()\n <-> 0b001_0100 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x14, attr: '7', type: 8 }\n]}" }, { "number": 78, "source": "mapping clause encdec = F_BIN_TYPE_S(rs2, rs1, rd, FMAX_S) if haveSingleFPU()\n <-> 0b001_0100 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x14, attr: '7', type: 8 }\n]}" }, { "number": 79, "source": "mapping clause encdec = F_BIN_TYPE_S(rs2, rs1, rd, FEQ_S) if haveSingleFPU()\n <-> 0b101_0000 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x50, attr: '7', type: 8 }\n]}" }, { "number": 80, "source": "mapping clause encdec = F_BIN_TYPE_S(rs2, rs1, rd, FLT_S) if haveSingleFPU()\n <-> 0b101_0000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x50, attr: '7', type: 8 }\n]}" }, { "number": 81, "source": "mapping clause encdec = F_BIN_TYPE_S(rs2, rs1, rd, FLE_S) if haveSingleFPU()\n <-> 0b101_0000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x50, attr: '7', type: 8 }\n]}" }, { "number": 82, "source": "mapping clause encdec = F_UN_TYPE_S(rs1, rd, FCLASS_S) if haveSingleFPU()\n <-> 0b111_0000 @ 0b00000 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveSingleFPU()", "left": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1110000" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x70, attr: '7', type: 8 }\n]}" }, { "number": 83, "source": "mapping clause encdec = F_UN_TYPE_S(rs1, rd, FMV_X_W) if haveFExt()\n <-> 0b111_0000 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveFExt()", "left": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_W" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1110000" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x70, attr: '7', type: 8 }\n]}" }, { "number": 84, "source": "mapping clause encdec = F_UN_TYPE_S(rs1, rd, FMV_W_X) if haveFExt()\n <-> 0b111_1000 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveFExt()", "left": { "type": "app", "id": "F_UN_TYPE_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_W_X" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1111000" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x78, attr: '7', type: 8 }\n]}" }, { "number": 85, "source": "mapping clause encdec =\n F_MADD_TYPE_D(rs3, rs2, rs1, rm, rd, FMADD_D) if haveDoubleFPU() & validDoubleRegs([rs3, rs2, rs1, rd])\n<-> rs3 @ 0b01 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_0011 if haveDoubleFPU() & validDoubleRegs([rs3, rs2, rs1, rd])", "left": { "type": "app", "id": "F_MADD_TYPE_D", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMADD_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1000011" } ] } }, { "number": 86, "source": "mapping clause encdec =\n F_MADD_TYPE_D(rs3, rs2, rs1, rm, rd, FMSUB_D) if haveDoubleFPU() & validDoubleRegs([rs3, rs2, rs1, rd])\n<-> rs3 @ 0b01 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_0111 if haveDoubleFPU() & validDoubleRegs([rs3, rs2, rs1, rd])", "left": { "type": "app", "id": "F_MADD_TYPE_D", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMSUB_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1000111" } ] } }, { "number": 87, "source": "mapping clause encdec =\n F_MADD_TYPE_D(rs3, rs2, rs1, rm, rd, FNMSUB_D) if haveDoubleFPU() & validDoubleRegs([rs3, rs2, rs1, rd])\n<-> rs3 @ 0b01 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_1011 if haveDoubleFPU() & validDoubleRegs([rs3, rs2, rs1, rd])", "left": { "type": "app", "id": "F_MADD_TYPE_D", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FNMSUB_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1001011" } ] } }, { "number": 88, "source": "mapping clause encdec =\n F_MADD_TYPE_D(rs3, rs2, rs1, rm, rd, FNMADD_D) if haveDoubleFPU() & validDoubleRegs([rs3, rs2, rs1, rd])\n<-> rs3 @ 0b01 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_1111 if haveDoubleFPU() & validDoubleRegs([rs3, rs2, rs1, rd])", "left": { "type": "app", "id": "F_MADD_TYPE_D", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FNMADD_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1001111" } ] } }, { "number": 89, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_D(rs2, rs1, rm, rd, FADD_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n<-> 0b000_0001 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FADD_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 90, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_D(rs2, rs1, rm, rd, FSUB_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n<-> 0b000_0101 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSUB_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 91, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_D(rs2, rs1, rm, rd, FMUL_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n<-> 0b000_1001 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMUL_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0001001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 92, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_D(rs2, rs1, rm, rd, FDIV_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n<-> 0b000_1101 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FDIV_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0001101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 93, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FSQRT_D) if haveDoubleFPU() & validDoubleRegs([rs1, rd])\n<-> 0b010_1101 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs1, rd])", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0101101" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 94, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_W_D) if haveDoubleFPU() & validDoubleRegs([rs1])\n<-> 0b110_0001 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs1])", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100001" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 95, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_WU_D) if haveDoubleFPU() & validDoubleRegs([rs1])\n<-> 0b110_0001 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs1])", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100001" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 96, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_W) if haveDoubleFPU() & validDoubleRegs([rd])\n<-> 0b110_1001 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rd])", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_W" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101001" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 97, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_WU) if haveDoubleFPU() & validDoubleRegs([rd])\n<-> 0b110_1001 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rd])", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_WU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101001" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 98, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_S_D) if haveDoubleFPU() & validDoubleRegs([rs1])\n<-> 0b010_0000 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs1])", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 99, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_S) if haveDoubleFPU() & validDoubleRegs([rd])\n<-> 0b010_0001 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rd])", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100001" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 100, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D) if haveDoubleFPU() & sizeof(xlen) >= 64\n<-> 0b110_0001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100001" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 101, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D) if haveDoubleFPU() & sizeof(xlen) >= 64\n<-> 0b110_0001 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100001" }, { "type": "literal", "value": "0b00011" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 102, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L) if haveDoubleFPU() & sizeof(xlen) >= 64\n<-> 0b110_1001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_L" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101001" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 103, "source": "mapping clause encdec =\n F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU) if haveDoubleFPU() & sizeof(xlen) >= 64\n<-> 0b110_1001 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_LU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101001" }, { "type": "literal", "value": "0b00011" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 104, "source": "mapping clause encdec = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJ_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n <-> 0b001_0001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x11, attr: '7', type: 8 }\n]}" }, { "number": 105, "source": "mapping clause encdec = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJN_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n <-> 0b001_0001 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x11, attr: '7', type: 8 }\n]}" }, { "number": 106, "source": "mapping clause encdec = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJX_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n <-> 0b001_0001 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x11, attr: '7', type: 8 }\n]}" }, { "number": 107, "source": "mapping clause encdec = F_BIN_TYPE_D(rs2, rs1, rd, FMIN_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n <-> 0b001_0101 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x15, attr: '7', type: 8 }\n]}" }, { "number": 108, "source": "mapping clause encdec = F_BIN_TYPE_D(rs2, rs1, rd, FMAX_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])\n <-> 0b001_0101 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1, rd])", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x15, attr: '7', type: 8 }\n]}" }, { "number": 109, "source": "mapping clause encdec = F_BIN_TYPE_D(rs2, rs1, rd, FEQ_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1])\n <-> 0b101_0001 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1])", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x51, attr: '7', type: 8 }\n]}" }, { "number": 110, "source": "mapping clause encdec = F_BIN_TYPE_D(rs2, rs1, rd, FLT_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1])\n <-> 0b101_0001 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1])", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x51, attr: '7', type: 8 }\n]}" }, { "number": 111, "source": "mapping clause encdec = F_BIN_TYPE_D(rs2, rs1, rd, FLE_D) if haveDoubleFPU() & validDoubleRegs([rs2, rs1])\n <-> 0b101_0001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs2, rs1])", "left": { "type": "app", "id": "F_BIN_TYPE_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x51, attr: '7', type: 8 }\n]}" }, { "number": 112, "source": "mapping clause encdec = F_UN_TYPE_D(rs1, rd, FCLASS_D) if haveDoubleFPU() & validDoubleRegs([rs1])\n <-> 0b111_0001 @ 0b00000 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveDoubleFPU() & validDoubleRegs([rs1])", "left": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1110001" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x71, attr: '7', type: 8 }\n]}" }, { "number": 113, "source": "mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_X_D) if haveDExt()\n <-> 0b111_0001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDExt()", "left": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1110001" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x71, attr: '7', type: 8 }\n]}" }, { "number": 114, "source": "mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_D_X) if haveDExt()\n <-> 0b111_1001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDExt()", "left": { "type": "app", "id": "F_UN_TYPE_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_D_X" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1111001" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x79, attr: '7', type: 8 }\n]}" }, { "number": 115, "source": "mapping clause encdec = RISCV_SLLIUW(shamt, rs1, rd) if haveZba() & sizeof(xlen) == 64\n <-> 0b000010 @ shamt @ rs1 @ 0b001 @ rd @ 0b0011011 if haveZba() & sizeof(xlen) == 64", "left": { "type": "app", "id": "RISCV_SLLIUW", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000010" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x02, attr: '6', type: 8 }\n]}" }, { "number": 116, "source": "mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_ADDUW) if haveZba() & sizeof(xlen) == 64\n <-> 0b0000100 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011 if haveZba() & sizeof(xlen) == 64", "left": { "type": "app", "id": "ZBA_RTYPEUW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ADDUW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x04, attr: '7', type: 8 }\n]}" }, { "number": 117, "source": "mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_SH1ADDUW) if haveZba() & sizeof(xlen) == 64\n <-> 0b0010000 @ rs2 @ rs1 @ 0b010 @ rd @ 0b0111011 if haveZba() & sizeof(xlen) == 64", "left": { "type": "app", "id": "ZBA_RTYPEUW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SH1ADDUW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 118, "source": "mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_SH2ADDUW) if haveZba() & sizeof(xlen) == 64\n <-> 0b0010000 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0111011 if haveZba() & sizeof(xlen) == 64", "left": { "type": "app", "id": "ZBA_RTYPEUW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SH2ADDUW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 119, "source": "mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_SH3ADDUW) if haveZba() & sizeof(xlen) == 64\n <-> 0b0010000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0111011 if haveZba() & sizeof(xlen) == 64", "left": { "type": "app", "id": "ZBA_RTYPEUW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SH3ADDUW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 120, "source": "mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, RISCV_SH1ADD) if haveZba()\n <-> 0b0010000 @ rs2 @ rs1 @ 0b010 @ rd @ 0b0110011 if haveZba()", "left": { "type": "app", "id": "ZBA_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SH1ADD" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 121, "source": "mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, RISCV_SH2ADD) if haveZba()\n <-> 0b0010000 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011 if haveZba()", "left": { "type": "app", "id": "ZBA_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SH2ADD" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 122, "source": "mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, RISCV_SH3ADD) if haveZba()\n <-> 0b0010000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011 if haveZba()", "left": { "type": "app", "id": "ZBA_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SH3ADD" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x10, attr: '7', type: 8 }\n]}" }, { "number": 123, "source": "mapping clause encdec = RISCV_RORIW(shamt, rs1, rd) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64\n <-> 0b0110000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64", "left": { "type": "app", "id": "RISCV_RORIW", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0110000" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'shamt', attr: '5', type: 2 },\n { bits: 7, name: 0x30, attr: '7', type: 8 }\n]}" }, { "number": 124, "source": "mapping clause encdec = RISCV_RORI(shamt, rs1, rd) if (haveZbb() | haveZbkb()) & (sizeof(xlen) == 64 | shamt[5] == bitzero)\n <-> 0b011000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | haveZbkb()) & (sizeof(xlen) == 64 | shamt[5] == bitzero)", "left": { "type": "app", "id": "RISCV_RORI", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011000" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x18, attr: '6', type: 8 }\n]}" }, { "number": 125, "source": "mapping clause encdec = ZBB_RTYPEW(rs2, rs1, rd, RISCV_ROLW) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64\n <-> 0b0110000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0111011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64", "left": { "type": "app", "id": "ZBB_RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ROLW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0110000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x30, attr: '7', type: 8 }\n]}" }, { "number": 126, "source": "mapping clause encdec = ZBB_RTYPEW(rs2, rs1, rd, RISCV_RORW) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64\n <-> 0b0110000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64", "left": { "type": "app", "id": "ZBB_RTYPEW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_RORW" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0110000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x30, attr: '7', type: 8 }\n]}" }, { "number": 127, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ANDN) if haveZbb() | haveZbkb()\n <-> 0b0100000 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011 if haveZbb() | haveZbkb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ANDN" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b111" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x20, attr: '7', type: 8 }\n]}" }, { "number": 128, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ORN) if haveZbb() | haveZbkb()\n <-> 0b0100000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011 if haveZbb() | haveZbkb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ORN" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x20, attr: '7', type: 8 }\n]}" }, { "number": 129, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_XNOR) if haveZbb() | haveZbkb()\n <-> 0b0100000 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011 if haveZbb() | haveZbkb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_XNOR" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x20, attr: '7', type: 8 }\n]}" }, { "number": 130, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_MAX) if haveZbb()\n <-> 0b0000101 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011 if haveZbb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_MAX" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x05, attr: '7', type: 8 }\n]}" }, { "number": 131, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_MAXU) if haveZbb()\n <-> 0b0000101 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011 if haveZbb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_MAXU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b111" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x05, attr: '7', type: 8 }\n]}" }, { "number": 132, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_MIN) if haveZbb()\n <-> 0b0000101 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011 if haveZbb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_MIN" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x05, attr: '7', type: 8 }\n]}" }, { "number": 133, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_MINU) if haveZbb()\n <-> 0b0000101 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 if haveZbb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_MINU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x05, attr: '7', type: 8 }\n]}" }, { "number": 134, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ROL) if haveZbb() | haveZbkb()\n <-> 0b0110000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if haveZbb() | haveZbkb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ROL" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0110000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x30, attr: '7', type: 8 }\n]}" }, { "number": 135, "source": "mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ROR) if haveZbb() | haveZbkb()\n <-> 0b0110000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 if haveZbb() | haveZbkb()", "left": { "type": "app", "id": "ZBB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ROR" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0110000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x30, attr: '7', type: 8 }\n]}" }, { "number": 136, "source": "mapping clause encdec = ZBB_EXTOP(rs1, rd, RISCV_SEXTB) if haveZbb()\n <-> 0b0110000 @ 0b00100 @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbb()", "left": { "type": "app", "id": "ZBB_EXTOP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SEXTB" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0110000" }, { "type": "literal", "value": "0b00100" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x04, attr: '5', type: 8 },\n { bits: 7, name: 0x30, attr: '7', type: 8 }\n]}" }, { "number": 137, "source": "mapping clause encdec = ZBB_EXTOP(rs1, rd, RISCV_SEXTH) if haveZbb()\n <-> 0b0110000 @ 0b00101 @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbb()", "left": { "type": "app", "id": "ZBB_EXTOP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_SEXTH" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0110000" }, { "type": "literal", "value": "0b00101" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x05, attr: '5', type: 8 },\n { bits: 7, name: 0x30, attr: '7', type: 8 }\n]}" }, { "number": 138, "source": "mapping clause encdec = ZBB_EXTOP(rs1, rd, RISCV_ZEXTH) if haveZbb() & sizeof(xlen) == 32\n <-> 0b0000100 @ 0b00000 @ rs1 @ 0b100 @ rd @ 0b0110011 if haveZbb() & sizeof(xlen) == 32", "left": { "type": "app", "id": "ZBB_EXTOP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ZEXTH" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000100" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x04, attr: '7', type: 8 }\n]}" }, { "number": 139, "source": "mapping clause encdec = ZBB_EXTOP(rs1, rd, RISCV_ZEXTH) if haveZbb() & sizeof(xlen) == 64\n <-> 0b0000100 @ 0b00000 @ rs1 @ 0b100 @ rd @ 0b0111011 if haveZbb() & sizeof(xlen) == 64", "left": { "type": "app", "id": "ZBB_EXTOP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_ZEXTH" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000100" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x04, attr: '7', type: 8 }\n]}" }, { "number": 140, "source": "mapping clause encdec = RISCV_REV8(rs1, rd) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 32\n <-> 0b011010011000 @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 32", "left": { "type": "app", "id": "RISCV_REV8", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011010011000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x698, attr: '12', type: 8 }\n]}" }, { "number": 141, "source": "mapping clause encdec = RISCV_REV8(rs1, rd) if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64\n <-> 0b011010111000 @ rs1 @ 0b101 @ rd @ 0b0010011 if (haveZbb() | haveZbkb()) & sizeof(xlen) == 64", "left": { "type": "app", "id": "RISCV_REV8", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011010111000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x6B8, attr: '12', type: 8 }\n]}" }, { "number": 142, "source": "mapping clause encdec = RISCV_ORCB(rs1, rd) if haveZbb()\n <-> 0b001010000111 @ rs1 @ 0b101 @ rd @ 0b0010011 if haveZbb()", "left": { "type": "app", "id": "RISCV_ORCB", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b001010000111" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x287, attr: '12', type: 8 }\n]}" }, { "number": 143, "source": "mapping clause encdec = RISCV_CPOP(rs1, rd) if haveZbb()\n <-> 0b011000000010 @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbb()", "left": { "type": "app", "id": "RISCV_CPOP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011000000010" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x602, attr: '12', type: 8 }\n]}" }, { "number": 144, "source": "mapping clause encdec = RISCV_CPOPW(rs1, rd) if haveZbb() & sizeof(xlen) == 64\n <-> 0b011000000010 @ rs1 @ 0b001 @ rd @ 0b0011011 if haveZbb() & sizeof(xlen) == 64", "left": { "type": "app", "id": "RISCV_CPOPW", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011000000010" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x602, attr: '12', type: 8 }\n]}" }, { "number": 145, "source": "mapping clause encdec = RISCV_CLZ(rs1, rd) if haveZbb()\n <-> 0b011000000000 @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbb()", "left": { "type": "app", "id": "RISCV_CLZ", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011000000000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x600, attr: '12', type: 8 }\n]}" }, { "number": 146, "source": "mapping clause encdec = RISCV_CLZW(rs1, rd) if haveZbb() & sizeof(xlen) == 64\n <-> 0b011000000000 @ rs1 @ 0b001 @ rd @ 0b0011011 if haveZbb() & sizeof(xlen) == 64", "left": { "type": "app", "id": "RISCV_CLZW", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011000000000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x600, attr: '12', type: 8 }\n]}" }, { "number": 147, "source": "mapping clause encdec = RISCV_CTZ(rs1, rd) if haveZbb()\n <-> 0b011000000001 @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbb()", "left": { "type": "app", "id": "RISCV_CTZ", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011000000001" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x601, attr: '12', type: 8 }\n]}" }, { "number": 148, "source": "mapping clause encdec = RISCV_CTZW(rs1, rd) if haveZbb() & sizeof(xlen) == 64\n <-> 0b011000000001 @ rs1 @ 0b001 @ rd @ 0b0011011 if haveZbb() & sizeof(xlen) == 64", "left": { "type": "app", "id": "RISCV_CTZW", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011000000001" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0011011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x1B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x601, attr: '12', type: 8 }\n]}" }, { "number": 149, "source": "mapping clause encdec = RISCV_CLMUL(rs2, rs1, rd) if haveZbc() | haveZbkc()\n <-> 0b0000101 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if haveZbc() | haveZbkc()", "left": { "type": "app", "id": "RISCV_CLMUL", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x05, attr: '7', type: 8 }\n]}" }, { "number": 150, "source": "mapping clause encdec = RISCV_CLMULH(rs2, rs1, rd) if haveZbc() | haveZbkc()\n <-> 0b0000101 @ rs2 @ rs1 @ 0b011 @ rd @ 0b0110011 if haveZbc() | haveZbkc()", "left": { "type": "app", "id": "RISCV_CLMULH", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x05, attr: '7', type: 8 }\n]}" }, { "number": 151, "source": "mapping clause encdec = RISCV_CLMULR(rs2, rs1, rd) if haveZbc()\n <-> 0b0000101 @ rs2 @ rs1 @ 0b010 @ rd @ 0b0110011 if haveZbc()", "left": { "type": "app", "id": "RISCV_CLMULR", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x05, attr: '7', type: 8 }\n]}" }, { "number": 152, "source": "mapping clause encdec = ZBS_IOP(shamt, rs1, rd, RISCV_BCLRI) if haveZbs() & (sizeof(xlen) == 64 | shamt[5] == bitzero)\n <-> 0b010010 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbs() & (sizeof(xlen) == 64 | shamt[5] == bitzero)", "left": { "type": "app", "id": "ZBS_IOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_BCLRI" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010010" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x12, attr: '6', type: 8 }\n]}" }, { "number": 153, "source": "mapping clause encdec = ZBS_IOP(shamt, rs1, rd, RISCV_BEXTI) if haveZbs() & (sizeof(xlen) == 64 | shamt[5] == bitzero)\n <-> 0b010010 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if haveZbs() & (sizeof(xlen) == 64 | shamt[5] == bitzero)", "left": { "type": "app", "id": "ZBS_IOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_BEXTI" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010010" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x12, attr: '6', type: 8 }\n]}" }, { "number": 154, "source": "mapping clause encdec = ZBS_IOP(shamt, rs1, rd, RISCV_BINVI) if haveZbs() & (sizeof(xlen) == 64 | shamt[5] == bitzero)\n <-> 0b011010 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbs() & (sizeof(xlen) == 64 | shamt[5] == bitzero)", "left": { "type": "app", "id": "ZBS_IOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_BINVI" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011010" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x1A, attr: '6', type: 8 }\n]}" }, { "number": 155, "source": "mapping clause encdec = ZBS_IOP(shamt, rs1, rd, RISCV_BSETI) if haveZbs() & (sizeof(xlen) == 64 | shamt[5] == bitzero)\n <-> 0b001010 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbs() & (sizeof(xlen) == 64 | shamt[5] == bitzero)", "left": { "type": "app", "id": "ZBS_IOP", "patterns": [ { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_BSETI" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b001010" }, { "type": "id", "id": "shamt" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 6, name: 'shamt', attr: '6', type: 2 },\n { bits: 6, name: 0x0A, attr: '6', type: 8 }\n]}" }, { "number": 156, "source": "mapping clause encdec = ZBS_RTYPE(rs2, rs1, rd, RISCV_BCLR) if haveZbs()\n <-> 0b0100100 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if haveZbs()", "left": { "type": "app", "id": "ZBS_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_BCLR" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x24, attr: '7', type: 8 }\n]}" }, { "number": 157, "source": "mapping clause encdec = ZBS_RTYPE(rs2, rs1, rd, RISCV_BEXT) if haveZbs()\n <-> 0b0100100 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 if haveZbs()", "left": { "type": "app", "id": "ZBS_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_BEXT" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x24, attr: '7', type: 8 }\n]}" }, { "number": 158, "source": "mapping clause encdec = ZBS_RTYPE(rs2, rs1, rd, RISCV_BINV) if haveZbs()\n <-> 0b0110100 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if haveZbs()", "left": { "type": "app", "id": "ZBS_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_BINV" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0110100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x34, attr: '7', type: 8 }\n]}" }, { "number": 159, "source": "mapping clause encdec = ZBS_RTYPE(rs2, rs1, rd, RISCV_BSET) if haveZbs()\n <-> 0b0010100 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if haveZbs()", "left": { "type": "app", "id": "ZBS_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_BSET" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x14, attr: '7', type: 8 }\n]}" }, { "number": 160, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_H(rs2, rs1, rm, rd, FADD_H) if haveHalfFPU()\n<-> 0b000_0010 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FADD_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 161, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_H(rs2, rs1, rm, rd, FSUB_H) if haveHalfFPU()\n<-> 0b000_0110 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSUB_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000110" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 162, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_H(rs2, rs1, rm, rd, FMUL_H) if haveHalfFPU()\n<-> 0b000_1010 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMUL_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0001010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 163, "source": "mapping clause encdec =\n F_BIN_RM_TYPE_H(rs2, rs1, rm, rd, FDIV_H) if haveHalfFPU()\n<-> 0b000_1110 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FDIV_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0001110" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 164, "source": "mapping clause encdec =\n F_MADD_TYPE_H(rs3, rs2, rs1, rm, rd, FMADD_H) if haveHalfFPU()\n<-> rs3 @ 0b10 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_MADD_TYPE_H", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMADD_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b10" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1000011" } ] } }, { "number": 165, "source": "mapping clause encdec =\n F_MADD_TYPE_H(rs3, rs2, rs1, rm, rd, FMSUB_H) if haveHalfFPU()\n<-> rs3 @ 0b10 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_0111 if haveHalfFPU()", "left": { "type": "app", "id": "F_MADD_TYPE_H", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMSUB_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b10" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1000111" } ] } }, { "number": 166, "source": "mapping clause encdec =\n F_MADD_TYPE_H(rs3, rs2, rs1, rm, rd, FNMSUB_H) if haveHalfFPU()\n<-> rs3 @ 0b10 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_1011 if haveHalfFPU()", "left": { "type": "app", "id": "F_MADD_TYPE_H", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FNMSUB_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b10" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1001011" } ] } }, { "number": 167, "source": "mapping clause encdec =\n F_MADD_TYPE_H(rs3, rs2, rs1, rm, rd, FNMADD_H) if haveHalfFPU()\n<-> rs3 @ 0b10 @ rs2 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b100_1111 if haveHalfFPU()", "left": { "type": "app", "id": "F_MADD_TYPE_H", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FNMADD_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "rs3" }, { "type": "literal", "value": "0b10" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1001111" } ] } }, { "number": 168, "source": "mapping clause encdec = F_BIN_TYPE_H(rs2, rs1, rd, FSGNJ_H) if haveHalfFPU()\n <-> 0b001_0010 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJ_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x12, attr: '7', type: 8 }\n]}" }, { "number": 169, "source": "mapping clause encdec = F_BIN_TYPE_H(rs2, rs1, rd, FSGNJN_H) if haveHalfFPU()\n <-> 0b001_0010 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJN_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x12, attr: '7', type: 8 }\n]}" }, { "number": 170, "source": "mapping clause encdec = F_BIN_TYPE_H(rs2, rs1, rd, FSGNJX_H) if haveHalfFPU()\n <-> 0b001_0010 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSGNJX_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x12, attr: '7', type: 8 }\n]}" }, { "number": 171, "source": "mapping clause encdec = F_BIN_TYPE_H(rs2, rs1, rd, FMIN_H) if haveHalfFPU()\n <-> 0b001_0110 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMIN_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010110" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x16, attr: '7', type: 8 }\n]}" }, { "number": 172, "source": "mapping clause encdec = F_BIN_TYPE_H(rs2, rs1, rd, FMAX_H) if haveHalfFPU()\n <-> 0b001_0110 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMAX_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010110" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x16, attr: '7', type: 8 }\n]}" }, { "number": 173, "source": "mapping clause encdec = F_BIN_TYPE_H(rs2, rs1, rd, FEQ_H) if haveHalfFPU()\n <-> 0b101_0010 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FEQ_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x52, attr: '7', type: 8 }\n]}" }, { "number": 174, "source": "mapping clause encdec = F_BIN_TYPE_H(rs2, rs1, rd, FLT_H) if haveHalfFPU()\n <-> 0b101_0010 @ rs2 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLT_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x52, attr: '7', type: 8 }\n]}" }, { "number": 175, "source": "mapping clause encdec = F_BIN_TYPE_H(rs2, rs1, rd, FLE_H) if haveHalfFPU()\n <-> 0b101_0010 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_BIN_TYPE_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FLE_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x52, attr: '7', type: 8 }\n]}" }, { "number": 176, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FSQRT_H) if haveHalfFPU()\n<-> 0b010_1110 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FSQRT_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0101110" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 177, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_W_H) if haveHalfFPU()\n<-> 0b110_0010 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_W_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100010" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 178, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_WU_H) if haveHalfFPU()\n<-> 0b110_0010 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_WU_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100010" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 179, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_W) if haveHalfFPU()\n<-> 0b110_1010 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_W" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101010" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 180, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_WU) if haveHalfFPU()\n<-> 0b110_1010 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_WU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101010" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 181, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_S) if haveHalfFPU()\n<-> 0b010_0010 @ 0b00000 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_S" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100010" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 182, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_D) if haveHalfFPU()\n<-> 0b010_0010 @ 0b00001 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_D" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100010" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 183, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_S_H) if haveHalfFPU()\n<-> 0b010_0000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_S_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 184, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_D_H) if haveHalfFPU()\n<-> 0b010_0001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_D_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100001" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 185, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_L_H) if haveHalfFPU() & sizeof(xlen) >= 64\n<-> 0b110_0010 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_L_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100010" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 186, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_LU_H) if haveHalfFPU() & sizeof(xlen) >= 64\n<-> 0b110_0010 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_LU_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100010" }, { "type": "literal", "value": "0b00011" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 187, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_L) if haveHalfFPU() & sizeof(xlen) >= 64\n<-> 0b110_1010 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_L" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101010" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 188, "source": "mapping clause encdec =\n F_UN_RM_TYPE_H(rs1, rm, rd, FCVT_H_LU) if haveHalfFPU() & sizeof(xlen) >= 64\n<-> 0b110_1010 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveHalfFPU() & sizeof(xlen) >= 64", "left": { "type": "app", "id": "F_UN_RM_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCVT_H_LU" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1101010" }, { "type": "literal", "value": "0b00011" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 189, "source": "mapping clause encdec = F_UN_TYPE_H(rs1, rd, FCLASS_H) if haveHalfFPU()\n <-> 0b111_0010 @ 0b00000 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveHalfFPU()", "left": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FCLASS_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1110010" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x72, attr: '7', type: 8 }\n]}" }, { "number": 190, "source": "mapping clause encdec = F_UN_TYPE_H(rs1, rd, FMV_X_H) if haveZfh()\n <-> 0b111_0010 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveZfh()", "left": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_X_H" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1110010" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x72, attr: '7', type: 8 }\n]}" }, { "number": 191, "source": "mapping clause encdec = F_UN_TYPE_H(rs1, rd, FMV_H_X) if haveZfh()\n <-> 0b111_1010 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveZfh()", "left": { "type": "app", "id": "F_UN_TYPE_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "FMV_H_X" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1111010" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 7, name: 0x7A, attr: '7', type: 8 }\n]}" }, { "number": 192, "source": "mapping clause encdec = RISCV_FLI_H(rs1, rd) if haveZfh() & haveZfa()\n <-> 0b111_1010 @ 0b00001 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveZfh() & haveZfa()", "left": { "type": "app", "id": "RISCV_FLI_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1111010" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x01, attr: '5', type: 8 },\n { bits: 7, name: 0x7A, attr: '7', type: 8 }\n]}" }, { "number": 193, "source": "mapping clause encdec = RISCV_FLI_S(rs1, rd) if haveZfa()\n <-> 0b111_1000 @ 0b00001 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveZfa()", "left": { "type": "app", "id": "RISCV_FLI_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1111000" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x01, attr: '5', type: 8 },\n { bits: 7, name: 0x78, attr: '7', type: 8 }\n]}" }, { "number": 194, "source": "mapping clause encdec = RISCV_FLI_D(rs1, rd) if haveDExt() & haveZfa()\n <-> 0b111_1001 @ 0b00001 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDExt() & haveZfa()", "left": { "type": "app", "id": "RISCV_FLI_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1111001" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x01, attr: '5', type: 8 },\n { bits: 7, name: 0x79, attr: '7', type: 8 }\n]}" }, { "number": 195, "source": "mapping clause encdec = RISCV_FMINM_H(rs2, rs1, rd) if haveZfh() & haveZfa()\n <-> 0b001_0110 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveZfh() & haveZfa()", "left": { "type": "app", "id": "RISCV_FMINM_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010110" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x16, attr: '7', type: 8 }\n]}" }, { "number": 196, "source": "mapping clause encdec = RISCV_FMAXM_H(rs2, rs1, rd) if haveZfh() & haveZfa()\n <-> 0b001_0110 @ rs2 @ rs1 @ 0b011 @ rd @ 0b101_0011 if haveZfh() & haveZfa()", "left": { "type": "app", "id": "RISCV_FMAXM_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010110" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x16, attr: '7', type: 8 }\n]}" }, { "number": 197, "source": "mapping clause encdec = RISCV_FMINM_S(rs2, rs1, rd) if haveZfa()\n <-> 0b001_0100 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveZfa()", "left": { "type": "app", "id": "RISCV_FMINM_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x14, attr: '7', type: 8 }\n]}" }, { "number": 198, "source": "mapping clause encdec = RISCV_FMAXM_S(rs2, rs1, rd) if haveZfa()\n <-> 0b001_0100 @ rs2 @ rs1 @ 0b011 @ rd @ 0b101_0011 if haveZfa()", "left": { "type": "app", "id": "RISCV_FMAXM_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x14, attr: '7', type: 8 }\n]}" }, { "number": 199, "source": "mapping clause encdec = RISCV_FMINM_D(rs2, rs1, rd) if haveDExt() & haveZfa()\n <-> 0b001_0101 @ rs2 @ rs1 @ 0b010 @ rd @ 0b101_0011 if haveDExt() & haveZfa()", "left": { "type": "app", "id": "RISCV_FMINM_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x15, attr: '7', type: 8 }\n]}" }, { "number": 200, "source": "mapping clause encdec = RISCV_FMAXM_D(rs2, rs1, rd) if haveDExt() & haveZfa()\n <-> 0b001_0101 @ rs2 @ rs1 @ 0b011 @ rd @ 0b101_0011 if haveDExt() & haveZfa()", "left": { "type": "app", "id": "RISCV_FMAXM_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x15, attr: '7', type: 8 }\n]}" }, { "number": 201, "source": "mapping clause encdec = RISCV_FROUND_H(rs1, rm, rd) if haveZfh() & haveZfa()\n <-> 0b010_0010 @ 0b00100 @ rs1 @ encdec_rounding_mode(rm) @ rd @ 0b101_0011 if haveZfh() & haveZfa()", "left": { "type": "app", "id": "RISCV_FROUND_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100010" }, { "type": "literal", "value": "0b00100" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 202, "source": "mapping clause encdec = RISCV_FROUNDNX_H(rs1, rm, rd) if haveZfh() & haveZfa()\n <-> 0b010_0010 @ 0b00101 @ rs1 @ encdec_rounding_mode(rm) @ rd @ 0b101_0011 if haveZfh() & haveZfa()", "left": { "type": "app", "id": "RISCV_FROUNDNX_H", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100010" }, { "type": "literal", "value": "0b00101" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 203, "source": "mapping clause encdec = RISCV_FROUND_S(rs1, rm, rd) if haveZfa()\n <-> 0b010_0000 @ 0b00100 @ rs1 @ encdec_rounding_mode(rm) @ rd @ 0b101_0011 if haveZfa()", "left": { "type": "app", "id": "RISCV_FROUND_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "literal", "value": "0b00100" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 204, "source": "mapping clause encdec = RISCV_FROUNDNX_S(rs1, rm, rd) if haveZfa()\n <-> 0b010_0000 @ 0b00101 @ rs1 @ encdec_rounding_mode(rm) @ rd @ 0b101_0011 if haveZfa()", "left": { "type": "app", "id": "RISCV_FROUNDNX_S", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100000" }, { "type": "literal", "value": "0b00101" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 205, "source": "mapping clause encdec = RISCV_FROUND_D(rs1, rm, rd) if haveDExt() & haveZfa()\n <-> 0b010_0001 @ 0b00100 @ rs1 @ encdec_rounding_mode(rm) @ rd @ 0b101_0011 if haveDExt() & haveZfa()", "left": { "type": "app", "id": "RISCV_FROUND_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100001" }, { "type": "literal", "value": "0b00100" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 206, "source": "mapping clause encdec = RISCV_FROUNDNX_D(rs1, rm, rd) if haveDExt() & haveZfa()\n <-> 0b010_0001 @ 0b00101 @ rs1 @ encdec_rounding_mode(rm) @ rd @ 0b101_0011 if haveDExt() & haveZfa()", "left": { "type": "app", "id": "RISCV_FROUNDNX_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0100001" }, { "type": "literal", "value": "0b00101" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_rounding_mode", "patterns": [ { "type": "id", "id": "rm" } ] }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] } }, { "number": 207, "source": "mapping clause encdec = RISCV_FMVH_X_D(rs1, rd) if haveDExt() & haveZfa() & in32BitMode()\n <-> 0b111_0001 @ 0b00001 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDExt() & haveZfa() & in32BitMode()", "left": { "type": "app", "id": "RISCV_FMVH_X_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1110001" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x01, attr: '5', type: 8 },\n { bits: 7, name: 0x71, attr: '7', type: 8 }\n]}" }, { "number": 208, "source": "mapping clause encdec = RISCV_FMVP_D_X(rs2, rs1, rd) if haveDExt() & haveZfa() & in32BitMode()\n <-> 0b101_1001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b101_0011 if haveDExt() & haveZfa() & in32BitMode()", "left": { "type": "app", "id": "RISCV_FMVP_D_X", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1011001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x59, attr: '7', type: 8 }\n]}" }, { "number": 209, "source": "mapping clause encdec = RISCV_FLEQ_H(rs2, rs1, rd) if haveZfh() & haveZfa()\n <-> 0b101_0010 @ rs2 @ rs1 @ 0b100 @ rd @ 0b101_0011 if haveZfh() & haveZfa()", "left": { "type": "app", "id": "RISCV_FLEQ_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x52, attr: '7', type: 8 }\n]}" }, { "number": 210, "source": "mapping clause encdec = RISCV_FLTQ_H(rs2, rs1, rd) if haveZfh() & haveZfa()\n <-> 0b101_0010 @ rs2 @ rs1 @ 0b101 @ rd @ 0b101_0011 if haveZfh() & haveZfa()", "left": { "type": "app", "id": "RISCV_FLTQ_H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x52, attr: '7', type: 8 }\n]}" }, { "number": 211, "source": "mapping clause encdec = RISCV_FLEQ_S(rs2, rs1, rd) if haveZfa()\n <-> 0b101_0000 @ rs2 @ rs1 @ 0b100 @ rd @ 0b101_0011 if haveZfa()", "left": { "type": "app", "id": "RISCV_FLEQ_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x50, attr: '7', type: 8 }\n]}" }, { "number": 212, "source": "mapping clause encdec = RISCV_FLTQ_S(rs2, rs1, rd) if haveZfa()\n <-> 0b101_0000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b101_0011 if haveZfa()", "left": { "type": "app", "id": "RISCV_FLTQ_S", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x50, attr: '7', type: 8 }\n]}" }, { "number": 213, "source": "mapping clause encdec = RISCV_FLEQ_D(rs2, rs1, rd) if haveDExt() & haveZfa()\n <-> 0b101_0001 @ rs2 @ rs1 @ 0b100 @ rd @ 0b101_0011 if haveDExt() & haveZfa()", "left": { "type": "app", "id": "RISCV_FLEQ_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x51, attr: '7', type: 8 }\n]}" }, { "number": 214, "source": "mapping clause encdec = RISCV_FLTQ_D(rs2, rs1, rd) if haveDExt() & haveZfa()\n <-> 0b101_0001 @ rs2 @ rs1 @ 0b101 @ rd @ 0b101_0011 if haveDExt() & haveZfa()", "left": { "type": "app", "id": "RISCV_FLTQ_D", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1010001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x51, attr: '7', type: 8 }\n]}" }, { "number": 215, "source": "mapping clause encdec = RISCV_FCVTMOD_W_D(rs1, rd) if haveDExt() & haveZfa()\n <-> 0b110_0001 @ 0b01000 @ rs1 @ 0b001 @ rd @ 0b101_0011 if haveDExt() & haveZfa()", "left": { "type": "app", "id": "RISCV_FCVTMOD_W_D", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100001" }, { "type": "literal", "value": "0b01000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x53, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 7, name: 0x61, attr: '7', type: 8 }\n]}" }, { "number": 216, "source": "mapping clause encdec = SHA256SUM0 (rs1, rd) if haveZknh()\n <-> 0b00 @ 0b01000 @ 0b00000 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SHA256SUM0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 217, "source": "mapping clause encdec = SHA256SUM1 (rs1, rd) if haveZknh()\n <-> 0b00 @ 0b01000 @ 0b00001 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SHA256SUM1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b00001" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x01, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 218, "source": "mapping clause encdec = SHA256SIG0 (rs1, rd) if haveZknh()\n <-> 0b00 @ 0b01000 @ 0b00010 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SHA256SIG0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x02, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 219, "source": "mapping clause encdec = SHA256SIG1 (rs1, rd) if haveZknh()\n <-> 0b00 @ 0b01000 @ 0b00011 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SHA256SIG1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b00011" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x03, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 220, "source": "mapping clause encdec = AES32ESMI (bs, rs2, rs1, rd) if haveZkne() & sizeof(xlen) == 32\n <-> bs @ 0b10011 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES32ESMI", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "bs" }, { "type": "literal", "value": "0b10011" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x13, attr: '5', type: 8 },\n { bits: 2, name: 'bs', attr: '2', type: 2 }\n]}" }, { "number": 221, "source": "mapping clause encdec = AES32ESI (bs, rs2, rs1, rd) if haveZkne() & sizeof(xlen) == 32\n <-> bs @ 0b10001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES32ESI", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "bs" }, { "type": "literal", "value": "0b10001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x11, attr: '5', type: 8 },\n { bits: 2, name: 'bs', attr: '2', type: 2 }\n]}" }, { "number": 222, "source": "mapping clause encdec = AES32DSMI (bs, rs2, rs1, rd) if haveZknd() & sizeof(xlen) == 32\n <-> bs @ 0b10111 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES32DSMI", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "bs" }, { "type": "literal", "value": "0b10111" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x17, attr: '5', type: 8 },\n { bits: 2, name: 'bs', attr: '2', type: 2 }\n]}" }, { "number": 223, "source": "mapping clause encdec = AES32DSI (bs, rs2, rs1, rd) if haveZknd() & sizeof(xlen) == 32\n <-> bs @ 0b10101 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES32DSI", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "bs" }, { "type": "literal", "value": "0b10101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x15, attr: '5', type: 8 },\n { bits: 2, name: 'bs', attr: '2', type: 2 }\n]}" }, { "number": 224, "source": "mapping clause encdec = SHA512SUM0R (rs2, rs1, rd) if haveZknh() & sizeof(xlen) == 32\n <-> 0b01 @ 0b01000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "SHA512SUM0R", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b01" }, { "type": "literal", "value": "0b01000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x1, attr: '2', type: 8 }\n]}" }, { "number": 225, "source": "mapping clause encdec = SHA512SUM1R (rs2, rs1, rd) if haveZknh() & sizeof(xlen) == 32\n <-> 0b01 @ 0b01001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "SHA512SUM1R", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b01" }, { "type": "literal", "value": "0b01001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x09, attr: '5', type: 8 },\n { bits: 2, name: 0x1, attr: '2', type: 8 }\n]}" }, { "number": 226, "source": "mapping clause encdec = SHA512SIG0L (rs2, rs1, rd) if haveZknh() & sizeof(xlen) == 32\n <-> 0b01 @ 0b01010 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "SHA512SIG0L", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b01" }, { "type": "literal", "value": "0b01010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x0A, attr: '5', type: 8 },\n { bits: 2, name: 0x1, attr: '2', type: 8 }\n]}" }, { "number": 227, "source": "mapping clause encdec = SHA512SIG0H (rs2, rs1, rd) if haveZknh() & sizeof(xlen) == 32\n <-> 0b01 @ 0b01110 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "SHA512SIG0H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b01" }, { "type": "literal", "value": "0b01110" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x0E, attr: '5', type: 8 },\n { bits: 2, name: 0x1, attr: '2', type: 8 }\n]}" }, { "number": 228, "source": "mapping clause encdec = SHA512SIG1L (rs2, rs1, rd) if haveZknh() & sizeof(xlen) == 32\n <-> 0b01 @ 0b01011 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "SHA512SIG1L", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b01" }, { "type": "literal", "value": "0b01011" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x0B, attr: '5', type: 8 },\n { bits: 2, name: 0x1, attr: '2', type: 8 }\n]}" }, { "number": 229, "source": "mapping clause encdec = SHA512SIG1H (rs2, rs1, rd) if haveZknh() & sizeof(xlen) == 32\n <-> 0b01 @ 0b01111 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "SHA512SIG1H", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b01" }, { "type": "literal", "value": "0b01111" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x0F, attr: '5', type: 8 },\n { bits: 2, name: 0x1, attr: '2', type: 8 }\n]}" }, { "number": 230, "source": "mapping clause encdec = AES64KS1I (rnum, rs1, rd) if (haveZkne() | haveZknd()) & (sizeof(xlen) == 64) & (rnum <_u 0xB)\n <-> 0b00 @ 0b11000 @ 0b1 @ rnum @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "AES64KS1I", "patterns": [ { "type": "id", "id": "rnum" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b11000" }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "rnum" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 4, name: 'rnum', attr: '4', type: 2 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 5, name: 0x18, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 231, "source": "mapping clause encdec = AES64IM (rs1, rd) if haveZknd() & sizeof(xlen) == 64\n <-> 0b00 @ 0b11000 @ 0b00000 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "AES64IM", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b11000" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 0x18, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 232, "source": "mapping clause encdec = AES64KS2 (rs2, rs1, rd) if (haveZkne() | haveZknd()) & sizeof(xlen) == 64\n <-> 0b01 @ 0b11111 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES64KS2", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b01" }, { "type": "literal", "value": "0b11111" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x1F, attr: '5', type: 8 },\n { bits: 2, name: 0x1, attr: '2', type: 8 }\n]}" }, { "number": 233, "source": "mapping clause encdec = AES64ESM (rs2, rs1, rd) if haveZkne() & sizeof(xlen) == 64\n <-> 0b00 @ 0b11011 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES64ESM", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b11011" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x1B, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 234, "source": "mapping clause encdec = AES64ES (rs2, rs1, rd) if haveZkne() & sizeof(xlen) == 64\n <-> 0b00 @ 0b11001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES64ES", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b11001" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x19, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 235, "source": "mapping clause encdec = AES64DSM (rs2, rs1, rd) if haveZknd() & sizeof(xlen) == 64\n <-> 0b00 @ 0b11111 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES64DSM", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b11111" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x1F, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 236, "source": "mapping clause encdec = AES64DS (rs2, rs1, rd) if haveZknd() & sizeof(xlen) == 64\n <-> 0b00 @ 0b11101 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "AES64DS", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b11101" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x1D, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 237, "source": "mapping clause encdec = SHA512SUM0 (rs1, rd) if haveZknh() & sizeof(xlen) == 64\n <-> 0b00 @ 0b01000 @ 0b00100 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SHA512SUM0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b00100" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x04, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 238, "source": "mapping clause encdec = SHA512SUM1 (rs1, rd) if haveZknh() & sizeof(xlen) == 64\n <-> 0b00 @ 0b01000 @ 0b00101 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SHA512SUM1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b00101" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x05, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 239, "source": "mapping clause encdec = SHA512SIG0 (rs1, rd) if haveZknh() & sizeof(xlen) == 64\n <-> 0b00 @ 0b01000 @ 0b00110 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SHA512SIG0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b00110" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x06, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 240, "source": "mapping clause encdec = SHA512SIG1 (rs1, rd) if haveZknh() & sizeof(xlen) == 64\n <-> 0b00 @ 0b01000 @ 0b00111 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SHA512SIG1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b00111" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x07, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 241, "source": "mapping clause encdec = SM3P0 (rs1, rd) if haveZksh()\n <-> 0b00 @ 0b01000 @ 0b01000 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SM3P0", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b01000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 242, "source": "mapping clause encdec = SM3P1 (rs1, rd) if haveZksh()\n <-> 0b00 @ 0b01000 @ 0b01001 @ rs1 @ 0b001 @ rd @ 0b0010011", "left": { "type": "app", "id": "SM3P1", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b01000" }, { "type": "literal", "value": "0b01001" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x09, attr: '5', type: 8 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 }\n]}" }, { "number": 243, "source": "mapping clause encdec = SM4ED (bs, rs2, rs1, rd) if haveZksed()\n <-> bs @ 0b11000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "SM4ED", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "bs" }, { "type": "literal", "value": "0b11000" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x18, attr: '5', type: 8 },\n { bits: 2, name: 'bs', attr: '2', type: 2 }\n]}" }, { "number": 244, "source": "mapping clause encdec = SM4KS (bs, rs2, rs1, rd) if haveZksed()\n <-> bs @ 0b11010 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011", "left": { "type": "app", "id": "SM4KS", "patterns": [ { "type": "id", "id": "bs" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "bs" }, { "type": "literal", "value": "0b11010" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x1A, attr: '5', type: 8 },\n { bits: 2, name: 'bs', attr: '2', type: 2 }\n]}" }, { "number": 245, "source": "mapping clause encdec = ZBKB_RTYPE(rs2, rs1, rd, RISCV_PACK) if haveZbkb()\n <-> 0b0000100 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011 if haveZbkb()", "left": { "type": "app", "id": "ZBKB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_PACK" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x04, attr: '7', type: 8 }\n]}" }, { "number": 246, "source": "mapping clause encdec = ZBKB_RTYPE(rs2, rs1, rd, RISCV_PACKH) if haveZbkb()\n <-> 0b0000100 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011 if haveZbkb()", "left": { "type": "app", "id": "ZBKB_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_PACKH" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b111" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x04, attr: '7', type: 8 }\n]}" }, { "number": 247, "source": "mapping clause encdec = ZBKB_PACKW(rs2, rs1, rd) if haveZbkb() & sizeof(xlen) == 64\n <-> 0b0000100 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0111011 if haveZbkb() & sizeof(xlen) == 64", "left": { "type": "app", "id": "ZBKB_PACKW", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0111011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x3B, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x04, attr: '7', type: 8 }\n]}" }, { "number": 248, "source": "mapping clause encdec = RISCV_ZIP(rs1, rd) if haveZbkb() & sizeof(xlen) == 32\n <-> 0b000010001111 @ rs1 @ 0b001 @ rd @ 0b0010011 if haveZbkb() & sizeof(xlen) == 32", "left": { "type": "app", "id": "RISCV_ZIP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000010001111" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x08F, attr: '12', type: 8 }\n]}" }, { "number": 249, "source": "mapping clause encdec = RISCV_UNZIP(rs1, rd) if haveZbkb() & sizeof(xlen) == 32\n <-> 0b000010001111 @ rs1 @ 0b101 @ rd @ 0b0010011 if haveZbkb() & sizeof(xlen) == 32", "left": { "type": "app", "id": "RISCV_UNZIP", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000010001111" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x08F, attr: '12', type: 8 }\n]}" }, { "number": 250, "source": "mapping clause encdec = RISCV_BREV8(rs1, rd) if haveZbkb()\n <-> 0b011010000111 @ rs1 @ 0b101 @ rd @ 0b0010011 if haveZbkb()", "left": { "type": "app", "id": "RISCV_BREV8", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011010000111" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0010011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x13, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 12, name: 0x687, attr: '12', type: 8 }\n]}" }, { "number": 251, "source": "mapping clause encdec = RISCV_XPERM8(rs2, rs1, rd) if haveZbkx()\n <-> 0b0010100 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011 if haveZbkx()", "left": { "type": "app", "id": "RISCV_XPERM8", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x14, attr: '7', type: 8 }\n]}" }, { "number": 252, "source": "mapping clause encdec = RISCV_XPERM4(rs2, rs1, rd) if haveZbkx()\n <-> 0b0010100 @ rs2 @ rs1 @ 0b010 @ rd @ 0b0110011 if haveZbkx()", "left": { "type": "app", "id": "RISCV_XPERM4", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0010100" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x14, attr: '7', type: 8 }\n]}" }, { "number": 253, "source": "mapping clause encdec = ZICOND_RTYPE(rs2, rs1, rd, RISCV_CZERO_EQZ) if haveZicond()\n <-> 0b0000111 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 if haveZicond()", "left": { "type": "app", "id": "ZICOND_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_CZERO_EQZ" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000111" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x07, attr: '7', type: 8 }\n]}" }, { "number": 254, "source": "mapping clause encdec = ZICOND_RTYPE(rs2, rs1, rd, RISCV_CZERO_NEZ) if haveZicond()\n <-> 0b0000111 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011 if haveZicond()", "left": { "type": "app", "id": "ZICOND_RTYPE", "patterns": [ { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "RISCV_CZERO_NEZ" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b0000111" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b111" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b0110011" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x33, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 7, name: 0x07, attr: '7', type: 8 }\n]}" }, { "number": 255, "source": "mapping clause encdec = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) if haveVExt()\n <-> encdec_vsetop(op) @ ma @ ta @ sew @ lmul @ rs1 @ 0b111 @ rd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VSET_TYPE", "patterns": [ { "type": "id", "id": "op" }, { "type": "id", "id": "ma" }, { "type": "id", "id": "ta" }, { "type": "id", "id": "sew" }, { "type": "id", "id": "lmul" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vsetop", "patterns": [ { "type": "id", "id": "op" } ] }, { "type": "id", "id": "ma" }, { "type": "id", "id": "ta" }, { "type": "id", "id": "sew" }, { "type": "id", "id": "lmul" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b111" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 256, "source": "mapping clause encdec = VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) if haveVExt()\n <-> 0b1100 @ ma @ ta @ sew @ lmul @ uimm @ 0b111 @ rd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VSETI_TYPE", "patterns": [ { "type": "id", "id": "ma" }, { "type": "id", "id": "ta" }, { "type": "id", "id": "sew" }, { "type": "id", "id": "lmul" }, { "type": "id", "id": "uimm" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b1100" }, { "type": "id", "id": "ma" }, { "type": "id", "id": "ta" }, { "type": "id", "id": "sew" }, { "type": "id", "id": "lmul" }, { "type": "id", "id": "uimm" }, { "type": "literal", "value": "0b111" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 },\n { bits: 5, name: 'uimm', attr: '5', type: 2 },\n { bits: 3, name: 'lmul', attr: '3', type: 2 },\n { bits: 3, name: 'sew', attr: '3', type: 2 },\n { bits: 1, name: 'ta', attr: '1', type: 2 },\n { bits: 1, name: 'ma', attr: '1', type: 2 },\n { bits: 4, name: 0xC, attr: '4', type: 8 }\n]}" }, { "number": 257, "source": "mapping clause encdec = VVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_vvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 258, "source": "mapping clause encdec = NVSTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_nvsfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "NVSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_nvsfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 259, "source": "mapping clause encdec = NVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_nvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "NVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_nvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 260, "source": "mapping clause encdec = MASKTYPEV (vs2, vs1, vd) if haveVExt()\n <-> 0b010111 @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MASKTYPEV", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'vs1', attr: '5', type: 2 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 261, "source": "mapping clause encdec = MOVETYPEV (vs1, vd) if haveVExt()\n <-> 0b010111 @ 0b1 @ 0b00000 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MOVETYPEV", "patterns": [ { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'vs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 262, "source": "mapping clause encdec = VXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_vxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vxfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 263, "source": "mapping clause encdec = NXSTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_nxsfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "NXSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_nxsfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 264, "source": "mapping clause encdec = NXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_nxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "NXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_nxfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 265, "source": "mapping clause encdec = VXSG(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_vxsgfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VXSG", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vxsgfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 266, "source": "mapping clause encdec = MASKTYPEX(vs2, rs1, vd) if haveVExt()\n <-> 0b010111 @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MASKTYPEX", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 267, "source": "mapping clause encdec = MOVETYPEX (rs1, vd) if haveVExt()\n <-> 0b010111 @ 0b1 @ 0b00000 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MOVETYPEX", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 268, "source": "mapping clause encdec = VITYPE(funct6, vm, vs2, simm, vd) if haveVExt()\n <-> encdec_vifunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VITYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vifunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 269, "source": "mapping clause encdec = NISTYPE(funct6, vm, vs2, simm, vd) if haveVExt()\n <-> encdec_nisfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "NISTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_nisfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 270, "source": "mapping clause encdec = NITYPE(funct6, vm, vs2, simm, vd) if haveVExt()\n <-> encdec_nifunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "NITYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_nifunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 271, "source": "mapping clause encdec = VISG(funct6, vm, vs2, simm, vd) if haveVExt()\n <-> encdec_visgfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VISG", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_visgfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 272, "source": "mapping clause encdec = MASKTYPEI(vs2, simm, vd) if haveVExt()\n <-> 0b010111 @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MASKTYPEI", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'simm', attr: '5', type: 2 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 273, "source": "mapping clause encdec = MOVETYPEI (vd, simm) if haveVExt()\n <-> 0b010111 @ 0b1 @ 0b00000 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MOVETYPEI", "patterns": [ { "type": "id", "id": "vd" }, { "type": "id", "id": "simm" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'simm', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 274, "source": "mapping clause encdec = VMVRTYPE(vs2, simm, vd) if haveVExt()\n <-> 0b100111 @ 0b1 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VMVRTYPE", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100111" }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 },\n { bits: 5, name: 'simm', attr: '5', type: 2 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x27, attr: '6', type: 8 }\n]}" }, { "number": 275, "source": "mapping clause encdec = MVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_mvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_mvvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 276, "source": "mapping clause encdec = MVVMATYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_mvvmafunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MVVMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_mvvmafunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 277, "source": "mapping clause encdec = WVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_wvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "WVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_wvvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 278, "source": "mapping clause encdec = WVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_wvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "WVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_wvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 279, "source": "mapping clause encdec = WMVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_wmvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "WMVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_wmvvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 280, "source": "mapping clause encdec = VEXT2TYPE(funct6, vm, vs2, vd) if haveVExt()\n <-> 0b010010 @ vm @ vs2 @ vext2_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VEXT2TYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010010" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "app", "id": "vext2_vs1", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 281, "source": "mapping clause encdec = VEXT4TYPE(funct6, vm, vs2, vd) if haveVExt()\n <-> 0b010010 @ vm @ vs2 @ vext4_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VEXT4TYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010010" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "app", "id": "vext4_vs1", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 282, "source": "mapping clause encdec = VEXT8TYPE(funct6, vm, vs2, vd) if haveVExt()\n <-> 0b010010 @ vm @ vs2 @ vext8_vs1(funct6) @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VEXT8TYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010010" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "app", "id": "vext8_vs1", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 283, "source": "mapping clause encdec = VMVXS(vs2, rd) if haveVExt()\n <-> 0b010000 @ 0b1 @ vs2 @ 0b00000 @ 0b010 @ rd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VMVXS", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010000" }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x10, attr: '6', type: 8 }\n]}" }, { "number": 284, "source": "mapping clause encdec = MVVCOMPRESS(vs2, vs1, vd) if haveVExt()\n <-> 0b010111 @ 0b1 @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MVVCOMPRESS", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 'vs1', attr: '5', type: 2 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 285, "source": "mapping clause encdec = MVXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_mvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MVXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_mvxfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 286, "source": "mapping clause encdec = MVXMATYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_mvxmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MVXMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_mvxmafunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 287, "source": "mapping clause encdec = WVXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_wvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "WVXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_wvxfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 288, "source": "mapping clause encdec = WXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_wxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "WXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_wxfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 289, "source": "mapping clause encdec = WMVXTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_wmvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "WMVXTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_wmvxfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 290, "source": "mapping clause encdec = VMVSX(rs1, vd) if haveVExt()\n <-> 0b010000 @ 0b1 @ 0b00000 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VMVSX", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010000" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b110" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x10, attr: '6', type: 8 }\n]}" }, { "number": 291, "source": "mapping clause encdec = FVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_fvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fvvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 292, "source": "mapping clause encdec = FVVMATYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_fvvmafunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FVVMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fvvmafunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 293, "source": "mapping clause encdec = FWVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_fwvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FWVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fwvvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 294, "source": "mapping clause encdec = FWVVMATYPE(funct6, vm, vs1, vs2, vd) if haveVExt()\n <-> encdec_fwvvmafunct6(funct6) @ vm @ vs1 @ vs2 @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FWVVMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fwvvmafunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 295, "source": "mapping clause encdec = FWVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_fwvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FWVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fwvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 296, "source": "mapping clause encdec = VFUNARY0(vm, vs2, vfunary0, vd) if haveVExt()\n <-> 0b010010 @ vm @ vs2 @ encdec_vfunary0_vs1(vfunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFUNARY0", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfunary0" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010010" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "app", "id": "encdec_vfunary0_vs1", "patterns": [ { "type": "id", "id": "vfunary0" } ] }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 297, "source": "mapping clause encdec = VFWUNARY0(vm, vs2, vfwunary0, vd) if haveVExt()\n <-> 0b010010 @ vm @ vs2 @ encdec_vfwunary0_vs1(vfwunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFWUNARY0", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfwunary0" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010010" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "app", "id": "encdec_vfwunary0_vs1", "patterns": [ { "type": "id", "id": "vfwunary0" } ] }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 298, "source": "mapping clause encdec = VFNUNARY0(vm, vs2, vfnunary0, vd) if haveVExt()\n <-> 0b010010 @ vm @ vs2 @ encdec_vfnunary0_vs1(vfnunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFNUNARY0", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfnunary0" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010010" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "app", "id": "encdec_vfnunary0_vs1", "patterns": [ { "type": "id", "id": "vfnunary0" } ] }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 299, "source": "mapping clause encdec = VFUNARY1(vm, vs2, vfunary1, vd) if haveVExt()\n <-> 0b010011 @ vm @ vs2 @ encdec_vfunary1_vs1(vfunary1) @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFUNARY1", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vfunary1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010011" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "app", "id": "encdec_vfunary1_vs1", "patterns": [ { "type": "id", "id": "vfunary1" } ] }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 300, "source": "mapping clause encdec = VFMVFS(vs2, rd) if haveVExt()\n <-> 0b010000 @ 0b1 @ vs2 @ 0b00000 @ 0b001 @ rd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFMVFS", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010000" }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x10, attr: '6', type: 8 }\n]}" }, { "number": 301, "source": "mapping clause encdec = FVFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_fvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FVFTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fvffunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 302, "source": "mapping clause encdec = FVFMATYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_fvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FVFMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fvfmafunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 303, "source": "mapping clause encdec = FWVFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_fwvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FWVFTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fwvffunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 304, "source": "mapping clause encdec = FWVFMATYPE(funct6, vm, rs1, vs2, vd) if haveVExt()\n <-> encdec_fwvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FWVFMATYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fwvfmafunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 305, "source": "mapping clause encdec = FWFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_fwffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FWFTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fwffunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 306, "source": "mapping clause encdec = VFMERGE(vs2, rs1, vd) if haveVExt()\n <-> 0b010111 @ 0b0 @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFMERGE", "patterns": [ { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 307, "source": "mapping clause encdec = VFMV(rs1, vd) if haveVExt()\n <-> 0b010111 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFMV", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010111" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x17, attr: '6', type: 8 }\n]}" }, { "number": 308, "source": "mapping clause encdec = VFMVSF(rs1, vd) if haveVExt()\n <-> 0b010000 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFMVSF", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010000" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 6, name: 0x10, attr: '6', type: 8 }\n]}" }, { "number": 309, "source": "mapping clause encdec = VLSEGTYPE(nf, vm, rs1, width, vd) if haveVExt()\n <-> nf @ 0b0 @ 0b00 @ vm @ 0b00000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt()", "left": { "type": "app", "id": "VLSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "vm" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b0000111" } ] } }, { "number": 310, "source": "mapping clause encdec = VLSEGFFTYPE(nf, vm, rs1, width, vd) if haveVExt()\n <-> nf @ 0b0 @ 0b00 @ vm @ 0b10000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt()", "left": { "type": "app", "id": "VLSEGFFTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "vm" }, { "type": "literal", "value": "0b10000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b0000111" } ] } }, { "number": 311, "source": "mapping clause encdec = VSSEGTYPE(nf, vm, rs1, width, vs3) if haveVExt()\n <-> nf @ 0b0 @ 0b00 @ vm @ 0b00000 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveVExt()", "left": { "type": "app", "id": "VSSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "vm" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vs3" }, { "type": "literal", "value": "0b0100111" } ] } }, { "number": 312, "source": "mapping clause encdec = VLSSEGTYPE(nf, vm, rs2, rs1, width, vd) if haveVExt()\n <-> nf @ 0b0 @ 0b10 @ vm @ rs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt()", "left": { "type": "app", "id": "VLSSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b10" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b0000111" } ] } }, { "number": 313, "source": "mapping clause encdec = VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3) if haveVExt()\n <-> nf @ 0b0 @ 0b10 @ vm @ rs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveVExt()", "left": { "type": "app", "id": "VSSSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b10" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "rs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vs3" }, { "type": "literal", "value": "0b0100111" } ] } }, { "number": 314, "source": "mapping clause encdec = VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd) if haveVExt()\n <-> nf @ 0b0 @ 0b01 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt()", "left": { "type": "app", "id": "VLUXSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b0000111" } ] } }, { "number": 315, "source": "mapping clause encdec = VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd) if haveVExt()\n <-> nf @ 0b0 @ 0b11 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt()", "left": { "type": "app", "id": "VLOXSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b0000111" } ] } }, { "number": 316, "source": "mapping clause encdec = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) if haveVExt()\n <-> nf @ 0b0 @ 0b01 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveVExt()", "left": { "type": "app", "id": "VSUXSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vs3" }, { "type": "literal", "value": "0b0100111" } ] } }, { "number": 317, "source": "mapping clause encdec = VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3) if haveVExt()\n <-> nf @ 0b0 @ 0b11 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveVExt()", "left": { "type": "app", "id": "VSOXSEGTYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vs3" }, { "type": "literal", "value": "0b0100111" } ] } }, { "number": 318, "source": "mapping clause encdec = VLRETYPE(nf, rs1, width, vd) if haveVExt()\n <-> nf @ 0b0 @ 0b00 @ 0b1 @ 0b01000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveVExt()", "left": { "type": "app", "id": "VLRETYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "width" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b01000" }, { "type": "id", "id": "rs1" }, { "type": "app", "id": "encdec_vlewidth", "patterns": [ { "type": "id", "id": "width" } ] }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b0000111" } ] } }, { "number": 319, "source": "mapping clause encdec = VSRETYPE(nf, rs1, vs3) if haveVExt()\n <-> nf @ 0b0 @ 0b00 @ 0b1 @ 0b01000 @ rs1 @ 0b000 @ vs3 @ 0b0100111 if haveVExt()", "left": { "type": "app", "id": "VSRETYPE", "patterns": [ { "type": "id", "id": "nf" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vs3" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nf" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b01000" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vs3" }, { "type": "literal", "value": "0b0100111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x27, attr: '7', type: 8 },\n { bits: 5, name: 'vs3', attr: '5', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 5, name: 0x08, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 'nf', attr: '3', type: 2 }\n]}" }, { "number": 320, "source": "mapping clause encdec = VMTYPE(rs1, vd_or_vs3, op) if haveVExt()\n <-> 0b000 @ 0b0 @ 0b00 @ 0b1 @ 0b01011 @ rs1 @ 0b000 @ vd_or_vs3 @ encdec_lsop(op) if haveVExt()", "left": { "type": "app", "id": "VMTYPE", "patterns": [ { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd_or_vs3" }, { "type": "id", "id": "op" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b01011" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd_or_vs3" }, { "type": "app", "id": "encdec_lsop", "patterns": [ { "type": "id", "id": "op" } ] } ] } }, { "number": 321, "source": "mapping clause encdec = MMTYPE(funct6, vs2, vs1, vd) if haveVExt()\n <-> encdec_mmfunct6(funct6) @ 0b1 @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "MMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_mmfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 322, "source": "mapping clause encdec = VCPOP_M(vm, vs2, rd) if haveVExt()\n <-> 0b010000 @ vm @ vs2 @ 0b10000 @ 0b010 @ rd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VCPOP_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010000" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b10000" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 0x10, attr: '5', type: 8 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 'vm', attr: '1', type: 2 },\n { bits: 6, name: 0x10, attr: '6', type: 8 }\n]}" }, { "number": 323, "source": "mapping clause encdec = VFIRST_M(vm, vs2, rd) if haveVExt()\n <-> 0b010000 @ vm @ vs2 @ 0b10001 @ 0b010 @ rd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VFIRST_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010000" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b10001" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 0x11, attr: '5', type: 8 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 'vm', attr: '1', type: 2 },\n { bits: 6, name: 0x10, attr: '6', type: 8 }\n]}" }, { "number": 324, "source": "mapping clause encdec = VMSBF_M(vm, vs2, vd) if haveVExt()\n <-> 0b010100 @ vm @ vs2 @ 0b00001 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VMSBF_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010100" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b00001" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 0x01, attr: '5', type: 8 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 'vm', attr: '1', type: 2 },\n { bits: 6, name: 0x14, attr: '6', type: 8 }\n]}" }, { "number": 325, "source": "mapping clause encdec = VMSIF_M(vm, vs2, vd) if haveVExt()\n <-> 0b010100 @ vm @ vs2 @ 0b00011 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VMSIF_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010100" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b00011" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 0x03, attr: '5', type: 8 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 'vm', attr: '1', type: 2 },\n { bits: 6, name: 0x14, attr: '6', type: 8 }\n]}" }, { "number": 326, "source": "mapping clause encdec = VMSOF_M(vm, vs2, vd) if haveVExt()\n <-> 0b010100 @ vm @ vs2 @ 0b00010 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VMSOF_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010100" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b00010" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 0x02, attr: '5', type: 8 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 'vm', attr: '1', type: 2 },\n { bits: 6, name: 0x14, attr: '6', type: 8 }\n]}" }, { "number": 327, "source": "mapping clause encdec = VIOTA_M(vm, vs2, vd) if haveVExt()\n <-> 0b010100 @ vm @ vs2 @ 0b10000 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VIOTA_M", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010100" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "literal", "value": "0b10000" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 0x10, attr: '5', type: 8 },\n { bits: 5, name: 'vs2', attr: '5', type: 2 },\n { bits: 1, name: 'vm', attr: '1', type: 2 },\n { bits: 6, name: 0x14, attr: '6', type: 8 }\n]}" }, { "number": 328, "source": "mapping clause encdec = VID_V(vm, vd) if haveVExt()\n <-> 0b010100 @ vm @ 0b00000 @ 0b10001 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VID_V", "patterns": [ { "type": "id", "id": "vm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010100" }, { "type": "id", "id": "vm" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b10001" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] }, "right_wavedrom": "{reg:[\n { bits: 7, name: 0x57, attr: '7', type: 8 },\n { bits: 5, name: 'vd', attr: '5', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 },\n { bits: 5, name: 0x11, attr: '5', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 'vm', attr: '1', type: 2 },\n { bits: 6, name: 0x14, attr: '6', type: 8 }\n]}" }, { "number": 329, "source": "mapping clause encdec = VVMTYPE(funct6, vs2, vs1, vd) if haveVExt()\n <-> encdec_vvmfunct6(funct6) @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VVMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vvmfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 330, "source": "mapping clause encdec = VVMCTYPE(funct6, vs2, vs1, vd) if haveVExt()\n <-> encdec_vvmcfunct6(funct6) @ 0b1 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VVMCTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vvmcfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 331, "source": "mapping clause encdec = VVMSTYPE(funct6, vs2, vs1, vd) if haveVExt()\n <-> encdec_vvmsfunct6(funct6) @ 0b0 @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VVMSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vvmsfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 332, "source": "mapping clause encdec = VVCMPTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_vvcmpfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VVCMPTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vvcmpfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 333, "source": "mapping clause encdec = VXMTYPE(funct6, vs2, rs1, vd) if haveVExt()\n <-> encdec_vxmfunct6(funct6) @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VXMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vxmfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 334, "source": "mapping clause encdec = VXMCTYPE(funct6, vs2, rs1, vd) if haveVExt()\n <-> encdec_vxmcfunct6(funct6) @ 0b1 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VXMCTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vxmcfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 335, "source": "mapping clause encdec = VXMSTYPE(funct6, vs2, rs1, vd) if haveVExt()\n <-> encdec_vxmsfunct6(funct6) @ 0b0 @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VXMSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vxmsfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 336, "source": "mapping clause encdec = VXCMPTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_vxcmpfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b100 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VXCMPTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vxcmpfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b100" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 337, "source": "mapping clause encdec = VIMTYPE(funct6, vs2, simm, vd) if haveVExt()\n <-> encdec_vimfunct6(funct6) @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VIMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vimfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 338, "source": "mapping clause encdec = VIMCTYPE(funct6, vs2, simm, vd) if haveVExt()\n <-> encdec_vimcfunct6(funct6) @ 0b1 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VIMCTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vimcfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 339, "source": "mapping clause encdec = VIMSTYPE(funct6, vs2, simm, vd) if haveVExt()\n <-> encdec_vimsfunct6(funct6) @ 0b0 @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VIMSTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vimsfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 340, "source": "mapping clause encdec = VICMPTYPE(funct6, vm, vs2, simm, vd) if haveVExt()\n <-> encdec_vicmpfunct6(funct6) @ vm @ vs2 @ simm @ 0b011 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "VICMPTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_vicmpfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "simm" }, { "type": "literal", "value": "0b011" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 341, "source": "mapping clause encdec = FVVMTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_fvvmfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FVVMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fvvmfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 342, "source": "mapping clause encdec = FVFMTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()\n <-> encdec_fvfmfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "FVFMTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_fvfmfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b101" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 343, "source": "mapping clause encdec = RIVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_rivvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b000 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "RIVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_rivvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b000" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 344, "source": "mapping clause encdec = RMVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_rmvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "RMVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_rmvvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b010" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 345, "source": "mapping clause encdec = RFVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()\n <-> encdec_rfvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()", "left": { "type": "app", "id": "RFVVTYPE", "patterns": [ { "type": "id", "id": "funct6" }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "id", "id": "vd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "app", "id": "encdec_rfvvfunct6", "patterns": [ { "type": "id", "id": "funct6" } ] }, { "type": "id", "id": "vm" }, { "type": "id", "id": "vs2" }, { "type": "id", "id": "vs1" }, { "type": "literal", "value": "0b001" }, { "type": "id", "id": "vd" }, { "type": "literal", "value": "0b1010111" } ] } }, { "number": 346, "source": "mapping clause encdec = ILLEGAL(s) <-> s", "left": { "type": "app", "id": "ILLEGAL", "patterns": [ { "type": "id", "id": "s" } ] }, "right": { "type": "id", "id": "s" } } ] }, "encdec_amoop": { "mapping": [ { "number": 0, "source": "AMOSWAP <-> 0b00001", "left": { "type": "id", "id": "AMOSWAP" }, "right": { "type": "literal", "value": "0b00001" } }, { "number": 1, "source": "AMOADD <-> 0b00000", "left": { "type": "id", "id": "AMOADD" }, "right": { "type": "literal", "value": "0b00000" } }, { "number": 2, "source": "AMOXOR <-> 0b00100", "left": { "type": "id", "id": "AMOXOR" }, "right": { "type": "literal", "value": "0b00100" } }, { "number": 3, "source": "AMOAND <-> 0b01100", "left": { "type": "id", "id": "AMOAND" }, "right": { "type": "literal", "value": "0b01100" } }, { "number": 4, "source": "AMOOR <-> 0b01000", "left": { "type": "id", "id": "AMOOR" }, "right": { "type": "literal", "value": "0b01000" } }, { "number": 5, "source": "AMOMIN <-> 0b10000", "left": { "type": "id", "id": "AMOMIN" }, "right": { "type": "literal", "value": "0b10000" } }, { "number": 6, "source": "AMOMAX <-> 0b10100", "left": { "type": "id", "id": "AMOMAX" }, "right": { "type": "literal", "value": "0b10100" } }, { "number": 7, "source": "AMOMINU <-> 0b11000", "left": { "type": "id", "id": "AMOMINU" }, "right": { "type": "literal", "value": "0b11000" } }, { "number": 8, "source": "AMOMAXU <-> 0b11100", "left": { "type": "id", "id": "AMOMAXU" }, "right": { "type": "literal", "value": "0b11100" } } ] }, "encdec_bop": { "mapping": [ { "number": 0, "source": "RISCV_BEQ <-> 0b000", "left": { "type": "id", "id": "RISCV_BEQ" }, "right": { "type": "literal", "value": "0b000" } }, { "number": 1, "source": "RISCV_BNE <-> 0b001", "left": { "type": "id", "id": "RISCV_BNE" }, "right": { "type": "literal", "value": "0b001" } }, { "number": 2, "source": "RISCV_BLT <-> 0b100", "left": { "type": "id", "id": "RISCV_BLT" }, "right": { "type": "literal", "value": "0b100" } }, { "number": 3, "source": "RISCV_BGE <-> 0b101", "left": { "type": "id", "id": "RISCV_BGE" }, "right": { "type": "literal", "value": "0b101" } }, { "number": 4, "source": "RISCV_BLTU <-> 0b110", "left": { "type": "id", "id": "RISCV_BLTU" }, "right": { "type": "literal", "value": "0b110" } }, { "number": 5, "source": "RISCV_BGEU <-> 0b111", "left": { "type": "id", "id": "RISCV_BGEU" }, "right": { "type": "literal", "value": "0b111" } } ] }, "encdec_compressed": { "mapping": [ { "number": 0, "source": "mapping clause encdec_compressed = C_NOP()\n <-> 0b000 @ 0b0 @ 0b00000 @ 0b00000 @ 0b01", "left": { "type": "app", "id": "C_NOP", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 }\n]}" }, { "number": 1, "source": "mapping clause encdec_compressed = C_ADDI4SPN(rd, nz96 @ nz54 @ nz3 @ nz2)\n if nz96 @ nz54 @ nz3 @ nz2 != 0b00000000\n <-> 0b000 @ nz54 : bits(2) @ nz96 : bits(4) @ nz2 : bits(1) @ nz3 : bits(1) @ rd : cregidx @ 0b00\n if nz96 @ nz54 @ nz3 @ nz2 != 0b00000000", "left": { "type": "app", "id": "C_ADDI4SPN", "patterns": [ { "type": "id", "id": "rd" }, { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nz96" }, { "type": "id", "id": "nz54" }, { "type": "id", "id": "nz3" }, { "type": "id", "id": "nz2" } ] } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000" }, { "type": "id", "id": "nz54" }, { "type": "id", "id": "nz96" }, { "type": "id", "id": "nz2" }, { "type": "id", "id": "nz3" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rd', attr: '3', type: 2 },\n { bits: 1, name: 'nz3', attr: '1', type: 2 },\n { bits: 1, name: 'nz2', attr: '1', type: 2 },\n { bits: 4, name: 'nz96', attr: '4', type: 2 },\n { bits: 2, name: 'nz54', attr: '2', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 }\n]}" }, { "number": 2, "source": "mapping clause encdec_compressed = C_LW(ui6 @ ui53 @ ui2, rs1, rd)\n <-> 0b010 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00", "left": { "type": "app", "id": "C_LW", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui6" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "ui2" } ] }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "ui2" }, { "type": "id", "id": "ui6" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rd', attr: '3', type: 2 },\n { bits: 1, name: 'ui6', attr: '1', type: 2 },\n { bits: 1, name: 'ui2', attr: '1', type: 2 },\n { bits: 3, name: 'rs1', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 }\n]}" }, { "number": 3, "source": "mapping clause encdec_compressed = C_LD(ui76 @ ui53, rs1, rd)\n if sizeof(xlen) == 64\n <-> 0b011 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_LD", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui76" }, { "type": "id", "id": "ui53" } ] }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "ui76" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rd', attr: '3', type: 2 },\n { bits: 2, name: 'ui76', attr: '2', type: 2 },\n { bits: 3, name: 'rs1', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 }\n]}" }, { "number": 4, "source": "mapping clause encdec_compressed = C_SW(ui6 @ ui53 @ ui2, rs1, rs2)\n <-> 0b110 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00", "left": { "type": "app", "id": "C_SW", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui6" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "ui2" } ] }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b110" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "ui2" }, { "type": "id", "id": "ui6" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 1, name: 'ui6', attr: '1', type: 2 },\n { bits: 1, name: 'ui2', attr: '1', type: 2 },\n { bits: 3, name: 'rs1', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 }\n]}" }, { "number": 5, "source": "mapping clause encdec_compressed = C_SD(ui76 @ ui53, rs1, rs2)\n if sizeof(xlen) == 64\n <-> 0b111 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_SD", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui76" }, { "type": "id", "id": "ui53" } ] }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b111" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "ui76" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 2, name: 'ui76', attr: '2', type: 2 },\n { bits: 3, name: 'rs1', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 }\n]}" }, { "number": 6, "source": "mapping clause encdec_compressed = C_ADDI(nzi5 @ nzi40, rsd)\n if nzi5 @ nzi40 != 0b000000 & rsd != zreg\n <-> 0b000 @ nzi5 : bits(1) @ rsd : regidx @ nzi40 : bits(5) @ 0b01\n if nzi5 @ nzi40 != 0b000000 & rsd != zreg", "left": { "type": "app", "id": "C_ADDI", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nzi5" }, { "type": "id", "id": "nzi40" } ] }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000" }, { "type": "id", "id": "nzi5" }, { "type": "id", "id": "rsd" }, { "type": "id", "id": "nzi40" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'nzi40', attr: '5', type: 2 },\n { bits: 5, name: 'rsd', attr: '5', type: 2 },\n { bits: 1, name: 'nzi5', attr: '1', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 }\n]}" }, { "number": 7, "source": "mapping clause encdec_compressed = C_JAL(i11 @ i10 @ i98 @ i7 @ i6 @ i5 @ i4 @ i31)\n if sizeof(xlen) == 32\n <-> 0b001 @ i11 : bits(1) @ i4 : bits(1) @ i98 : bits(2) @ i10 : bits(1) @ i6 : bits(1) @ i7 : bits(1) @ i31 : bits(3) @ i5 : bits(1) @ 0b01\n if sizeof(xlen) == 32", "left": { "type": "app", "id": "C_JAL", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "i11" }, { "type": "id", "id": "i10" }, { "type": "id", "id": "i98" }, { "type": "id", "id": "i7" }, { "type": "id", "id": "i6" }, { "type": "id", "id": "i5" }, { "type": "id", "id": "i4" }, { "type": "id", "id": "i31" } ] } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b001" }, { "type": "id", "id": "i11" }, { "type": "id", "id": "i4" }, { "type": "id", "id": "i98" }, { "type": "id", "id": "i10" }, { "type": "id", "id": "i6" }, { "type": "id", "id": "i7" }, { "type": "id", "id": "i31" }, { "type": "id", "id": "i5" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 1, name: 'i5', attr: '1', type: 2 },\n { bits: 3, name: 'i31', attr: '3', type: 2 },\n { bits: 1, name: 'i7', attr: '1', type: 2 },\n { bits: 1, name: 'i6', attr: '1', type: 2 },\n { bits: 1, name: 'i10', attr: '1', type: 2 },\n { bits: 2, name: 'i98', attr: '2', type: 2 },\n { bits: 1, name: 'i4', attr: '1', type: 2 },\n { bits: 1, name: 'i11', attr: '1', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 }\n]}" }, { "number": 8, "source": "mapping clause encdec_compressed = C_ADDIW(imm5 @ imm40, rsd)\n if rsd != zreg & sizeof(xlen) == 64\n <-> 0b001 @ imm5 : bits(1) @ rsd : regidx @ imm40 : bits(5) @ 0b01\n if rsd != zreg & sizeof(xlen) == 64", "left": { "type": "app", "id": "C_ADDIW", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm5" }, { "type": "id", "id": "imm40" } ] }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b001" }, { "type": "id", "id": "imm5" }, { "type": "id", "id": "rsd" }, { "type": "id", "id": "imm40" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'imm40', attr: '5', type: 2 },\n { bits: 5, name: 'rsd', attr: '5', type: 2 },\n { bits: 1, name: 'imm5', attr: '1', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 }\n]}" }, { "number": 9, "source": "mapping clause encdec_compressed = C_LI(imm5 @ imm40, rd)\n if rd != zreg\n <-> 0b010 @ imm5 : bits(1) @ rd : regidx @ imm40 : bits(5) @ 0b01\n if rd != zreg", "left": { "type": "app", "id": "C_LI", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm5" }, { "type": "id", "id": "imm40" } ] }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010" }, { "type": "id", "id": "imm5" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "imm40" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'imm40', attr: '5', type: 2 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 1, name: 'imm5', attr: '1', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 }\n]}" }, { "number": 10, "source": "mapping clause encdec_compressed = C_ADDI16SP(nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4)\n if nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 != 0b000000\n <-> 0b011 @ nzi9 : bits(1) @ /* x2 */ 0b00010 @ nzi4 : bits(1) @ nzi6 : bits(1) @ nzi87 : bits(2) @ nzi5 : bits(1) @ 0b01\n if nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 != 0b000000", "left": { "type": "app", "id": "C_ADDI16SP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nzi9" }, { "type": "id", "id": "nzi87" }, { "type": "id", "id": "nzi6" }, { "type": "id", "id": "nzi5" }, { "type": "id", "id": "nzi4" } ] } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011" }, { "type": "id", "id": "nzi9" }, { "type": "literal", "value": "0b00010" }, { "type": "id", "id": "nzi4" }, { "type": "id", "id": "nzi6" }, { "type": "id", "id": "nzi87" }, { "type": "id", "id": "nzi5" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 1, name: 'nzi5', attr: '1', type: 2 },\n { bits: 2, name: 'nzi87', attr: '2', type: 2 },\n { bits: 1, name: 'nzi6', attr: '1', type: 2 },\n { bits: 1, name: 'nzi4', attr: '1', type: 2 },\n { bits: 5, name: 0x02, attr: '5', type: 8 },\n { bits: 1, name: 'nzi9', attr: '1', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 }\n]}" }, { "number": 11, "source": "mapping clause encdec_compressed = C_LUI(imm17 @ imm1612, rd)\n if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000\n <-> 0b011 @ imm17 : bits(1) @ rd : regidx @ imm1612 : bits(5) @ 0b01\n if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000", "left": { "type": "app", "id": "C_LUI", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm17" }, { "type": "id", "id": "imm1612" } ] }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011" }, { "type": "id", "id": "imm17" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "imm1612" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'imm1612', attr: '5', type: 2 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 1, name: 'imm17', attr: '1', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 }\n]}" }, { "number": 12, "source": "mapping clause encdec_compressed = C_SRLI(nzui5 @ nzui40, rsd)\n if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0)\n <-> 0b100 @ nzui5 : bits(1) @ 0b00 @ rsd : cregidx @ nzui40 : bits(5) @ 0b01\n if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0)", "left": { "type": "app", "id": "C_SRLI", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nzui5" }, { "type": "id", "id": "nzui40" } ] }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "id", "id": "nzui5" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "rsd" }, { "type": "id", "id": "nzui40" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'nzui40', attr: '5', type: 2 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 1, name: 'nzui5', attr: '1', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 13, "source": "mapping clause encdec_compressed = C_SRAI(nzui5 @ nzui40, rsd)\n if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0)\n <-> 0b100 @ nzui5 : bits(1) @ 0b01 @ rsd : cregidx @ nzui40 : bits(5) @ 0b01\n if nzui5 @ nzui40 != 0b000000 & (sizeof(xlen) == 64 | nzui5 == 0b0)", "left": { "type": "app", "id": "C_SRAI", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nzui5" }, { "type": "id", "id": "nzui40" } ] }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "id", "id": "nzui5" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "rsd" }, { "type": "id", "id": "nzui40" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'nzui40', attr: '5', type: 2 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 1, name: 'nzui5', attr: '1', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 14, "source": "mapping clause encdec_compressed = C_ANDI(i5 @ i40, rsd)\n <-> 0b100 @ i5 : bits(1) @ 0b10 @ rsd : cregidx @ i40 : bits(5) @ 0b01", "left": { "type": "app", "id": "C_ANDI", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "i5" }, { "type": "id", "id": "i40" } ] }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "id", "id": "i5" }, { "type": "literal", "value": "0b10" }, { "type": "id", "id": "rsd" }, { "type": "id", "id": "i40" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'i40', attr: '5', type: 2 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 1, name: 'i5', attr: '1', type: 2 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 15, "source": "mapping clause encdec_compressed = C_SUB(rsd, rs2)\n <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b00 @ rs2 : cregidx @ 0b01", "left": { "type": "app", "id": "C_SUB", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x3, attr: '2', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 16, "source": "mapping clause encdec_compressed = C_XOR(rsd, rs2)\n <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b01 @ rs2 : cregidx @ 0b01", "left": { "type": "app", "id": "C_XOR", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x3, attr: '2', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 17, "source": "mapping clause encdec_compressed = C_OR(rsd, rs2)\n <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b10 @ rs2 : cregidx @ 0b01", "left": { "type": "app", "id": "C_OR", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b10" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x3, attr: '2', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 18, "source": "mapping clause encdec_compressed = C_AND(rsd, rs2)\n <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregidx @ 0b11 @ rs2 : cregidx @ 0b01", "left": { "type": "app", "id": "C_AND", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 2, name: 0x3, attr: '2', type: 8 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x3, attr: '2', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 19, "source": "mapping clause encdec_compressed = C_SUBW(rsd, rs2)\n if sizeof(xlen) == 64\n <-> 0b100 @ 0b1 @ 0b11 @ rsd : cregidx @ 0b00 @ rs2 : cregidx @ 0b01\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_SUBW", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x3, attr: '2', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 20, "source": "mapping clause encdec_compressed = C_ADDW(rsd, rs2)\n if sizeof(xlen) == 64\n <-> 0b100 @ 0b1 @ 0b11 @ rsd : cregidx @ 0b01 @ rs2 : cregidx @ 0b01\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_ADDW", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b11" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x3, attr: '2', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 21, "source": "mapping clause encdec_compressed = C_J(i11 @ i10 @ i98 @ i7 @ i6 @ i5 @ i4 @ i31)\n <-> 0b101 @ i11 : bits(1) @ i4 : bits(1) @ i98 : bits(2) @ i10 : bits(1) @ i6 : bits(1) @ i7 : bits(1) @ i31 : bits(3) @ i5 : bits(1) @ 0b01", "left": { "type": "app", "id": "C_J", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "i11" }, { "type": "id", "id": "i10" }, { "type": "id", "id": "i98" }, { "type": "id", "id": "i7" }, { "type": "id", "id": "i6" }, { "type": "id", "id": "i5" }, { "type": "id", "id": "i4" }, { "type": "id", "id": "i31" } ] } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b101" }, { "type": "id", "id": "i11" }, { "type": "id", "id": "i4" }, { "type": "id", "id": "i98" }, { "type": "id", "id": "i10" }, { "type": "id", "id": "i6" }, { "type": "id", "id": "i7" }, { "type": "id", "id": "i31" }, { "type": "id", "id": "i5" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 1, name: 'i5', attr: '1', type: 2 },\n { bits: 3, name: 'i31', attr: '3', type: 2 },\n { bits: 1, name: 'i7', attr: '1', type: 2 },\n { bits: 1, name: 'i6', attr: '1', type: 2 },\n { bits: 1, name: 'i10', attr: '1', type: 2 },\n { bits: 2, name: 'i98', attr: '2', type: 2 },\n { bits: 1, name: 'i4', attr: '1', type: 2 },\n { bits: 1, name: 'i11', attr: '1', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 }\n]}" }, { "number": 22, "source": "mapping clause encdec_compressed = C_BEQZ(i8 @ i76 @ i5 @ i43 @ i21, rs)\n <-> 0b110 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregidx @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01", "left": { "type": "app", "id": "C_BEQZ", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "i8" }, { "type": "id", "id": "i76" }, { "type": "id", "id": "i5" }, { "type": "id", "id": "i43" }, { "type": "id", "id": "i21" } ] }, { "type": "id", "id": "rs" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b110" }, { "type": "id", "id": "i8" }, { "type": "id", "id": "i43" }, { "type": "id", "id": "rs" }, { "type": "id", "id": "i76" }, { "type": "id", "id": "i21" }, { "type": "id", "id": "i5" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 1, name: 'i5', attr: '1', type: 2 },\n { bits: 2, name: 'i21', attr: '2', type: 2 },\n { bits: 2, name: 'i76', attr: '2', type: 2 },\n { bits: 3, name: 'rs', attr: '3', type: 2 },\n { bits: 2, name: 'i43', attr: '2', type: 2 },\n { bits: 1, name: 'i8', attr: '1', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 }\n]}" }, { "number": 23, "source": "mapping clause encdec_compressed = C_BNEZ(i8 @ i76 @ i5 @ i43 @ i21, rs)\n <-> 0b111 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregidx @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01", "left": { "type": "app", "id": "C_BNEZ", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "i8" }, { "type": "id", "id": "i76" }, { "type": "id", "id": "i5" }, { "type": "id", "id": "i43" }, { "type": "id", "id": "i21" } ] }, { "type": "id", "id": "rs" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b111" }, { "type": "id", "id": "i8" }, { "type": "id", "id": "i43" }, { "type": "id", "id": "rs" }, { "type": "id", "id": "i76" }, { "type": "id", "id": "i21" }, { "type": "id", "id": "i5" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 1, name: 'i5', attr: '1', type: 2 },\n { bits: 2, name: 'i21', attr: '2', type: 2 },\n { bits: 2, name: 'i76', attr: '2', type: 2 },\n { bits: 3, name: 'rs', attr: '3', type: 2 },\n { bits: 2, name: 'i43', attr: '2', type: 2 },\n { bits: 1, name: 'i8', attr: '1', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 }\n]}" }, { "number": 24, "source": "mapping clause encdec_compressed = C_SLLI(nzui5 @ nzui40, rsd)\n if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == 0b0)\n <-> 0b000 @ nzui5 : bits(1) @ rsd : regidx @ nzui40 : bits(5) @ 0b10\n if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == 0b0)", "left": { "type": "app", "id": "C_SLLI", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nzui5" }, { "type": "id", "id": "nzui40" } ] }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000" }, { "type": "id", "id": "nzui5" }, { "type": "id", "id": "rsd" }, { "type": "id", "id": "nzui40" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'nzui40', attr: '5', type: 2 },\n { bits: 5, name: 'rsd', attr: '5', type: 2 },\n { bits: 1, name: 'nzui5', attr: '1', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 }\n]}" }, { "number": 25, "source": "mapping clause encdec_compressed = C_LWSP(ui76 @ ui5 @ ui42, rd)\n if rd != zreg\n <-> 0b010 @ ui5 : bits(1) @ rd : regidx @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10\n if rd != zreg", "left": { "type": "app", "id": "C_LWSP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui76" }, { "type": "id", "id": "ui5" }, { "type": "id", "id": "ui42" } ] }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010" }, { "type": "id", "id": "ui5" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "ui42" }, { "type": "id", "id": "ui76" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 2, name: 'ui76', attr: '2', type: 2 },\n { bits: 3, name: 'ui42', attr: '3', type: 2 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 1, name: 'ui5', attr: '1', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 }\n]}" }, { "number": 26, "source": "mapping clause encdec_compressed = C_LDSP(ui86 @ ui5 @ ui43, rd)\n if rd != zreg & sizeof(xlen) == 64\n <-> 0b011 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10\n if rd != zreg & sizeof(xlen) == 64", "left": { "type": "app", "id": "C_LDSP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui86" }, { "type": "id", "id": "ui5" }, { "type": "id", "id": "ui43" } ] }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011" }, { "type": "id", "id": "ui5" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "ui43" }, { "type": "id", "id": "ui86" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 3, name: 'ui86', attr: '3', type: 2 },\n { bits: 2, name: 'ui43', attr: '2', type: 2 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 1, name: 'ui5', attr: '1', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 }\n]}" }, { "number": 27, "source": "mapping clause encdec_compressed = C_SWSP(ui76 @ ui52, rs2)\n <-> 0b110 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10", "left": { "type": "app", "id": "C_SWSP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui76" }, { "type": "id", "id": "ui52" } ] }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b110" }, { "type": "id", "id": "ui52" }, { "type": "id", "id": "ui76" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 2, name: 'ui76', attr: '2', type: 2 },\n { bits: 4, name: 'ui52', attr: '4', type: 2 },\n { bits: 3, name: 0x6, attr: '3', type: 8 }\n]}" }, { "number": 28, "source": "mapping clause encdec_compressed = C_SDSP(ui86 @ ui53, rs2)\n if sizeof(xlen) == 64\n <-> 0b111 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10\n if sizeof(xlen) == 64", "left": { "type": "app", "id": "C_SDSP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui86" }, { "type": "id", "id": "ui53" } ] }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b111" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "ui86" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 3, name: 'ui86', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 }\n]}" }, { "number": 29, "source": "mapping clause encdec_compressed = C_JR(rs1)\n if rs1 != zreg\n <-> 0b100 @ 0b0 @ rs1 : regidx @ 0b00000 @ 0b10\n if rs1 != zreg", "left": { "type": "app", "id": "C_JR", "patterns": [ { "type": "id", "id": "rs1" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 30, "source": "mapping clause encdec_compressed = C_JALR(rs1)\n if rs1 != zreg\n <-> 0b100 @ 0b1 @ rs1 : regidx @ 0b00000 @ 0b10\n if rs1 != zreg", "left": { "type": "app", "id": "C_JALR", "patterns": [ { "type": "id", "id": "rs1" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "rs1" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 'rs1', attr: '5', type: 2 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 31, "source": "mapping clause encdec_compressed = C_MV(rd, rs2)\n if rd != zreg & rs2 != zreg\n <-> 0b100 @ 0b0 @ rd : regidx @ rs2 : regidx @ 0b10\n if rd != zreg & rs2 != zreg", "left": { "type": "app", "id": "C_MV", "patterns": [ { "type": "id", "id": "rd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 32, "source": "mapping clause encdec_compressed = C_EBREAK()\n <-> 0b100 @ 0b1 @ 0b00000 @ 0b00000 @ 0b10", "left": { "type": "app", "id": "C_EBREAK", "patterns": [ { "type": "literal", "value": "()" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 33, "source": "mapping clause encdec_compressed = C_ADD(rsd, rs2)\n if rsd != zreg & rs2 != zreg\n <-> 0b100 @ 0b1 @ rsd : regidx @ rs2 : regidx @ 0b10\n if rsd != zreg & rs2 != zreg", "left": { "type": "app", "id": "C_ADD", "patterns": [ { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b1" }, { "type": "id", "id": "rsd" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 'rsd', attr: '5', type: 2 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 34, "source": "mapping clause encdec_compressed = C_NOP_HINT(im5 @ im40)\n if im5 @ im40 != 0b000000\n <-> 0b000 @ im5 : bits(1) @ 0b00000 @ im40 : bits(5) @ 0b01\n if im5 @ im40 != 0b000000", "left": { "type": "app", "id": "C_NOP_HINT", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "im5" }, { "type": "id", "id": "im40" } ] } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000" }, { "type": "id", "id": "im5" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "im40" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'im40', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 'im5', attr: '1', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 }\n]}" }, { "number": 35, "source": "mapping clause encdec_compressed = C_ADDI_HINT(rsd)\n if rsd != zreg\n <-> 0b000 @ 0b0 @ rsd : regidx @ 0b00000 @ 0b01\n if rsd != zreg", "left": { "type": "app", "id": "C_ADDI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000" }, { "type": "literal", "value": "0b0" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 5, name: 'rsd', attr: '5', type: 2 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x0, attr: '3', type: 8 }\n]}" }, { "number": 36, "source": "mapping clause encdec_compressed = C_LI_HINT(imm5 @ imm40)\n <-> 0b010 @ imm5 : bits(1) @ 0b00000 @ imm40 : bits(5) @ 0b01", "left": { "type": "app", "id": "C_LI_HINT", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm5" }, { "type": "id", "id": "imm40" } ] } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b010" }, { "type": "id", "id": "imm5" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "imm40" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'imm40', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 'imm5', attr: '1', type: 2 },\n { bits: 3, name: 0x2, attr: '3', type: 8 }\n]}" }, { "number": 37, "source": "mapping clause encdec_compressed = C_LUI_HINT(imm17 @ imm1612)\n if imm17 @ imm1612 != 0b000000\n <-> 0b011 @ imm17 : bits(1) @ 0b00000 @ imm1612 : bits(5) @ 0b01\n if imm17 @ imm1612 != 0b000000", "left": { "type": "app", "id": "C_LUI_HINT", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "imm17" }, { "type": "id", "id": "imm1612" } ] } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011" }, { "type": "id", "id": "imm17" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "imm1612" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 'imm1612', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 'imm17', attr: '1', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 }\n]}" }, { "number": 38, "source": "mapping clause encdec_compressed = C_MV_HINT(rs2)\n if rs2 != zreg\n <-> 0b100 @ 0b0 @ 0b00000 @ rs2 : regidx @ 0b10\n if rs2 != zreg", "left": { "type": "app", "id": "C_MV_HINT", "patterns": [ { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 39, "source": "mapping clause encdec_compressed = C_ADD_HINT(rs2)\n if rs2 != zreg\n <-> 0b100 @ 0b1 @ 0b00000 @ rs2 : regidx @ 0b10\n if rs2 != zreg", "left": { "type": "app", "id": "C_ADD_HINT", "patterns": [ { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b1" }, { "type": "literal", "value": "0b00000" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 1, name: 0x1, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 40, "source": "mapping clause encdec_compressed = C_SLLI_HINT(nzui5 @ nzui40, rsd)\n if (nzui5 @ nzui40 == 0b000000 | rsd == zreg) & (sizeof(xlen) == 64 | nzui5 == 0b0)\n <-> 0b000 @ nzui5 : bits(1) @ rsd : regidx @ nzui40 : bits(5) @ 0b10\n if (nzui5 @ nzui40 == 0b000000 | rsd == zreg) & (sizeof(xlen) == 64 | nzui5 == 0b0)", "left": { "type": "app", "id": "C_SLLI_HINT", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "nzui5" }, { "type": "id", "id": "nzui40" } ] }, { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b000" }, { "type": "id", "id": "nzui5" }, { "type": "id", "id": "rsd" }, { "type": "id", "id": "nzui40" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'nzui40', attr: '5', type: 2 },\n { bits: 5, name: 'rsd', attr: '5', type: 2 },\n { bits: 1, name: 'nzui5', attr: '1', type: 2 },\n { bits: 3, name: 0x0, attr: '3', type: 8 }\n]}" }, { "number": 41, "source": "mapping clause encdec_compressed = C_SRLI_HINT(rsd)\n <-> 0b100 @ 0b0 @ 0b00 @ rsd : cregidx @ 0b00000 @ 0b01", "left": { "type": "app", "id": "C_SRLI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b00" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 42, "source": "mapping clause encdec_compressed = C_SRAI_HINT(rsd)\n <-> 0b100 @ 0b0 @ 0b01 @ rsd : cregidx @ 0b00000 @ 0b01", "left": { "type": "app", "id": "C_SRAI_HINT", "patterns": [ { "type": "id", "id": "rsd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b100" }, { "type": "literal", "value": "0b0" }, { "type": "literal", "value": "0b01" }, { "type": "id", "id": "rsd" }, { "type": "literal", "value": "0b00000" }, { "type": "literal", "value": "0b01" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 5, name: 0x00, attr: '5', type: 8 },\n { bits: 3, name: 'rsd', attr: '3', type: 2 },\n { bits: 2, name: 0x1, attr: '2', type: 8 },\n { bits: 1, name: 0x0, attr: '1', type: 8 },\n { bits: 3, name: 0x4, attr: '3', type: 8 }\n]}" }, { "number": 43, "source": "mapping clause encdec_compressed = C_FLWSP(ui76 @ ui5 @ ui42, rd)\n if sizeof(xlen) == 32 & haveRVC() & haveFExt()\n <-> 0b011 @ ui5 : bits(1) @ rd : regidx @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10\n if sizeof(xlen) == 32 & haveRVC() & haveFExt()", "left": { "type": "app", "id": "C_FLWSP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui76" }, { "type": "id", "id": "ui5" }, { "type": "id", "id": "ui42" } ] }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011" }, { "type": "id", "id": "ui5" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "ui42" }, { "type": "id", "id": "ui76" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 2, name: 'ui76', attr: '2', type: 2 },\n { bits: 3, name: 'ui42', attr: '3', type: 2 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 1, name: 'ui5', attr: '1', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 }\n]}" }, { "number": 44, "source": "mapping clause encdec_compressed = C_FSWSP(ui76 @ ui52, rs2)\n if sizeof(xlen) == 32 & haveRVC() & haveFExt()\n <-> 0b111 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regidx @ 0b10\n if sizeof(xlen) == 32 & haveRVC() & haveFExt()", "left": { "type": "app", "id": "C_FSWSP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui76" }, { "type": "id", "id": "ui52" } ] }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b111" }, { "type": "id", "id": "ui52" }, { "type": "id", "id": "ui76" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 2, name: 'ui76', attr: '2', type: 2 },\n { bits: 4, name: 'ui52', attr: '4', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 }\n]}" }, { "number": 45, "source": "mapping clause encdec_compressed = C_FLW(ui6 @ ui53 @ ui2, rs1, rd)\n if sizeof(xlen) == 32 & haveRVC() & haveFExt()\n <-> 0b011 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregidx @ 0b00\n if sizeof(xlen) == 32 & haveRVC() & haveFExt()", "left": { "type": "app", "id": "C_FLW", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui6" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "ui2" } ] }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b011" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "ui2" }, { "type": "id", "id": "ui6" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rd', attr: '3', type: 2 },\n { bits: 1, name: 'ui6', attr: '1', type: 2 },\n { bits: 1, name: 'ui2', attr: '1', type: 2 },\n { bits: 3, name: 'rs1', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x3, attr: '3', type: 8 }\n]}" }, { "number": 46, "source": "mapping clause encdec_compressed = C_FSW(ui6 @ ui53 @ ui2, rs1, rs2)\n if sizeof(xlen) == 32 & haveRVC() & haveFExt()\n <-> 0b111 @ ui53 : bits(3) @ rs1 : cregidx @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregidx @ 0b00\n if sizeof(xlen) == 32 & haveRVC() & haveFExt()", "left": { "type": "app", "id": "C_FSW", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui6" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "ui2" } ] }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b111" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "ui2" }, { "type": "id", "id": "ui6" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 1, name: 'ui6', attr: '1', type: 2 },\n { bits: 1, name: 'ui2', attr: '1', type: 2 },\n { bits: 3, name: 'rs1', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x7, attr: '3', type: 8 }\n]}" }, { "number": 47, "source": "mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()\n <-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()", "left": { "type": "app", "id": "C_FLDSP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui86" }, { "type": "id", "id": "ui5" }, { "type": "id", "id": "ui43" } ] }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b001" }, { "type": "id", "id": "ui5" }, { "type": "id", "id": "rd" }, { "type": "id", "id": "ui43" }, { "type": "id", "id": "ui86" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 3, name: 'ui86', attr: '3', type: 2 },\n { bits: 2, name: 'ui43', attr: '2', type: 2 },\n { bits: 5, name: 'rd', attr: '5', type: 2 },\n { bits: 1, name: 'ui5', attr: '1', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 }\n]}" }, { "number": 48, "source": "mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()\n <-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()", "left": { "type": "app", "id": "C_FSDSP", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui86" }, { "type": "id", "id": "ui53" } ] }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b101" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "ui86" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b10" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x2, attr: '2', type: 8 },\n { bits: 5, name: 'rs2', attr: '5', type: 2 },\n { bits: 3, name: 'ui86', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 }\n]}" }, { "number": 49, "source": "mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()\n <-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()", "left": { "type": "app", "id": "C_FLD", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui76" }, { "type": "id", "id": "ui53" } ] }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rd" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b001" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "ui76" }, { "type": "id", "id": "rd" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rd', attr: '3', type: 2 },\n { bits: 2, name: 'ui76', attr: '2', type: 2 },\n { bits: 3, name: 'rs1', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x1, attr: '3', type: 8 }\n]}" }, { "number": 50, "source": "mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2)\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()\n <-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00\n if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & haveRVC() & haveDExt()", "left": { "type": "app", "id": "C_FSD", "patterns": [ { "type": "vector_concat", "patterns": [ { "type": "id", "id": "ui76" }, { "type": "id", "id": "ui53" } ] }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "rs2" } ] }, "right": { "type": "vector_concat", "patterns": [ { "type": "literal", "value": "0b101" }, { "type": "id", "id": "ui53" }, { "type": "id", "id": "rs1" }, { "type": "id", "id": "ui76" }, { "type": "id", "id": "rs2" }, { "type": "literal", "value": "0b00" } ] }, "right_wavedrom": "{reg:[\n { bits: 2, name: 0x0, attr: '2', type: 8 },\n { bits: 3, name: 'rs2', attr: '3', type: 2 },\n { bits: 2, name: 'ui76', attr: '2', type: 2 },\n { bits: 3, name: 'rs1', attr: '3', type: 2 },\n { bits: 3, name: 'ui53', attr: '3', type: 2 },\n { bits: 3, name: 0x5, attr: '3', type: 8 }\n]}" }, { "number": 51, "source": "mapping clause encdec_compressed = C_ILLEGAL(s) <-> s", "left": { "type": "app", "id": "C_ILLEGAL", "patterns": [ { "type": "id", "id": "s" } ] }, "right": { "type": "id", "id": "s" } } ] }, "encdec_csrop": { "mapping": [ { "number": 0, "source": "CSRRW <-> 0b01", "left": { "type": "id", "id": "CSRRW" }, "right": { "type": "literal", "value": "0b01" } }, { "number": 1, "source": "CSRRS <-> 0b10", "left": { "type": "id", "id": "CSRRS" }, "right": { "type": "literal", "value": "0b10" } }, { "number": 2, "source": "CSRRC <-> 0b11", "left": { "type": "id", "id": "CSRRC" }, "right": { "type": "literal", "value": "0b11" } } ] }, "encdec_fvffunct6": { "mapping": [ { "number": 0, "source": "VF_VADD <-> 0b000000", "left": { "type": "id", "id": "VF_VADD" }, "right": { "type": "literal", "value": "0b000000" } }, { "number": 1, "source": "VF_VSUB <-> 0b000010", "left": { "type": "id", "id": "VF_VSUB" }, "right": { "type": "literal", "value": "0b000010" } }, { "number": 2, "source": "VF_VMIN <-> 0b000100", "left": { "type": "id", "id": "VF_VMIN" }, "right": { "type": "literal", "value": "0b000100" } }, { "number": 3, "source": "VF_VMAX <-> 0b000110", "left": { "type": "id", "id": "VF_VMAX" }, "right": { "type": "literal", "value": "0b000110" } }, { "number": 4, "source": "VF_VSGNJ <-> 0b001000", "left": { "type": "id", "id": "VF_VSGNJ" }, "right": { "type": "literal", "value": "0b001000" } }, { "number": 5, "source": "VF_VSGNJN <-> 0b001001", "left": { "type": "id", "id": "VF_VSGNJN" }, "right": { "type": "literal", "value": "0b001001" } }, { "number": 6, "source": "VF_VSGNJX <-> 0b001010", "left": { "type": "id", "id": "VF_VSGNJX" }, "right": { "type": "literal", "value": "0b001010" } }, { "number": 7, "source": "VF_VSLIDE1UP <-> 0b001110", "left": { "type": "id", "id": "VF_VSLIDE1UP" }, "right": { "type": "literal", "value": "0b001110" } }, { "number": 8, "source": "VF_VSLIDE1DOWN <-> 0b001111", "left": { "type": "id", "id": "VF_VSLIDE1DOWN" }, "right": { "type": "literal", "value": "0b001111" } }, { "number": 9, "source": "VF_VDIV <-> 0b100000", "left": { "type": "id", "id": "VF_VDIV" }, "right": { "type": "literal", "value": "0b100000" } }, { "number": 10, "source": "VF_VRDIV <-> 0b100001", "left": { "type": "id", "id": "VF_VRDIV" }, "right": { "type": "literal", "value": "0b100001" } }, { "number": 11, "source": "VF_VMUL <-> 0b100100", "left": { "type": "id", "id": "VF_VMUL" }, "right": { "type": "literal", "value": "0b100100" } }, { "number": 12, "source": "VF_VRSUB <-> 0b100111", "left": { "type": "id", "id": "VF_VRSUB" }, "right": { "type": "literal", "value": "0b100111" } } ] }, "encdec_fvfmafunct6": { "mapping": [ { "number": 0, "source": "VF_VMADD <-> 0b101000", "left": { "type": "id", "id": "VF_VMADD" }, "right": { "type": "literal", "value": "0b101000" } }, { "number": 1, "source": "VF_VNMADD <-> 0b101001", "left": { "type": "id", "id": "VF_VNMADD" }, "right": { "type": "literal", "value": "0b101001" } }, { "number": 2, "source": "VF_VMSUB <-> 0b101010", "left": { "type": "id", "id": "VF_VMSUB" }, "right": { "type": "literal", "value": "0b101010" } }, { "number": 3, "source": "VF_VNMSUB <-> 0b101011", "left": { "type": "id", "id": "VF_VNMSUB" }, "right": { "type": "literal", "value": "0b101011" } }, { "number": 4, "source": "VF_VMACC <-> 0b101100", "left": { "type": "id", "id": "VF_VMACC" }, "right": { "type": "literal", "value": "0b101100" } }, { "number": 5, "source": "VF_VNMACC <-> 0b101101", "left": { "type": "id", "id": "VF_VNMACC" }, "right": { "type": "literal", "value": "0b101101" } }, { "number": 6, "source": "VF_VMSAC <-> 0b101110", "left": { "type": "id", "id": "VF_VMSAC" }, "right": { "type": "literal", "value": "0b101110" } }, { "number": 7, "source": "VF_VNMSAC <-> 0b101111", "left": { "type": "id", "id": "VF_VNMSAC" }, "right": { "type": "literal", "value": "0b101111" } } ] }, "encdec_fvfmfunct6": { "mapping": [ { "number": 0, "source": "VFM_VMFEQ <-> 0b011000", "left": { "type": "id", "id": "VFM_VMFEQ" }, "right": { "type": "literal", "value": "0b011000" } }, { "number": 1, "source": "VFM_VMFLE <-> 0b011001", "left": { "type": "id", "id": "VFM_VMFLE" }, "right": { "type": "literal", "value": "0b011001" } }, { "number": 2, "source": "VFM_VMFLT <-> 0b011011", "left": { "type": "id", "id": "VFM_VMFLT" }, "right": { "type": "literal", "value": "0b011011" } }, { "number": 3, "source": "VFM_VMFNE <-> 0b011100", "left": { "type": "id", "id": "VFM_VMFNE" }, "right": { "type": "literal", "value": "0b011100" } }, { "number": 4, "source": "VFM_VMFGT <-> 0b011101", "left": { "type": "id", "id": "VFM_VMFGT" }, "right": { "type": "literal", "value": "0b011101" } }, { "number": 5, "source": "VFM_VMFGE <-> 0b011111", "left": { "type": "id", "id": "VFM_VMFGE" }, "right": { "type": "literal", "value": "0b011111" } } ] }, "encdec_fvvfunct6": { "mapping": [ { "number": 0, "source": "FVV_VADD <-> 0b000000", "left": { "type": "id", "id": "FVV_VADD" }, "right": { "type": "literal", "value": "0b000000" } }, { "number": 1, "source": "FVV_VSUB <-> 0b000010", "left": { "type": "id", "id": "FVV_VSUB" }, "right": { "type": "literal", "value": "0b000010" } }, { "number": 2, "source": "FVV_VMIN <-> 0b000100", "left": { "type": "id", "id": "FVV_VMIN" }, "right": { "type": "literal", "value": "0b000100" } }, { "number": 3, "source": "FVV_VMAX <-> 0b000110", "left": { "type": "id", "id": "FVV_VMAX" }, "right": { "type": "literal", "value": "0b000110" } }, { "number": 4, "source": "FVV_VSGNJ <-> 0b001000", "left": { "type": "id", "id": "FVV_VSGNJ" }, "right": { "type": "literal", "value": "0b001000" } }, { "number": 5, "source": "FVV_VSGNJN <-> 0b001001", "left": { "type": "id", "id": "FVV_VSGNJN" }, "right": { "type": "literal", "value": "0b001001" } }, { "number": 6, "source": "FVV_VSGNJX <-> 0b001010", "left": { "type": "id", "id": "FVV_VSGNJX" }, "right": { "type": "literal", "value": "0b001010" } }, { "number": 7, "source": "FVV_VDIV <-> 0b100000", "left": { "type": "id", "id": "FVV_VDIV" }, "right": { "type": "literal", "value": "0b100000" } }, { "number": 8, "source": "FVV_VMUL <-> 0b100100", "left": { "type": "id", "id": "FVV_VMUL" }, "right": { "type": "literal", "value": "0b100100" } } ] }, "encdec_fvvmafunct6": { "mapping": [ { "number": 0, "source": "FVV_VMADD <-> 0b101000", "left": { "type": "id", "id": "FVV_VMADD" }, "right": { "type": "literal", "value": "0b101000" } }, { "number": 1, "source": "FVV_VNMADD <-> 0b101001", "left": { "type": "id", "id": "FVV_VNMADD" }, "right": { "type": "literal", "value": "0b101001" } }, { "number": 2, "source": "FVV_VMSUB <-> 0b101010", "left": { "type": "id", "id": "FVV_VMSUB" }, "right": { "type": "literal", "value": "0b101010" } }, { "number": 3, "source": "FVV_VNMSUB <-> 0b101011", "left": { "type": "id", "id": "FVV_VNMSUB" }, "right": { "type": "literal", "value": "0b101011" } }, { "number": 4, "source": "FVV_VMACC <-> 0b101100", "left": { "type": "id", "id": "FVV_VMACC" }, "right": { "type": "literal", "value": "0b101100" } }, { "number": 5, "source": "FVV_VNMACC <-> 0b101101", "left": { "type": "id", "id": "FVV_VNMACC" }, "right": { "type": "literal", "value": "0b101101" } }, { "number": 6, "source": "FVV_VMSAC <-> 0b101110", "left": { "type": "id", "id": "FVV_VMSAC" }, "right": { "type": "literal", "value": "0b101110" } }, { "number": 7, "source": "FVV_VNMSAC <-> 0b101111", "left": { "type": "id", "id": "FVV_VNMSAC" }, "right": { "type": "literal", "value": "0b101111" } } ] }, "encdec_fvvmfunct6": { "mapping": [ { "number": 0, "source": "FVVM_VMFEQ <-> 0b011000", "left": { "type": "id", "id": "FVVM_VMFEQ" }, "right": { "type": "literal", "value": "0b011000" } }, { "number": 1, "source": "FVVM_VMFLE <-> 0b011001", "left": { "type": "id", "id": "FVVM_VMFLE" }, "right": { "type": "literal", "value": "0b011001" } }, { "number": 2, "source": "FVVM_VMFLT <-> 0b011011", "left": { "type": "id", "id": "FVVM_VMFLT" }, "right": { "type": "literal", "value": "0b011011" } }, { "number": 3, "source": "FVVM_VMFNE <-> 0b011100", "left": { "type": "id", "id": "FVVM_VMFNE" }, "right": { "type": "literal", "value": "0b011100" } } ] }, "encdec_fwffunct6": { "mapping": [ { "number": 0, "source": "FWF_VADD <-> 0b110100", "left": { "type": "id", "id": "FWF_VADD" }, "right": { "type": "literal", "value": "0b110100" } }, { "number": 1, "source": "FWF_VSUB <-> 0b110110", "left": { "type": "id", "id": "FWF_VSUB" }, "right": { "type": "literal", "value": "0b110110" } } ] }, "encdec_fwvffunct6": { "mapping": [ { "number": 0, "source": "FWVF_VADD <-> 0b110000", "left": { "type": "id", "id": "FWVF_VADD" }, "right": { "type": "literal", "value": "0b110000" } }, { "number": 1, "source": "FWVF_VSUB <-> 0b110010", "left": { "type": "id", "id": "FWVF_VSUB" }, "right": { "type": "literal", "value": "0b110010" } }, { "number": 2, "source": "FWVF_VMUL <-> 0b111000", "left": { "type": "id", "id": "FWVF_VMUL" }, "right": { "type": "literal", "value": "0b111000" } } ] }, "encdec_fwvfmafunct6": { "mapping": [ { "number": 0, "source": "FWVF_VMACC <-> 0b111100", "left": { "type": "id", "id": "FWVF_VMACC" }, "right": { "type": "literal", "value": "0b111100" } }, { "number": 1, "source": "FWVF_VNMACC <-> 0b111101", "left": { "type": "id", "id": "FWVF_VNMACC" }, "right": { "type": "literal", "value": "0b111101" } }, { "number": 2, "source": "FWVF_VMSAC <-> 0b111110", "left": { "type": "id", "id": "FWVF_VMSAC" }, "right": { "type": "literal", "value": "0b111110" } }, { "number": 3, "source": "FWVF_VNMSAC <-> 0b111111", "left": { "type": "id", "id": "FWVF_VNMSAC" }, "right": { "type": "literal", "value": "0b111111" } } ] }, "encdec_fwvfunct6": { "mapping": [ { "number": 0, "source": "FWV_VADD <-> 0b110100", "left": { "type": "id", "id": "FWV_VADD" }, "right": { "type": "literal", "value": "0b110100" } }, { "number": 1, "source": "FWV_VSUB <-> 0b110110", "left": { "type": "id", "id": "FWV_VSUB" }, "right": { "type": "literal", "value": "0b110110" } } ] }, "encdec_fwvvfunct6": { "mapping": [ { "number": 0, "source": "FWVV_VADD <-> 0b110000", "left": { "type": "id", "id": "FWVV_VADD" }, "right": { "type": "literal", "value": "0b110000" } }, { "number": 1, "source": "FWVV_VSUB <-> 0b110010", "left": { "type": "id", "id": "FWVV_VSUB" }, "right": { "type": "literal", "value": "0b110010" } }, { "number": 2, "source": "FWVV_VMUL <-> 0b111000", "left": { "type": "id", "id": "FWVV_VMUL" }, "right": { "type": "literal", "value": "0b111000" } } ] }, "encdec_fwvvmafunct6": { "mapping": [ { "number": 0, "source": "FWVV_VMACC <-> 0b111100", "left": { "type": "id", "id": "FWVV_VMACC" }, "right": { "type": "literal", "value": "0b111100" } }, { "number": 1, "source": "FWVV_VNMACC <-> 0b111101", "left": { "type": "id", "id": "FWVV_VNMACC" }, "right": { "type": "literal", "value": "0b111101" } }, { "number": 2, "source": "FWVV_VMSAC <-> 0b111110", "left": { "type": "id", "id": "FWVV_VMSAC" }, "right": { "type": "literal", "value": "0b111110" } }, { "number": 3, "source": "FWVV_VNMSAC <-> 0b111111", "left": { "type": "id", "id": "FWVV_VNMSAC" }, "right": { "type": "literal", "value": "0b111111" } } ] }, "encdec_iop": { "mapping": [ { "number": 0, "source": "RISCV_ADDI <-> 0b000", "left": { "type": "id", "id": "RISCV_ADDI" }, "right": { "type": "literal", "value": "0b000" } }, { "number": 1, "source": "RISCV_SLTI <-> 0b010", "left": { "type": "id", "id": "RISCV_SLTI" }, "right": { "type": "literal", "value": "0b010" } }, { "number": 2, "source": "RISCV_SLTIU <-> 0b011", "left": { "type": "id", "id": "RISCV_SLTIU" }, "right": { "type": "literal", "value": "0b011" } }, { "number": 3, "source": "RISCV_ANDI <-> 0b111", "left": { "type": "id", "id": "RISCV_ANDI" }, "right": { "type": "literal", "value": "0b111" } }, { "number": 4, "source": "RISCV_ORI <-> 0b110", "left": { "type": "id", "id": "RISCV_ORI" }, "right": { "type": "literal", "value": "0b110" } }, { "number": 5, "source": "RISCV_XORI <-> 0b100", "left": { "type": "id", "id": "RISCV_XORI" }, "right": { "type": "literal", "value": "0b100" } } ] }, "encdec_lsop": { "mapping": [ { "number": 0, "source": "VLM <-> 0b0000111", "left": { "type": "id", "id": "VLM" }, "right": { "type": "literal", "value": "0b0000111" } }, { "number": 1, "source": "VSM <-> 0b0100111", "left": { "type": "id", "id": "VSM" }, "right": { "type": "literal", "value": "0b0100111" } } ] }, "encdec_mmfunct6": { "mapping": [ { "number": 0, "source": "MM_VMAND <-> 0b011001", "left": { "type": "id", "id": "MM_VMAND" }, "right": { "type": "literal", "value": "0b011001" } }, { "number": 1, "source": "MM_VMNAND <-> 0b011101", "left": { "type": "id", "id": "MM_VMNAND" }, "right": { "type": "literal", "value": "0b011101" } }, { "number": 2, "source": "MM_VMANDNOT <-> 0b011000", "left": { "type": "id", "id": "MM_VMANDNOT" }, "right": { "type": "literal", "value": "0b011000" } }, { "number": 3, "source": "MM_VMXOR <-> 0b011011", "left": { "type": "id", "id": "MM_VMXOR" }, "right": { "type": "literal", "value": "0b011011" } }, { "number": 4, "source": "MM_VMOR <-> 0b011010", "left": { "type": "id", "id": "MM_VMOR" }, "right": { "type": "literal", "value": "0b011010" } }, { "number": 5, "source": "MM_VMNOR <-> 0b011110", "left": { "type": "id", "id": "MM_VMNOR" }, "right": { "type": "literal", "value": "0b011110" } }, { "number": 6, "source": "MM_VMORNOT <-> 0b011100", "left": { "type": "id", "id": "MM_VMORNOT" }, "right": { "type": "literal", "value": "0b011100" } }, { "number": 7, "source": "MM_VMXNOR <-> 0b011111", "left": { "type": "id", "id": "MM_VMXNOR" }, "right": { "type": "literal", "value": "0b011111" } } ] }, "encdec_mul_op": { "mapping": [ { "number": 0, "source": "(false, true, true) <-> 0b000", "left": { "type": "tuple", "patterns": [ { "type": "literal", "value": "false" }, { "type": "literal", "value": "true" }, { "type": "literal", "value": "true" } ] }, "right": { "type": "literal", "value": "0b000" } }, { "number": 1, "source": "(true, true, true) <-> 0b001", "left": { "type": "tuple", "patterns": [ { "type": "literal", "value": "true" }, { "type": "literal", "value": "true" }, { "type": "literal", "value": "true" } ] }, "right": { "type": "literal", "value": "0b001" } }, { "number": 2, "source": "(true, true, false) <-> 0b010", "left": { "type": "tuple", "patterns": [ { "type": "literal", "value": "true" }, { "type": "literal", "value": "true" }, { "type": "literal", "value": "false" } ] }, "right": { "type": "literal", "value": "0b010" } }, { "number": 3, "source": "(true, false, false) <-> 0b011", "left": { "type": "tuple", "patterns": [ { "type": "literal", "value": "true" }, { "type": "literal", "value": "false" }, { "type": "literal", "value": "false" } ] }, "right": { "type": "literal", "value": "0b011" } } ] }, "encdec_mvvfunct6": { "mapping": [ { "number": 0, "source": "MVV_VAADDU <-> 0b001000", "left": { "type": "id", "id": "MVV_VAADDU" }, "right": { "type": "literal", "value": "0b001000" } }, { "number": 1, "source": "MVV_VAADD <-> 0b001001", "left": { "type": "id", "id": "MVV_VAADD" }, "right": { "type": "literal", "value": "0b001001" } }, { "number": 2, "source": "MVV_VASUBU <-> 0b001010", "left": { "type": "id", "id": "MVV_VASUBU" }, "right": { "type": "literal", "value": "0b001010" } }, { "number": 3, "source": "MVV_VASUB <-> 0b001011", "left": { "type": "id", "id": "MVV_VASUB" }, "right": { "type": "literal", "value": "0b001011" } }, { "number": 4, "source": "MVV_VMUL <-> 0b100101", "left": { "type": "id", "id": "MVV_VMUL" }, "right": { "type": "literal", "value": "0b100101" } }, { "number": 5, "source": "MVV_VMULH <-> 0b100111", "left": { "type": "id", "id": "MVV_VMULH" }, "right": { "type": "literal", "value": "0b100111" } }, { "number": 6, "source": "MVV_VMULHU <-> 0b100100", "left": { "type": "id", "id": "MVV_VMULHU" }, "right": { "type": "literal", "value": "0b100100" } }, { "number": 7, "source": "MVV_VMULHSU <-> 0b100110", "left": { "type": "id", "id": "MVV_VMULHSU" }, "right": { "type": "literal", "value": "0b100110" } }, { "number": 8, "source": "MVV_VDIVU <-> 0b100000", "left": { "type": "id", "id": "MVV_VDIVU" }, "right": { "type": "literal", "value": "0b100000" } }, { "number": 9, "source": "MVV_VDIV <-> 0b100001", "left": { "type": "id", "id": "MVV_VDIV" }, "right": { "type": "literal", "value": "0b100001" } }, { "number": 10, "source": "MVV_VREMU <-> 0b100010", "left": { "type": "id", "id": "MVV_VREMU" }, "right": { "type": "literal", "value": "0b100010" } }, { "number": 11, "source": "MVV_VREM <-> 0b100011", "left": { "type": "id", "id": "MVV_VREM" }, "right": { "type": "literal", "value": "0b100011" } } ] }, "encdec_mvvmafunct6": { "mapping": [ { "number": 0, "source": "MVV_VMACC <-> 0b101101", "left": { "type": "id", "id": "MVV_VMACC" }, "right": { "type": "literal", "value": "0b101101" } }, { "number": 1, "source": "MVV_VNMSAC <-> 0b101111", "left": { "type": "id", "id": "MVV_VNMSAC" }, "right": { "type": "literal", "value": "0b101111" } }, { "number": 2, "source": "MVV_VMADD <-> 0b101001", "left": { "type": "id", "id": "MVV_VMADD" }, "right": { "type": "literal", "value": "0b101001" } }, { "number": 3, "source": "MVV_VNMSUB <-> 0b101011", "left": { "type": "id", "id": "MVV_VNMSUB" }, "right": { "type": "literal", "value": "0b101011" } } ] }, "encdec_mvxfunct6": { "mapping": [ { "number": 0, "source": "MVX_VAADDU <-> 0b001000", "left": { "type": "id", "id": "MVX_VAADDU" }, "right": { "type": "literal", "value": "0b001000" } }, { "number": 1, "source": "MVX_VAADD <-> 0b001001", "left": { "type": "id", "id": "MVX_VAADD" }, "right": { "type": "literal", "value": "0b001001" } }, { "number": 2, "source": "MVX_VASUBU <-> 0b001010", "left": { "type": "id", "id": "MVX_VASUBU" }, "right": { "type": "literal", "value": "0b001010" } }, { "number": 3, "source": "MVX_VASUB <-> 0b001011", "left": { "type": "id", "id": "MVX_VASUB" }, "right": { "type": "literal", "value": "0b001011" } }, { "number": 4, "source": "MVX_VSLIDE1UP <-> 0b001110", "left": { "type": "id", "id": "MVX_VSLIDE1UP" }, "right": { "type": "literal", "value": "0b001110" } }, { "number": 5, "source": "MVX_VSLIDE1DOWN <-> 0b001111", "left": { "type": "id", "id": "MVX_VSLIDE1DOWN" }, "right": { "type": "literal", "value": "0b001111" } }, { "number": 6, "source": "MVX_VMUL <-> 0b100101", "left": { "type": "id", "id": "MVX_VMUL" }, "right": { "type": "literal", "value": "0b100101" } }, { "number": 7, "source": "MVX_VMULH <-> 0b100111", "left": { "type": "id", "id": "MVX_VMULH" }, "right": { "type": "literal", "value": "0b100111" } }, { "number": 8, "source": "MVX_VMULHU <-> 0b100100", "left": { "type": "id", "id": "MVX_VMULHU" }, "right": { "type": "literal", "value": "0b100100" } }, { "number": 9, "source": "MVX_VMULHSU <-> 0b100110", "left": { "type": "id", "id": "MVX_VMULHSU" }, "right": { "type": "literal", "value": "0b100110" } }, { "number": 10, "source": "MVX_VDIVU <-> 0b100000", "left": { "type": "id", "id": "MVX_VDIVU" }, "right": { "type": "literal", "value": "0b100000" } }, { "number": 11, "source": "MVX_VDIV <-> 0b100001", "left": { "type": "id", "id": "MVX_VDIV" }, "right": { "type": "literal", "value": "0b100001" } }, { "number": 12, "source": "MVX_VREMU <-> 0b100010", "left": { "type": "id", "id": "MVX_VREMU" }, "right": { "type": "literal", "value": "0b100010" } }, { "number": 13, "source": "MVX_VREM <-> 0b100011", "left": { "type": "id", "id": "MVX_VREM" }, "right": { "type": "literal", "value": "0b100011" } } ] }, "encdec_mvxmafunct6": { "mapping": [ { "number": 0, "source": "MVX_VMACC <-> 0b101101", "left": { "type": "id", "id": "MVX_VMACC" }, "right": { "type": "literal", "value": "0b101101" } }, { "number": 1, "source": "MVX_VNMSAC <-> 0b101111", "left": { "type": "id", "id": "MVX_VNMSAC" }, "right": { "type": "literal", "value": "0b101111" } }, { "number": 2, "source": "MVX_VMADD <-> 0b101001", "left": { "type": "id", "id": "MVX_VMADD" }, "right": { "type": "literal", "value": "0b101001" } }, { "number": 3, "source": "MVX_VNMSUB <-> 0b101011", "left": { "type": "id", "id": "MVX_VNMSUB" }, "right": { "type": "literal", "value": "0b101011" } } ] }, "encdec_nifunct6": { "mapping": [ { "number": 0, "source": "NI_VNCLIPU <-> 0b101110", "left": { "type": "id", "id": "NI_VNCLIPU" }, "right": { "type": "literal", "value": "0b101110" } }, { "number": 1, "source": "NI_VNCLIP <-> 0b101111", "left": { "type": "id", "id": "NI_VNCLIP" }, "right": { "type": "literal", "value": "0b101111" } } ] }, "encdec_nisfunct6": { "mapping": [ { "number": 0, "source": "NIS_VNSRL <-> 0b101100", "left": { "type": "id", "id": "NIS_VNSRL" }, "right": { "type": "literal", "value": "0b101100" } }, { "number": 1, "source": "NIS_VNSRA <-> 0b101101", "left": { "type": "id", "id": "NIS_VNSRA" }, "right": { "type": "literal", "value": "0b101101" } } ] }, "encdec_nvfunct6": { "mapping": [ { "number": 0, "source": "NV_VNCLIPU <-> 0b101110", "left": { "type": "id", "id": "NV_VNCLIPU" }, "right": { "type": "literal", "value": "0b101110" } }, { "number": 1, "source": "NV_VNCLIP <-> 0b101111", "left": { "type": "id", "id": "NV_VNCLIP" }, "right": { "type": "literal", "value": "0b101111" } } ] }, "encdec_nvsfunct6": { "mapping": [ { "number": 0, "source": "NVS_VNSRL <-> 0b101100", "left": { "type": "id", "id": "NVS_VNSRL" }, "right": { "type": "literal", "value": "0b101100" } }, { "number": 1, "source": "NVS_VNSRA <-> 0b101101", "left": { "type": "id", "id": "NVS_VNSRA" }, "right": { "type": "literal", "value": "0b101101" } } ] }, "encdec_nxfunct6": { "mapping": [ { "number": 0, "source": "NX_VNCLIPU <-> 0b101110", "left": { "type": "id", "id": "NX_VNCLIPU" }, "right": { "type": "literal", "value": "0b101110" } }, { "number": 1, "source": "NX_VNCLIP <-> 0b101111", "left": { "type": "id", "id": "NX_VNCLIP" }, "right": { "type": "literal", "value": "0b101111" } } ] }, "encdec_nxsfunct6": { "mapping": [ { "number": 0, "source": "NXS_VNSRL <-> 0b101100", "left": { "type": "id", "id": "NXS_VNSRL" }, "right": { "type": "literal", "value": "0b101100" } }, { "number": 1, "source": "NXS_VNSRA <-> 0b101101", "left": { "type": "id", "id": "NXS_VNSRA" }, "right": { "type": "literal", "value": "0b101101" } } ] }, "encdec_rfvvfunct6": { "mapping": [ { "number": 0, "source": "FVV_VFREDOSUM <-> 0b000011", "left": { "type": "id", "id": "FVV_VFREDOSUM" }, "right": { "type": "literal", "value": "0b000011" } }, { "number": 1, "source": "FVV_VFREDUSUM <-> 0b000001", "left": { "type": "id", "id": "FVV_VFREDUSUM" }, "right": { "type": "literal", "value": "0b000001" } }, { "number": 2, "source": "FVV_VFREDMAX <-> 0b000111", "left": { "type": "id", "id": "FVV_VFREDMAX" }, "right": { "type": "literal", "value": "0b000111" } }, { "number": 3, "source": "FVV_VFREDMIN <-> 0b000101", "left": { "type": "id", "id": "FVV_VFREDMIN" }, "right": { "type": "literal", "value": "0b000101" } }, { "number": 4, "source": "FVV_VFWREDOSUM <-> 0b110011", "left": { "type": "id", "id": "FVV_VFWREDOSUM" }, "right": { "type": "literal", "value": "0b110011" } }, { "number": 5, "source": "FVV_VFWREDUSUM <-> 0b110001", "left": { "type": "id", "id": "FVV_VFWREDUSUM" }, "right": { "type": "literal", "value": "0b110001" } } ] }, "encdec_rivvfunct6": { "mapping": [ { "number": 0, "source": "IVV_VWREDSUMU <-> 0b110000", "left": { "type": "id", "id": "IVV_VWREDSUMU" }, "right": { "type": "literal", "value": "0b110000" } }, { "number": 1, "source": "IVV_VWREDSUM <-> 0b110001", "left": { "type": "id", "id": "IVV_VWREDSUM" }, "right": { "type": "literal", "value": "0b110001" } } ] }, "encdec_rmvvfunct6": { "mapping": [ { "number": 0, "source": "MVV_VREDSUM <-> 0b000000", "left": { "type": "id", "id": "MVV_VREDSUM" }, "right": { "type": "literal", "value": "0b000000" } }, { "number": 1, "source": "MVV_VREDAND <-> 0b000001", "left": { "type": "id", "id": "MVV_VREDAND" }, "right": { "type": "literal", "value": "0b000001" } }, { "number": 2, "source": "MVV_VREDOR <-> 0b000010", "left": { "type": "id", "id": "MVV_VREDOR" }, "right": { "type": "literal", "value": "0b000010" } }, { "number": 3, "source": "MVV_VREDXOR <-> 0b000011", "left": { "type": "id", "id": "MVV_VREDXOR" }, "right": { "type": "literal", "value": "0b000011" } }, { "number": 4, "source": "MVV_VREDMINU <-> 0b000100", "left": { "type": "id", "id": "MVV_VREDMINU" }, "right": { "type": "literal", "value": "0b000100" } }, { "number": 5, "source": "MVV_VREDMIN <-> 0b000101", "left": { "type": "id", "id": "MVV_VREDMIN" }, "right": { "type": "literal", "value": "0b000101" } }, { "number": 6, "source": "MVV_VREDMAXU <-> 0b000110", "left": { "type": "id", "id": "MVV_VREDMAXU" }, "right": { "type": "literal", "value": "0b000110" } }, { "number": 7, "source": "MVV_VREDMAX <-> 0b000111", "left": { "type": "id", "id": "MVV_VREDMAX" }, "right": { "type": "literal", "value": "0b000111" } } ] }, "encdec_rounding_mode": { "mapping": [ { "number": 0, "source": "RM_RNE <-> 0b000", "left": { "type": "id", "id": "RM_RNE" }, "right": { "type": "literal", "value": "0b000" } }, { "number": 1, "source": "RM_RTZ <-> 0b001", "left": { "type": "id", "id": "RM_RTZ" }, "right": { "type": "literal", "value": "0b001" } }, { "number": 2, "source": "RM_RDN <-> 0b010", "left": { "type": "id", "id": "RM_RDN" }, "right": { "type": "literal", "value": "0b010" } }, { "number": 3, "source": "RM_RUP <-> 0b011", "left": { "type": "id", "id": "RM_RUP" }, "right": { "type": "literal", "value": "0b011" } }, { "number": 4, "source": "RM_RMM <-> 0b100", "left": { "type": "id", "id": "RM_RMM" }, "right": { "type": "literal", "value": "0b100" } }, { "number": 5, "source": "RM_DYN <-> 0b111", "left": { "type": "id", "id": "RM_DYN" }, "right": { "type": "literal", "value": "0b111" } } ] }, "encdec_sop": { "mapping": [ { "number": 0, "source": "RISCV_SLLI <-> 0b001", "left": { "type": "id", "id": "RISCV_SLLI" }, "right": { "type": "literal", "value": "0b001" } }, { "number": 1, "source": "RISCV_SRLI <-> 0b101", "left": { "type": "id", "id": "RISCV_SRLI" }, "right": { "type": "literal", "value": "0b101" } }, { "number": 2, "source": "RISCV_SRAI <-> 0b101", "left": { "type": "id", "id": "RISCV_SRAI" }, "right": { "type": "literal", "value": "0b101" } } ] }, "encdec_uop": { "mapping": [ { "number": 0, "source": "RISCV_LUI <-> 0b0110111", "left": { "type": "id", "id": "RISCV_LUI" }, "right": { "type": "literal", "value": "0b0110111" } }, { "number": 1, "source": "RISCV_AUIPC <-> 0b0010111", "left": { "type": "id", "id": "RISCV_AUIPC" }, "right": { "type": "literal", "value": "0b0010111" } } ] }, "encdec_vfnunary0_vs1": { "mapping": [ { "number": 0, "source": "FNV_CVT_XU_F <-> 0b10000", "left": { "type": "id", "id": "FNV_CVT_XU_F" }, "right": { "type": "literal", "value": "0b10000" } }, { "number": 1, "source": "FNV_CVT_X_F <-> 0b10001", "left": { "type": "id", "id": "FNV_CVT_X_F" }, "right": { "type": "literal", "value": "0b10001" } }, { "number": 2, "source": "FNV_CVT_F_XU <-> 0b10010", "left": { "type": "id", "id": "FNV_CVT_F_XU" }, "right": { "type": "literal", "value": "0b10010" } }, { "number": 3, "source": "FNV_CVT_F_X <-> 0b10011", "left": { "type": "id", "id": "FNV_CVT_F_X" }, "right": { "type": "literal", "value": "0b10011" } }, { "number": 4, "source": "FNV_CVT_F_F <-> 0b10100", "left": { "type": "id", "id": "FNV_CVT_F_F" }, "right": { "type": "literal", "value": "0b10100" } }, { "number": 5, "source": "FNV_CVT_ROD_F_F <-> 0b10101", "left": { "type": "id", "id": "FNV_CVT_ROD_F_F" }, "right": { "type": "literal", "value": "0b10101" } }, { "number": 6, "source": "FNV_CVT_RTZ_XU_F <-> 0b10110", "left": { "type": "id", "id": "FNV_CVT_RTZ_XU_F" }, "right": { "type": "literal", "value": "0b10110" } }, { "number": 7, "source": "FNV_CVT_RTZ_X_F <-> 0b10111", "left": { "type": "id", "id": "FNV_CVT_RTZ_X_F" }, "right": { "type": "literal", "value": "0b10111" } } ] }, "encdec_vfunary0_vs1": { "mapping": [ { "number": 0, "source": "FV_CVT_XU_F <-> 0b00000", "left": { "type": "id", "id": "FV_CVT_XU_F" }, "right": { "type": "literal", "value": "0b00000" } }, { "number": 1, "source": "FV_CVT_X_F <-> 0b00001", "left": { "type": "id", "id": "FV_CVT_X_F" }, "right": { "type": "literal", "value": "0b00001" } }, { "number": 2, "source": "FV_CVT_F_XU <-> 0b00010", "left": { "type": "id", "id": "FV_CVT_F_XU" }, "right": { "type": "literal", "value": "0b00010" } }, { "number": 3, "source": "FV_CVT_F_X <-> 0b00011", "left": { "type": "id", "id": "FV_CVT_F_X" }, "right": { "type": "literal", "value": "0b00011" } }, { "number": 4, "source": "FV_CVT_RTZ_XU_F <-> 0b00110", "left": { "type": "id", "id": "FV_CVT_RTZ_XU_F" }, "right": { "type": "literal", "value": "0b00110" } }, { "number": 5, "source": "FV_CVT_RTZ_X_F <-> 0b00111", "left": { "type": "id", "id": "FV_CVT_RTZ_X_F" }, "right": { "type": "literal", "value": "0b00111" } } ] }, "encdec_vfunary1_vs1": { "mapping": [ { "number": 0, "source": "FVV_VSQRT <-> 0b00000", "left": { "type": "id", "id": "FVV_VSQRT" }, "right": { "type": "literal", "value": "0b00000" } }, { "number": 1, "source": "FVV_VRSQRT7 <-> 0b00100", "left": { "type": "id", "id": "FVV_VRSQRT7" }, "right": { "type": "literal", "value": "0b00100" } }, { "number": 2, "source": "FVV_VREC7 <-> 0b00101", "left": { "type": "id", "id": "FVV_VREC7" }, "right": { "type": "literal", "value": "0b00101" } }, { "number": 3, "source": "FVV_VCLASS <-> 0b10000", "left": { "type": "id", "id": "FVV_VCLASS" }, "right": { "type": "literal", "value": "0b10000" } } ] }, "encdec_vfwunary0_vs1": { "mapping": [ { "number": 0, "source": "FWV_CVT_XU_F <-> 0b01000", "left": { "type": "id", "id": "FWV_CVT_XU_F" }, "right": { "type": "literal", "value": "0b01000" } }, { "number": 1, "source": "FWV_CVT_X_F <-> 0b01001", "left": { "type": "id", "id": "FWV_CVT_X_F" }, "right": { "type": "literal", "value": "0b01001" } }, { "number": 2, "source": "FWV_CVT_F_XU <-> 0b01010", "left": { "type": "id", "id": "FWV_CVT_F_XU" }, "right": { "type": "literal", "value": "0b01010" } }, { "number": 3, "source": "FWV_CVT_F_X <-> 0b01011", "left": { "type": "id", "id": "FWV_CVT_F_X" }, "right": { "type": "literal", "value": "0b01011" } }, { "number": 4, "source": "FWV_CVT_F_F <-> 0b01100", "left": { "type": "id", "id": "FWV_CVT_F_F" }, "right": { "type": "literal", "value": "0b01100" } }, { "number": 5, "source": "FWV_CVT_RTZ_XU_F <-> 0b01110", "left": { "type": "id", "id": "FWV_CVT_RTZ_XU_F" }, "right": { "type": "literal", "value": "0b01110" } }, { "number": 6, "source": "FWV_CVT_RTZ_X_F <-> 0b01111", "left": { "type": "id", "id": "FWV_CVT_RTZ_X_F" }, "right": { "type": "literal", "value": "0b01111" } } ] }, "encdec_vicmpfunct6": { "mapping": [ { "number": 0, "source": "VICMP_VMSEQ <-> 0b011000", "left": { "type": "id", "id": "VICMP_VMSEQ" }, "right": { "type": "literal", "value": "0b011000" } }, { "number": 1, "source": "VICMP_VMSNE <-> 0b011001", "left": { "type": "id", "id": "VICMP_VMSNE" }, "right": { "type": "literal", "value": "0b011001" } }, { "number": 2, "source": "VICMP_VMSLEU <-> 0b011100", "left": { "type": "id", "id": "VICMP_VMSLEU" }, "right": { "type": "literal", "value": "0b011100" } }, { "number": 3, "source": "VICMP_VMSLE <-> 0b011101", "left": { "type": "id", "id": "VICMP_VMSLE" }, "right": { "type": "literal", "value": "0b011101" } }, { "number": 4, "source": "VICMP_VMSGTU <-> 0b011110", "left": { "type": "id", "id": "VICMP_VMSGTU" }, "right": { "type": "literal", "value": "0b011110" } }, { "number": 5, "source": "VICMP_VMSGT <-> 0b011111", "left": { "type": "id", "id": "VICMP_VMSGT" }, "right": { "type": "literal", "value": "0b011111" } } ] }, "encdec_vifunct6": { "mapping": [ { "number": 0, "source": "VI_VADD <-> 0b000000", "left": { "type": "id", "id": "VI_VADD" }, "right": { "type": "literal", "value": "0b000000" } }, { "number": 1, "source": "VI_VRSUB <-> 0b000011", "left": { "type": "id", "id": "VI_VRSUB" }, "right": { "type": "literal", "value": "0b000011" } }, { "number": 2, "source": "VI_VAND <-> 0b001001", "left": { "type": "id", "id": "VI_VAND" }, "right": { "type": "literal", "value": "0b001001" } }, { "number": 3, "source": "VI_VOR <-> 0b001010", "left": { "type": "id", "id": "VI_VOR" }, "right": { "type": "literal", "value": "0b001010" } }, { "number": 4, "source": "VI_VXOR <-> 0b001011", "left": { "type": "id", "id": "VI_VXOR" }, "right": { "type": "literal", "value": "0b001011" } }, { "number": 5, "source": "VI_VSADDU <-> 0b100000", "left": { "type": "id", "id": "VI_VSADDU" }, "right": { "type": "literal", "value": "0b100000" } }, { "number": 6, "source": "VI_VSADD <-> 0b100001", "left": { "type": "id", "id": "VI_VSADD" }, "right": { "type": "literal", "value": "0b100001" } }, { "number": 7, "source": "VI_VSLL <-> 0b100101", "left": { "type": "id", "id": "VI_VSLL" }, "right": { "type": "literal", "value": "0b100101" } }, { "number": 8, "source": "VI_VSRL <-> 0b101000", "left": { "type": "id", "id": "VI_VSRL" }, "right": { "type": "literal", "value": "0b101000" } }, { "number": 9, "source": "VI_VSRA <-> 0b101001", "left": { "type": "id", "id": "VI_VSRA" }, "right": { "type": "literal", "value": "0b101001" } }, { "number": 10, "source": "VI_VSSRL <-> 0b101010", "left": { "type": "id", "id": "VI_VSSRL" }, "right": { "type": "literal", "value": "0b101010" } }, { "number": 11, "source": "VI_VSSRA <-> 0b101011", "left": { "type": "id", "id": "VI_VSSRA" }, "right": { "type": "literal", "value": "0b101011" } } ] }, "encdec_vimcfunct6": { "mapping": [ { "number": 0, "source": "VIMC_VMADC <-> 0b010001", "left": { "type": "id", "id": "VIMC_VMADC" }, "right": { "type": "literal", "value": "0b010001" } } ] }, "encdec_vimfunct6": { "mapping": [ { "number": 0, "source": "VIM_VMADC <-> 0b010001", "left": { "type": "id", "id": "VIM_VMADC" }, "right": { "type": "literal", "value": "0b010001" } } ] }, "encdec_vimsfunct6": { "mapping": [ { "number": 0, "source": "VIMS_VADC <-> 0b010000", "left": { "type": "id", "id": "VIMS_VADC" }, "right": { "type": "literal", "value": "0b010000" } } ] }, "encdec_visgfunct6": { "mapping": [ { "number": 0, "source": "VI_VSLIDEUP <-> 0b001110", "left": { "type": "id", "id": "VI_VSLIDEUP" }, "right": { "type": "literal", "value": "0b001110" } }, { "number": 1, "source": "VI_VSLIDEDOWN <-> 0b001111", "left": { "type": "id", "id": "VI_VSLIDEDOWN" }, "right": { "type": "literal", "value": "0b001111" } }, { "number": 2, "source": "VI_VRGATHER <-> 0b001100", "left": { "type": "id", "id": "VI_VRGATHER" }, "right": { "type": "literal", "value": "0b001100" } } ] }, "encdec_vlewidth": { "mapping": [ { "number": 0, "source": "VLE8 <-> 0b000", "left": { "type": "id", "id": "VLE8" }, "right": { "type": "literal", "value": "0b000" } }, { "number": 1, "source": "VLE16 <-> 0b101", "left": { "type": "id", "id": "VLE16" }, "right": { "type": "literal", "value": "0b101" } }, { "number": 2, "source": "VLE32 <-> 0b110", "left": { "type": "id", "id": "VLE32" }, "right": { "type": "literal", "value": "0b110" } }, { "number": 3, "source": "VLE64 <-> 0b111", "left": { "type": "id", "id": "VLE64" }, "right": { "type": "literal", "value": "0b111" } } ] }, "encdec_vsetop": { "mapping": [ { "number": 0, "source": "VSETVLI <-> 0b0000", "left": { "type": "id", "id": "VSETVLI" }, "right": { "type": "literal", "value": "0b0000" } }, { "number": 1, "source": "VSETVL <-> 0b1000", "left": { "type": "id", "id": "VSETVL" }, "right": { "type": "literal", "value": "0b1000" } } ] }, "encdec_vvcmpfunct6": { "mapping": [ { "number": 0, "source": "VVCMP_VMSEQ <-> 0b011000", "left": { "type": "id", "id": "VVCMP_VMSEQ" }, "right": { "type": "literal", "value": "0b011000" } }, { "number": 1, "source": "VVCMP_VMSNE <-> 0b011001", "left": { "type": "id", "id": "VVCMP_VMSNE" }, "right": { "type": "literal", "value": "0b011001" } }, { "number": 2, "source": "VVCMP_VMSLTU <-> 0b011010", "left": { "type": "id", "id": "VVCMP_VMSLTU" }, "right": { "type": "literal", "value": "0b011010" } }, { "number": 3, "source": "VVCMP_VMSLT <-> 0b011011", "left": { "type": "id", "id": "VVCMP_VMSLT" }, "right": { "type": "literal", "value": "0b011011" } }, { "number": 4, "source": "VVCMP_VMSLEU <-> 0b011100", "left": { "type": "id", "id": "VVCMP_VMSLEU" }, "right": { "type": "literal", "value": "0b011100" } }, { "number": 5, "source": "VVCMP_VMSLE <-> 0b011101", "left": { "type": "id", "id": "VVCMP_VMSLE" }, "right": { "type": "literal", "value": "0b011101" } } ] }, "encdec_vvfunct6": { "mapping": [ { "number": 0, "source": "VV_VADD <-> 0b000000", "left": { "type": "id", "id": "VV_VADD" }, "right": { "type": "literal", "value": "0b000000" } }, { "number": 1, "source": "VV_VSUB <-> 0b000010", "left": { "type": "id", "id": "VV_VSUB" }, "right": { "type": "literal", "value": "0b000010" } }, { "number": 2, "source": "VV_VMINU <-> 0b000100", "left": { "type": "id", "id": "VV_VMINU" }, "right": { "type": "literal", "value": "0b000100" } }, { "number": 3, "source": "VV_VMIN <-> 0b000101", "left": { "type": "id", "id": "VV_VMIN" }, "right": { "type": "literal", "value": "0b000101" } }, { "number": 4, "source": "VV_VMAXU <-> 0b000110", "left": { "type": "id", "id": "VV_VMAXU" }, "right": { "type": "literal", "value": "0b000110" } }, { "number": 5, "source": "VV_VMAX <-> 0b000111", "left": { "type": "id", "id": "VV_VMAX" }, "right": { "type": "literal", "value": "0b000111" } }, { "number": 6, "source": "VV_VAND <-> 0b001001", "left": { "type": "id", "id": "VV_VAND" }, "right": { "type": "literal", "value": "0b001001" } }, { "number": 7, "source": "VV_VOR <-> 0b001010", "left": { "type": "id", "id": "VV_VOR" }, "right": { "type": "literal", "value": "0b001010" } }, { "number": 8, "source": "VV_VXOR <-> 0b001011", "left": { "type": "id", "id": "VV_VXOR" }, "right": { "type": "literal", "value": "0b001011" } }, { "number": 9, "source": "VV_VRGATHER <-> 0b001100", "left": { "type": "id", "id": "VV_VRGATHER" }, "right": { "type": "literal", "value": "0b001100" } }, { "number": 10, "source": "VV_VRGATHEREI16 <-> 0b001110", "left": { "type": "id", "id": "VV_VRGATHEREI16" }, "right": { "type": "literal", "value": "0b001110" } }, { "number": 11, "source": "VV_VSADDU <-> 0b100000", "left": { "type": "id", "id": "VV_VSADDU" }, "right": { "type": "literal", "value": "0b100000" } }, { "number": 12, "source": "VV_VSADD <-> 0b100001", "left": { "type": "id", "id": "VV_VSADD" }, "right": { "type": "literal", "value": "0b100001" } }, { "number": 13, "source": "VV_VSSUBU <-> 0b100010", "left": { "type": "id", "id": "VV_VSSUBU" }, "right": { "type": "literal", "value": "0b100010" } }, { "number": 14, "source": "VV_VSSUB <-> 0b100011", "left": { "type": "id", "id": "VV_VSSUB" }, "right": { "type": "literal", "value": "0b100011" } }, { "number": 15, "source": "VV_VSLL <-> 0b100101", "left": { "type": "id", "id": "VV_VSLL" }, "right": { "type": "literal", "value": "0b100101" } }, { "number": 16, "source": "VV_VSMUL <-> 0b100111", "left": { "type": "id", "id": "VV_VSMUL" }, "right": { "type": "literal", "value": "0b100111" } }, { "number": 17, "source": "VV_VSRL <-> 0b101000", "left": { "type": "id", "id": "VV_VSRL" }, "right": { "type": "literal", "value": "0b101000" } }, { "number": 18, "source": "VV_VSRA <-> 0b101001", "left": { "type": "id", "id": "VV_VSRA" }, "right": { "type": "literal", "value": "0b101001" } }, { "number": 19, "source": "VV_VSSRL <-> 0b101010", "left": { "type": "id", "id": "VV_VSSRL" }, "right": { "type": "literal", "value": "0b101010" } }, { "number": 20, "source": "VV_VSSRA <-> 0b101011", "left": { "type": "id", "id": "VV_VSSRA" }, "right": { "type": "literal", "value": "0b101011" } } ] }, "encdec_vvmcfunct6": { "mapping": [ { "number": 0, "source": "VVMC_VMADC <-> 0b010001", "left": { "type": "id", "id": "VVMC_VMADC" }, "right": { "type": "literal", "value": "0b010001" } }, { "number": 1, "source": "VVMC_VMSBC <-> 0b010011", "left": { "type": "id", "id": "VVMC_VMSBC" }, "right": { "type": "literal", "value": "0b010011" } } ] }, "encdec_vvmfunct6": { "mapping": [ { "number": 0, "source": "VVM_VMADC <-> 0b010001", "left": { "type": "id", "id": "VVM_VMADC" }, "right": { "type": "literal", "value": "0b010001" } }, { "number": 1, "source": "VVM_VMSBC <-> 0b010011", "left": { "type": "id", "id": "VVM_VMSBC" }, "right": { "type": "literal", "value": "0b010011" } } ] }, "encdec_vvmsfunct6": { "mapping": [ { "number": 0, "source": "VVMS_VADC <-> 0b010000", "left": { "type": "id", "id": "VVMS_VADC" }, "right": { "type": "literal", "value": "0b010000" } }, { "number": 1, "source": "VVMS_VSBC <-> 0b010010", "left": { "type": "id", "id": "VVMS_VSBC" }, "right": { "type": "literal", "value": "0b010010" } } ] }, "encdec_vxcmpfunct6": { "mapping": [ { "number": 0, "source": "VXCMP_VMSEQ <-> 0b011000", "left": { "type": "id", "id": "VXCMP_VMSEQ" }, "right": { "type": "literal", "value": "0b011000" } }, { "number": 1, "source": "VXCMP_VMSNE <-> 0b011001", "left": { "type": "id", "id": "VXCMP_VMSNE" }, "right": { "type": "literal", "value": "0b011001" } }, { "number": 2, "source": "VXCMP_VMSLTU <-> 0b011010", "left": { "type": "id", "id": "VXCMP_VMSLTU" }, "right": { "type": "literal", "value": "0b011010" } }, { "number": 3, "source": "VXCMP_VMSLT <-> 0b011011", "left": { "type": "id", "id": "VXCMP_VMSLT" }, "right": { "type": "literal", "value": "0b011011" } }, { "number": 4, "source": "VXCMP_VMSLEU <-> 0b011100", "left": { "type": "id", "id": "VXCMP_VMSLEU" }, "right": { "type": "literal", "value": "0b011100" } }, { "number": 5, "source": "VXCMP_VMSLE <-> 0b011101", "left": { "type": "id", "id": "VXCMP_VMSLE" }, "right": { "type": "literal", "value": "0b011101" } }, { "number": 6, "source": "VXCMP_VMSGTU <-> 0b011110", "left": { "type": "id", "id": "VXCMP_VMSGTU" }, "right": { "type": "literal", "value": "0b011110" } }, { "number": 7, "source": "VXCMP_VMSGT <-> 0b011111", "left": { "type": "id", "id": "VXCMP_VMSGT" }, "right": { "type": "literal", "value": "0b011111" } } ] }, "encdec_vxfunct6": { "mapping": [ { "number": 0, "source": "VX_VADD <-> 0b000000", "left": { "type": "id", "id": "VX_VADD" }, "right": { "type": "literal", "value": "0b000000" } }, { "number": 1, "source": "VX_VSUB <-> 0b000010", "left": { "type": "id", "id": "VX_VSUB" }, "right": { "type": "literal", "value": "0b000010" } }, { "number": 2, "source": "VX_VRSUB <-> 0b000011", "left": { "type": "id", "id": "VX_VRSUB" }, "right": { "type": "literal", "value": "0b000011" } }, { "number": 3, "source": "VX_VMINU <-> 0b000100", "left": { "type": "id", "id": "VX_VMINU" }, "right": { "type": "literal", "value": "0b000100" } }, { "number": 4, "source": "VX_VMIN <-> 0b000101", "left": { "type": "id", "id": "VX_VMIN" }, "right": { "type": "literal", "value": "0b000101" } }, { "number": 5, "source": "VX_VMAXU <-> 0b000110", "left": { "type": "id", "id": "VX_VMAXU" }, "right": { "type": "literal", "value": "0b000110" } }, { "number": 6, "source": "VX_VMAX <-> 0b000111", "left": { "type": "id", "id": "VX_VMAX" }, "right": { "type": "literal", "value": "0b000111" } }, { "number": 7, "source": "VX_VAND <-> 0b001001", "left": { "type": "id", "id": "VX_VAND" }, "right": { "type": "literal", "value": "0b001001" } }, { "number": 8, "source": "VX_VOR <-> 0b001010", "left": { "type": "id", "id": "VX_VOR" }, "right": { "type": "literal", "value": "0b001010" } }, { "number": 9, "source": "VX_VXOR <-> 0b001011", "left": { "type": "id", "id": "VX_VXOR" }, "right": { "type": "literal", "value": "0b001011" } }, { "number": 10, "source": "VX_VSADDU <-> 0b100000", "left": { "type": "id", "id": "VX_VSADDU" }, "right": { "type": "literal", "value": "0b100000" } }, { "number": 11, "source": "VX_VSADD <-> 0b100001", "left": { "type": "id", "id": "VX_VSADD" }, "right": { "type": "literal", "value": "0b100001" } }, { "number": 12, "source": "VX_VSSUBU <-> 0b100010", "left": { "type": "id", "id": "VX_VSSUBU" }, "right": { "type": "literal", "value": "0b100010" } }, { "number": 13, "source": "VX_VSSUB <-> 0b100011", "left": { "type": "id", "id": "VX_VSSUB" }, "right": { "type": "literal", "value": "0b100011" } }, { "number": 14, "source": "VX_VSLL <-> 0b100101", "left": { "type": "id", "id": "VX_VSLL" }, "right": { "type": "literal", "value": "0b100101" } }, { "number": 15, "source": "VX_VSMUL <-> 0b100111", "left": { "type": "id", "id": "VX_VSMUL" }, "right": { "type": "literal", "value": "0b100111" } }, { "number": 16, "source": "VX_VSRL <-> 0b101000", "left": { "type": "id", "id": "VX_VSRL" }, "right": { "type": "literal", "value": "0b101000" } }, { "number": 17, "source": "VX_VSRA <-> 0b101001", "left": { "type": "id", "id": "VX_VSRA" }, "right": { "type": "literal", "value": "0b101001" } }, { "number": 18, "source": "VX_VSSRL <-> 0b101010", "left": { "type": "id", "id": "VX_VSSRL" }, "right": { "type": "literal", "value": "0b101010" } }, { "number": 19, "source": "VX_VSSRA <-> 0b101011", "left": { "type": "id", "id": "VX_VSSRA" }, "right": { "type": "literal", "value": "0b101011" } } ] }, "encdec_vxmcfunct6": { "mapping": [ { "number": 0, "source": "VXMC_VMADC <-> 0b010001", "left": { "type": "id", "id": "VXMC_VMADC" }, "right": { "type": "literal", "value": "0b010001" } }, { "number": 1, "source": "VXMC_VMSBC <-> 0b010011", "left": { "type": "id", "id": "VXMC_VMSBC" }, "right": { "type": "literal", "value": "0b010011" } } ] }, "encdec_vxmfunct6": { "mapping": [ { "number": 0, "source": "VXM_VMADC <-> 0b010001", "left": { "type": "id", "id": "VXM_VMADC" }, "right": { "type": "literal", "value": "0b010001" } }, { "number": 1, "source": "VXM_VMSBC <-> 0b010011", "left": { "type": "id", "id": "VXM_VMSBC" }, "right": { "type": "literal", "value": "0b010011" } } ] }, "encdec_vxmsfunct6": { "mapping": [ { "number": 0, "source": "VXMS_VADC <-> 0b010000", "left": { "type": "id", "id": "VXMS_VADC" }, "right": { "type": "literal", "value": "0b010000" } }, { "number": 1, "source": "VXMS_VSBC <-> 0b010010", "left": { "type": "id", "id": "VXMS_VSBC" }, "right": { "type": "literal", "value": "0b010010" } } ] }, "encdec_vxsgfunct6": { "mapping": [ { "number": 0, "source": "VX_VSLIDEUP <-> 0b001110", "left": { "type": "id", "id": "VX_VSLIDEUP" }, "right": { "type": "literal", "value": "0b001110" } }, { "number": 1, "source": "VX_VSLIDEDOWN <-> 0b001111", "left": { "type": "id", "id": "VX_VSLIDEDOWN" }, "right": { "type": "literal", "value": "0b001111" } }, { "number": 2, "source": "VX_VRGATHER <-> 0b001100", "left": { "type": "id", "id": "VX_VRGATHER" }, "right": { "type": "literal", "value": "0b001100" } } ] }, "encdec_wmvvfunct6": { "mapping": [ { "number": 0, "source": "WMVV_VWMACCU <-> 0b111100", "left": { "type": "id", "id": "WMVV_VWMACCU" }, "right": { "type": "literal", "value": "0b111100" } }, { "number": 1, "source": "WMVV_VWMACC <-> 0b111101", "left": { "type": "id", "id": "WMVV_VWMACC" }, "right": { "type": "literal", "value": "0b111101" } }, { "number": 2, "source": "WMVV_VWMACCSU <-> 0b111111", "left": { "type": "id", "id": "WMVV_VWMACCSU" }, "right": { "type": "literal", "value": "0b111111" } } ] }, "encdec_wmvxfunct6": { "mapping": [ { "number": 0, "source": "WMVX_VWMACCU <-> 0b111100", "left": { "type": "id", "id": "WMVX_VWMACCU" }, "right": { "type": "literal", "value": "0b111100" } }, { "number": 1, "source": "WMVX_VWMACC <-> 0b111101", "left": { "type": "id", "id": "WMVX_VWMACC" }, "right": { "type": "literal", "value": "0b111101" } }, { "number": 2, "source": "WMVX_VWMACCUS <-> 0b111110", "left": { "type": "id", "id": "WMVX_VWMACCUS" }, "right": { "type": "literal", "value": "0b111110" } }, { "number": 3, "source": "WMVX_VWMACCSU <-> 0b111111", "left": { "type": "id", "id": "WMVX_VWMACCSU" }, "right": { "type": "literal", "value": "0b111111" } } ] }, "encdec_wvfunct6": { "mapping": [ { "number": 0, "source": "WV_VADD <-> 0b110101", "left": { "type": "id", "id": "WV_VADD" }, "right": { "type": "literal", "value": "0b110101" } }, { "number": 1, "source": "WV_VSUB <-> 0b110111", "left": { "type": "id", "id": "WV_VSUB" }, "right": { "type": "literal", "value": "0b110111" } }, { "number": 2, "source": "WV_VADDU <-> 0b110100", "left": { "type": "id", "id": "WV_VADDU" }, "right": { "type": "literal", "value": "0b110100" } }, { "number": 3, "source": "WV_VSUBU <-> 0b110110", "left": { "type": "id", "id": "WV_VSUBU" }, "right": { "type": "literal", "value": "0b110110" } } ] }, "encdec_wvvfunct6": { "mapping": [ { "number": 0, "source": "WVV_VADD <-> 0b110001", "left": { "type": "id", "id": "WVV_VADD" }, "right": { "type": "literal", "value": "0b110001" } }, { "number": 1, "source": "WVV_VSUB <-> 0b110011", "left": { "type": "id", "id": "WVV_VSUB" }, "right": { "type": "literal", "value": "0b110011" } }, { "number": 2, "source": "WVV_VADDU <-> 0b110000", "left": { "type": "id", "id": "WVV_VADDU" }, "right": { "type": "literal", "value": "0b110000" } }, { "number": 3, "source": "WVV_VSUBU <-> 0b110010", "left": { "type": "id", "id": "WVV_VSUBU" }, "right": { "type": "literal", "value": "0b110010" } }, { "number": 4, "source": "WVV_VWMUL <-> 0b111011", "left": { "type": "id", "id": "WVV_VWMUL" }, "right": { "type": "literal", "value": "0b111011" } }, { "number": 5, "source": "WVV_VWMULU <-> 0b111000", "left": { "type": "id", "id": "WVV_VWMULU" }, "right": { "type": "literal", "value": "0b111000" } }, { "number": 6, "source": "WVV_VWMULSU <-> 0b111010", "left": { "type": "id", "id": "WVV_VWMULSU" }, "right": { "type": "literal", "value": "0b111010" } } ] }, "encdec_wvxfunct6": { "mapping": [ { "number": 0, "source": "WVX_VADD <-> 0b110001", "left": { "type": "id", "id": "WVX_VADD" }, "right": { "type": "literal", "value": "0b110001" } }, { "number": 1, "source": "WVX_VSUB <-> 0b110011", "left": { "type": "id", "id": "WVX_VSUB" }, "right": { "type": "literal", "value": "0b110011" } }, { "number": 2, "source": "WVX_VADDU <-> 0b110000", "left": { "type": "id", "id": "WVX_VADDU" }, "right": { "type": "literal", "value": "0b110000" } }, { "number": 3, "source": "WVX_VSUBU <-> 0b110010", "left": { "type": "id", "id": "WVX_VSUBU" }, "right": { "type": "literal", "value": "0b110010" } }, { "number": 4, "source": "WVX_VWMUL <-> 0b111011", "left": { "type": "id", "id": "WVX_VWMUL" }, "right": { "type": "literal", "value": "0b111011" } }, { "number": 5, "source": "WVX_VWMULU <-> 0b111000", "left": { "type": "id", "id": "WVX_VWMULU" }, "right": { "type": "literal", "value": "0b111000" } }, { "number": 6, "source": "WVX_VWMULSU <-> 0b111010", "left": { "type": "id", "id": "WVX_VWMULSU" }, "right": { "type": "literal", "value": "0b111010" } } ] }, "encdec_wxfunct6": { "mapping": [ { "number": 0, "source": "WX_VADD <-> 0b110101", "left": { "type": "id", "id": "WX_VADD" }, "right": { "type": "literal", "value": "0b110101" } }, { "number": 1, "source": "WX_VSUB <-> 0b110111", "left": { "type": "id", "id": "WX_VSUB" }, "right": { "type": "literal", "value": "0b110111" } }, { "number": 2, "source": "WX_VADDU <-> 0b110100", "left": { "type": "id", "id": "WX_VADDU" }, "right": { "type": "literal", "value": "0b110100" } }, { "number": 3, "source": "WX_VSUBU <-> 0b110110", "left": { "type": "id", "id": "WX_VSUBU" }, "right": { "type": "literal", "value": "0b110110" } } ] }, "f_bin_rm_type_mnemonic_D": { "mapping": [ { "number": 0, "source": "FADD_D <-> \"fadd.d\"", "left": { "type": "id", "id": "FADD_D" }, "right": { "type": "literal", "value": "\"fadd.d\"" } }, { "number": 1, "source": "FSUB_D <-> \"fsub.d\"", "left": { "type": "id", "id": "FSUB_D" }, "right": { "type": "literal", "value": "\"fsub.d\"" } }, { "number": 2, "source": "FMUL_D <-> \"fmul.d\"", "left": { "type": "id", "id": "FMUL_D" }, "right": { "type": "literal", "value": "\"fmul.d\"" } }, { "number": 3, "source": "FDIV_D <-> \"fdiv.d\"", "left": { "type": "id", "id": "FDIV_D" }, "right": { "type": "literal", "value": "\"fdiv.d\"" } } ] }, "f_bin_rm_type_mnemonic_H": { "mapping": [ { "number": 0, "source": "FADD_H <-> \"fadd.h\"", "left": { "type": "id", "id": "FADD_H" }, "right": { "type": "literal", "value": "\"fadd.h\"" } }, { "number": 1, "source": "FSUB_H <-> \"fsub.h\"", "left": { "type": "id", "id": "FSUB_H" }, "right": { "type": "literal", "value": "\"fsub.h\"" } }, { "number": 2, "source": "FMUL_H <-> \"fmul.h\"", "left": { "type": "id", "id": "FMUL_H" }, "right": { "type": "literal", "value": "\"fmul.h\"" } }, { "number": 3, "source": "FDIV_H <-> \"fdiv.h\"", "left": { "type": "id", "id": "FDIV_H" }, "right": { "type": "literal", "value": "\"fdiv.h\"" } } ] }, "f_bin_rm_type_mnemonic_S": { "mapping": [ { "number": 0, "source": "FADD_S <-> \"fadd.s\"", "left": { "type": "id", "id": "FADD_S" }, "right": { "type": "literal", "value": "\"fadd.s\"" } }, { "number": 1, "source": "FSUB_S <-> \"fsub.s\"", "left": { "type": "id", "id": "FSUB_S" }, "right": { "type": "literal", "value": "\"fsub.s\"" } }, { "number": 2, "source": "FMUL_S <-> \"fmul.s\"", "left": { "type": "id", "id": "FMUL_S" }, "right": { "type": "literal", "value": "\"fmul.s\"" } }, { "number": 3, "source": "FDIV_S <-> \"fdiv.s\"", "left": { "type": "id", "id": "FDIV_S" }, "right": { "type": "literal", "value": "\"fdiv.s\"" } } ] }, "f_bin_type_mnemonic_D": { "mapping": [ { "number": 0, "source": "FSGNJ_D <-> \"fsgnj.d\"", "left": { "type": "id", "id": "FSGNJ_D" }, "right": { "type": "literal", "value": "\"fsgnj.d\"" } }, { "number": 1, "source": "FSGNJN_D <-> \"fsgnjn.d\"", "left": { "type": "id", "id": "FSGNJN_D" }, "right": { "type": "literal", "value": "\"fsgnjn.d\"" } }, { "number": 2, "source": "FSGNJX_D <-> \"fsgnjx.d\"", "left": { "type": "id", "id": "FSGNJX_D" }, "right": { "type": "literal", "value": "\"fsgnjx.d\"" } }, { "number": 3, "source": "FMIN_D <-> \"fmin.d\"", "left": { "type": "id", "id": "FMIN_D" }, "right": { "type": "literal", "value": "\"fmin.d\"" } }, { "number": 4, "source": "FMAX_D <-> \"fmax.d\"", "left": { "type": "id", "id": "FMAX_D" }, "right": { "type": "literal", "value": "\"fmax.d\"" } }, { "number": 5, "source": "FEQ_D <-> \"feq.d\"", "left": { "type": "id", "id": "FEQ_D" }, "right": { "type": "literal", "value": "\"feq.d\"" } }, { "number": 6, "source": "FLT_D <-> \"flt.d\"", "left": { "type": "id", "id": "FLT_D" }, "right": { "type": "literal", "value": "\"flt.d\"" } }, { "number": 7, "source": "FLE_D <-> \"fle.d\"", "left": { "type": "id", "id": "FLE_D" }, "right": { "type": "literal", "value": "\"fle.d\"" } } ] }, "f_bin_type_mnemonic_H": { "mapping": [ { "number": 0, "source": "FSGNJ_H <-> \"fsgnj.h\"", "left": { "type": "id", "id": "FSGNJ_H" }, "right": { "type": "literal", "value": "\"fsgnj.h\"" } }, { "number": 1, "source": "FSGNJN_H <-> \"fsgnjn.h\"", "left": { "type": "id", "id": "FSGNJN_H" }, "right": { "type": "literal", "value": "\"fsgnjn.h\"" } }, { "number": 2, "source": "FSGNJX_H <-> \"fsgnjx.h\"", "left": { "type": "id", "id": "FSGNJX_H" }, "right": { "type": "literal", "value": "\"fsgnjx.h\"" } }, { "number": 3, "source": "FMIN_H <-> \"fmin.h\"", "left": { "type": "id", "id": "FMIN_H" }, "right": { "type": "literal", "value": "\"fmin.h\"" } }, { "number": 4, "source": "FMAX_H <-> \"fmax.h\"", "left": { "type": "id", "id": "FMAX_H" }, "right": { "type": "literal", "value": "\"fmax.h\"" } }, { "number": 5, "source": "FEQ_H <-> \"feq.h\"", "left": { "type": "id", "id": "FEQ_H" }, "right": { "type": "literal", "value": "\"feq.h\"" } }, { "number": 6, "source": "FLT_H <-> \"flt.h\"", "left": { "type": "id", "id": "FLT_H" }, "right": { "type": "literal", "value": "\"flt.h\"" } }, { "number": 7, "source": "FLE_H <-> \"fle.h\"", "left": { "type": "id", "id": "FLE_H" }, "right": { "type": "literal", "value": "\"fle.h\"" } } ] }, "f_bin_type_mnemonic_S": { "mapping": [ { "number": 0, "source": "FSGNJ_S <-> \"fsgnj.s\"", "left": { "type": "id", "id": "FSGNJ_S" }, "right": { "type": "literal", "value": "\"fsgnj.s\"" } }, { "number": 1, "source": "FSGNJN_S <-> \"fsgnjn.s\"", "left": { "type": "id", "id": "FSGNJN_S" }, "right": { "type": "literal", "value": "\"fsgnjn.s\"" } }, { "number": 2, "source": "FSGNJX_S <-> \"fsgnjx.s\"", "left": { "type": "id", "id": "FSGNJX_S" }, "right": { "type": "literal", "value": "\"fsgnjx.s\"" } }, { "number": 3, "source": "FMIN_S <-> \"fmin.s\"", "left": { "type": "id", "id": "FMIN_S" }, "right": { "type": "literal", "value": "\"fmin.s\"" } }, { "number": 4, "source": "FMAX_S <-> \"fmax.s\"", "left": { "type": "id", "id": "FMAX_S" }, "right": { "type": "literal", "value": "\"fmax.s\"" } }, { "number": 5, "source": "FEQ_S <-> \"feq.s\"", "left": { "type": "id", "id": "FEQ_S" }, "right": { "type": "literal", "value": "\"feq.s\"" } }, { "number": 6, "source": "FLT_S <-> \"flt.s\"", "left": { "type": "id", "id": "FLT_S" }, "right": { "type": "literal", "value": "\"flt.s\"" } }, { "number": 7, "source": "FLE_S <-> \"fle.s\"", "left": { "type": "id", "id": "FLE_S" }, "right": { "type": "literal", "value": "\"fle.s\"" } } ] }, "f_madd_type_mnemonic_D": { "mapping": [ { "number": 0, "source": "FMADD_D <-> \"fmadd.d\"", "left": { "type": "id", "id": "FMADD_D" }, "right": { "type": "literal", "value": "\"fmadd.d\"" } }, { "number": 1, "source": "FMSUB_D <-> \"fmsub.d\"", "left": { "type": "id", "id": "FMSUB_D" }, "right": { "type": "literal", "value": "\"fmsub.d\"" } }, { "number": 2, "source": "FNMSUB_D <-> \"fnmsub.d\"", "left": { "type": "id", "id": "FNMSUB_D" }, "right": { "type": "literal", "value": "\"fnmsub.d\"" } }, { "number": 3, "source": "FNMADD_D <-> \"fnmadd.d\"", "left": { "type": "id", "id": "FNMADD_D" }, "right": { "type": "literal", "value": "\"fnmadd.d\"" } } ] }, "f_madd_type_mnemonic_H": { "mapping": [ { "number": 0, "source": "FMADD_H <-> \"fmadd.h\"", "left": { "type": "id", "id": "FMADD_H" }, "right": { "type": "literal", "value": "\"fmadd.h\"" } }, { "number": 1, "source": "FMSUB_H <-> \"fmsub.h\"", "left": { "type": "id", "id": "FMSUB_H" }, "right": { "type": "literal", "value": "\"fmsub.h\"" } }, { "number": 2, "source": "FNMSUB_H <-> \"fnmsub.h\"", "left": { "type": "id", "id": "FNMSUB_H" }, "right": { "type": "literal", "value": "\"fnmsub.h\"" } }, { "number": 3, "source": "FNMADD_H <-> \"fnmadd.h\"", "left": { "type": "id", "id": "FNMADD_H" }, "right": { "type": "literal", "value": "\"fnmadd.h\"" } } ] }, "f_madd_type_mnemonic_S": { "mapping": [ { "number": 0, "source": "FMADD_S <-> \"fmadd.s\"", "left": { "type": "id", "id": "FMADD_S" }, "right": { "type": "literal", "value": "\"fmadd.s\"" } }, { "number": 1, "source": "FMSUB_S <-> \"fmsub.s\"", "left": { "type": "id", "id": "FMSUB_S" }, "right": { "type": "literal", "value": "\"fmsub.s\"" } }, { "number": 2, "source": "FNMSUB_S <-> \"fnmsub.s\"", "left": { "type": "id", "id": "FNMSUB_S" }, "right": { "type": "literal", "value": "\"fnmsub.s\"" } }, { "number": 3, "source": "FNMADD_S <-> \"fnmadd.s\"", "left": { "type": "id", "id": "FNMADD_S" }, "right": { "type": "literal", "value": "\"fnmadd.s\"" } } ] }, "f_un_rm_type_mnemonic_D": { "mapping": [ { "number": 0, "source": "FSQRT_D <-> \"fsqrt.d\"", "left": { "type": "id", "id": "FSQRT_D" }, "right": { "type": "literal", "value": "\"fsqrt.d\"" } }, { "number": 1, "source": "FCVT_W_D <-> \"fcvt.w.d\"", "left": { "type": "id", "id": "FCVT_W_D" }, "right": { "type": "literal", "value": "\"fcvt.w.d\"" } }, { "number": 2, "source": "FCVT_WU_D <-> \"fcvt.wu.d\"", "left": { "type": "id", "id": "FCVT_WU_D" }, "right": { "type": "literal", "value": "\"fcvt.wu.d\"" } }, { "number": 3, "source": "FCVT_D_W <-> \"fcvt.d.w\"", "left": { "type": "id", "id": "FCVT_D_W" }, "right": { "type": "literal", "value": "\"fcvt.d.w\"" } }, { "number": 4, "source": "FCVT_D_WU <-> \"fcvt.d.wu\"", "left": { "type": "id", "id": "FCVT_D_WU" }, "right": { "type": "literal", "value": "\"fcvt.d.wu\"" } }, { "number": 5, "source": "FCVT_L_D <-> \"fcvt.l.d\"", "left": { "type": "id", "id": "FCVT_L_D" }, "right": { "type": "literal", "value": "\"fcvt.l.d\"" } }, { "number": 6, "source": "FCVT_LU_D <-> \"fcvt.lu.d\"", "left": { "type": "id", "id": "FCVT_LU_D" }, "right": { "type": "literal", "value": "\"fcvt.lu.d\"" } }, { "number": 7, "source": "FCVT_D_L <-> \"fcvt.d.l\"", "left": { "type": "id", "id": "FCVT_D_L" }, "right": { "type": "literal", "value": "\"fcvt.d.l\"" } }, { "number": 8, "source": "FCVT_D_LU <-> \"fcvt.d.lu\"", "left": { "type": "id", "id": "FCVT_D_LU" }, "right": { "type": "literal", "value": "\"fcvt.d.lu\"" } }, { "number": 9, "source": "FCVT_S_D <-> \"fcvt.s.d\"", "left": { "type": "id", "id": "FCVT_S_D" }, "right": { "type": "literal", "value": "\"fcvt.s.d\"" } }, { "number": 10, "source": "FCVT_D_S <-> \"fcvt.d.s\"", "left": { "type": "id", "id": "FCVT_D_S" }, "right": { "type": "literal", "value": "\"fcvt.d.s\"" } } ] }, "f_un_rm_type_mnemonic_H": { "mapping": [ { "number": 0, "source": "FSQRT_H <-> \"fsqrt.h\"", "left": { "type": "id", "id": "FSQRT_H" }, "right": { "type": "literal", "value": "\"fsqrt.h\"" } }, { "number": 1, "source": "FCVT_W_H <-> \"fcvt.w.h\"", "left": { "type": "id", "id": "FCVT_W_H" }, "right": { "type": "literal", "value": "\"fcvt.w.h\"" } }, { "number": 2, "source": "FCVT_WU_H <-> \"fcvt.wu.h\"", "left": { "type": "id", "id": "FCVT_WU_H" }, "right": { "type": "literal", "value": "\"fcvt.wu.h\"" } }, { "number": 3, "source": "FCVT_H_W <-> \"fcvt.h.w\"", "left": { "type": "id", "id": "FCVT_H_W" }, "right": { "type": "literal", "value": "\"fcvt.h.w\"" } }, { "number": 4, "source": "FCVT_H_WU <-> \"fcvt.h.wu\"", "left": { "type": "id", "id": "FCVT_H_WU" }, "right": { "type": "literal", "value": "\"fcvt.h.wu\"" } }, { "number": 5, "source": "FCVT_H_S <-> \"fcvt.h.s\"", "left": { "type": "id", "id": "FCVT_H_S" }, "right": { "type": "literal", "value": "\"fcvt.h.s\"" } }, { "number": 6, "source": "FCVT_H_D <-> \"fcvt.h.d\"", "left": { "type": "id", "id": "FCVT_H_D" }, "right": { "type": "literal", "value": "\"fcvt.h.d\"" } }, { "number": 7, "source": "FCVT_S_H <-> \"fcvt.s.h\"", "left": { "type": "id", "id": "FCVT_S_H" }, "right": { "type": "literal", "value": "\"fcvt.s.h\"" } }, { "number": 8, "source": "FCVT_D_H <-> \"fcvt.d.h\"", "left": { "type": "id", "id": "FCVT_D_H" }, "right": { "type": "literal", "value": "\"fcvt.d.h\"" } }, { "number": 9, "source": "FCVT_L_H <-> \"fcvt.l.h\"", "left": { "type": "id", "id": "FCVT_L_H" }, "right": { "type": "literal", "value": "\"fcvt.l.h\"" } }, { "number": 10, "source": "FCVT_LU_H <-> \"fcvt.lu.h\"", "left": { "type": "id", "id": "FCVT_LU_H" }, "right": { "type": "literal", "value": "\"fcvt.lu.h\"" } }, { "number": 11, "source": "FCVT_H_L <-> \"fcvt.h.l\"", "left": { "type": "id", "id": "FCVT_H_L" }, "right": { "type": "literal", "value": "\"fcvt.h.l\"" } }, { "number": 12, "source": "FCVT_H_LU <-> \"fcvt.h.lu\"", "left": { "type": "id", "id": "FCVT_H_LU" }, "right": { "type": "literal", "value": "\"fcvt.h.lu\"" } } ] }, "f_un_rm_type_mnemonic_S": { "mapping": [ { "number": 0, "source": "FSQRT_S <-> \"fsqrt.s\"", "left": { "type": "id", "id": "FSQRT_S" }, "right": { "type": "literal", "value": "\"fsqrt.s\"" } }, { "number": 1, "source": "FCVT_W_S <-> \"fcvt.w.s\"", "left": { "type": "id", "id": "FCVT_W_S" }, "right": { "type": "literal", "value": "\"fcvt.w.s\"" } }, { "number": 2, "source": "FCVT_WU_S <-> \"fcvt.wu.s\"", "left": { "type": "id", "id": "FCVT_WU_S" }, "right": { "type": "literal", "value": "\"fcvt.wu.s\"" } }, { "number": 3, "source": "FCVT_S_W <-> \"fcvt.s.w\"", "left": { "type": "id", "id": "FCVT_S_W" }, "right": { "type": "literal", "value": "\"fcvt.s.w\"" } }, { "number": 4, "source": "FCVT_S_WU <-> \"fcvt.s.wu\"", "left": { "type": "id", "id": "FCVT_S_WU" }, "right": { "type": "literal", "value": "\"fcvt.s.wu\"" } }, { "number": 5, "source": "FCVT_L_S <-> \"fcvt.l.s\"", "left": { "type": "id", "id": "FCVT_L_S" }, "right": { "type": "literal", "value": "\"fcvt.l.s\"" } }, { "number": 6, "source": "FCVT_LU_S <-> \"fcvt.lu.s\"", "left": { "type": "id", "id": "FCVT_LU_S" }, "right": { "type": "literal", "value": "\"fcvt.lu.s\"" } }, { "number": 7, "source": "FCVT_S_L <-> \"fcvt.s.l\"", "left": { "type": "id", "id": "FCVT_S_L" }, "right": { "type": "literal", "value": "\"fcvt.s.l\"" } }, { "number": 8, "source": "FCVT_S_LU <-> \"fcvt.s.lu\"", "left": { "type": "id", "id": "FCVT_S_LU" }, "right": { "type": "literal", "value": "\"fcvt.s.lu\"" } } ] }, "f_un_type_mnemonic_D": { "mapping": [ { "number": 0, "source": "FMV_X_D <-> \"fmv.x.d\"", "left": { "type": "id", "id": "FMV_X_D" }, "right": { "type": "literal", "value": "\"fmv.x.d\"" } }, { "number": 1, "source": "FCLASS_D <-> \"fclass.d\"", "left": { "type": "id", "id": "FCLASS_D" }, "right": { "type": "literal", "value": "\"fclass.d\"" } }, { "number": 2, "source": "FMV_D_X <-> \"fmv.d.x\"", "left": { "type": "id", "id": "FMV_D_X" }, "right": { "type": "literal", "value": "\"fmv.d.x\"" } } ] }, "f_un_type_mnemonic_H": { "mapping": [ { "number": 0, "source": "FMV_X_H <-> \"fmv.x.h\"", "left": { "type": "id", "id": "FMV_X_H" }, "right": { "type": "literal", "value": "\"fmv.x.h\"" } }, { "number": 1, "source": "FCLASS_H <-> \"fclass.h\"", "left": { "type": "id", "id": "FCLASS_H" }, "right": { "type": "literal", "value": "\"fclass.h\"" } }, { "number": 2, "source": "FMV_H_X <-> \"fmv.h.x\"", "left": { "type": "id", "id": "FMV_H_X" }, "right": { "type": "literal", "value": "\"fmv.h.x\"" } } ] }, "f_un_type_mnemonic_S": { "mapping": [ { "number": 0, "source": "FMV_X_W <-> \"fmv.x.w\"", "left": { "type": "id", "id": "FMV_X_W" }, "right": { "type": "literal", "value": "\"fmv.x.w\"" } }, { "number": 1, "source": "FCLASS_S <-> \"fclass.s\"", "left": { "type": "id", "id": "FCLASS_S" }, "right": { "type": "literal", "value": "\"fclass.s\"" } }, { "number": 2, "source": "FMV_W_X <-> \"fmv.w.x\"", "left": { "type": "id", "id": "FMV_W_X" }, "right": { "type": "literal", "value": "\"fmv.w.x\"" } } ] }, "fence_bits": { "mapping": [ { "number": 0, "source": "i : bits(1) @ o : bits(1) @ r : bits(1) @ w : bits(1) <-> bit_maybe_i(i) ^ bit_maybe_o(o) ^ bit_maybe_r(r) ^ bit_maybe_w(w)", "left": { "type": "vector_concat", "patterns": [ { "type": "id", "id": "i" }, { "type": "id", "id": "o" }, { "type": "id", "id": "r" }, { "type": "id", "id": "w" } ] }, "left_wavedrom": "{reg:[\n { bits: 1, name: 'w', attr: '1', type: 2 },\n { bits: 1, name: 'r', attr: '1', type: 2 },\n { bits: 1, name: 'o', attr: '1', type: 2 },\n { bits: 1, name: 'i', attr: '1', type: 2 }\n]}", "right": { "type": "string_append", "patterns": [ { "type": "app", "id": "bit_maybe_i", "patterns": [ { "type": "id", "id": "i" } ] }, { "type": "app", "id": "bit_maybe_o", "patterns": [ { "type": "id", "id": "o" } ] }, { "type": "app", "id": "bit_maybe_r", "patterns": [ { "type": "id", "id": "r" } ] }, { "type": "app", "id": "bit_maybe_w", "patterns": [ { "type": "id", "id": "w" } ] } ] } } ] }, "freg_name": { "mapping": [ { "number": 0, "source": "0b00000 <-> \"ft0\"", "left": { "type": "literal", "value": "0b00000" }, "right": { "type": "literal", "value": "\"ft0\"" } }, { "number": 1, "source": "0b00001 <-> \"ft1\"", "left": { "type": "literal", "value": "0b00001" }, "right": { "type": "literal", "value": "\"ft1\"" } }, { "number": 2, "source": "0b00010 <-> \"ft2\"", "left": { "type": "literal", "value": "0b00010" }, "right": { "type": "literal", "value": "\"ft2\"" } }, { "number": 3, "source": "0b00011 <-> \"ft3\"", "left": { "type": "literal", "value": "0b00011" }, "right": { "type": "literal", "value": "\"ft3\"" } }, { "number": 4, "source": "0b00100 <-> \"ft4\"", "left": { "type": "literal", "value": "0b00100" }, "right": { "type": "literal", "value": "\"ft4\"" } }, { "number": 5, "source": "0b00101 <-> \"ft5\"", "left": { "type": "literal", "value": "0b00101" }, "right": { "type": "literal", "value": "\"ft5\"" } }, { "number": 6, "source": "0b00110 <-> \"ft6\"", "left": { "type": "literal", "value": "0b00110" }, "right": { "type": "literal", "value": "\"ft6\"" } }, { "number": 7, "source": "0b00111 <-> \"ft7\"", "left": { "type": "literal", "value": "0b00111" }, "right": { "type": "literal", "value": "\"ft7\"" } }, { "number": 8, "source": "0b01000 <-> \"fs0\"", "left": { "type": "literal", "value": "0b01000" }, "right": { "type": "literal", "value": "\"fs0\"" } }, { "number": 9, "source": "0b01001 <-> \"fs1\"", "left": { "type": "literal", "value": "0b01001" }, "right": { "type": "literal", "value": "\"fs1\"" } }, { "number": 10, "source": "0b01010 <-> \"fa0\"", "left": { "type": "literal", "value": "0b01010" }, "right": { "type": "literal", "value": "\"fa0\"" } }, { "number": 11, "source": "0b01011 <-> \"fa1\"", "left": { "type": "literal", "value": "0b01011" }, "right": { "type": "literal", "value": "\"fa1\"" } }, { "number": 12, "source": "0b01100 <-> \"fa2\"", "left": { "type": "literal", "value": "0b01100" }, "right": { "type": "literal", "value": "\"fa2\"" } }, { "number": 13, "source": "0b01101 <-> \"fa3\"", "left": { "type": "literal", "value": "0b01101" }, "right": { "type": "literal", "value": "\"fa3\"" } }, { "number": 14, "source": "0b01110 <-> \"fa4\"", "left": { "type": "literal", "value": "0b01110" }, "right": { "type": "literal", "value": "\"fa4\"" } }, { "number": 15, "source": "0b01111 <-> \"fa5\"", "left": { "type": "literal", "value": "0b01111" }, "right": { "type": "literal", "value": "\"fa5\"" } }, { "number": 16, "source": "0b10000 <-> \"fa6\"", "left": { "type": "literal", "value": "0b10000" }, "right": { "type": "literal", "value": "\"fa6\"" } }, { "number": 17, "source": "0b10001 <-> \"fa7\"", "left": { "type": "literal", "value": "0b10001" }, "right": { "type": "literal", "value": "\"fa7\"" } }, { "number": 18, "source": "0b10010 <-> \"fs2\"", "left": { "type": "literal", "value": "0b10010" }, "right": { "type": "literal", "value": "\"fs2\"" } }, { "number": 19, "source": "0b10011 <-> \"fs3\"", "left": { "type": "literal", "value": "0b10011" }, "right": { "type": "literal", "value": "\"fs3\"" } }, { "number": 20, "source": "0b10100 <-> \"fs4\"", "left": { "type": "literal", "value": "0b10100" }, "right": { "type": "literal", "value": "\"fs4\"" } }, { "number": 21, "source": "0b10101 <-> \"fs5\"", "left": { "type": "literal", "value": "0b10101" }, "right": { "type": "literal", "value": "\"fs5\"" } }, { "number": 22, "source": "0b10110 <-> \"fs6\"", "left": { "type": "literal", "value": "0b10110" }, "right": { "type": "literal", "value": "\"fs6\"" } }, { "number": 23, "source": "0b10111 <-> \"fs7\"", "left": { "type": "literal", "value": "0b10111" }, "right": { "type": "literal", "value": "\"fs7\"" } }, { "number": 24, "source": "0b11000 <-> \"fs8\"", "left": { "type": "literal", "value": "0b11000" }, "right": { "type": "literal", "value": "\"fs8\"" } }, { "number": 25, "source": "0b11001 <-> \"fs9\"", "left": { "type": "literal", "value": "0b11001" }, "right": { "type": "literal", "value": "\"fs9\"" } }, { "number": 26, "source": "0b11010 <-> \"fs10\"", "left": { "type": "literal", "value": "0b11010" }, "right": { "type": "literal", "value": "\"fs10\"" } }, { "number": 27, "source": "0b11011 <-> \"fs11\"", "left": { "type": "literal", "value": "0b11011" }, "right": { "type": "literal", "value": "\"fs11\"" } }, { "number": 28, "source": "0b11100 <-> \"ft8\"", "left": { "type": "literal", "value": "0b11100" }, "right": { "type": "literal", "value": "\"ft8\"" } }, { "number": 29, "source": "0b11101 <-> \"ft9\"", "left": { "type": "literal", "value": "0b11101" }, "right": { "type": "literal", "value": "\"ft9\"" } }, { "number": 30, "source": "0b11110 <-> \"ft10\"", "left": { "type": "literal", "value": "0b11110" }, "right": { "type": "literal", "value": "\"ft10\"" } }, { "number": 31, "source": "0b11111 <-> \"ft11\"", "left": { "type": "literal", "value": "0b11111" }, "right": { "type": "literal", "value": "\"ft11\"" } } ] }, "freg_name_abi": { "mapping": [ { "number": 0, "source": "0b00000 <-> \"ft0\"", "left": { "type": "literal", "value": "0b00000" }, "right": { "type": "literal", "value": "\"ft0\"" } }, { "number": 1, "source": "0b00001 <-> \"ft1\"", "left": { "type": "literal", "value": "0b00001" }, "right": { "type": "literal", "value": "\"ft1\"" } }, { "number": 2, "source": "0b00010 <-> \"ft2\"", "left": { "type": "literal", "value": "0b00010" }, "right": { "type": "literal", "value": "\"ft2\"" } }, { "number": 3, "source": "0b00011 <-> \"ft3\"", "left": { "type": "literal", "value": "0b00011" }, "right": { "type": "literal", "value": "\"ft3\"" } }, { "number": 4, "source": "0b00100 <-> \"ft4\"", "left": { "type": "literal", "value": "0b00100" }, "right": { "type": "literal", "value": "\"ft4\"" } }, { "number": 5, "source": "0b00101 <-> \"ft5\"", "left": { "type": "literal", "value": "0b00101" }, "right": { "type": "literal", "value": "\"ft5\"" } }, { "number": 6, "source": "0b00110 <-> \"ft6\"", "left": { "type": "literal", "value": "0b00110" }, "right": { "type": "literal", "value": "\"ft6\"" } }, { "number": 7, "source": "0b00111 <-> \"ft7\"", "left": { "type": "literal", "value": "0b00111" }, "right": { "type": "literal", "value": "\"ft7\"" } }, { "number": 8, "source": "0b01000 <-> \"fs0\"", "left": { "type": "literal", "value": "0b01000" }, "right": { "type": "literal", "value": "\"fs0\"" } }, { "number": 9, "source": "0b01001 <-> \"fs1\"", "left": { "type": "literal", "value": "0b01001" }, "right": { "type": "literal", "value": "\"fs1\"" } }, { "number": 10, "source": "0b01010 <-> \"fa0\"", "left": { "type": "literal", "value": "0b01010" }, "right": { "type": "literal", "value": "\"fa0\"" } }, { "number": 11, "source": "0b01011 <-> \"fa1\"", "left": { "type": "literal", "value": "0b01011" }, "right": { "type": "literal", "value": "\"fa1\"" } }, { "number": 12, "source": "0b01100 <-> \"fa2\"", "left": { "type": "literal", "value": "0b01100" }, "right": { "type": "literal", "value": "\"fa2\"" } }, { "number": 13, "source": "0b01101 <-> \"fa3\"", "left": { "type": "literal", "value": "0b01101" }, "right": { "type": "literal", "value": "\"fa3\"" } }, { "number": 14, "source": "0b01110 <-> \"fa4\"", "left": { "type": "literal", "value": "0b01110" }, "right": { "type": "literal", "value": "\"fa4\"" } }, { "number": 15, "source": "0b01111 <-> \"fa5\"", "left": { "type": "literal", "value": "0b01111" }, "right": { "type": "literal", "value": "\"fa5\"" } }, { "number": 16, "source": "0b10000 <-> \"fa6\"", "left": { "type": "literal", "value": "0b10000" }, "right": { "type": "literal", "value": "\"fa6\"" } }, { "number": 17, "source": "0b10001 <-> \"fa7\"", "left": { "type": "literal", "value": "0b10001" }, "right": { "type": "literal", "value": "\"fa7\"" } }, { "number": 18, "source": "0b10010 <-> \"fs2\"", "left": { "type": "literal", "value": "0b10010" }, "right": { "type": "literal", "value": "\"fs2\"" } }, { "number": 19, "source": "0b10011 <-> \"fs3\"", "left": { "type": "literal", "value": "0b10011" }, "right": { "type": "literal", "value": "\"fs3\"" } }, { "number": 20, "source": "0b10100 <-> \"fs4\"", "left": { "type": "literal", "value": "0b10100" }, "right": { "type": "literal", "value": "\"fs4\"" } }, { "number": 21, "source": "0b10101 <-> \"fs5\"", "left": { "type": "literal", "value": "0b10101" }, "right": { "type": "literal", "value": "\"fs5\"" } }, { "number": 22, "source": "0b10110 <-> \"fs6\"", "left": { "type": "literal", "value": "0b10110" }, "right": { "type": "literal", "value": "\"fs6\"" } }, { "number": 23, "source": "0b10111 <-> \"fs7\"", "left": { "type": "literal", "value": "0b10111" }, "right": { "type": "literal", "value": "\"fs7\"" } }, { "number": 24, "source": "0b11000 <-> \"fs8\"", "left": { "type": "literal", "value": "0b11000" }, "right": { "type": "literal", "value": "\"fs8\"" } }, { "number": 25, "source": "0b11001 <-> \"fs9\"", "left": { "type": "literal", "value": "0b11001" }, "right": { "type": "literal", "value": "\"fs9\"" } }, { "number": 26, "source": "0b11010 <-> \"fs10\"", "left": { "type": "literal", "value": "0b11010" }, "right": { "type": "literal", "value": "\"fs10\"" } }, { "number": 27, "source": "0b11011 <-> \"fs11\"", "left": { "type": "literal", "value": "0b11011" }, "right": { "type": "literal", "value": "\"fs11\"" } }, { "number": 28, "source": "0b11100 <-> \"ft8\"", "left": { "type": "literal", "value": "0b11100" }, "right": { "type": "literal", "value": "\"ft8\"" } }, { "number": 29, "source": "0b11101 <-> \"ft9\"", "left": { "type": "literal", "value": "0b11101" }, "right": { "type": "literal", "value": "\"ft9\"" } }, { "number": 30, "source": "0b11110 <-> \"ft10\"", "left": { "type": "literal", "value": "0b11110" }, "right": { "type": "literal", "value": "\"ft10\"" } }, { "number": 31, "source": "0b11111 <-> \"ft11\"", "left": { "type": "literal", "value": "0b11111" }, "right": { "type": "literal", "value": "\"ft11\"" } } ] }, "freg_or_reg_name": { "mapping": [ { "number": 0, "source": "reg if sys_enable_fdext() <-> freg_name(reg) if sys_enable_fdext()", "left": { "type": "id", "id": "reg" }, "right": { "type": "app", "id": "freg_name", "patterns": [ { "type": "id", "id": "reg" } ] } }, { "number": 1, "source": "reg if sys_enable_zfinx() <-> reg_name(reg) if sys_enable_zfinx()", "left": { "type": "id", "id": "reg" }, "right": { "type": "app", "id": "reg_name", "patterns": [ { "type": "id", "id": "reg" } ] } } ] }, "frm_mnemonic": { "mapping": [ { "number": 0, "source": "RM_RNE <-> \"rne\"", "left": { "type": "id", "id": "RM_RNE" }, "right": { "type": "literal", "value": "\"rne\"" } }, { "number": 1, "source": "RM_RTZ <-> \"rtz\"", "left": { "type": "id", "id": "RM_RTZ" }, "right": { "type": "literal", "value": "\"rtz\"" } }, { "number": 2, "source": "RM_RDN <-> \"rdn\"", "left": { "type": "id", "id": "RM_RDN" }, "right": { "type": "literal", "value": "\"rdn\"" } }, { "number": 3, "source": "RM_RUP <-> \"rup\"", "left": { "type": "id", "id": "RM_RUP" }, "right": { "type": "literal", "value": "\"rup\"" } }, { "number": 4, "source": "RM_RMM <-> \"rmm\"", "left": { "type": "id", "id": "RM_RMM" }, "right": { "type": "literal", "value": "\"rmm\"" } }, { "number": 5, "source": "RM_DYN <-> \"dyn\"", "left": { "type": "id", "id": "RM_DYN" }, "right": { "type": "literal", "value": "\"dyn\"" } } ] }, "fvfmatype_mnemonic": { "mapping": [ { "number": 0, "source": "VF_VMADD <-> \"vfmadd.vf\"", "left": { "type": "id", "id": "VF_VMADD" }, "right": { "type": "literal", "value": "\"vfmadd.vf\"" } }, { "number": 1, "source": "VF_VNMADD <-> \"vfnmadd.vf\"", "left": { "type": "id", "id": "VF_VNMADD" }, "right": { "type": "literal", "value": "\"vfnmadd.vf\"" } }, { "number": 2, "source": "VF_VMSUB <-> \"vfmsub.vf\"", "left": { "type": "id", "id": "VF_VMSUB" }, "right": { "type": "literal", "value": "\"vfmsub.vf\"" } }, { "number": 3, "source": "VF_VNMSUB <-> \"vfnmsub.vf\"", "left": { "type": "id", "id": "VF_VNMSUB" }, "right": { "type": "literal", "value": "\"vfnmsub.vf\"" } }, { "number": 4, "source": "VF_VMACC <-> \"vfmacc.vf\"", "left": { "type": "id", "id": "VF_VMACC" }, "right": { "type": "literal", "value": "\"vfmacc.vf\"" } }, { "number": 5, "source": "VF_VNMACC <-> \"vfnmacc.vf\"", "left": { "type": "id", "id": "VF_VNMACC" }, "right": { "type": "literal", "value": "\"vfnmacc.vf\"" } }, { "number": 6, "source": "VF_VMSAC <-> \"vfmsac.vf\"", "left": { "type": "id", "id": "VF_VMSAC" }, "right": { "type": "literal", "value": "\"vfmsac.vf\"" } }, { "number": 7, "source": "VF_VNMSAC <-> \"vfnmsac.vf\"", "left": { "type": "id", "id": "VF_VNMSAC" }, "right": { "type": "literal", "value": "\"vfnmsac.vf\"" } } ] }, "fvfmtype_mnemonic": { "mapping": [ { "number": 0, "source": "VFM_VMFEQ <-> \"vmfeq.vf\"", "left": { "type": "id", "id": "VFM_VMFEQ" }, "right": { "type": "literal", "value": "\"vmfeq.vf\"" } }, { "number": 1, "source": "VFM_VMFLE <-> \"vmfle.vf\"", "left": { "type": "id", "id": "VFM_VMFLE" }, "right": { "type": "literal", "value": "\"vmfle.vf\"" } }, { "number": 2, "source": "VFM_VMFLT <-> \"vmflt.vf\"", "left": { "type": "id", "id": "VFM_VMFLT" }, "right": { "type": "literal", "value": "\"vmflt.vf\"" } }, { "number": 3, "source": "VFM_VMFNE <-> \"vmfne.vf\"", "left": { "type": "id", "id": "VFM_VMFNE" }, "right": { "type": "literal", "value": "\"vmfne.vf\"" } }, { "number": 4, "source": "VFM_VMFGT <-> \"vmfgt.vf\"", "left": { "type": "id", "id": "VFM_VMFGT" }, "right": { "type": "literal", "value": "\"vmfgt.vf\"" } }, { "number": 5, "source": "VFM_VMFGE <-> \"vmfge.vf\"", "left": { "type": "id", "id": "VFM_VMFGE" }, "right": { "type": "literal", "value": "\"vmfge.vf\"" } } ] }, "fvftype_mnemonic": { "mapping": [ { "number": 0, "source": "VF_VADD <-> \"vfadd.vf\"", "left": { "type": "id", "id": "VF_VADD" }, "right": { "type": "literal", "value": "\"vfadd.vf\"" } }, { "number": 1, "source": "VF_VSUB <-> \"vfsub.vf\"", "left": { "type": "id", "id": "VF_VSUB" }, "right": { "type": "literal", "value": "\"vfsub.vf\"" } }, { "number": 2, "source": "VF_VMIN <-> \"vfmin.vf\"", "left": { "type": "id", "id": "VF_VMIN" }, "right": { "type": "literal", "value": "\"vfmin.vf\"" } }, { "number": 3, "source": "VF_VMAX <-> \"vfmax.vf\"", "left": { "type": "id", "id": "VF_VMAX" }, "right": { "type": "literal", "value": "\"vfmax.vf\"" } }, { "number": 4, "source": "VF_VSGNJ <-> \"vfsgnj.vf\"", "left": { "type": "id", "id": "VF_VSGNJ" }, "right": { "type": "literal", "value": "\"vfsgnj.vf\"" } }, { "number": 5, "source": "VF_VSGNJN <-> \"vfsgnjn.vf\"", "left": { "type": "id", "id": "VF_VSGNJN" }, "right": { "type": "literal", "value": "\"vfsgnjn.vf\"" } }, { "number": 6, "source": "VF_VSGNJX <-> \"vfsgnjx.vf\"", "left": { "type": "id", "id": "VF_VSGNJX" }, "right": { "type": "literal", "value": "\"vfsgnjx.vf\"" } }, { "number": 7, "source": "VF_VSLIDE1UP <-> \"vfslide1up.vf\"", "left": { "type": "id", "id": "VF_VSLIDE1UP" }, "right": { "type": "literal", "value": "\"vfslide1up.vf\"" } }, { "number": 8, "source": "VF_VSLIDE1DOWN <-> \"vfslide1down.vf\"", "left": { "type": "id", "id": "VF_VSLIDE1DOWN" }, "right": { "type": "literal", "value": "\"vfslide1down.vf\"" } }, { "number": 9, "source": "VF_VDIV <-> \"vfdiv.vf\"", "left": { "type": "id", "id": "VF_VDIV" }, "right": { "type": "literal", "value": "\"vfdiv.vf\"" } }, { "number": 10, "source": "VF_VRDIV <-> \"vfrdiv.vf\"", "left": { "type": "id", "id": "VF_VRDIV" }, "right": { "type": "literal", "value": "\"vfrdiv.vf\"" } }, { "number": 11, "source": "VF_VMUL <-> \"vfmul.vf\"", "left": { "type": "id", "id": "VF_VMUL" }, "right": { "type": "literal", "value": "\"vfmul.vf\"" } }, { "number": 12, "source": "VF_VRSUB <-> \"vfrsub.vf\"", "left": { "type": "id", "id": "VF_VRSUB" }, "right": { "type": "literal", "value": "\"vfrsub.vf\"" } } ] }, "fvvmatype_mnemonic": { "mapping": [ { "number": 0, "source": "FVV_VMADD <-> \"vfmadd.vv\"", "left": { "type": "id", "id": "FVV_VMADD" }, "right": { "type": "literal", "value": "\"vfmadd.vv\"" } }, { "number": 1, "source": "FVV_VNMADD <-> \"vfnmadd.vv\"", "left": { "type": "id", "id": "FVV_VNMADD" }, "right": { "type": "literal", "value": "\"vfnmadd.vv\"" } }, { "number": 2, "source": "FVV_VMSUB <-> \"vfmsub.vv\"", "left": { "type": "id", "id": "FVV_VMSUB" }, "right": { "type": "literal", "value": "\"vfmsub.vv\"" } }, { "number": 3, "source": "FVV_VNMSUB <-> \"vfnmsub.vv\"", "left": { "type": "id", "id": "FVV_VNMSUB" }, "right": { "type": "literal", "value": "\"vfnmsub.vv\"" } }, { "number": 4, "source": "FVV_VMACC <-> \"vfmacc.vv\"", "left": { "type": "id", "id": "FVV_VMACC" }, "right": { "type": "literal", "value": "\"vfmacc.vv\"" } }, { "number": 5, "source": "FVV_VNMACC <-> \"vfnmacc.vv\"", "left": { "type": "id", "id": "FVV_VNMACC" }, "right": { "type": "literal", "value": "\"vfnmacc.vv\"" } }, { "number": 6, "source": "FVV_VMSAC <-> \"vfmsac.vv\"", "left": { "type": "id", "id": "FVV_VMSAC" }, "right": { "type": "literal", "value": "\"vfmsac.vv\"" } }, { "number": 7, "source": "FVV_VNMSAC <-> \"vfnmsac.vv\"", "left": { "type": "id", "id": "FVV_VNMSAC" }, "right": { "type": "literal", "value": "\"vfnmsac.vv\"" } } ] }, "fvvmtype_mnemonic": { "mapping": [ { "number": 0, "source": "FVVM_VMFEQ <-> \"vmfeq.vv\"", "left": { "type": "id", "id": "FVVM_VMFEQ" }, "right": { "type": "literal", "value": "\"vmfeq.vv\"" } }, { "number": 1, "source": "FVVM_VMFLE <-> \"vmfle.vv\"", "left": { "type": "id", "id": "FVVM_VMFLE" }, "right": { "type": "literal", "value": "\"vmfle.vv\"" } }, { "number": 2, "source": "FVVM_VMFLT <-> \"vmflt.vv\"", "left": { "type": "id", "id": "FVVM_VMFLT" }, "right": { "type": "literal", "value": "\"vmflt.vv\"" } }, { "number": 3, "source": "FVVM_VMFNE <-> \"vmfne.vv\"", "left": { "type": "id", "id": "FVVM_VMFNE" }, "right": { "type": "literal", "value": "\"vmfne.vv\"" } } ] }, "fvvtype_mnemonic": { "mapping": [ { "number": 0, "source": "FVV_VADD <-> \"vfadd.vv\"", "left": { "type": "id", "id": "FVV_VADD" }, "right": { "type": "literal", "value": "\"vfadd.vv\"" } }, { "number": 1, "source": "FVV_VSUB <-> \"vfsub.vv\"", "left": { "type": "id", "id": "FVV_VSUB" }, "right": { "type": "literal", "value": "\"vfsub.vv\"" } }, { "number": 2, "source": "FVV_VMIN <-> \"vfmin.vv\"", "left": { "type": "id", "id": "FVV_VMIN" }, "right": { "type": "literal", "value": "\"vfmin.vv\"" } }, { "number": 3, "source": "FVV_VMAX <-> \"vfmax.vv\"", "left": { "type": "id", "id": "FVV_VMAX" }, "right": { "type": "literal", "value": "\"vfmax.vv\"" } }, { "number": 4, "source": "FVV_VSGNJ <-> \"vfsgnj.vv\"", "left": { "type": "id", "id": "FVV_VSGNJ" }, "right": { "type": "literal", "value": "\"vfsgnj.vv\"" } }, { "number": 5, "source": "FVV_VSGNJN <-> \"vfsgnjn.vv\"", "left": { "type": "id", "id": "FVV_VSGNJN" }, "right": { "type": "literal", "value": "\"vfsgnjn.vv\"" } }, { "number": 6, "source": "FVV_VSGNJX <-> \"vfsgnjx.vv\"", "left": { "type": "id", "id": "FVV_VSGNJX" }, "right": { "type": "literal", "value": "\"vfsgnjx.vv\"" } }, { "number": 7, "source": "FVV_VDIV <-> \"vfdiv.vv\"", "left": { "type": "id", "id": "FVV_VDIV" }, "right": { "type": "literal", "value": "\"vfdiv.vv\"" } }, { "number": 8, "source": "FVV_VMUL <-> \"vfmul.vv\"", "left": { "type": "id", "id": "FVV_VMUL" }, "right": { "type": "literal", "value": "\"vfmul.vv\"" } } ] }, "fwftype_mnemonic": { "mapping": [ { "number": 0, "source": "FWF_VADD <-> \"vfwadd.wf\"", "left": { "type": "id", "id": "FWF_VADD" }, "right": { "type": "literal", "value": "\"vfwadd.wf\"" } }, { "number": 1, "source": "FWF_VSUB <-> \"vfwsub.wf\"", "left": { "type": "id", "id": "FWF_VSUB" }, "right": { "type": "literal", "value": "\"vfwsub.wf\"" } } ] }, "fwvfmatype_mnemonic": { "mapping": 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\"m2\" <-> 0b001", "left": { "type": "string_append", "patterns": [ { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"m2\"" } ] }, "right": { "type": "literal", "value": "0b001" } }, { "number": 6, "source": "sep() ^ \"m4\" <-> 0b010", "left": { "type": "string_append", "patterns": [ { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"m4\"" } ] }, "right": { "type": "literal", "value": "0b010" } }, { "number": 7, "source": "sep() ^ \"m8\" <-> 0b011", "left": { "type": "string_append", "patterns": [ { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"m8\"" } ] }, "right": { "type": "literal", "value": "0b011" } } ] }, "maybe_ma_flag": { "mapping": [ { "number": 0, "source": "\"\" <-> 0b0", "left": { "type": "literal", "value": "\"\"" }, "right": { "type": "literal", "value": "0b0" } }, { "number": 1, "source": "sep() ^ \"ma\" <-> 0b1", "left": { "type": "string_append", "patterns": [ { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"ma\"" } ] }, "right": { "type": "literal", "value": "0b1" } }, { "number": 2, "source": "sep() ^ \"mu\" <-> 0b0", "left": { "type": "string_append", "patterns": [ { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"mu\"" } ] }, "right": { "type": "literal", "value": "0b0" } } ] }, "maybe_not_u": { "mapping": [ { "number": 0, "source": "false <-> \"u\"", "left": { "type": "literal", "value": "false" }, "right": { "type": "literal", "value": "\"u\"" } }, { "number": 1, "source": "true <-> \"\"", "left": { "type": "literal", "value": "true" }, "right": { "type": "literal", "value": "\"\"" } } ] }, "maybe_rl": { "mapping": [ { "number": 0, "source": "true <-> \".rl\"", "left": { "type": "literal", "value": "true" }, "right": { "type": "literal", "value": "\".rl\"" } }, { "number": 1, "source": "false <-> \"\"", "left": { "type": "literal", "value": "false" }, "right": { "type": "literal", "value": "\"\"" } } ] }, "maybe_ta_flag": { "mapping": [ { "number": 0, "source": "\"\" <-> 0b0", "left": { "type": "literal", "value": "\"\"" }, "right": { "type": "literal", "value": "0b0" } }, { "number": 1, "source": "sep() ^ \"ta\" <-> 0b1", "left": { "type": "string_append", "patterns": [ { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"ta\"" } ] }, "right": { "type": "literal", "value": "0b1" } }, { "number": 2, "source": "sep() ^ \"tu\" <-> 0b0", "left": { "type": "string_append", "patterns": [ { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"tu\"" } ] }, "right": { "type": "literal", "value": "0b0" } } ] }, "maybe_u": { "mapping": [ { "number": 0, "source": "true <-> \"u\"", "left": { "type": "literal", "value": "true" }, "right": { "type": "literal", "value": "\"u\"" } }, { "number": 1, "source": "false <-> \"\"", "left": { "type": "literal", "value": "false" }, "right": { "type": "literal", "value": "\"\"" } } ] }, "maybe_vmask": { "mapping": [ { "number": 0, "source": "\"\" <-> 0b1", "left": { "type": "literal", "value": "\"\"" }, "right": { "type": "literal", "value": "0b1" } }, { "number": 1, "source": "sep() ^ \"v0.t\" <-> 0b0", "left": { "type": "string_append", "patterns": [ { "type": "app", "id": "sep", "patterns": [ { "type": "literal", "value": "()" } ] }, { "type": "literal", "value": "\"v0.t\"" } ] }, "right": { "type": "literal", "value": "0b0" } } ] }, "mmtype_mnemonic": { "mapping": [ { "number": 0, "source": "MM_VMAND <-> \"vmand.mm\"", "left": { "type": "id", "id": "MM_VMAND" }, "right": { "type": "literal", "value": "\"vmand.mm\"" } }, { "number": 1, "source": "MM_VMNAND <-> \"vmnand.mm\"", "left": { "type": "id", "id": "MM_VMNAND" }, "right": { "type": "literal", "value": "\"vmnand.mm\"" } }, { "number": 2, "source": "MM_VMANDNOT <-> \"vmandnot.mm\"", "left": { "type": "id", "id": "MM_VMANDNOT" }, "right": { "type": "literal", "value": "\"vmandnot.mm\"" } }, { "number": 3, "source": "MM_VMXOR <-> \"vmxor.mm\"", "left": { "type": "id", "id": "MM_VMXOR" }, "right": { "type": "literal", "value": "\"vmxor.mm\"" } }, { "number": 4, "source": "MM_VMOR <-> \"vmor.mm\"", "left": { "type": "id", "id": "MM_VMOR" }, "right": { "type": "literal", "value": "\"vmor.mm\"" } }, { "number": 5, "source": "MM_VMNOR <-> \"vmnor.mm\"", "left": { "type": "id", "id": "MM_VMNOR" }, "right": { "type": "literal", "value": "\"vmnor.mm\"" } }, { "number": 6, "source": "MM_VMORNOT <-> \"vmornot.mm\"", "left": { "type": "id", "id": "MM_VMORNOT" }, "right": { "type": "literal", "value": "\"vmornot.mm\"" } }, { "number": 7, "source": "MM_VMXNOR <-> \"vmxnor.mm\"", "left": { "type": "id", "id": "MM_VMXNOR" }, "right": { "type": "literal", "value": "\"vmxnor.mm\"" } } ] }, "mul_mnemonic": { "mapping": [ { "number": 0, "source": "(false, true, true) <-> \"mul\"", "left": { "type": "tuple", "patterns": [ { "type": "literal", "value": "false" }, { "type": "literal", "value": "true" }, { "type": "literal", "value": "true" } ] }, "right": { "type": "literal", "value": "\"mul\"" } }, { "number": 1, "source": "(true, true, true) <-> \"mulh\"", "left": { "type": "tuple", "patterns": [ { "type": "literal", "value": "true" }, { "type": "literal", "value": "true" }, { "type": "literal", "value": "true" } ] }, "right": { "type": "literal", "value": "\"mulh\"" } }, { "number": 2, "source": "(true, true, false) <-> \"mulhsu\"", "left": { "type": "tuple", "patterns": [ { "type": "literal", "value": "true" }, { "type": "literal", "value": "true" }, { "type": "literal", "value": "false" } ] }, "right": { "type": "literal", "value": "\"mulhsu\"" } }, { "number": 3, "source": "(true, false, false) <-> \"mulhu\"", "left": { "type": "tuple", "patterns": [ { "type": "literal", "value": "true" }, { "type": "literal", "value": "false" }, { "type": "literal", "value": "false" } ] }, "right": { "type": "literal", "value": "\"mulhu\"" } } ] }, "mvvmatype_mnemonic": { "mapping": [ { "number": 0, "source": "MVV_VMACC <-> \"vmacc.vv\"", "left": { "type": "id", "id": "MVV_VMACC" }, "right": { "type": "literal", "value": "\"vmacc.vv\"" } }, { "number": 1, "source": "MVV_VNMSAC <-> \"vnmsac.vv\"", "left": { "type": "id", "id": "MVV_VNMSAC" }, "right": { "type": "literal", "value": "\"vnmsac.vv\"" } }, { "number": 2, "source": "MVV_VMADD <-> \"vmadd.vv\"", "left": { "type": "id", "id": "MVV_VMADD" }, "right": { "type": "literal", "value": "\"vmadd.vv\"" } }, { "number": 3, "source": "MVV_VNMSUB <-> \"vnmsub.vv\"", "left": { "type": "id", "id": "MVV_VNMSUB" }, "right": { "type": "literal", "value": "\"vnmsub.vv\"" } } ] }, "mvvtype_mnemonic": { "mapping": [ { "number": 0, "source": "MVV_VAADDU <-> \"vaaddu.vv\"", "left": { "type": "id", "id": "MVV_VAADDU" }, "right": { "type": "literal", "value": "\"vaaddu.vv\"" } }, { "number": 1, "source": "MVV_VAADD <-> \"vaadd.vv\"", "left": { "type": "id", "id": "MVV_VAADD" }, "right": { "type": "literal", "value": "\"vaadd.vv\"" } }, { "number": 2, "source": "MVV_VASUBU <-> \"vasubu.vv\"", "left": { "type": "id", "id": "MVV_VASUBU" }, "right": { "type": "literal", "value": "\"vasubu.vv\"" } }, { "number": 3, "source": "MVV_VASUB <-> \"vasub.vv\"", "left": { "type": "id", "id": "MVV_VASUB" }, "right": { "type": "literal", "value": "\"vasub.vv\"" } }, { "number": 4, "source": "MVV_VMUL <-> \"vmul.vv\"", "left": { "type": "id", "id": "MVV_VMUL" }, "right": { "type": "literal", "value": "\"vmul.vv\"" } }, { "number": 5, "source": "MVV_VMULH <-> \"vmulh.vv\"", "left": { "type": "id", "id": "MVV_VMULH" }, "right": { "type": "literal", "value": "\"vmulh.vv\"" } }, { "number": 6, "source": "MVV_VMULHU <-> \"vmulhu.vv\"", "left": { "type": "id", "id": "MVV_VMULHU" }, "right": { "type": "literal", "value": "\"vmulhu.vv\"" } }, { "number": 7, "source": "MVV_VMULHSU <-> \"vmulhsu.vv\"", "left": { "type": "id", "id": "MVV_VMULHSU" }, "right": { "type": "literal", "value": "\"vmulhsu.vv\"" } }, { "number": 8, "source": "MVV_VDIVU <-> \"vdivu.vv\"", "left": { "type": "id", "id": "MVV_VDIVU" }, "right": { "type": "literal", "value": "\"vdivu.vv\"" } }, { "number": 9, "source": "MVV_VDIV <-> \"vdiv.vv\"", "left": { "type": "id", "id": "MVV_VDIV" }, "right": { "type": "literal", "value": "\"vdiv.vv\"" } }, { "number": 10, "source": "MVV_VREMU <-> \"vremu.vv\"", "left": { "type": "id", "id": "MVV_VREMU" }, "right": { "type": "literal", "value": "\"vremu.vv\"" } }, { "number": 11, "source": "MVV_VREM <-> \"vrem.vv\"", "left": { "type": "id", "id": "MVV_VREM" }, "right": { "type": "literal", "value": "\"vrem.vv\"" } } ] }, "mvxmatype_mnemonic": { "mapping": [ { "number": 0, "source": "MVX_VMACC <-> \"vmacc.vx\"", "left": { "type": "id", "id": "MVX_VMACC" }, "right": { "type": "literal", "value": "\"vmacc.vx\"" } }, { "number": 1, "source": "MVX_VNMSAC <-> \"vnmsac.vx\"", "left": { "type": "id", "id": "MVX_VNMSAC" }, "right": { "type": "literal", "value": "\"vnmsac.vx\"" } }, { "number": 2, "source": "MVX_VMADD <-> \"vmadd.vx\"", "left": { "type": "id", "id": "MVX_VMADD" }, "right": { "type": "literal", "value": "\"vmadd.vx\"" } }, { "number": 3, "source": "MVX_VNMSUB <-> \"vnmsub.vx\"", "left": { "type": "id", "id": "MVX_VNMSUB" }, "right": { "type": "literal", "value": "\"vnmsub.vx\"" } } ] }, "mvxtype_mnemonic": { "mapping": [ { "number": 0, "source": "MVX_VAADDU <-> \"vaaddu.vx\"", "left": { "type": "id", "id": "MVX_VAADDU" }, "right": { "type": "literal", "value": "\"vaaddu.vx\"" } }, { "number": 1, "source": "MVX_VAADD <-> \"vaadd.vx\"", "left": { "type": "id", "id": "MVX_VAADD" }, "right": { "type": "literal", "value": "\"vaadd.vx\"" } }, { "number": 2, "source": "MVX_VASUBU <-> \"vasubu.vx\"", "left": { "type": "id", "id": "MVX_VASUBU" }, "right": { "type": "literal", "value": "\"vasubu.vx\"" } }, { "number": 3, "source": "MVX_VASUB <-> \"vasub.vx\"", "left": { "type": "id", "id": "MVX_VASUB" }, "right": { "type": "literal", "value": "\"vasub.vx\"" } }, { "number": 4, "source": "MVX_VSLIDE1UP <-> \"vslide1up.vx\"", "left": { "type": "id", "id": "MVX_VSLIDE1UP" }, "right": { "type": "literal", "value": "\"vslide1up.vx\"" } }, { "number": 5, "source": "MVX_VSLIDE1DOWN <-> \"vslide1down.vx\"", "left": { "type": "id", "id": "MVX_VSLIDE1DOWN" }, "right": { "type": "literal", "value": "\"vslide1down.vx\"" } }, { "number": 6, "source": "MVX_VMUL <-> \"vmul.vx\"", "left": { "type": "id", "id": "MVX_VMUL" }, "right": { "type": "literal", "value": "\"vmul.vx\"" } }, { "number": 7, "source": "MVX_VMULH <-> \"vmulh.vx\"", "left": { "type": "id", "id": "MVX_VMULH" }, "right": { "type": "literal", "value": "\"vmulh.vx\"" } }, { "number": 8, "source": "MVX_VMULHU <-> \"vmulhu.vx\"", "left": { "type": "id", "id": "MVX_VMULHU" }, "right": { "type": "literal", "value": "\"vmulhu.vx\"" } }, { "number": 9, "source": "MVX_VMULHSU <-> \"vmulhsu.vx\"", "left": { "type": "id", "id": "MVX_VMULHSU" }, "right": { "type": "literal", "value": "\"vmulhsu.vx\"" } }, { "number": 10, "source": "MVX_VDIVU <-> \"vdivu.vx\"", "left": { "type": "id", "id": "MVX_VDIVU" }, "right": { "type": "literal", "value": "\"vdivu.vx\"" } }, { "number": 11, "source": "MVX_VDIV <-> \"vdiv.vx\"", "left": { "type": "id", "id": "MVX_VDIV" }, "right": { "type": "literal", "value": "\"vdiv.vx\"" } }, { "number": 12, "source": "MVX_VREMU <-> \"vremu.vx\"", "left": { "type": "id", "id": "MVX_VREMU" }, "right": { "type": "literal", "value": "\"vremu.vx\"" } }, { "number": 13, "source": "MVX_VREM <-> \"vrem.vx\"", "left": { "type": "id", "id": "MVX_VREM" }, "right": { "type": "literal", "value": "\"vrem.vx\"" } } ] }, "nfields_int": { "mapping": [ { "number": 0, "source": "0b000 <-> 1", "left": { "type": "literal", "value": "0b000" }, "right": { "type": "literal", "value": "1" } }, { "number": 1, "source": "0b001 <-> 2", "left": { "type": "literal", "value": "0b001" }, "right": { "type": "literal", "value": "2" } }, { "number": 2, "source": "0b010 <-> 3", "left": { "type": "literal", "value": "0b010" }, "right": { "type": "literal", "value": "3" } }, { "number": 3, "source": "0b011 <-> 4", "left": { "type": "literal", "value": "0b011" }, "right": { "type": "literal", "value": "4" } }, { "number": 4, "source": "0b100 <-> 5", "left": { "type": "literal", "value": "0b100" }, "right": { "type": "literal", "value": "5" } }, { "number": 5, "source": "0b101 <-> 6", "left": { "type": "literal", "value": "0b101" }, "right": { "type": "literal", "value": "6" } }, { "number": 6, "source": "0b110 <-> 7", "left": { "type": "literal", "value": "0b110" }, "right": { "type": "literal", "value": "7" } }, { "number": 7, "source": "0b111 <-> 8", "left": { "type": "literal", "value": "0b111" }, "right": { "type": "literal", "value": "8" } } ] }, "nfields_string": { "mapping": [ { "number": 0, "source": "0b000 <-> \"\"", "left": { "type": "literal", "value": "0b000" }, "right": { "type": "literal", "value": "\"\"" } }, { "number": 1, "source": "0b001 <-> \"seg2\"", "left": { "type": "literal", "value": "0b001" }, "right": { "type": "literal", "value": "\"seg2\"" } }, { "number": 2, "source": "0b010 <-> \"seg3\"", "left": { "type": "literal", "value": "0b010" }, "right": { "type": "literal", "value": "\"seg3\"" } }, { "number": 3, "source": "0b011 <-> \"seg4\"", "left": { "type": "literal", "value": "0b011" }, "right": { "type": "literal", "value": "\"seg4\"" } }, { "number": 4, "source": "0b100 <-> \"seg5\"", "left": { "type": "literal", "value": "0b100" }, "right": { "type": "literal", "value": "\"seg5\"" } }, { "number": 5, "source": "0b101 <-> \"seg6\"", "left": { "type": "literal", "value": "0b101" }, "right": { "type": "literal", "value": "\"seg6\"" } }, { "number": 6, "source": "0b110 <-> \"seg7\"", "left": { "type": "literal", "value": "0b110" }, "right": { "type": "literal", "value": "\"seg7\"" } }, { "number": 7, "source": "0b111 <-> \"seg8\"", "left": { "type": "literal", "value": "0b111" }, "right": { "type": "literal", "value": "\"seg8\"" } } ] }, "nistype_mnemonic": { "mapping": [ { "number": 0, "source": "NIS_VNSRL <-> \"vnsrl.wi\"", "left": { "type": "id", "id": "NIS_VNSRL" }, "right": { "type": "literal", "value": "\"vnsrl.wi\"" } }, { "number": 1, "source": "NIS_VNSRA <-> \"vnsra.wi\"", "left": { "type": "id", "id": "NIS_VNSRA" }, "right": { "type": "literal", "value": "\"vnsra.wi\"" } } ] }, "nitype_mnemonic": { "mapping": [ { "number": 0, "source": "NI_VNCLIPU <-> \"vnclipu.wi\"", "left": { "type": "id", "id": "NI_VNCLIPU" }, "right": { "type": "literal", "value": "\"vnclipu.wi\"" } }, { "number": 1, "source": "NI_VNCLIP <-> \"vnclip.wi\"", "left": { "type": "id", "id": "NI_VNCLIP" }, "right": { "type": "literal", "value": "\"vnclip.wi\"" } } ] }, "nvstype_mnemonic": { "mapping": [ { "number": 0, "source": "NVS_VNSRL <-> \"vnsrl.wv\"", "left": { "type": "id", "id": "NVS_VNSRL" }, "right": { "type": "literal", "value": "\"vnsrl.wv\"" } }, { "number": 1, "source": "NVS_VNSRA <-> \"vnsra.wv\"", "left": { "type": "id", "id": "NVS_VNSRA" }, "right": { "type": "literal", "value": "\"vnsra.wv\"" } } ] }, "nvtype_mnemonic": { "mapping": [ { "number": 0, "source": "NV_VNCLIPU <-> \"vnclipu.wv\"", "left": { "type": "id", "id": "NV_VNCLIPU" }, "right": { "type": "literal", "value": "\"vnclipu.wv\"" } }, { "number": 1, "source": "NV_VNCLIP <-> \"vnclip.wv\"", "left": { "type": "id", "id": "NV_VNCLIP" }, "right": { "type": "literal", "value": "\"vnclip.wv\"" } } ] }, "nxstype_mnemonic": { "mapping": [ { "number": 0, "source": "NXS_VNSRL <-> \"vnsrl.wx\"", "left": { "type": "id", "id": "NXS_VNSRL" }, "right": { "type": "literal", "value": "\"vnsrl.wx\"" } }, { "number": 1, "source": "NXS_VNSRA <-> \"vnsra.wx\"", "left": { "type": "id", "id": "NXS_VNSRA" }, "right": { "type": "literal", "value": "\"vnsra.wx\"" } } ] }, "nxtype_mnemonic": { "mapping": [ { "number": 0, "source": "NX_VNCLIPU <-> \"vnclipu.wx\"", "left": { "type": "id", "id": "NX_VNCLIPU" }, "right": { "type": "literal", "value": "\"vnclipu.wx\"" } }, { "number": 1, "source": "NX_VNCLIP <-> \"vnclip.wx\"", "left": { "type": "id", "id": "NX_VNCLIP" }, "right": { "type": "literal", "value": "\"vnclip.wx\"" } } ] }, "opst_code": { "mapping": [ { "number": 0, "source": "BIST <-> 0b00", "left": { "type": "id", "id": "BIST" }, "right": { "type": "literal", "value": "0b00" } }, { "number": 1, "source": "WAIT <-> 0b01", "left": { "type": "id", "id": "WAIT" }, "right": { "type": "literal", "value": "0b01" } }, { "number": 2, "source": "ES16 <-> 0b10", "left": { "type": "id", "id": "ES16" }, "right": { "type": "literal", "value": "0b10" } }, { "number": 3, "source": "DEAD <-> 0b11", "left": { "type": "id", "id": "DEAD" }, "right": { "type": "literal", "value": "0b11" } } ] }, "reg_name": { "mapping": [ { "number": 0, "source": "0b00000 <-> \"zero\"", "left": { "type": "literal", "value": "0b00000" }, "right": { "type": "literal", "value": "\"zero\"" } }, { "number": 1, "source": "0b00001 <-> \"ra\"", "left": { "type": "literal", "value": "0b00001" }, "right": { "type": "literal", "value": "\"ra\"" } }, { "number": 2, "source": "0b00010 <-> \"sp\"", "left": { "type": "literal", "value": "0b00010" }, "right": { "type": "literal", "value": "\"sp\"" } }, { "number": 3, "source": "0b00011 <-> \"gp\"", "left": { "type": "literal", "value": "0b00011" }, "right": { "type": "literal", "value": "\"gp\"" } }, { "number": 4, "source": "0b00100 <-> \"tp\"", "left": { "type": "literal", "value": "0b00100" }, "right": { "type": "literal", "value": "\"tp\"" } }, { "number": 5, "source": "0b00101 <-> \"t0\"", "left": { "type": "literal", "value": "0b00101" }, "right": { "type": "literal", "value": "\"t0\"" } }, { "number": 6, "source": "0b00110 <-> \"t1\"", "left": { "type": "literal", "value": "0b00110" }, "right": { "type": "literal", "value": "\"t1\"" } }, { "number": 7, "source": "0b00111 <-> \"t2\"", "left": { "type": "literal", "value": "0b00111" }, "right": { "type": "literal", "value": "\"t2\"" } }, { "number": 8, "source": "0b01000 <-> \"fp\"", "left": { "type": "literal", "value": "0b01000" }, "right": { "type": "literal", "value": "\"fp\"" } }, { "number": 9, "source": "0b01001 <-> \"s1\"", "left": { "type": "literal", "value": "0b01001" }, "right": { "type": "literal", "value": "\"s1\"" } }, { "number": 10, "source": "0b01010 <-> \"a0\"", "left": { "type": "literal", "value": "0b01010" }, "right": { "type": "literal", "value": "\"a0\"" } }, { "number": 11, "source": "0b01011 <-> \"a1\"", "left": { "type": "literal", "value": "0b01011" }, "right": { "type": "literal", "value": "\"a1\"" } }, { "number": 12, "source": "0b01100 <-> \"a2\"", "left": { "type": "literal", "value": "0b01100" }, "right": { "type": "literal", "value": "\"a2\"" } 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"source": "0b11010 <-> \"s10\"", "left": { "type": "literal", "value": "0b11010" }, "right": { "type": "literal", "value": "\"s10\"" } }, { "number": 27, "source": "0b11011 <-> \"s11\"", "left": { "type": "literal", "value": "0b11011" }, "right": { "type": "literal", "value": "\"s11\"" } }, { "number": 28, "source": "0b11100 <-> \"t3\"", "left": { "type": "literal", "value": "0b11100" }, "right": { "type": "literal", "value": "\"t3\"" } }, { "number": 29, "source": "0b11101 <-> \"t4\"", "left": { "type": "literal", "value": "0b11101" }, "right": { "type": "literal", "value": "\"t4\"" } }, { "number": 30, "source": "0b11110 <-> \"t5\"", "left": { "type": "literal", "value": "0b11110" }, "right": { "type": "literal", "value": "\"t5\"" } }, { "number": 31, "source": "0b11111 <-> \"t6\"", "left": { "type": "literal", "value": "0b11111" }, "right": { "type": "literal", "value": "\"t6\"" } } ] }, "rfvvtype_mnemonic": { "mapping": [ { "number": 0, "source": "FVV_VFREDOSUM <-> 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} } ] }, "rivvtype_mnemonic": { "mapping": [ { "number": 0, "source": "IVV_VWREDSUMU <-> \"vwredsumu.vs\"", "left": { "type": "id", "id": "IVV_VWREDSUMU" }, "right": { "type": "literal", "value": "\"vwredsumu.vs\"" } }, { "number": 1, "source": "IVV_VWREDSUM <-> \"vwredsum.vs\"", "left": { "type": "id", "id": "IVV_VWREDSUM" }, "right": { "type": "literal", "value": "\"vwredsum.vs\"" } } ] }, "rmvvtype_mnemonic": { "mapping": [ { "number": 0, "source": "MVV_VREDSUM <-> \"vredsum.vs\"", "left": { "type": "id", "id": "MVV_VREDSUM" }, "right": { "type": "literal", "value": "\"vredsum.vs\"" } }, { "number": 1, "source": "MVV_VREDAND <-> \"vredand.vs\"", "left": { "type": "id", "id": "MVV_VREDAND" }, "right": { "type": "literal", "value": "\"vredand.vs\"" } }, { "number": 2, "source": "MVV_VREDOR <-> \"vredor.vs\"", "left": { "type": "id", "id": "MVV_VREDOR" }, "right": { "type": "literal", "value": "\"vredor.vs\"" } }, { "number": 3, "source": "MVV_VREDXOR <-> \"vredxor.vs\"", "left": { "type": "id", "id": "MVV_VREDXOR" }, "right": { "type": "literal", "value": "\"vredxor.vs\"" } }, { "number": 4, "source": "MVV_VREDMINU <-> \"vredminu.vs\"", "left": { "type": "id", "id": "MVV_VREDMINU" }, "right": { "type": "literal", "value": "\"vredminu.vs\"" } }, { "number": 5, "source": "MVV_VREDMIN <-> \"vredmin.vs\"", "left": { "type": "id", "id": "MVV_VREDMIN" }, "right": { "type": "literal", "value": "\"vredmin.vs\"" } }, { "number": 6, "source": "MVV_VREDMAXU <-> \"vredmaxu.vs\"", "left": { "type": "id", "id": "MVV_VREDMAXU" }, "right": { "type": "literal", "value": "\"vredmaxu.vs\"" } }, { "number": 7, "source": "MVV_VREDMAX <-> \"vredmax.vs\"", "left": { "type": "id", "id": "MVV_VREDMAX" }, "right": { "type": "literal", "value": "\"vredmax.vs\"" } } ] }, "rtype_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_ADD <-> \"add\"", "left": { "type": "id", "id": "RISCV_ADD" }, "right": { "type": "literal", "value": "\"add\"" } }, { "number": 1, "source": "RISCV_SLT <-> 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}, { "number": 8, "source": "RISCV_SUB <-> \"sub\"", "left": { "type": "id", "id": "RISCV_SUB" }, "right": { "type": "literal", "value": "\"sub\"" } }, { "number": 9, "source": "RISCV_SRA <-> \"sra\"", "left": { "type": "id", "id": "RISCV_SRA" }, "right": { "type": "literal", "value": "\"sra\"" } } ] }, "rtypew_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_ADDW <-> \"addw\"", "left": { "type": "id", "id": "RISCV_ADDW" }, "right": { "type": "literal", "value": "\"addw\"" } }, { "number": 1, "source": "RISCV_SUBW <-> \"subw\"", "left": { "type": "id", "id": "RISCV_SUBW" }, "right": { "type": "literal", "value": "\"subw\"" } }, { "number": 2, "source": "RISCV_SLLW <-> \"sllw\"", "left": { "type": "id", "id": "RISCV_SLLW" }, "right": { "type": "literal", "value": "\"sllw\"" } }, { "number": 3, "source": "RISCV_SRLW <-> \"srlw\"", "left": { "type": "id", "id": "RISCV_SRLW" }, "right": { "type": "literal", "value": "\"srlw\"" } }, { "number": 4, "source": "RISCV_SRAW <-> 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}, { "number": 3, "source": "\"e64\" <-> 0b011", "left": { "type": "literal", "value": "\"e64\"" }, "right": { "type": "literal", "value": "0b011" } } ] }, "shiftiop_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_SLLI <-> \"slli\"", "left": { "type": "id", "id": "RISCV_SLLI" }, "right": { "type": "literal", "value": "\"slli\"" } }, { "number": 1, "source": "RISCV_SRLI <-> \"srli\"", "left": { "type": "id", "id": "RISCV_SRLI" }, "right": { "type": "literal", "value": "\"srli\"" } }, { "number": 2, "source": "RISCV_SRAI <-> \"srai\"", "left": { "type": "id", "id": "RISCV_SRAI" }, "right": { "type": "literal", "value": "\"srai\"" } } ] }, "shiftiwop_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_SLLIW <-> \"slliw\"", "left": { "type": "id", "id": "RISCV_SLLIW" }, "right": { "type": "literal", "value": "\"slliw\"" } }, { "number": 1, "source": "RISCV_SRLIW <-> \"srliw\"", "left": { "type": "id", "id": "RISCV_SRLIW" }, "right": { "type": "literal", "value": "\"srliw\"" } }, { "number": 2, "source": "RISCV_SRAIW <-> \"sraiw\"", "left": { "type": "id", "id": "RISCV_SRAIW" }, "right": { "type": "literal", "value": "\"sraiw\"" } } ] }, "simm_string": { "mapping": [ { "number": 0, "source": "0b00000 <-> \"1\"", "left": { "type": "literal", "value": "0b00000" }, "right": { "type": "literal", "value": "\"1\"" } }, { "number": 1, "source": "0b00001 <-> \"2\"", "left": { "type": "literal", "value": "0b00001" }, "right": { "type": "literal", "value": "\"2\"" } }, { "number": 2, "source": "0b00011 <-> \"4\"", "left": { "type": "literal", "value": "0b00011" }, "right": { "type": "literal", "value": "\"4\"" } }, { "number": 3, "source": "0b00111 <-> \"8\"", "left": { "type": "literal", "value": "0b00111" }, "right": { "type": "literal", "value": "\"8\"" } } ] }, "size_bits": { "mapping": [ { "number": 0, "source": "BYTE <-> 0b00", "left": { "type": "id", "id": "BYTE" }, "right": { "type": "literal", "value": "0b00" } }, { "number": 1, "source": "HALF <-> 0b01", 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"source": "RISCV_LUI <-> \"lui\"", "left": { "type": "id", "id": "RISCV_LUI" }, "right": { "type": "literal", "value": "\"lui\"" } }, { "number": 1, "source": "RISCV_AUIPC <-> \"auipc\"", "left": { "type": "id", "id": "RISCV_AUIPC" }, "right": { "type": "literal", "value": "\"auipc\"" } } ] }, "vext2_vs1": { "mapping": [ { "number": 0, "source": "VEXT2_ZVF2 <-> 0b00110", "left": { "type": "id", "id": "VEXT2_ZVF2" }, "right": { "type": "literal", "value": "0b00110" } }, { "number": 1, "source": "VEXT2_SVF2 <-> 0b00111", "left": { "type": "id", "id": "VEXT2_SVF2" }, "right": { "type": "literal", "value": "0b00111" } } ] }, "vext2type_mnemonic": { "mapping": [ { "number": 0, "source": "VEXT2_ZVF2 <-> \"vzext.vf2\"", "left": { "type": "id", "id": "VEXT2_ZVF2" }, "right": { "type": "literal", "value": "\"vzext.vf2\"" } }, { "number": 1, "source": "VEXT2_SVF2 <-> \"vsext.vf2\"", "left": { "type": "id", "id": "VEXT2_SVF2" }, "right": { "type": "literal", "value": "\"vsext.vf2\"" } } ] }, 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"literal", "value": "0b00011" } } ] }, "vext8type_mnemonic": { "mapping": [ { "number": 0, "source": "VEXT8_ZVF8 <-> \"vzext.vf8\"", "left": { "type": "id", "id": "VEXT8_ZVF8" }, "right": { "type": "literal", "value": "\"vzext.vf8\"" } }, { "number": 1, "source": "VEXT8_SVF8 <-> \"vsext.vf8\"", "left": { "type": "id", "id": "VEXT8_SVF8" }, "right": { "type": "literal", "value": "\"vsext.vf8\"" } } ] }, "vfnunary0_mnemonic": { "mapping": [ { "number": 0, "source": "FNV_CVT_XU_F <-> \"vfncvt.xu.f.w\"", "left": { "type": "id", "id": "FNV_CVT_XU_F" }, "right": { "type": "literal", "value": "\"vfncvt.xu.f.w\"" } }, { "number": 1, "source": "FNV_CVT_X_F <-> \"vfncvt.x.f.w\"", "left": { "type": "id", "id": "FNV_CVT_X_F" }, "right": { "type": "literal", "value": "\"vfncvt.x.f.w\"" } }, { "number": 2, "source": "FNV_CVT_F_XU <-> \"vfncvt.f.xu.w\"", "left": { "type": "id", "id": "FNV_CVT_F_XU" }, "right": { "type": "literal", "value": "\"vfncvt.f.xu.w\"" } }, { "number": 3, "source": "FNV_CVT_F_X <-> \"vfncvt.f.x.w\"", "left": { "type": "id", "id": "FNV_CVT_F_X" }, "right": { "type": "literal", "value": "\"vfncvt.f.x.w\"" } }, { "number": 4, "source": "FNV_CVT_F_F <-> \"vfncvt.f.f.w\"", "left": { "type": "id", "id": "FNV_CVT_F_F" }, "right": { "type": "literal", "value": "\"vfncvt.f.f.w\"" } }, { "number": 5, "source": "FNV_CVT_ROD_F_F <-> \"vfncvt.rod.f.f.w\"", "left": { "type": "id", "id": "FNV_CVT_ROD_F_F" }, "right": { "type": "literal", "value": "\"vfncvt.rod.f.f.w\"" } }, { "number": 6, "source": "FNV_CVT_RTZ_XU_F <-> \"vfncvt.rtz.xu.f.w\"", "left": { "type": "id", "id": "FNV_CVT_RTZ_XU_F" }, "right": { "type": "literal", "value": "\"vfncvt.rtz.xu.f.w\"" } }, { "number": 7, "source": "FNV_CVT_RTZ_X_F <-> \"vfncvt.rtz.x.f.w\"", "left": { "type": "id", "id": "FNV_CVT_RTZ_X_F" }, "right": { "type": "literal", "value": "\"vfncvt.rtz.x.f.w\"" } } ] }, "vfunary0_mnemonic": { "mapping": [ { "number": 0, "source": "FV_CVT_XU_F <-> \"vfcvt.xu.f.v\"", "left": { "type": "id", "id": "FV_CVT_XU_F" }, "right": { "type": "literal", "value": "\"vfcvt.xu.f.v\"" } }, { "number": 1, "source": "FV_CVT_X_F <-> \"vfcvt.x.f.v\"", "left": { "type": "id", "id": "FV_CVT_X_F" }, "right": { "type": "literal", "value": "\"vfcvt.x.f.v\"" } }, { "number": 2, "source": "FV_CVT_F_XU <-> \"vfcvt.f.xu.v\"", "left": { "type": "id", "id": "FV_CVT_F_XU" }, "right": { "type": "literal", "value": "\"vfcvt.f.xu.v\"" } }, { "number": 3, "source": "FV_CVT_F_X <-> \"vfcvt.f.x.v\"", "left": { "type": "id", "id": "FV_CVT_F_X" }, "right": { "type": "literal", "value": "\"vfcvt.f.x.v\"" } }, { "number": 4, "source": "FV_CVT_RTZ_XU_F <-> \"vfcvt.rtz.xu.f.v\"", "left": { "type": "id", "id": "FV_CVT_RTZ_XU_F" }, "right": { "type": "literal", "value": "\"vfcvt.rtz.xu.f.v\"" } }, { "number": 5, "source": "FV_CVT_RTZ_X_F <-> \"vfcvt.rtz.x.f.v\"", "left": { "type": "id", "id": "FV_CVT_RTZ_X_F" }, "right": { "type": "literal", "value": "\"vfcvt.rtz.x.f.v\"" } } ] }, "vfunary1_mnemonic": { "mapping": [ { "number": 0, "source": "FVV_VSQRT <-> \"vfsqrt.v\"", "left": { "type": "id", "id": "FVV_VSQRT" }, "right": { "type": "literal", "value": "\"vfsqrt.v\"" } }, { "number": 1, "source": "FVV_VRSQRT7 <-> \"vfrsqrt7.v\"", "left": { "type": "id", "id": "FVV_VRSQRT7" }, "right": { "type": "literal", "value": "\"vfrsqrt7.v\"" } }, { "number": 2, "source": "FVV_VREC7 <-> \"vfrec7.v\"", "left": { "type": "id", "id": "FVV_VREC7" }, "right": { "type": "literal", "value": "\"vfrec7.v\"" } }, { "number": 3, "source": "FVV_VCLASS <-> \"vfclass.v\"", "left": { "type": "id", "id": "FVV_VCLASS" }, "right": { "type": "literal", "value": "\"vfclass.v\"" } } ] }, "vfwunary0_mnemonic": { "mapping": [ { "number": 0, "source": "FWV_CVT_XU_F <-> \"vfwcvt.xu.f.v\"", "left": { "type": "id", "id": "FWV_CVT_XU_F" }, "right": { "type": "literal", "value": "\"vfwcvt.xu.f.v\"" } }, { "number": 1, "source": "FWV_CVT_X_F <-> \"vfwcvt.x.f.v\"", "left": { "type": "id", "id": "FWV_CVT_X_F" }, "right": { "type": "literal", "value": "\"vfwcvt.x.f.v\"" } }, { "number": 2, "source": "FWV_CVT_F_XU <-> \"vfwcvt.f.xu.v\"", "left": { "type": "id", "id": "FWV_CVT_F_XU" }, "right": { "type": "literal", "value": "\"vfwcvt.f.xu.v\"" } }, { "number": 3, "source": "FWV_CVT_F_X <-> \"vfwcvt.f.x.v\"", "left": { "type": "id", "id": "FWV_CVT_F_X" }, "right": { "type": "literal", "value": "\"vfwcvt.f.x.v\"" } }, { "number": 4, "source": "FWV_CVT_F_F <-> \"vfwcvt.f.f.v\"", "left": { "type": "id", "id": "FWV_CVT_F_F" }, "right": { "type": "literal", "value": "\"vfwcvt.f.f.v\"" } }, { "number": 5, "source": "FWV_CVT_RTZ_XU_F <-> \"vfwcvt.rtz.xu.f.v\"", "left": { "type": "id", "id": "FWV_CVT_RTZ_XU_F" }, "right": { "type": "literal", "value": "\"vfwcvt.rtz.xu.f.v\"" } }, { "number": 6, "source": "FWV_CVT_RTZ_X_F <-> \"vfwcvt.rtz.x.f.v\"", "left": { "type": "id", "id": "FWV_CVT_RTZ_X_F" }, "right": { "type": "literal", "value": "\"vfwcvt.rtz.x.f.v\"" } } ] }, "vicmptype_mnemonic": { "mapping": [ { "number": 0, "source": "VICMP_VMSEQ <-> \"vmseq.vi\"", "left": { "type": "id", "id": "VICMP_VMSEQ" }, "right": { "type": "literal", "value": "\"vmseq.vi\"" } }, { "number": 1, "source": "VICMP_VMSNE <-> \"vmsne.vi\"", "left": { "type": "id", "id": "VICMP_VMSNE" }, "right": { "type": "literal", "value": "\"vmsne.vi\"" } }, { "number": 2, "source": "VICMP_VMSLEU <-> \"vmsleu.vi\"", "left": { "type": "id", "id": "VICMP_VMSLEU" }, "right": { "type": "literal", "value": "\"vmsleu.vi\"" } }, { "number": 3, "source": "VICMP_VMSLE <-> \"vmsle.vi\"", "left": { "type": "id", "id": "VICMP_VMSLE" }, "right": { "type": "literal", "value": "\"vmsle.vi\"" } }, { "number": 4, "source": "VICMP_VMSGTU <-> \"vmsgtu.vi\"", "left": { "type": "id", "id": "VICMP_VMSGTU" }, "right": { "type": "literal", "value": "\"vmsgtu.vi\"" } }, { "number": 5, "source": "VICMP_VMSGT <-> \"vmsgt.vi\"", "left": { "type": "id", "id": "VICMP_VMSGT" }, "right": { "type": "literal", "value": "\"vmsgt.vi\"" } } ] }, "vimctype_mnemonic": { "mapping": [ { "number": 0, "source": "VIMC_VMADC <-> \"vmadc.vi\"", "left": { "type": "id", "id": "VIMC_VMADC" }, "right": { "type": "literal", "value": "\"vmadc.vi\"" } } ] }, "vimstype_mnemonic": { "mapping": [ { "number": 0, "source": "VIMS_VADC <-> \"vadc.vim\"", "left": { "type": "id", "id": "VIMS_VADC" }, "right": { "type": "literal", "value": "\"vadc.vim\"" } } ] }, "vimtype_mnemonic": { "mapping": [ { "number": 0, "source": "VIM_VMADC <-> \"vmadc.vim\"", "left": { "type": "id", "id": "VIM_VMADC" }, "right": { "type": "literal", "value": "\"vmadc.vim\"" } } ] }, "visg_mnemonic": { "mapping": [ { "number": 0, "source": "VI_VSLIDEUP <-> \"vslideup.vi\"", "left": { "type": "id", "id": "VI_VSLIDEUP" }, "right": { "type": "literal", "value": "\"vslideup.vi\"" } }, { "number": 1, "source": "VI_VSLIDEDOWN <-> \"vslidedown.vi\"", "left": { "type": "id", "id": "VI_VSLIDEDOWN" }, "right": { "type": "literal", "value": "\"vslidedown.vi\"" } }, { "number": 2, "source": "VI_VRGATHER <-> \"vrgather.vi\"", "left": { "type": "id", "id": "VI_VRGATHER" }, "right": { "type": "literal", "value": "\"vrgather.vi\"" } } ] }, "vitype_mnemonic": { "mapping": [ { "number": 0, "source": "VI_VADD <-> \"vadd.vi\"", "left": { "type": "id", "id": "VI_VADD" }, "right": { "type": "literal", "value": "\"vadd.vi\"" } }, { "number": 1, "source": "VI_VRSUB <-> \"vrsub.vi\"", "left": { "type": "id", "id": "VI_VRSUB" }, "right": { "type": "literal", "value": "\"vrsub.vi\"" } }, { "number": 2, "source": "VI_VAND <-> \"vand.vi\"", "left": { "type": "id", "id": "VI_VAND" }, "right": { "type": "literal", "value": "\"vand.vi\"" } }, { "number": 3, "source": "VI_VOR <-> \"vor.vi\"", "left": { "type": "id", "id": "VI_VOR" }, "right": { "type": "literal", "value": "\"vor.vi\"" } }, { "number": 4, "source": "VI_VXOR <-> \"vxor.vi\"", "left": { "type": "id", "id": "VI_VXOR" }, "right": { "type": "literal", "value": "\"vxor.vi\"" } }, { "number": 5, "source": "VI_VSADDU <-> \"vsaddu.vi\"", "left": { "type": "id", "id": "VI_VSADDU" }, "right": { "type": "literal", "value": "\"vsaddu.vi\"" } }, { "number": 6, "source": "VI_VSADD <-> \"vsadd.vi\"", "left": { "type": "id", "id": "VI_VSADD" }, "right": { "type": "literal", "value": "\"vsadd.vi\"" } }, { "number": 7, "source": "VI_VSLL <-> \"vsll.vi\"", "left": { "type": "id", "id": "VI_VSLL" }, "right": { "type": "literal", "value": "\"vsll.vi\"" } }, { "number": 8, "source": "VI_VSRL <-> \"vsrl.vi\"", "left": { "type": "id", "id": "VI_VSRL" }, "right": { "type": "literal", "value": "\"vsrl.vi\"" } }, { "number": 9, "source": "VI_VSRA <-> \"vsra.vi\"", "left": { "type": "id", "id": "VI_VSRA" }, "right": { "type": "literal", "value": "\"vsra.vi\"" } }, { "number": 10, "source": "VI_VSSRL <-> \"vssrl.vi\"", "left": { "type": "id", "id": "VI_VSSRL" }, "right": { "type": "literal", "value": "\"vssrl.vi\"" } }, { "number": 11, "source": "VI_VSSRA <-> \"vssra.vi\"", "left": { "type": "id", "id": "VI_VSSRA" }, "right": { "type": "literal", "value": "\"vssra.vi\"" } } ] }, "vlewidth_bitsnumberstr": { "mapping": [ { "number": 0, "source": "VLE8 <-> \"8\"", "left": { "type": "id", "id": "VLE8" }, "right": { "type": "literal", "value": "\"8\"" } }, { "number": 1, "source": "VLE16 <-> \"16\"", "left": { "type": "id", "id": "VLE16" }, "right": { "type": "literal", "value": "\"16\"" } }, { "number": 2, "source": "VLE32 <-> \"32\"", "left": { "type": "id", "id": "VLE32" }, "right": { "type": "literal", "value": "\"32\"" } }, { "number": 3, "source": "VLE64 <-> \"64\"", "left": { "type": "id", "id": "VLE64" }, "right": { "type": "literal", "value": "\"64\"" } } ] }, "vlewidth_bytesnumber": { "mapping": [ { "number": 0, "source": "VLE8 <-> 1", "left": { "type": "id", "id": "VLE8" }, "right": { "type": "literal", "value": "1" } }, { "number": 1, "source": "VLE16 <-> 2", "left": { "type": "id", "id": "VLE16" }, "right": { "type": "literal", "value": "2" } }, { "number": 2, "source": "VLE32 <-> 4", "left": { "type": "id", "id": "VLE32" }, "right": { "type": "literal", "value": "4" } }, { "number": 3, "source": "VLE64 <-> 8", "left": { "type": "id", "id": "VLE64" }, "right": { "type": "literal", "value": "8" } } ] }, "vlewidth_pow": { "mapping": [ { "number": 0, "source": "VLE8 <-> 3", "left": { "type": "id", "id": "VLE8" }, "right": { "type": "literal", "value": "3" } }, { "number": 1, "source": "VLE16 <-> 4", "left": { "type": "id", "id": "VLE16" }, "right": { "type": "literal", "value": "4" } }, { "number": 2, "source": "VLE32 <-> 5", "left": { "type": "id", "id": "VLE32" }, "right": { "type": "literal", "value": "5" } }, { "number": 3, "source": "VLE64 <-> 6", "left": { "type": "id", "id": "VLE64" }, "right": { "type": "literal", "value": "6" } } ] }, "vmtype_mnemonic": { "mapping": [ { "number": 0, "source": "VLM <-> \"vlm.v\"", "left": { "type": "id", "id": "VLM" }, "right": { "type": "literal", "value": "\"vlm.v\"" } }, { "number": 1, "source": "VSM <-> \"vsm.v\"", "left": { "type": "id", "id": "VSM" }, "right": { "type": "literal", "value": "\"vsm.v\"" } } ] }, "vreg_name": { "mapping": [ { "number": 0, "source": "0b00000 <-> \"v0\"", "left": { "type": "literal", "value": "0b00000" }, "right": { "type": "literal", "value": "\"v0\"" } }, { "number": 1, "source": "0b00001 <-> \"v1\"", "left": { "type": "literal", "value": "0b00001" }, "right": { "type": "literal", "value": "\"v1\"" } }, { "number": 2, "source": "0b00010 <-> \"v2\"", "left": { "type": "literal", "value": "0b00010" }, "right": { "type": "literal", "value": "\"v2\"" } }, { "number": 3, "source": "0b00011 <-> \"v3\"", "left": { "type": "literal", "value": "0b00011" }, "right": { "type": "literal", "value": "\"v3\"" } }, { "number": 4, "source": "0b00100 <-> \"v4\"", "left": { "type": "literal", "value": "0b00100" }, "right": { "type": "literal", "value": "\"v4\"" } }, { "number": 5, "source": "0b00101 <-> \"v5\"", "left": { "type": "literal", "value": "0b00101" }, "right": { "type": "literal", "value": "\"v5\"" } }, { "number": 6, "source": "0b00110 <-> \"v6\"", "left": { "type": "literal", "value": "0b00110" }, "right": { "type": "literal", "value": "\"v6\"" } }, { "number": 7, "source": "0b00111 <-> \"v7\"", "left": { "type": "literal", "value": "0b00111" }, "right": { "type": "literal", "value": "\"v7\"" } }, { "number": 8, "source": "0b01000 <-> \"v8\"", "left": { "type": "literal", "value": "0b01000" }, "right": { "type": "literal", "value": "\"v8\"" } }, { "number": 9, "source": "0b01001 <-> \"v9\"", "left": { "type": "literal", "value": "0b01001" }, "right": { "type": "literal", "value": "\"v9\"" } }, { "number": 10, "source": "0b01010 <-> \"v10\"", "left": { "type": "literal", "value": "0b01010" }, "right": { "type": "literal", "value": "\"v10\"" } }, { "number": 11, "source": "0b01011 <-> \"v11\"", "left": { "type": "literal", "value": "0b01011" }, "right": { "type": "literal", "value": "\"v11\"" } }, { "number": 12, "source": "0b01100 <-> \"v12\"", "left": { "type": "literal", "value": "0b01100" }, "right": { "type": "literal", "value": "\"v12\"" } }, { "number": 13, "source": "0b01101 <-> \"v13\"", "left": { "type": "literal", "value": "0b01101" }, "right": { "type": "literal", "value": "\"v13\"" } }, { "number": 14, "source": "0b01110 <-> \"v14\"", "left": { "type": "literal", "value": "0b01110" }, "right": { "type": "literal", "value": "\"v14\"" } }, { "number": 15, "source": "0b01111 <-> \"v15\"", "left": { "type": "literal", "value": "0b01111" }, "right": { "type": "literal", "value": "\"v15\"" } }, { "number": 16, "source": "0b10000 <-> \"v16\"", "left": { "type": "literal", "value": "0b10000" }, "right": { "type": "literal", "value": "\"v16\"" } }, { "number": 17, "source": "0b10001 <-> \"v17\"", "left": { "type": "literal", "value": "0b10001" }, "right": { "type": "literal", "value": "\"v17\"" } }, { "number": 18, "source": "0b10010 <-> \"v18\"", "left": { "type": "literal", "value": "0b10010" }, "right": { "type": "literal", "value": "\"v18\"" } }, { "number": 19, "source": "0b10011 <-> \"v19\"", "left": { "type": "literal", "value": "0b10011" }, "right": { "type": "literal", "value": "\"v19\"" } }, { "number": 20, "source": "0b10100 <-> \"v20\"", "left": { "type": "literal", "value": "0b10100" }, "right": { "type": "literal", "value": "\"v20\"" } }, { "number": 21, "source": "0b10101 <-> \"v21\"", "left": { "type": "literal", "value": "0b10101" }, "right": { "type": "literal", "value": "\"v21\"" } }, { "number": 22, "source": "0b10110 <-> \"v22\"", "left": { "type": "literal", "value": "0b10110" }, "right": { "type": "literal", "value": "\"v22\"" } }, { "number": 23, "source": "0b10111 <-> \"v23\"", "left": { "type": "literal", "value": "0b10111" }, "right": { "type": "literal", "value": "\"v23\"" } }, { "number": 24, "source": "0b11000 <-> \"v24\"", "left": { "type": "literal", "value": "0b11000" }, "right": { "type": "literal", "value": "\"v24\"" } }, { "number": 25, "source": "0b11001 <-> \"v25\"", "left": { "type": "literal", "value": "0b11001" }, "right": { "type": "literal", "value": "\"v25\"" } }, { "number": 26, "source": "0b11010 <-> \"v26\"", "left": { "type": "literal", "value": "0b11010" }, "right": { "type": "literal", "value": "\"v26\"" } }, { "number": 27, "source": "0b11011 <-> \"v27\"", "left": { "type": "literal", "value": "0b11011" }, "right": { "type": "literal", "value": "\"v27\"" } }, { "number": 28, "source": "0b11100 <-> \"v28\"", "left": { "type": "literal", "value": "0b11100" }, "right": { "type": "literal", "value": "\"v28\"" } }, { "number": 29, "source": "0b11101 <-> \"v29\"", "left": { "type": "literal", "value": "0b11101" }, "right": { "type": "literal", "value": "\"v29\"" } }, { "number": 30, "source": "0b11110 <-> \"v30\"", "left": { "type": "literal", "value": "0b11110" }, "right": { "type": "literal", "value": "\"v30\"" } }, { "number": 31, "source": "0b11111 <-> \"v31\"", "left": { "type": "literal", "value": "0b11111" }, "right": { "type": "literal", "value": "\"v31\"" } } ] }, "vsettype_mnemonic": { "mapping": [ { "number": 0, "source": "VSETVLI <-> \"vsetvli\"", "left": { "type": "id", "id": "VSETVLI" }, "right": { "type": "literal", "value": "\"vsetvli\"" } }, { "number": 1, "source": "VSETVL <-> \"vsetvli\"", "left": { "type": "id", "id": "VSETVL" }, "right": { "type": "literal", "value": "\"vsetvli\"" } } ] }, "vvcmptype_mnemonic": { "mapping": [ { "number": 0, "source": "VVCMP_VMSEQ <-> \"vmseq.vv\"", "left": { "type": "id", "id": "VVCMP_VMSEQ" }, "right": { "type": "literal", "value": "\"vmseq.vv\"" } }, { "number": 1, "source": "VVCMP_VMSNE <-> \"vmsne.vv\"", "left": { "type": "id", "id": "VVCMP_VMSNE" }, "right": { "type": "literal", "value": "\"vmsne.vv\"" } }, { "number": 2, "source": "VVCMP_VMSLTU <-> \"vmsltu.vv\"", "left": { "type": "id", "id": "VVCMP_VMSLTU" }, "right": { "type": "literal", "value": "\"vmsltu.vv\"" } }, { "number": 3, "source": "VVCMP_VMSLT <-> \"vmslt.vv\"", "left": { "type": "id", "id": "VVCMP_VMSLT" }, "right": { "type": "literal", "value": "\"vmslt.vv\"" } }, { "number": 4, "source": "VVCMP_VMSLEU <-> \"vmsleu.vv\"", "left": { "type": "id", "id": "VVCMP_VMSLEU" }, "right": { "type": "literal", "value": "\"vmsleu.vv\"" } }, { "number": 5, "source": "VVCMP_VMSLE <-> \"vmsle.vv\"", "left": { "type": "id", "id": "VVCMP_VMSLE" }, "right": { "type": "literal", "value": "\"vmsle.vv\"" } } ] }, "vvmctype_mnemonic": { "mapping": [ { "number": 0, "source": "VVMC_VMADC <-> \"vmadc.vv\"", "left": { "type": "id", "id": "VVMC_VMADC" }, "right": { "type": "literal", "value": "\"vmadc.vv\"" } }, { "number": 1, "source": "VVMC_VMSBC <-> \"vmsbc.vv\"", "left": { "type": "id", "id": "VVMC_VMSBC" }, "right": { "type": "literal", "value": "\"vmsbc.vv\"" } } ] }, "vvmstype_mnemonic": { "mapping": [ { "number": 0, "source": "VVMS_VADC <-> \"vadc.vvm\"", "left": { "type": "id", "id": "VVMS_VADC" }, "right": { "type": "literal", "value": "\"vadc.vvm\"" } }, { "number": 1, "source": "VVMS_VSBC <-> \"vsbc.vvm\"", "left": { "type": "id", "id": "VVMS_VSBC" }, "right": { "type": "literal", "value": "\"vsbc.vvm\"" } } ] }, "vvmtype_mnemonic": { "mapping": [ { "number": 0, "source": "VVM_VMADC <-> \"vmadc.vvm\"", "left": { "type": "id", "id": "VVM_VMADC" }, "right": { "type": "literal", "value": "\"vmadc.vvm\"" } }, { "number": 1, "source": "VVM_VMSBC <-> \"vmsbc.vvm\"", "left": { "type": "id", "id": "VVM_VMSBC" }, "right": { "type": "literal", "value": "\"vmsbc.vvm\"" } } ] }, "vvtype_mnemonic": { "mapping": [ { "number": 0, "source": "VV_VADD <-> \"vadd.vv\"", "left": { "type": "id", "id": "VV_VADD" }, "right": { "type": "literal", "value": "\"vadd.vv\"" } }, { "number": 1, "source": "VV_VSUB <-> \"vsub.vv\"", "left": { "type": "id", "id": "VV_VSUB" }, "right": { "type": "literal", "value": "\"vsub.vv\"" } }, { "number": 2, "source": "VV_VAND <-> \"vand.vv\"", "left": { "type": "id", "id": "VV_VAND" }, "right": { "type": "literal", "value": "\"vand.vv\"" } }, { "number": 3, "source": "VV_VOR <-> \"vor.vv\"", "left": { "type": "id", "id": "VV_VOR" }, "right": { "type": "literal", "value": "\"vor.vv\"" } }, { "number": 4, "source": "VV_VXOR <-> \"vxor.vv\"", "left": { "type": "id", "id": "VV_VXOR" }, "right": { "type": "literal", "value": "\"vxor.vv\"" } }, { "number": 5, "source": "VV_VRGATHER <-> \"vrgather.vv\"", "left": { "type": "id", "id": "VV_VRGATHER" }, "right": { "type": "literal", "value": "\"vrgather.vv\"" } }, { "number": 6, "source": "VV_VRGATHEREI16 <-> \"vrgatherei16.vv\"", "left": { "type": "id", "id": "VV_VRGATHEREI16" }, "right": { "type": "literal", "value": "\"vrgatherei16.vv\"" } }, { "number": 7, "source": "VV_VSADDU <-> \"vsaddu.vv\"", "left": { "type": "id", "id": "VV_VSADDU" }, "right": { "type": "literal", "value": "\"vsaddu.vv\"" } }, { "number": 8, "source": "VV_VSADD <-> \"vsadd.vv\"", "left": { "type": "id", "id": "VV_VSADD" }, "right": { "type": "literal", "value": "\"vsadd.vv\"" } }, { "number": 9, "source": "VV_VSSUBU <-> \"vssubu.vv\"", "left": { "type": "id", "id": "VV_VSSUBU" }, "right": { "type": "literal", "value": "\"vssubu.vv\"" } }, { "number": 10, "source": "VV_VSSUB <-> \"vssub.vv\"", "left": { "type": "id", "id": "VV_VSSUB" }, "right": { "type": "literal", "value": "\"vssub.vv\"" } }, { "number": 11, "source": "VV_VSLL <-> \"vsll.vv\"", "left": { "type": "id", "id": "VV_VSLL" }, "right": { "type": "literal", "value": "\"vsll.vv\"" } }, { "number": 12, "source": "VV_VSMUL <-> \"vsmul.vv\"", "left": { "type": "id", "id": "VV_VSMUL" }, "right": { "type": "literal", "value": "\"vsmul.vv\"" } }, { "number": 13, "source": "VV_VSRL <-> \"vsrl.vv\"", "left": { "type": "id", "id": "VV_VSRL" }, "right": { "type": "literal", "value": "\"vsrl.vv\"" } }, { "number": 14, "source": "VV_VSRA <-> \"vsra.vv\"", "left": { "type": "id", "id": "VV_VSRA" }, "right": { "type": "literal", "value": "\"vsra.vv\"" } }, { "number": 15, "source": "VV_VSSRL <-> \"vssrl.vv\"", "left": { "type": "id", "id": "VV_VSSRL" }, "right": { "type": "literal", "value": "\"vssrl.vv\"" } }, { "number": 16, "source": "VV_VSSRA <-> \"vssra.vv\"", "left": { "type": "id", "id": "VV_VSSRA" }, "right": { "type": "literal", "value": "\"vssra.vv\"" } }, { "number": 17, "source": "VV_VMINU <-> \"vminu.vv\"", "left": { "type": "id", "id": "VV_VMINU" }, "right": { "type": "literal", "value": "\"vminu.vv\"" } }, { "number": 18, "source": "VV_VMIN <-> \"vmin.vv\"", "left": { "type": "id", "id": "VV_VMIN" }, "right": { "type": "literal", "value": "\"vmin.vv\"" } }, { "number": 19, "source": "VV_VMAXU <-> \"vmaxu.vv\"", "left": { "type": "id", "id": "VV_VMAXU" }, "right": { "type": "literal", "value": "\"vmaxu.vv\"" } }, { "number": 20, "source": "VV_VMAX <-> \"vmax.vv\"", "left": { "type": "id", "id": "VV_VMAX" }, "right": { "type": "literal", "value": "\"vmax.vv\"" } } ] }, "vxcmptype_mnemonic": { "mapping": [ { "number": 0, "source": "VXCMP_VMSEQ <-> \"vmseq.vx\"", "left": { "type": "id", "id": "VXCMP_VMSEQ" }, "right": { "type": "literal", "value": "\"vmseq.vx\"" } }, { "number": 1, "source": "VXCMP_VMSNE <-> \"vmsne.vx\"", "left": { "type": "id", "id": "VXCMP_VMSNE" }, "right": { "type": "literal", "value": "\"vmsne.vx\"" } }, { "number": 2, "source": "VXCMP_VMSLTU <-> \"vmsltu.vx\"", "left": { "type": "id", "id": "VXCMP_VMSLTU" }, "right": { "type": "literal", "value": "\"vmsltu.vx\"" } }, { "number": 3, "source": "VXCMP_VMSLT <-> \"vmslt.vx\"", "left": { "type": "id", "id": "VXCMP_VMSLT" }, "right": { "type": "literal", "value": "\"vmslt.vx\"" } }, { "number": 4, "source": "VXCMP_VMSLEU <-> \"vmsleu.vx\"", "left": { "type": "id", "id": "VXCMP_VMSLEU" }, "right": { "type": "literal", "value": "\"vmsleu.vx\"" } }, { "number": 5, "source": "VXCMP_VMSLE <-> \"vmsle.vx\"", "left": { "type": "id", "id": "VXCMP_VMSLE" }, "right": { "type": "literal", "value": "\"vmsle.vx\"" } }, { "number": 6, "source": "VXCMP_VMSGTU <-> \"vmsgtu.vx\"", "left": { "type": "id", "id": "VXCMP_VMSGTU" }, "right": { "type": "literal", "value": "\"vmsgtu.vx\"" } }, { "number": 7, "source": "VXCMP_VMSGT <-> \"vmsgt.vx\"", "left": { "type": "id", "id": "VXCMP_VMSGT" }, "right": { "type": "literal", "value": "\"vmsgt.vx\"" } } ] }, "vxmctype_mnemonic": { "mapping": [ { "number": 0, "source": "VXMC_VMADC <-> \"vmadc.vx\"", "left": { "type": "id", "id": "VXMC_VMADC" }, "right": { "type": "literal", "value": "\"vmadc.vx\"" } }, { "number": 1, "source": "VXMC_VMSBC <-> \"vmsbc.vx\"", "left": { "type": "id", "id": "VXMC_VMSBC" }, "right": { "type": "literal", "value": "\"vmsbc.vx\"" } } ] }, "vxmstype_mnemonic": { "mapping": [ { "number": 0, "source": "VXMS_VADC <-> \"vadc.vxm\"", "left": { "type": "id", "id": "VXMS_VADC" }, "right": { "type": "literal", "value": "\"vadc.vxm\"" } }, { "number": 1, "source": "VXMS_VSBC <-> \"vsbc.vxm\"", "left": { "type": "id", "id": "VXMS_VSBC" }, "right": { "type": "literal", "value": "\"vsbc.vxm\"" } } ] }, "vxmtype_mnemonic": { "mapping": [ { "number": 0, "source": "VXM_VMADC <-> \"vmadc.vxm\"", "left": { "type": "id", "id": "VXM_VMADC" }, "right": { "type": "literal", "value": "\"vmadc.vxm\"" } }, { "number": 1, "source": "VXM_VMSBC <-> \"vmsbc.vxm\"", "left": { "type": "id", "id": "VXM_VMSBC" }, "right": { "type": "literal", "value": "\"vmsbc.vxm\"" } } ] }, "vxsg_mnemonic": { "mapping": [ { "number": 0, "source": "VX_VSLIDEUP <-> \"vslideup.vx\"", "left": { "type": "id", "id": "VX_VSLIDEUP" }, "right": { "type": "literal", "value": "\"vslideup.vx\"" } }, { "number": 1, "source": "VX_VSLIDEDOWN <-> \"vslidedown.vx\"", "left": { "type": "id", "id": "VX_VSLIDEDOWN" }, "right": { "type": "literal", "value": "\"vslidedown.vx\"" } }, { "number": 2, "source": "VX_VRGATHER <-> \"vrgather.vx\"", "left": { "type": "id", "id": "VX_VRGATHER" }, "right": { "type": "literal", "value": "\"vrgather.vx\"" } } ] }, "vxtype_mnemonic": { "mapping": [ { "number": 0, "source": "VX_VADD <-> \"vadd.vx\"", "left": { "type": "id", "id": "VX_VADD" }, "right": { "type": "literal", "value": "\"vadd.vx\"" } }, { "number": 1, "source": "VX_VSUB <-> \"vsub.vx\"", "left": { "type": "id", "id": "VX_VSUB" }, "right": { "type": "literal", "value": "\"vsub.vx\"" } }, { "number": 2, "source": "VX_VRSUB <-> \"vrsub.vx\"", "left": { "type": "id", "id": "VX_VRSUB" }, "right": { "type": "literal", "value": "\"vrsub.vx\"" } }, { "number": 3, "source": "VX_VAND <-> \"vand.vx\"", "left": { "type": "id", "id": "VX_VAND" }, "right": { "type": "literal", "value": "\"vand.vx\"" } }, { "number": 4, "source": "VX_VOR <-> \"vor.vx\"", "left": { "type": "id", "id": "VX_VOR" }, "right": { "type": "literal", "value": "\"vor.vx\"" } }, { "number": 5, "source": "VX_VXOR <-> \"vxor.vx\"", "left": { "type": "id", "id": "VX_VXOR" }, "right": { "type": "literal", "value": "\"vxor.vx\"" } }, { "number": 6, "source": "VX_VSADDU <-> \"vsaddu.vx\"", "left": { "type": "id", "id": "VX_VSADDU" }, "right": { "type": "literal", "value": "\"vsaddu.vx\"" } }, { "number": 7, "source": "VX_VSADD <-> \"vsadd.vx\"", "left": { "type": "id", "id": "VX_VSADD" }, "right": { "type": "literal", "value": "\"vsadd.vx\"" } }, { "number": 8, "source": "VX_VSSUBU <-> \"vssubu.vx\"", "left": { "type": "id", "id": "VX_VSSUBU" }, "right": { "type": "literal", "value": "\"vssubu.vx\"" } }, { "number": 9, "source": "VX_VSSUB <-> \"vssub.vx\"", "left": { "type": "id", "id": "VX_VSSUB" }, "right": { "type": "literal", "value": "\"vssub.vx\"" } }, { "number": 10, "source": "VX_VSLL <-> \"vsll.vx\"", "left": { "type": "id", "id": "VX_VSLL" }, "right": { "type": "literal", "value": "\"vsll.vx\"" } }, { "number": 11, "source": "VX_VSMUL <-> \"vsmul.vx\"", "left": { "type": "id", "id": "VX_VSMUL" }, "right": { "type": "literal", "value": "\"vsmul.vx\"" } }, { "number": 12, "source": "VX_VSRL <-> \"vsrl.vx\"", "left": { "type": "id", "id": "VX_VSRL" }, "right": { "type": "literal", "value": "\"vsrl.vx\"" } }, { "number": 13, "source": "VX_VSRA <-> \"vsra.vx\"", "left": { "type": "id", "id": "VX_VSRA" }, "right": { "type": "literal", "value": "\"vsra.vx\"" } }, { "number": 14, "source": "VX_VSSRL <-> \"vssrl.vx\"", "left": { "type": "id", "id": "VX_VSSRL" }, "right": { "type": "literal", "value": "\"vssrl.vx\"" } }, { "number": 15, "source": "VX_VSSRA <-> \"vssra.vx\"", "left": { "type": "id", "id": "VX_VSSRA" }, "right": { "type": "literal", "value": "\"vssra.vx\"" } }, { "number": 16, "source": "VX_VMINU <-> \"vminu.vx\"", "left": { "type": "id", "id": "VX_VMINU" }, "right": { "type": "literal", "value": "\"vminu.vx\"" } }, { "number": 17, "source": "VX_VMIN <-> \"vmin.vx\"", "left": { "type": "id", "id": "VX_VMIN" }, "right": { "type": "literal", "value": "\"vmin.vx\"" } }, { "number": 18, "source": "VX_VMAXU <-> \"vmaxu.vx\"", "left": { "type": "id", "id": "VX_VMAXU" }, "right": { "type": "literal", "value": "\"vmaxu.vx\"" } }, { "number": 19, "source": "VX_VMAX <-> \"vmax.vx\"", "left": { "type": "id", "id": "VX_VMAX" }, "right": { "type": "literal", "value": "\"vmax.vx\"" } } ] }, "wmvvtype_mnemonic": { "mapping": [ { "number": 0, "source": "WMVV_VWMACCU <-> \"vwmaccu.vv\"", "left": { "type": "id", "id": "WMVV_VWMACCU" }, "right": { "type": "literal", "value": "\"vwmaccu.vv\"" } }, { "number": 1, "source": "WMVV_VWMACC <-> \"vwmacc.vv\"", "left": { "type": "id", "id": "WMVV_VWMACC" }, "right": { "type": "literal", "value": "\"vwmacc.vv\"" } }, { "number": 2, "source": "WMVV_VWMACCSU <-> \"vwmaccsu.vv\"", "left": { "type": "id", "id": "WMVV_VWMACCSU" }, "right": { "type": "literal", "value": "\"vwmaccsu.vv\"" } } ] }, "wmvxtype_mnemonic": { "mapping": [ { "number": 0, "source": "WMVX_VWMACCU <-> \"vwmaccu.vx\"", "left": { "type": "id", "id": "WMVX_VWMACCU" }, "right": { "type": "literal", "value": "\"vwmaccu.vx\"" } }, { "number": 1, "source": "WMVX_VWMACC <-> \"vwmacc.vx\"", "left": { "type": "id", "id": "WMVX_VWMACC" }, "right": { "type": "literal", "value": "\"vwmacc.vx\"" } }, { "number": 2, "source": "WMVX_VWMACCUS <-> \"vwmaccus.vx\"", "left": { "type": "id", "id": "WMVX_VWMACCUS" }, "right": { "type": "literal", "value": "\"vwmaccus.vx\"" } }, { "number": 3, "source": "WMVX_VWMACCSU <-> \"vwmaccsu.vx\"", "left": { "type": "id", "id": "WMVX_VWMACCSU" }, "right": { "type": "literal", "value": "\"vwmaccsu.vx\"" } } ] }, "wvtype_mnemonic": { "mapping": [ { "number": 0, "source": "WV_VADD <-> \"vwadd.wv\"", "left": { "type": "id", "id": "WV_VADD" }, "right": { "type": "literal", "value": "\"vwadd.wv\"" } }, { "number": 1, "source": "WV_VSUB <-> \"vwsub.wv\"", "left": { "type": "id", "id": "WV_VSUB" }, "right": { "type": "literal", "value": "\"vwsub.wv\"" } }, { "number": 2, "source": "WV_VADDU <-> \"vwaddu.wv\"", "left": { "type": "id", "id": "WV_VADDU" }, "right": { "type": "literal", "value": "\"vwaddu.wv\"" } }, { "number": 3, "source": "WV_VSUBU <-> \"vwsubu.wv\"", "left": { "type": "id", "id": "WV_VSUBU" }, "right": { "type": "literal", "value": "\"vwsubu.wv\"" } } ] }, "wvvtype_mnemonic": { "mapping": [ { "number": 0, "source": "WVV_VADD <-> \"vwadd.vv\"", "left": { "type": "id", "id": "WVV_VADD" }, "right": { "type": "literal", "value": "\"vwadd.vv\"" } }, { "number": 1, "source": "WVV_VSUB <-> \"vwsub.vv\"", "left": { "type": "id", "id": "WVV_VSUB" }, "right": { "type": "literal", "value": "\"vwsub.vv\"" } }, { "number": 2, "source": "WVV_VADDU <-> \"vwaddu.vv\"", "left": { "type": "id", "id": "WVV_VADDU" }, "right": { "type": "literal", "value": "\"vwaddu.vv\"" } }, { "number": 3, "source": "WVV_VSUBU <-> \"vwsubu.vv\"", "left": { "type": "id", "id": "WVV_VSUBU" }, "right": { "type": "literal", "value": "\"vwsubu.vv\"" } }, { "number": 4, "source": "WVV_VWMUL <-> \"vwmul.vv\"", "left": { "type": "id", "id": "WVV_VWMUL" }, "right": { "type": "literal", "value": "\"vwmul.vv\"" } }, { "number": 5, "source": "WVV_VWMULU <-> \"vwmulu.vv\"", "left": { "type": "id", "id": "WVV_VWMULU" }, "right": { "type": "literal", "value": "\"vwmulu.vv\"" } }, { "number": 6, "source": "WVV_VWMULSU <-> \"vwmulsu.vv\"", "left": { "type": "id", "id": "WVV_VWMULSU" }, "right": { "type": "literal", "value": "\"vwmulsu.vv\"" } } ] }, "wvxtype_mnemonic": { "mapping": [ { "number": 0, "source": "WVX_VADD <-> \"vwadd.vx\"", "left": { "type": "id", "id": "WVX_VADD" }, "right": { "type": "literal", "value": "\"vwadd.vx\"" } }, { "number": 1, "source": "WVX_VSUB <-> \"vwsub.vx\"", "left": { "type": "id", "id": "WVX_VSUB" }, "right": { "type": "literal", "value": "\"vwsub.vx\"" } }, { "number": 2, "source": "WVX_VADDU <-> \"vwaddu.vx\"", "left": { "type": "id", "id": "WVX_VADDU" }, "right": { "type": "literal", "value": "\"vwaddu.vx\"" } }, { "number": 3, "source": "WVX_VSUBU <-> \"vwsubu.vx\"", "left": { "type": "id", "id": "WVX_VSUBU" }, "right": { "type": "literal", "value": "\"vwsubu.vx\"" } }, { "number": 4, "source": "WVX_VWMUL <-> \"vwmul.vx\"", "left": { "type": "id", "id": "WVX_VWMUL" }, "right": { "type": "literal", "value": "\"vwmul.vx\"" } }, { "number": 5, "source": "WVX_VWMULU <-> \"vwmulu.vx\"", "left": { "type": "id", "id": "WVX_VWMULU" }, "right": { "type": "literal", "value": "\"vwmulu.vx\"" } }, { "number": 6, "source": "WVX_VWMULSU <-> \"vwmulsu.vx\"", "left": { "type": "id", "id": "WVX_VWMULSU" }, "right": { "type": "literal", "value": "\"vwmulsu.vx\"" } } ] }, "wxtype_mnemonic": { "mapping": [ { "number": 0, "source": "WX_VADD <-> \"vwadd.wx\"", "left": { "type": "id", "id": "WX_VADD" }, "right": { "type": "literal", "value": "\"vwadd.wx\"" } }, { "number": 1, "source": "WX_VSUB <-> \"vwsub.wx\"", "left": { "type": "id", "id": "WX_VSUB" }, "right": { "type": "literal", "value": "\"vwsub.wx\"" } }, { "number": 2, "source": "WX_VADDU <-> \"vwaddu.wx\"", "left": { "type": "id", "id": "WX_VADDU" }, "right": { "type": "literal", "value": "\"vwaddu.wx\"" } }, { "number": 3, "source": "WX_VSUBU <-> \"vwsubu.wx\"", "left": { "type": "id", "id": "WX_VSUBU" }, "right": { "type": "literal", "value": "\"vwsubu.wx\"" } } ] }, "zba_rtype_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_SH1ADD <-> \"sh1add\"", "left": { "type": "id", "id": "RISCV_SH1ADD" }, "right": { "type": "literal", "value": "\"sh1add\"" } }, { "number": 1, "source": "RISCV_SH2ADD <-> \"sh2add\"", "left": { "type": "id", "id": "RISCV_SH2ADD" }, "right": { "type": "literal", "value": "\"sh2add\"" } }, { "number": 2, "source": "RISCV_SH3ADD <-> \"sh3add\"", "left": { "type": "id", "id": "RISCV_SH3ADD" }, "right": { "type": "literal", "value": "\"sh3add\"" } } ] }, "zba_rtypeuw_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_ADDUW <-> \"add.uw\"", "left": { "type": "id", "id": "RISCV_ADDUW" }, "right": { "type": "literal", "value": "\"add.uw\"" } }, { "number": 1, "source": "RISCV_SH1ADDUW <-> \"sh1add.uw\"", "left": { "type": "id", "id": "RISCV_SH1ADDUW" }, "right": { "type": "literal", "value": "\"sh1add.uw\"" } }, { "number": 2, "source": "RISCV_SH2ADDUW <-> \"sh2add.uw\"", "left": { "type": "id", "id": "RISCV_SH2ADDUW" }, "right": { "type": "literal", "value": "\"sh2add.uw\"" } }, { "number": 3, "source": "RISCV_SH3ADDUW <-> \"sh3add.uw\"", "left": { "type": "id", "id": "RISCV_SH3ADDUW" }, "right": { "type": "literal", "value": "\"sh3add.uw\"" } } ] }, "zbb_extop_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_SEXTB <-> \"sext.b\"", "left": { "type": "id", "id": "RISCV_SEXTB" }, "right": { "type": "literal", "value": "\"sext.b\"" } }, { "number": 1, "source": "RISCV_SEXTH <-> \"sext.h\"", "left": { "type": "id", "id": "RISCV_SEXTH" }, "right": { "type": "literal", "value": "\"sext.h\"" } }, { "number": 2, "source": "RISCV_ZEXTH <-> \"zext.h\"", "left": { "type": "id", "id": "RISCV_ZEXTH" }, "right": { "type": "literal", "value": "\"zext.h\"" } } ] }, "zbb_rtype_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_ANDN <-> \"andn\"", "left": { "type": "id", "id": "RISCV_ANDN" }, "right": { "type": "literal", "value": "\"andn\"" } }, { "number": 1, "source": "RISCV_ORN <-> \"orn\"", "left": { "type": "id", "id": "RISCV_ORN" }, "right": { "type": "literal", "value": "\"orn\"" } }, { "number": 2, "source": "RISCV_XNOR <-> \"xnor\"", "left": { "type": "id", "id": "RISCV_XNOR" }, "right": { "type": "literal", "value": "\"xnor\"" } }, { "number": 3, "source": "RISCV_MAX <-> \"max\"", "left": { "type": "id", "id": "RISCV_MAX" }, "right": { "type": "literal", "value": "\"max\"" } }, { "number": 4, "source": "RISCV_MAXU <-> \"maxu\"", "left": { "type": "id", "id": "RISCV_MAXU" }, "right": { "type": "literal", "value": "\"maxu\"" } }, { "number": 5, "source": "RISCV_MIN <-> \"min\"", "left": { "type": "id", "id": "RISCV_MIN" }, "right": { "type": "literal", "value": "\"min\"" } }, { "number": 6, "source": "RISCV_MINU <-> \"minu\"", "left": { "type": "id", "id": "RISCV_MINU" }, "right": { "type": "literal", "value": "\"minu\"" } }, { "number": 7, "source": "RISCV_ROL <-> \"rol\"", "left": { "type": "id", "id": "RISCV_ROL" }, "right": { "type": "literal", "value": "\"rol\"" } }, { "number": 8, "source": "RISCV_ROR <-> \"ror\"", "left": { "type": "id", "id": "RISCV_ROR" }, "right": { "type": "literal", "value": "\"ror\"" } } ] }, "zbb_rtypew_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_ROLW <-> \"rolw\"", "left": { "type": "id", "id": "RISCV_ROLW" }, "right": { "type": "literal", "value": "\"rolw\"" } }, { "number": 1, "source": "RISCV_RORW <-> \"rorw\"", "left": { "type": "id", "id": "RISCV_RORW" }, "right": { "type": "literal", "value": "\"rorw\"" } } ] }, "zbkb_rtype_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_PACK <-> \"pack\"", "left": { "type": "id", "id": "RISCV_PACK" }, "right": { "type": "literal", "value": "\"pack\"" } }, { "number": 1, "source": "RISCV_PACKH <-> \"packh\"", "left": { "type": "id", "id": "RISCV_PACKH" }, "right": { "type": "literal", "value": "\"packh\"" } } ] }, "zbs_iop_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_BCLRI <-> \"bclri\"", "left": { "type": "id", "id": "RISCV_BCLRI" }, "right": { "type": "literal", "value": "\"bclri\"" } }, { "number": 1, "source": "RISCV_BEXTI <-> \"bexti\"", "left": { "type": "id", "id": "RISCV_BEXTI" }, "right": { "type": "literal", "value": "\"bexti\"" } }, { "number": 2, "source": "RISCV_BINVI <-> \"binvi\"", "left": { "type": "id", "id": "RISCV_BINVI" }, "right": { "type": "literal", "value": "\"binvi\"" } }, { "number": 3, "source": "RISCV_BSETI <-> \"bseti\"", "left": { "type": "id", "id": "RISCV_BSETI" }, "right": { "type": "literal", "value": "\"bseti\"" } } ] }, "zbs_rtype_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_BCLR <-> \"bclr\"", "left": { "type": "id", "id": "RISCV_BCLR" }, "right": { "type": "literal", "value": "\"bclr\"" } }, { "number": 1, "source": "RISCV_BEXT <-> \"bext\"", "left": { "type": "id", "id": "RISCV_BEXT" }, "right": { "type": "literal", "value": "\"bext\"" } }, { "number": 2, "source": "RISCV_BINV <-> \"binv\"", "left": { "type": "id", "id": "RISCV_BINV" }, "right": { "type": "literal", "value": "\"binv\"" } }, { "number": 3, "source": "RISCV_BSET <-> \"bset\"", "left": { "type": "id", "id": "RISCV_BSET" }, "right": { "type": "literal", "value": "\"bset\"" } } ] }, "zicond_mnemonic": { "mapping": [ { "number": 0, "source": "RISCV_CZERO_EQZ <-> \"czero.eqz\"", "left": { "type": "id", "id": "RISCV_CZERO_EQZ" }, "right": { "type": "literal", "value": "\"czero.eqz\"" } }, { "number": 1, "source": "RISCV_CZERO_NEZ <-> \"czero.nez\"", "left": { "type": "id", "id": "RISCV_CZERO_NEZ" }, "right": { "type": "literal", "value": "\"czero.nez\"" } } ] } }, "vals": { "Architecture_of_num": { "val": { "source": "val Architecture_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> Architecture", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> Architecture" } }, "ExtStatus_of_num": { "val": { "source": "val ExtStatus_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> ExtStatus", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> ExtStatus" } }, "FRegStr": { "val": { "source": "val FRegStr : fregtype -> string", "type": "fregtype -> string" } }, "GPRstr": { "val": { "source": "val GPRstr : bits(5) -> string", "type": "bits(5) -> string" } }, "InterruptType_of_num": { "val": { "source": "val InterruptType_of_num : forall 'e, (0 <= 'e & 'e <= 8). int('e) -> InterruptType", "type": "forall 'e, (0 <= 'e & 'e <= 8). int('e) -> InterruptType" } }, "MemoryOpResult_add_meta": { "val": { "source": "val MemoryOpResult_add_meta : forall ('t : Type). (MemoryOpResult('t), mem_meta) -> MemoryOpResult(('t, mem_meta))", "type": "forall ('t : Type). (MemoryOpResult('t), mem_meta) -> MemoryOpResult(('t, mem_meta))" } }, "MemoryOpResult_drop_meta": { "val": { "source": "val MemoryOpResult_drop_meta : forall ('t : Type). MemoryOpResult(('t, mem_meta)) -> MemoryOpResult('t)", "type": "forall ('t : Type). MemoryOpResult(('t, mem_meta)) -> MemoryOpResult('t)" } }, "PPNs_of_PTE": { "val": { "source": "val PPNs_of_PTE : (SV_Params, bits(64)) -> bits(64)", "type": "(SV_Params, bits(64)) -> bits(64)" } }, "PmpAddrMatchType_of_num": { "val": { "source": "val PmpAddrMatchType_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> PmpAddrMatchType", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> PmpAddrMatchType" } }, "Privilege_of_num": { "val": { "source": "val Privilege_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> Privilege", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> Privilege" } }, "RegStr": { "val": { "source": "val RegStr : regtype -> string", "type": "regtype -> string" } }, "Retired_of_num": { "val": { "source": "val Retired_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> Retired", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> Retired" } }, "SATPMode_of_num": { "val": { "source": "val SATPMode_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> SATPMode", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> SATPMode" } }, "TrapVectorMode_of_num": { "val": { "source": "val TrapVectorMode_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> TrapVectorMode", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> TrapVectorMode" } }, "__ReadRAM_Meta": { "val": { "source": "val __ReadRAM_Meta : forall 'n. (xlenbits, int('n)) -> mem_meta", "type": "forall 'n. (xlenbits, int('n)) -> mem_meta" } }, "__TraceMemoryRead": { "val": { "source": "val __TraceMemoryRead : forall 'n 'm. (int('n), bits('m), bits(8 * 'n)) -> unit", "type": "forall 'n 'm. (int('n), bits('m), bits(8 * 'n)) -> unit" } }, "__TraceMemoryWrite": { "val": { "source": "val __TraceMemoryWrite : forall 'n 'm. (int('n), bits('m), bits(8 * 'n)) -> unit", "type": "forall 'n 'm. (int('n), bits('m), bits(8 * 'n)) -> unit" } }, "__WriteRAM_Meta": { "val": { "source": "val __WriteRAM_Meta : forall 'n. (xlenbits, int('n), mem_meta) -> unit", "type": "forall 'n. (xlenbits, int('n), mem_meta) -> unit" } }, "__barrier": { "val": { "source": "val __barrier = monadic {ocaml: \"Platform.barrier\", c: \"platform_barrier\", _: \"barrier\"}: barrier_kind -> unit", "type": "barrier_kind -> unit" } }, "__branch_announce": { "val": { "source": "val __branch_announce = monadic {ocaml: \"Platform.branch_announce\", c: \"platform_branch_announce\", _: \"branch_announce\"}: forall 'addrsize, 'addrsize in {32, 64}.\n (int('addrsize), bits('addrsize)) -> unit", "type": "forall 'addrsize, 'addrsize in {32, 64}. (int('addrsize), bits('addrsize)) -> unit" } }, "__cache_maintenance": { "val": { "source": "val __cache_maintenance = monadic {ocaml: \"Platform.cache_maintenance\", c: \"platform_cache_maintenance\", _: \"cache_maintenance\"}: forall 'addrsize, 'addrsize in {32, 64}.\n (cache_op_kind, int('addrsize), bits('addrsize)) -> unit", "type": "forall 'addrsize, 'addrsize in {32, 64}. (cache_op_kind, int('addrsize), bits('addrsize)) -> unit" } }, "__deref": { "val": { "source": "val __deref = monadic {_: \"reg_deref\"}: forall ('a : Type). register('a) -> 'a", "type": "forall ('a : Type). register('a) -> 'a" } }, "__excl_res": { "val": { "source": "val __excl_res = monadic {ocaml: \"Platform.excl_res\", c: \"platform_excl_res\", _: \"excl_result\"}: unit -> bool", "type": "unit -> bool" } }, "__id": { "val": { "source": "val __id : forall 'n. int('n) -> int('n)", "type": "forall 'n. int('n) -> int('n)" } }, "__instr_announce": { "val": { "source": "val __instr_announce = monadic {ocaml: \"Platform.instr_announce\", c: \"platform_instr_announce\", _: \"instr_announce\"}: forall 'n, 'n > 0.\n bits('n) -> unit", "type": "forall 'n, 'n > 0. bits('n) -> unit" } }, "__read_mem": { "val": { "source": "val __read_mem = monadic {ocaml: \"Platform.read_mem\", c: \"platform_read_mem\", _: \"read_mem\"}: forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}).\n (read_kind, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n)", "type": "forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}).\n (read_kind, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n)" } }, "__read_memt": { "val": { "source": "val __read_memt = monadic {ocaml: \"Platform.read_memt\", c: \"platform_read_memt\", _: \"read_memt\"}: forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}).\n (read_kind, bits('addrsize), int('n)) -> (bits(8 * 'n), bit)", "type": "forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}). (read_kind, bits('addrsize), int('n)) -> (bits(8 * 'n), bit)" } }, "__write_mem": { "val": { "source": "val __write_mem = monadic {ocaml: \"Platform.write_mem\", c: \"platform_write_mem\", _: \"write_mem\"}: forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}).\n (write_kind, int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool", "type": "forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}).\n (write_kind, int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool" } }, "__write_mem_ea": { "val": { "source": "val __write_mem_ea = monadic {ocaml: \"Platform.write_mem_ea\", c: \"platform_write_mem_ea\", _: \"write_mem_ea\"}: forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}).\n (write_kind, int('addrsize), bits('addrsize), int('n)) -> unit", "type": "forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}). (write_kind, int('addrsize), bits('addrsize), int('n)) -> unit" } }, "__write_memt": { "val": { "source": "val __write_memt = monadic {ocaml: \"Platform.write_memt\", c: \"platform_write_memt\", _: \"write_memt\"}: forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}).\n (write_kind, bits('addrsize), int('n), bits(8 * 'n), bit) -> bool", "type": "forall 'n 'addrsize, ('n > 0 & 'addrsize in {32, 64}). (write_kind, bits('addrsize), int('n), bits(8 * 'n), bit) -> bool" } }, "__write_tag": { "val": { "source": "val __write_tag = monadic {ocaml: \"Platform.write_tag\", c: \"platform_write_tag\", _: \"write_tag\"}: forall 'addrsize, 'addrsize in {32, 64}.\n (write_kind, bits('addrsize), bit) -> bool", "type": "forall 'addrsize, 'addrsize in {32, 64}. (write_kind, bits('addrsize), bit) -> bool" } }, "_shl1": { "val": { "source": "val _shl1 = pure {c: \"shl_mach_int\", _: \"shl_int\"}: forall 'n, (0 <= 'n & 'n <= 3). (int(1), int('n)) -> {1, 2, 4, 8}", "type": "forall 'n, (0 <= 'n & 'n <= 3). (int(1), int('n)) -> {1, 2, 4, 8}" } }, "_shl32": { "val": { "source": "val _shl32 = pure {c: \"shl_mach_int\", _: \"shl_int\"}: forall 'n, 'n in {0, 1}. (int(32), int('n)) -> {32, 64}", "type": "forall 'n, 'n in {0, 1}. (int(32), int('n)) -> {32, 64}" } }, "_shl8": { "val": { "source": "val _shl8 = pure {c: \"shl_mach_int\", _: \"shl_int\"}: forall 'n, (0 <= 'n & 'n <= 3). (int(8), int('n)) -> {8, 16, 32, 64}", "type": "forall 'n, (0 <= 'n & 'n <= 3). (int(8), int('n)) -> {8, 16, 32, 64}" } }, "_shl_int": { "val": { "source": "val _shl_int = pure {_: \"shl_int\"}: forall 'n, 0 <= 'n. (int, int('n)) -> int", "type": "forall 'n, 0 <= 'n. (int, int('n)) -> int" } }, "_shl_int_general": { "val": { "source": "val _shl_int_general : (int, int) -> int", "type": "(int, int) -> int" } }, "_shr32": { "val": { "source": "val _shr32 = pure {c: \"shr_mach_int\", _: \"shr_int\"}: forall 'n, (0 <= 'n & 'n <= 31).\n (int('n), int(1)) -> {'m, (0 <= 'm & 'm <= 15). int('m)}", "type": "forall 'n, (0 <= 'n & 'n <= 31). (int('n), int(1)) -> {'m, (0 <= 'm & 'm <= 15). int('m)}" } }, "_shr_int": { "val": { "source": "val _shr_int = pure {_: \"shr_int\"}: forall 'n, 0 <= 'n. (int, int('n)) -> int", "type": "forall 'n, 0 <= 'n. (int, int('n)) -> int" } }, "_shr_int_general": { "val": { "source": "val _shr_int_general : (int, int) -> int", "type": "(int, int) -> int" } }, "_tmod_int": { "val": { "source": "val _tmod_int = pure {ocaml: \"tmod_int\", interpreter: \"tmod_int\", lem: \"tmod_int\", c: \"tmod_int\", coq: \"Z.rem\"}: (int, int) -> int", "type": "(int, int) -> int" } }, "_tmod_int_positive": { "val": { "source": "val _tmod_int_positive = pure {ocaml: \"tmod_int\", interpreter: \"tmod_int\", lem: \"tmod_int\", c: \"tmod_int\", coq: \"Z.rem\"}: forall 'n, 'n >= 1.\n (int, int('n)) -> nat", "type": "forall 'n, 'n >= 1. (int, int('n)) -> nat" } }, "a64_barrier_domain_of_num": { "val": { "source": "val a64_barrier_domain_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> a64_barrier_domain", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> a64_barrier_domain" } }, "a64_barrier_type_of_num": { "val": { "source": "val a64_barrier_type_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> a64_barrier_type", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> a64_barrier_type" } }, "abs_int_atom": { "val": { "source": "val abs_int_atom = pure {ocaml: \"abs_int\", interpreter: \"abs_int\", lem: \"integerAbs\", c: \"abs_int\", coq: \"Z.abs\"}: forall 'n.\n int('n) -> int(abs('n))", "type": "forall 'n. int('n) -> int(abs('n))" } }, "abs_int_plain": { "val": { "source": "val abs_int_plain = pure {smt: \"abs\", ocaml: \"abs_int\", interpreter: \"abs_int\", lem: \"integerAbs\", c: \"abs_int\", coq: \"Z.abs\"}: int -> int", "type": "int -> int" } }, "accessToFault": { "val": { "source": "val accessToFault : AccessType(ext_access_type) -> ExceptionType", "type": "AccessType(ext_access_type) -> ExceptionType" } }, "accessType_to_str": { "val": { "source": "val accessType_to_str : AccessType(ext_access_type) -> string", "type": "AccessType(ext_access_type) -> string" } }, "accrue_fflags": { "val": { "source": "val accrue_fflags : (bits(5)) -> unit", "type": "(bits(5)) -> unit" } }, "add_atom": { "val": { "source": "val add_atom = pure {ocaml: \"add_int\", interpreter: \"add_int\", lem: \"integerAdd\", c: \"add_int\", coq: \"Z.add\"}: forall 'n 'm.\n (int('n), int('m)) -> int('n + 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> int('n + 'm)" } }, "add_bits": { "val": { "source": "val add_bits = pure {ocaml: \"add_vec\", interpreter: \"add_vec\", lem: \"add_vec\", c: \"add_bits\", coq: \"add_vec\"}: forall 'n.\n (bits('n), bits('n)) -> bits('n)", "type": "forall 'n. (bits('n), bits('n)) -> bits('n)" } }, "add_bits_int": { "val": { "source": "val add_bits_int = pure {ocaml: \"add_vec_int\", interpreter: \"add_vec_int\", lem: \"add_vec_int\", c: \"add_bits_int\", coq: \"add_vec_int\"}: forall 'n.\n (bits('n), int) -> bits('n)", "type": "forall 'n. (bits('n), int) -> bits('n)" } }, "add_int": { "val": { "source": "val add_int = pure {ocaml: \"add_int\", interpreter: \"add_int\", lem: \"integerAdd\", c: \"add_int\", coq: \"Z.add\"}: (int, int) -> int", "type": "(int, int) -> int" } }, "add_to_TLB": { "val": { "source": "val add_to_TLB : (asidbits, bits(64), bits(64), bits(64), bits(64), nat, bool, nat, nat) -> unit", "type": "(asidbits, bits(64), bits(64), bits(64), bits(64), nat, bool, nat, nat) -> unit" } }, "aes_apply_fwd_sbox_to_each_byte": { "val": { "source": "val aes_apply_fwd_sbox_to_each_byte : bits(64) -> bits(64)", "type": "bits(64) -> bits(64)" } }, "aes_apply_inv_sbox_to_each_byte": { "val": { "source": "val aes_apply_inv_sbox_to_each_byte : bits(64) -> bits(64)", "type": "bits(64) -> bits(64)" } }, "aes_decode_rcon": { "val": { "source": "val aes_decode_rcon : bits(4) -> bits(32)", "type": "bits(4) -> bits(32)" } }, "aes_get_column": { "val": { "source": "val aes_get_column : (bits(128), nat) -> bits(32)", "type": "(bits(128), nat) -> bits(32)" } }, "aes_mixcolumn_byte_fwd": { "val": { "source": "val aes_mixcolumn_byte_fwd : bits(8) -> bits(32)", "type": "bits(8) -> bits(32)" } }, "aes_mixcolumn_byte_inv": { "val": { "source": "val aes_mixcolumn_byte_inv : bits(8) -> bits(32)", "type": "bits(8) -> bits(32)" } }, "aes_mixcolumn_fwd": { "val": { "source": "val aes_mixcolumn_fwd : bits(32) -> bits(32)", "type": "bits(32) -> bits(32)" } }, "aes_mixcolumn_inv": { "val": { "source": "val aes_mixcolumn_inv : bits(32) -> bits(32)", "type": "bits(32) -> bits(32)" } }, "aes_mixcolumns_fwd": { "val": { "source": "val aes_mixcolumns_fwd : bits(128) -> bits(128)", "type": "bits(128) -> bits(128)" } }, "aes_mixcolumns_inv": { "val": { "source": "val aes_mixcolumns_inv : bits(128) -> bits(128)", "type": "bits(128) -> bits(128)" } }, "aes_rv64_shiftrows_fwd": { "val": { "source": "val aes_rv64_shiftrows_fwd : (bits(64), bits(64)) -> bits(64)", "type": "(bits(64), bits(64)) -> bits(64)" } }, "aes_rv64_shiftrows_inv": { "val": { "source": "val aes_rv64_shiftrows_inv : (bits(64), bits(64)) -> bits(64)", "type": "(bits(64), bits(64)) -> bits(64)" } }, "aes_sbox_fwd": { "val": { "source": "val aes_sbox_fwd : bits(8) -> bits(8)", "type": "bits(8) -> bits(8)" } }, "aes_sbox_inv": { "val": { "source": "val aes_sbox_inv : bits(8) -> bits(8)", "type": "bits(8) -> bits(8)" } }, "aes_shift_rows_fwd": { "val": { "source": "val aes_shift_rows_fwd : bits(128) -> bits(128)", "type": "bits(128) -> bits(128)" } }, "aes_shift_rows_inv": { "val": { "source": "val aes_shift_rows_inv : bits(128) -> bits(128)", "type": "bits(128) -> bits(128)" } }, "aes_subbytes_fwd": { "val": { "source": "val aes_subbytes_fwd : bits(128) -> bits(128)", "type": "bits(128) -> bits(128)" } }, "aes_subbytes_inv": { "val": { "source": "val aes_subbytes_inv : bits(128) -> bits(128)", "type": "bits(128) -> bits(128)" } }, "aes_subword_fwd": { "val": { "source": "val aes_subword_fwd : bits(32) -> bits(32)", "type": "bits(32) -> bits(32)" } }, "aes_subword_inv": { "val": { "source": "val aes_subword_inv : bits(32) -> bits(32)", "type": "bits(32) -> bits(32)" } }, "agtype_of_num": { "val": { "source": "val agtype_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> agtype", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> agtype" } }, "amo_mnemonic": { "val": { "source": "val amo_mnemonic : amoop <-> string", "type": "amoop <-> string" } }, "amo_width_valid": { "val": { "source": "val amo_width_valid : word_width -> bool", "type": "word_width -> bool" } }, "amoop_of_num": { "val": { "source": "val amoop_of_num : forall 'e, (0 <= 'e & 'e <= 8). int('e) -> amoop", "type": "forall 'e, (0 <= 'e & 'e <= 8). int('e) -> amoop" } }, "and_bool": { "val": { "source": "val and_bool = pure {coq: \"andb\", _: \"and_bool\"}: forall ('p : Bool) ('q : Bool).\n (bool('p), bool('q)) -> bool(('p & 'q))", "type": "forall ('p : Bool) ('q : Bool). (bool('p), bool('q)) -> bool(('p & 'q))" } }, "and_bool_no_flow": { "val": { "source": "val and_bool_no_flow = pure {coq: \"andb\", _: \"and_bool\"}: (bool, bool) -> bool", "type": "(bool, bool) -> bool" } }, "and_vec": { "val": { "source": "val and_vec = pure {lem: \"and_vec\", c: \"and_bits\", coq: \"and_vec\", ocaml: \"and_vec\", interpreter: \"and_vec\"}: forall 'n.\n (bits('n), bits('n)) -> bits('n)", "type": "forall 'n. (bits('n), bits('n)) -> bits('n)" } }, "append_64": { "val": { "source": "val append_64 = pure {_: \"append_64\"}: forall 'n. (bits('n), bits(64)) -> bits('n + 64)", "type": "forall 'n. (bits('n), bits(64)) -> bits('n + 64)" } }, "aqrl_str": { "val": { "source": "val aqrl_str : (bool, bool) -> string", "type": "(bool, bool) -> string" } }, "arch_to_bits": { "val": { "source": "val arch_to_bits : Architecture -> arch_xlen", "type": "Architecture -> arch_xlen" } }, "architecture": { "val": { "source": "val architecture : arch_xlen -> option(Architecture)", "type": "arch_xlen -> option(Architecture)" } }, "assembly": { "val": { "source": "val assembly : ast <-> string", "type": "ast <-> string" } }, "assert_vstart": { "val": { "source": "val assert_vstart : int -> bool", "type": "int -> bool" } }, "biop_zbs_of_num": { "val": { "source": "val biop_zbs_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> biop_zbs", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> biop_zbs" } }, "bit_maybe_i": { "val": { "source": "val bit_maybe_i : bitvector(1) <-> string", "type": "bitvector(1) <-> string" } }, "bit_maybe_o": { "val": { "source": "val bit_maybe_o : bitvector(1) <-> string", "type": "bitvector(1) <-> string" } }, "bit_maybe_r": { "val": { "source": "val bit_maybe_r : bitvector(1) <-> string", "type": "bitvector(1) <-> string" } }, "bit_maybe_w": { "val": { "source": "val bit_maybe_w : bitvector(1) <-> string", "type": "bitvector(1) <-> string" } }, "bit_str": { "val": { "source": "val bit_str : bit -> string", "type": "bit -> string" } }, "bit_to_bool": { "val": { "source": "val bit_to_bool : bit -> bool", "type": "bit -> bool" } }, "bits_str": { "val": { "source": "val bits_str = pure {_: \"string_of_bits\"}: forall 'n. bitvector('n) -> string", "type": "forall 'n. bitvector('n) -> string" } }, "bitvector_access": { "val": { "source": "val bitvector_access = pure {ocaml: \"access\", interpreter: \"access\", lem: \"access_vec_dec\", coq: \"access_vec_dec\", c: \"vector_access\"}: forall 'n 'm, (0 <= 'm & 'm < 'n).\n (bits('n), int('m)) -> bit", "type": "forall 'n 'm, (0 <= 'm & 'm < 'n). (bits('n), int('m)) -> bit" } }, "bitvector_concat": { "val": { "source": "val bitvector_concat = pure {ocaml: \"append\", interpreter: \"append\", lem: \"concat_vec\", c: \"append\", coq: \"concat_vec\"}: forall 'n 'm.\n (bits('n), bits('m)) -> bits('n + 'm)", "type": "forall 'n 'm. (bits('n), bits('m)) -> bits('n + 'm)" } }, "bitvector_length": { "val": { "source": "val bitvector_length = pure {coq: \"length_mword\", _: \"length\"}: forall 'n. bits('n) -> int('n)", "type": "forall 'n. bits('n) -> int('n)" } }, "bitvector_update": { "val": { "source": "val bitvector_update = pure {ocaml: \"update\", interpreter: \"update\", lem: \"update_vec_dec\", coq: \"update_vec_dec\", c: \"vector_update\"}: forall 'n 'm, (0 <= 'm & 'm < 'n).\n (bits('n), int('m), bit) -> bits('n)", "type": "forall 'n 'm, (0 <= 'm & 'm < 'n). (bits('n), int('m), bit) -> bits('n)" } }, "bool_bits": { "val": { "source": "val bool_bits : bool <-> bitvector(1)", "type": "bool <-> bitvector(1)" } }, "bool_not_bits": { "val": { "source": "val bool_not_bits : bool <-> bitvector(1)", "type": "bool <-> bitvector(1)" } }, "bool_to_bit": { "val": { "source": "val bool_to_bit : bool -> bit", "type": "bool -> bit" } }, "bool_to_bits": { "val": { "source": "val bool_to_bits : bool -> bits(1)", "type": "bool -> bits(1)" } }, "bop_of_num": { "val": { "source": "val bop_of_num : forall 'e, (0 <= 'e & 'e <= 5). int('e) -> bop", "type": "forall 'e, (0 <= 'e & 'e <= 5). int('e) -> bop" } }, "brop_zba_of_num": { "val": { "source": "val brop_zba_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> brop_zba", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> brop_zba" } }, "brop_zbb_of_num": { "val": { "source": "val brop_zbb_of_num : forall 'e, (0 <= 'e & 'e <= 8). int('e) -> brop_zbb", "type": "forall 'e, (0 <= 'e & 'e <= 8). int('e) -> brop_zbb" } }, "brop_zbkb_of_num": { "val": { "source": "val brop_zbkb_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> brop_zbkb", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> brop_zbkb" } }, "brop_zbs_of_num": { "val": { "source": "val brop_zbs_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> brop_zbs", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> brop_zbs" } }, "bropw_zba_of_num": { "val": { "source": "val bropw_zba_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> bropw_zba", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> bropw_zba" } }, "bropw_zbb_of_num": { "val": { "source": "val bropw_zbb_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> bropw_zbb", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> bropw_zbb" } }, "btype_mnemonic": { "val": { "source": "val btype_mnemonic : bop <-> string", "type": "bop <-> string" } }, "bytes_wordwidth": { "val": { "source": "val bytes_wordwidth : {1, 2, 4, 8} <-> word_width", "type": "{1, 2, 4, 8} <-> word_width" } }, "cache_op_kind_of_num": { "val": { "source": "val cache_op_kind_of_num : forall 'e, (0 <= 'e & 'e <= 10). int('e) -> cache_op_kind", "type": "forall 'e, (0 <= 'e & 'e <= 10). int('e) -> cache_op_kind" } }, "cancel_reservation": { "val": { "source": "val cancel_reservation = {ocaml: \"Platform.cancel_reservation\", interpreter: \"Platform.cancel_reservation\", c: \"cancel_reservation\", lem: \"cancel_reservation\"} : unit -> unit", "type": "unit -> unit" } }, "canonical_NaN": { "val": { "source": "val canonical_NaN : forall 'm, 'm in {16, 32, 64}. int('m) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. int('m) -> bits('m)" } }, "canonical_NaN_D": { "val": { "source": "val canonical_NaN_D : unit -> bits(64)", "type": "unit -> bits(64)" } }, "canonical_NaN_H": { "val": { "source": "val canonical_NaN_H : unit -> bits(16)", "type": "unit -> bits(16)" } }, "canonical_NaN_S": { "val": { "source": "val canonical_NaN_S : unit -> bits(32)", "type": "unit -> bits(32)" } }, "check_CSR": { "val": { "source": "val check_CSR : (csreg, Privilege, bool) -> bool", "type": "(csreg, Privilege, bool) -> bool" } }, "check_CSR_access": { "val": { "source": "val check_CSR_access : (csrRW, priv_level, Privilege, bool) -> bool", "type": "(csrRW, priv_level, Privilege, bool) -> bool" } }, "check_Counteren": { "val": { "source": "val check_Counteren : (csreg, Privilege) -> bool", "type": "(csreg, Privilege) -> bool" } }, "check_PTE_permission": { "val": { "source": "val check_PTE_permission : (AccessType(ext_access_type), Privilege, bool, bool, PTE_Flags, extPte, ext_ptw) -> PTE_Check", "type": "(AccessType(ext_access_type), Privilege, bool, bool, PTE_Flags, extPte, ext_ptw) -> PTE_Check" } }, "check_TVM_SATP": { "val": { "source": "val check_TVM_SATP : (csreg, Privilege) -> bool", "type": "(csreg, Privilege) -> bool" } }, "check_misaligned": { "val": { "source": "val check_misaligned : (xlenbits, word_width) -> bool", "type": "(xlenbits, word_width) -> bool" } }, "check_seed_CSR": { "val": { "source": "val check_seed_CSR : (csreg, Privilege, bool) -> bool", "type": "(csreg, Privilege, bool) -> bool" } }, "checked_mem_read": { "val": { "source": "val checked_mem_read : forall 'n, (0 < 'n & 'n <= max_mem_access).\n (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access).\n (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))" } }, "checked_mem_write": { "val": { "source": "val checked_mem_write : forall 'n, (0 < 'n & 'n <= max_mem_access).\n (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> MemoryOpResult(bool)", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access).\n (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> MemoryOpResult(bool)" } }, "clint_dispatch": { "val": { "source": "val clint_dispatch : unit -> unit", "type": "unit -> unit" } }, "clint_load": { "val": { "source": "val clint_load : forall 'n, 'n > 0. (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n))", "type": "forall 'n, 'n > 0. (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n))" } }, "clint_store": { "val": { "source": "val clint_store: forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool)", "type": "forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool)" } }, "concat_str": { "val": { "source": "val concat_str = pure {coq: \"String.append\", lem: \"stringAppend\", _: \"concat_str\"}: (string, string) -> string", "type": "(string, string) -> string" } }, "concat_str_bits": { "val": { "source": "val concat_str_bits : forall 'n. (string, bitvector('n)) -> string", "type": "forall 'n. (string, bitvector('n)) -> string" } }, "concat_str_dec": { "val": { "source": "val concat_str_dec : (string, int) -> string", "type": "(string, int) -> string" } }, "count_leading_zeros": { "val": { "source": "val count_leading_zeros = pure {_: \"count_leading_zeros\"}: forall 'N, 'N >= 1.\n bits('N) -> {'n, (0 <= 'n & 'n <= 'N). int('n)}", "type": "forall 'N, 'N >= 1. bits('N) -> {'n, (0 <= 'n & 'n <= 'N). int('n)}" } }, "count_leadingzeros": { "val": { "source": "val count_leadingzeros : (bits(64), int) -> int", "type": "(bits(64), int) -> int" } }, "creg2reg_idx": { "val": { "source": "val creg2reg_idx : cregidx -> regidx", "type": "cregidx -> regidx" } }, "creg_name": { "val": { "source": "val creg_name : bitvector(3) <-> string", "type": "bitvector(3) <-> string" } }, "csrAccess": { "val": { "source": "val csrAccess : csreg -> csrRW", "type": "csreg -> csrRW" } }, "csrPriv": { "val": { "source": "val csrPriv : csreg -> priv_level", "type": "csreg -> priv_level" } }, "csr_mnemonic": { "val": { "source": "val csr_mnemonic : csrop <-> string", "type": "csrop <-> string" } }, "csr_name": { "val": { "source": "val csr_name : csreg -> string", "type": "csreg -> string" } }, "csr_name_map": { "val": { "source": "val csr_name_map : csreg <-> string", "type": "csreg <-> string" } }, "csrop_of_num": { "val": { "source": "val csrop_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> csrop", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> csrop" } }, "cur_Architecture": { "val": { "source": "val cur_Architecture : unit -> Architecture", "type": "unit -> Architecture" } }, "dec_str": { "val": { "source": "val dec_str = pure {_: \"dec_str\"}: int -> string", "type": "int -> string" } }, "decode_agtype": { "val": { "source": "val decode_agtype : bits(1) -> agtype", "type": "bits(1) -> agtype" } }, "def_spc": { "val": { "source": "val def_spc : unit <-> string", "type": "unit <-> string" } }, "dirty_fd_context": { "val": { "source": "val dirty_fd_context : unit -> unit", "type": "unit -> unit" } }, "dirty_fd_context_if_present": { "val": { "source": "val dirty_fd_context_if_present : unit -> unit", "type": "unit -> unit" } }, "dirty_v_context": { "val": { "source": "val dirty_v_context : unit -> unit", "type": "unit -> unit" } }, "dirty_v_context_if_present": { "val": { "source": "val dirty_v_context_if_present : unit -> unit", "type": "unit -> unit" } }, "dispatchInterrupt": { "val": { "source": "val dispatchInterrupt : Privilege -> option((InterruptType, Privilege))", "type": "Privilege -> option((InterruptType, Privilege))" } }, "dzFlag": { "val": { "source": "val dzFlag : unit -> bits(5)", "type": "unit -> bits(5)" } }, "ediv_int": { "val": { "source": "val ediv_int = pure {ocaml: \"quotient\", interpreter: \"quotient\", lem: \"integerDiv\", c: \"ediv_int\", coq: \"ZEuclid.div\"}: forall 'n 'm.\n (int('n), int('m)) -> int(div('n, 'm))", "type": "forall 'n 'm. (int('n), int('m)) -> int(div('n, 'm))" } }, "effectivePrivilege": { "val": { "source": "val effectivePrivilege : (AccessType(ext_access_type), Mstatus, Privilege) -> Privilege", "type": "(AccessType(ext_access_type), Mstatus, Privilege) -> Privilege" } }, "effective_fence_set": { "val": { "source": "val effective_fence_set : (bits(4), bool) -> bits(4)", "type": "(bits(4), bool) -> bits(4)" } }, "elf_entry": { "val": { "source": "val elf_entry = {\n ocaml: \"Elf_loader.elf_entry\",\n interpreter: \"Elf_loader.elf_entry\",\n c: \"elf_entry\"\n} : unit -> int", "type": "unit -> int" } }, "elf_tohost": { "val": { "source": "val elf_tohost = {\n ocaml: \"Elf_loader.elf_tohost\",\n interpreter: \"Elf_loader.elf_tohost\",\n c: \"elf_tohost\"\n} : unit -> int", "type": "unit -> int" } }, "emod_int": { "val": { "source": "val emod_int = pure {ocaml: \"modulus\", interpreter: \"modulus\", lem: \"integerMod\", c: \"emod_int\", coq: \"ZEuclid.modulo\"}: forall 'n 'm.\n (int('n), int('m)) -> int(mod('n, 'm))", "type": "forall 'n 'm. (int('n), int('m)) -> int(mod('n, 'm))" } }, "encdec": { "val": { "source": "val encdec : ast <-> bits(32)", "type": "ast <-> bits(32)" } }, "encdec_amoop": { "val": { "source": "val encdec_amoop : amoop <-> bitvector(5)", "type": "amoop <-> bitvector(5)" } }, "encdec_bop": { "val": { "source": "val encdec_bop : bop <-> bitvector(3)", "type": "bop <-> bitvector(3)" } }, "encdec_compressed": { "val": { "source": "val encdec_compressed : ast <-> bits(16)", "type": "ast <-> bits(16)" } }, "encdec_csrop": { "val": { "source": "val encdec_csrop : csrop <-> bitvector(2)", "type": "csrop <-> bitvector(2)" } }, "encdec_fvffunct6": { "val": { "source": "val encdec_fvffunct6 : fvffunct6 <-> bitvector(6)", "type": "fvffunct6 <-> bitvector(6)" } }, "encdec_fvfmafunct6": { "val": { "source": "val encdec_fvfmafunct6 : fvfmafunct6 <-> bitvector(6)", "type": "fvfmafunct6 <-> bitvector(6)" } }, "encdec_fvfmfunct6": { "val": { "source": "val encdec_fvfmfunct6 : fvfmfunct6 <-> bitvector(6)", "type": "fvfmfunct6 <-> bitvector(6)" } }, "encdec_fvvfunct6": { "val": { "source": "val encdec_fvvfunct6 : fvvfunct6 <-> bitvector(6)", "type": "fvvfunct6 <-> bitvector(6)" } }, "encdec_fvvmafunct6": { "val": { "source": "val encdec_fvvmafunct6 : fvvmafunct6 <-> bitvector(6)", "type": "fvvmafunct6 <-> bitvector(6)" } }, "encdec_fvvmfunct6": { "val": { "source": "val encdec_fvvmfunct6 : fvvmfunct6 <-> bitvector(6)", "type": "fvvmfunct6 <-> bitvector(6)" } }, "encdec_fwffunct6": { "val": { "source": "val encdec_fwffunct6 : fwffunct6 <-> bitvector(6)", "type": "fwffunct6 <-> bitvector(6)" } }, "encdec_fwvffunct6": { "val": { "source": "val encdec_fwvffunct6 : fwvffunct6 <-> bitvector(6)", "type": "fwvffunct6 <-> bitvector(6)" } }, "encdec_fwvfmafunct6": { "val": { "source": "val encdec_fwvfmafunct6 : fwvfmafunct6 <-> bitvector(6)", "type": "fwvfmafunct6 <-> bitvector(6)" } }, "encdec_fwvfunct6": { "val": { "source": "val encdec_fwvfunct6 : fwvfunct6 <-> bitvector(6)", "type": "fwvfunct6 <-> bitvector(6)" } }, "encdec_fwvvfunct6": { "val": { "source": "val encdec_fwvvfunct6 : fwvvfunct6 <-> bitvector(6)", "type": "fwvvfunct6 <-> bitvector(6)" } }, "encdec_fwvvmafunct6": { "val": { "source": "val encdec_fwvvmafunct6 : fwvvmafunct6 <-> bitvector(6)", "type": "fwvvmafunct6 <-> bitvector(6)" } }, "encdec_iop": { "val": { "source": "val encdec_iop : iop <-> bitvector(3)", "type": "iop <-> bitvector(3)" } }, "encdec_lsop": { "val": { "source": "val encdec_lsop : vmlsop <-> bitvector(7)", "type": "vmlsop <-> bitvector(7)" } }, "encdec_mmfunct6": { "val": { "source": "val encdec_mmfunct6 : mmfunct6 <-> bitvector(6)", "type": "mmfunct6 <-> bitvector(6)" } }, "encdec_mul_op": { "val": { "source": "val encdec_mul_op : (bool, bool, bool) <-> bitvector(3)", "type": "(bool, bool, bool) <-> bitvector(3)" } }, "encdec_mvvfunct6": { "val": { "source": "val encdec_mvvfunct6 : mvvfunct6 <-> bitvector(6)", "type": "mvvfunct6 <-> bitvector(6)" } }, "encdec_mvvmafunct6": { "val": { "source": "val encdec_mvvmafunct6 : mvvmafunct6 <-> bitvector(6)", "type": "mvvmafunct6 <-> bitvector(6)" } }, "encdec_mvxfunct6": { "val": { "source": "val encdec_mvxfunct6 : mvxfunct6 <-> bitvector(6)", "type": "mvxfunct6 <-> bitvector(6)" } }, "encdec_mvxmafunct6": { "val": { "source": "val encdec_mvxmafunct6 : mvxmafunct6 <-> bitvector(6)", "type": "mvxmafunct6 <-> bitvector(6)" } }, "encdec_nifunct6": { "val": { "source": "val encdec_nifunct6 : nifunct6 <-> bitvector(6)", "type": "nifunct6 <-> bitvector(6)" } }, "encdec_nisfunct6": { "val": { "source": "val encdec_nisfunct6 : nisfunct6 <-> bitvector(6)", "type": "nisfunct6 <-> bitvector(6)" } }, "encdec_nvfunct6": { "val": { "source": "val encdec_nvfunct6 : nvfunct6 <-> bitvector(6)", "type": "nvfunct6 <-> bitvector(6)" } }, "encdec_nvsfunct6": { "val": { "source": "val encdec_nvsfunct6 : nvsfunct6 <-> bitvector(6)", "type": "nvsfunct6 <-> bitvector(6)" } }, "encdec_nxfunct6": { "val": { "source": "val encdec_nxfunct6 : nxfunct6 <-> bitvector(6)", "type": "nxfunct6 <-> bitvector(6)" } }, "encdec_nxsfunct6": { "val": { "source": "val encdec_nxsfunct6 : nxsfunct6 <-> bitvector(6)", "type": "nxsfunct6 <-> bitvector(6)" } }, "encdec_rfvvfunct6": { "val": { "source": "val encdec_rfvvfunct6 : rfvvfunct6 <-> bitvector(6)", "type": "rfvvfunct6 <-> bitvector(6)" } }, "encdec_rivvfunct6": { "val": { "source": "val encdec_rivvfunct6 : rivvfunct6 <-> bitvector(6)", "type": "rivvfunct6 <-> bitvector(6)" } }, "encdec_rmvvfunct6": { "val": { "source": "val encdec_rmvvfunct6 : rmvvfunct6 <-> bitvector(6)", "type": "rmvvfunct6 <-> bitvector(6)" } }, "encdec_rounding_mode": { "val": { "source": "val encdec_rounding_mode : rounding_mode <-> bitvector(3)", "type": "rounding_mode <-> bitvector(3)" } }, "encdec_sop": { "val": { "source": "val encdec_sop : sop <-> bitvector(3)", "type": "sop <-> bitvector(3)" } }, "encdec_uop": { "val": { "source": "val encdec_uop : uop <-> bitvector(7)", "type": "uop <-> bitvector(7)" } }, "encdec_vfnunary0_vs1": { "val": { "source": "val encdec_vfnunary0_vs1 : vfnunary0 <-> bitvector(5)", "type": "vfnunary0 <-> bitvector(5)" } }, "encdec_vfunary0_vs1": { "val": { "source": "val encdec_vfunary0_vs1 : vfunary0 <-> bitvector(5)", "type": "vfunary0 <-> bitvector(5)" } }, "encdec_vfunary1_vs1": { "val": { "source": "val encdec_vfunary1_vs1 : vfunary1 <-> bitvector(5)", "type": "vfunary1 <-> bitvector(5)" } }, "encdec_vfwunary0_vs1": { "val": { "source": "val encdec_vfwunary0_vs1 : vfwunary0 <-> bitvector(5)", "type": "vfwunary0 <-> bitvector(5)" } }, "encdec_vicmpfunct6": { "val": { "source": "val encdec_vicmpfunct6 : vicmpfunct6 <-> bitvector(6)", "type": "vicmpfunct6 <-> bitvector(6)" } }, "encdec_vifunct6": { "val": { "source": "val encdec_vifunct6 : vifunct6 <-> bitvector(6)", "type": "vifunct6 <-> bitvector(6)" } }, "encdec_vimcfunct6": { "val": { "source": "val encdec_vimcfunct6 : vimcfunct6 <-> bitvector(6)", "type": "vimcfunct6 <-> bitvector(6)" } }, "encdec_vimfunct6": { "val": { "source": "val encdec_vimfunct6 : vimfunct6 <-> bitvector(6)", "type": "vimfunct6 <-> bitvector(6)" } }, "encdec_vimsfunct6": { "val": { "source": "val encdec_vimsfunct6 : vimsfunct6 <-> bitvector(6)", "type": "vimsfunct6 <-> bitvector(6)" } }, "encdec_visgfunct6": { "val": { "source": "val encdec_visgfunct6 : visgfunct6 <-> bitvector(6)", "type": "visgfunct6 <-> bitvector(6)" } }, "encdec_vlewidth": { "val": { "source": "val encdec_vlewidth : vlewidth <-> bitvector(3)", "type": "vlewidth <-> bitvector(3)" } }, "encdec_vsetop": { "val": { "source": "val encdec_vsetop : vsetop <-> bitvector(4)", "type": "vsetop <-> bitvector(4)" } }, "encdec_vvcmpfunct6": { "val": { "source": "val encdec_vvcmpfunct6 : vvcmpfunct6 <-> bitvector(6)", "type": "vvcmpfunct6 <-> bitvector(6)" } }, "encdec_vvfunct6": { "val": { "source": "val encdec_vvfunct6 : vvfunct6 <-> bitvector(6)", "type": "vvfunct6 <-> bitvector(6)" } }, "encdec_vvmcfunct6": { "val": { "source": "val encdec_vvmcfunct6 : vvmcfunct6 <-> bitvector(6)", "type": "vvmcfunct6 <-> bitvector(6)" } }, "encdec_vvmfunct6": { "val": { "source": "val encdec_vvmfunct6 : vvmfunct6 <-> bitvector(6)", "type": "vvmfunct6 <-> bitvector(6)" } }, "encdec_vvmsfunct6": { "val": { "source": "val encdec_vvmsfunct6 : vvmsfunct6 <-> bitvector(6)", "type": "vvmsfunct6 <-> bitvector(6)" } }, "encdec_vxcmpfunct6": { "val": { "source": "val encdec_vxcmpfunct6 : vxcmpfunct6 <-> bitvector(6)", "type": "vxcmpfunct6 <-> bitvector(6)" } }, "encdec_vxfunct6": { "val": { "source": "val encdec_vxfunct6 : vxfunct6 <-> bitvector(6)", "type": "vxfunct6 <-> bitvector(6)" } }, "encdec_vxmcfunct6": { "val": { "source": "val encdec_vxmcfunct6 : vxmcfunct6 <-> bitvector(6)", "type": "vxmcfunct6 <-> bitvector(6)" } }, "encdec_vxmfunct6": { "val": { "source": "val encdec_vxmfunct6 : vxmfunct6 <-> bitvector(6)", "type": "vxmfunct6 <-> bitvector(6)" } }, "encdec_vxmsfunct6": { "val": { "source": "val encdec_vxmsfunct6 : vxmsfunct6 <-> bitvector(6)", "type": "vxmsfunct6 <-> bitvector(6)" } }, "encdec_vxsgfunct6": { "val": { "source": "val encdec_vxsgfunct6 : vxsgfunct6 <-> bitvector(6)", "type": "vxsgfunct6 <-> bitvector(6)" } }, "encdec_wmvvfunct6": { "val": { "source": "val encdec_wmvvfunct6 : wmvvfunct6 <-> bitvector(6)", "type": "wmvvfunct6 <-> bitvector(6)" } }, "encdec_wmvxfunct6": { "val": { "source": "val encdec_wmvxfunct6 : wmvxfunct6 <-> bitvector(6)", "type": "wmvxfunct6 <-> bitvector(6)" } }, "encdec_wvfunct6": { "val": { "source": "val encdec_wvfunct6 : wvfunct6 <-> bitvector(6)", "type": "wvfunct6 <-> bitvector(6)" } }, "encdec_wvvfunct6": { "val": { "source": "val encdec_wvvfunct6 : wvvfunct6 <-> bitvector(6)", "type": "wvvfunct6 <-> bitvector(6)" } }, "encdec_wvxfunct6": { "val": { "source": "val encdec_wvxfunct6 : wvxfunct6 <-> bitvector(6)", "type": "wvxfunct6 <-> bitvector(6)" } }, "encdec_wxfunct6": { "val": { "source": "val encdec_wxfunct6 : wxfunct6 <-> bitvector(6)", "type": "wxfunct6 <-> bitvector(6)" } }, "eq_anything": { "val": { "source": "val eq_anything = pure {ocaml: \"(fun (x, y) -> x = y)\", lem: \"eq\", coq: \"generic_eq\", _: \"eq_anything\"}: forall ('a : Type).\n ('a, 'a) -> bool", "type": "forall ('a : Type). ('a, 'a) -> bool" } }, "eq_bit": { "val": { "source": "val eq_bit = pure {lem: \"eq\", _: \"eq_bit\"}: (bit, bit) -> bool", "type": "(bit, bit) -> bool" } }, "eq_bits": { "val": { "source": "val eq_bits = pure {ocaml: \"eq_list\", interpreter: \"eq_list\", lem: \"eq_vec\", c: \"eq_bits\", coq: \"eq_vec\"}: forall 'n.\n (bits('n), bits('n)) -> bool", "type": "forall 'n. (bits('n), bits('n)) -> bool" } }, "eq_bool": { "val": { "source": "val eq_bool = pure {ocaml: \"eq_bool\", interpreter: \"eq_bool\", lem: \"eq\", c: \"eq_bool\", coq: \"Bool.eqb\"}: (bool, bool) -> bool", "type": "(bool, bool) -> bool" } }, "eq_int": { "val": { "source": "val eq_int = pure {ocaml: \"eq_int\", interpreter: \"eq_int\", lem: \"eq\", c: \"eq_int\", coq: \"Z.eqb\"}: forall 'n 'm.\n (int('n), int('m)) -> bool('n == 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> bool('n == 'm)" } }, "eq_string": { "val": { "source": "val eq_string = pure {lem: \"eq\", coq: \"generic_eq\", _: \"eq_string\"}: (string, string) -> bool", "type": "(string, string) -> bool" } }, "eq_unit": { "val": { "source": "val eq_unit : (unit, unit) -> bool(true)", "type": "(unit, unit) -> bool(true)" } }, "exceptionType_to_bits": { "val": { "source": "val exceptionType_to_bits : ExceptionType -> exc_code", "type": "ExceptionType -> exc_code" } }, "exceptionType_to_str": { "val": { "source": "val exceptionType_to_str : ExceptionType -> string", "type": "ExceptionType -> string" } }, "exception_delegatee": { "val": { "source": "val exception_delegatee : (ExceptionType, Privilege) -> Privilege", "type": "(ExceptionType, Privilege) -> Privilege" } }, "exception_handler": { "val": { "source": "val exception_handler : (Privilege, ctl_result, xlenbits) -> xlenbits", "type": "(Privilege, ctl_result, xlenbits) -> xlenbits" } }, "execute": { "val": { "source": "val execute : ast -> Retired", "type": "ast -> Retired" } }, "extStatus_of_bits": { "val": { "source": "val extStatus_of_bits : ext_status -> ExtStatus", "type": "ext_status -> ExtStatus" } }, "extStatus_to_bits": { "val": { "source": "val extStatus_to_bits : ExtStatus -> ext_status", "type": "ExtStatus -> ext_status" } }, "ext_check_CSR": { "val": { "source": "val ext_check_CSR : (bits(12), Privilege, bool) -> bool", "type": "(bits(12), Privilege, bool) -> bool" } }, "ext_check_CSR_fail": { "val": { "source": "val ext_check_CSR_fail : unit->unit", "type": "unit->unit" } }, "ext_check_phys_mem_read": { "val": { "source": "val ext_check_phys_mem_read : forall 'n, 0 < 'n <= max_mem_access . (AccessType (ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> Ext_PhysAddr_Check", "type": "forall 'n, 0 < 'n <= max_mem_access . (AccessType (ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> Ext_PhysAddr_Check" } }, "ext_check_phys_mem_write": { "val": { "source": "val ext_check_phys_mem_write : forall 'n, 0 < 'n <= max_mem_access . (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> Ext_PhysAddr_Check", "type": "forall 'n, 0 < 'n <= max_mem_access . (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> Ext_PhysAddr_Check" } }, "ext_check_xret_priv": { "val": { "source": "val ext_check_xret_priv : Privilege -> bool", "type": "Privilege -> bool" } }, "ext_control_check_addr": { "val": { "source": "val ext_control_check_addr : xlenbits -> Ext_ControlAddr_Check(ext_control_addr_error)", "type": "xlenbits -> Ext_ControlAddr_Check(ext_control_addr_error)" } }, "ext_control_check_pc": { "val": { "source": "val ext_control_check_pc : xlenbits -> Ext_ControlAddr_Check(ext_control_addr_error)", "type": "xlenbits -> Ext_ControlAddr_Check(ext_control_addr_error)" } }, "ext_data_get_addr": { "val": { "source": "val ext_data_get_addr : (regidx, xlenbits, AccessType(ext_access_type), word_width) -> Ext_DataAddr_Check(ext_data_addr_error)", "type": "(regidx, xlenbits, AccessType(ext_access_type), word_width) -> Ext_DataAddr_Check(ext_data_addr_error)" } }, "ext_decode": { "val": { "source": "val ext_decode : bits(32) -> ast", "type": "bits(32) -> ast" } }, "ext_decode_compressed": { "val": { "source": "val ext_decode_compressed : bits(16) -> ast", "type": "bits(16) -> ast" } }, "ext_exc_type_to_bits": { "val": { "source": "val ext_exc_type_to_bits : ext_exc_type -> exc_code", "type": "ext_exc_type -> exc_code" } }, "ext_exc_type_to_str": { "val": { "source": "val ext_exc_type_to_str : ext_exc_type -> string", "type": "ext_exc_type -> string" } }, "ext_fail_xret_priv": { "val": { "source": "val ext_fail_xret_priv : unit -> unit", "type": "unit -> unit" } }, "ext_fetch_check_pc": { "val": { "source": "val ext_fetch_check_pc : (xlenbits, xlenbits) -> Ext_FetchAddr_Check(ext_fetch_addr_error)", "type": "(xlenbits, xlenbits) -> Ext_FetchAddr_Check(ext_fetch_addr_error)" } }, "ext_fetch_hook": { "val": { "source": "val ext_fetch_hook : FetchResult -> FetchResult", "type": "FetchResult -> FetchResult" } }, "ext_get_ptw_error": { "val": { "source": "val ext_get_ptw_error : ext_ptw_fail -> PTW_Error", "type": "ext_ptw_fail -> PTW_Error" } }, "ext_handle_control_check_error": { "val": { "source": "val ext_handle_control_check_error : ext_control_addr_error -> unit", "type": "ext_control_addr_error -> unit" } }, "ext_handle_data_check_error": { "val": { "source": "val ext_handle_data_check_error : ext_data_addr_error -> unit", "type": "ext_data_addr_error -> unit" } }, "ext_handle_fetch_check_error": { "val": { "source": "val ext_handle_fetch_check_error : ext_fetch_addr_error -> unit", "type": "ext_fetch_addr_error -> unit" } }, "ext_init": { "val": { "source": "val ext_init : unit -> unit", "type": "unit -> unit" } }, "ext_init_regs": { "val": { "source": "val ext_init_regs : unit -> unit", "type": "unit -> unit" } }, "ext_is_CSR_defined": { "val": { "source": "val ext_is_CSR_defined : (csreg, Privilege) -> bool", "type": "(csreg, Privilege) -> bool" } }, "ext_post_step_hook": { "val": { "source": "val ext_post_step_hook : unit -> unit", "type": "unit -> unit" } }, "ext_pre_step_hook": { "val": { "source": "val ext_pre_step_hook : unit -> unit", "type": "unit -> unit" } }, "ext_read_CSR": { "val": { "source": "val ext_read_CSR : csreg -> option(xlenbits)", "type": "csreg -> option(xlenbits)" } }, "ext_rvfi_init": { "val": { "source": "val ext_rvfi_init : unit -> unit", "type": "unit -> unit" } }, "ext_translate_exception": { "val": { "source": "val ext_translate_exception : ext_ptw_error -> ext_exc_type", "type": "ext_ptw_error -> ext_exc_type" } }, "ext_veto_disable_C": { "val": { "source": "val ext_veto_disable_C : unit -> bool", "type": "unit -> bool" } }, "ext_write_CSR": { "val": { "source": "val ext_write_CSR : (csreg, xlenbits) -> option(xlenbits)", "type": "(csreg, xlenbits) -> option(xlenbits)" } }, "ext_write_fcsr": { "val": { "source": "val ext_write_fcsr : (bits(3), bits(5)) -> unit", "type": "(bits(3), bits(5)) -> unit" } }, "ext_write_vcsr": { "val": { "source": "val ext_write_vcsr : (bits(2), bits(1)) -> unit", "type": "(bits(2), bits(1)) -> unit" } }, "extend_value": { "val": { "source": "val extend_value : forall 'n, 0 < 'n <= xlen_bytes. (bool, MemoryOpResult(bits(8 * 'n))) -> MemoryOpResult(xlenbits)", "type": "forall 'n, 0 < 'n <= xlen_bytes. (bool, MemoryOpResult(bits(8 * 'n))) -> MemoryOpResult(xlenbits)" } }, "extern_f16Add": { "val": { "source": "val extern_f16Add = {c: \"softfloat_f16add\", ocaml: \"Softfloat.f16_add\", lem: \"softfloat_f16_add\"} : (bits_rm, bits_H, bits_H) -> unit", "type": "(bits_rm, bits_H, bits_H) -> unit" } }, "extern_f16Div": { "val": { "source": "val extern_f16Div = {c: \"softfloat_f16div\", ocaml: \"Softfloat.f16_div\", lem: \"softfloat_f16_div\"} : (bits_rm, bits_H, bits_H) -> unit", "type": "(bits_rm, bits_H, bits_H) -> unit" } }, "extern_f16Eq": { "val": { "source": "val extern_f16Eq = {c: \"softfloat_f16eq\", ocaml: \"Softfloat.f16_eq\", lem: \"softfloat_f16_eq\"} : (bits_H, bits_H) -> unit", "type": "(bits_H, bits_H) -> unit" } }, "extern_f16Le": { "val": { "source": "val extern_f16Le = {c: \"softfloat_f16le\", ocaml: \"Softfloat.f16_le\", lem: \"softfloat_f16_le\"} : (bits_H, bits_H) -> unit", "type": "(bits_H, bits_H) -> unit" } }, "extern_f16Le_quiet": { "val": { "source": "val extern_f16Le_quiet = {c: \"softfloat_f16le_quiet\", ocaml: \"Softfloat.f16_le_quiet\", lem: \"softfloat_f16_le_quiet\"} : (bits_H, bits_H) -> unit", "type": "(bits_H, bits_H) -> unit" } }, "extern_f16Lt": { "val": { "source": "val extern_f16Lt = {c: \"softfloat_f16lt\", ocaml: \"Softfloat.f16_lt\", lem: \"softfloat_f16_lt\"} : (bits_H, bits_H) -> unit", "type": "(bits_H, bits_H) -> unit" } }, "extern_f16Lt_quiet": { "val": { "source": "val extern_f16Lt_quiet = {c: \"softfloat_f16lt_quiet\", ocaml: \"Softfloat.f16_lt_quiet\", lem: \"softfloat_f16_lt_quiet\"} : (bits_H, bits_H) -> unit", "type": "(bits_H, bits_H) -> unit" } }, "extern_f16Mul": { "val": { "source": "val extern_f16Mul = {c: \"softfloat_f16mul\", ocaml: \"Softfloat.f16_mul\", lem: \"softfloat_f16_mul\"} : (bits_rm, bits_H, bits_H) -> unit", "type": "(bits_rm, bits_H, bits_H) -> unit" } }, "extern_f16MulAdd": { "val": { "source": "val extern_f16MulAdd = {c: \"softfloat_f16muladd\", ocaml: \"Softfloat.f16_muladd\", lem: \"softfloat_f16_muladd\"} : (bits_rm, bits_H, bits_H, bits_H) -> unit", "type": "(bits_rm, bits_H, bits_H, bits_H) -> unit" } }, "extern_f16Sqrt": { "val": { "source": "val extern_f16Sqrt = {c: \"softfloat_f16sqrt\", ocaml: \"Softfloat.f16_sqrt\", lem: \"softfloat_f16_sqrt\"} : (bits_rm, bits_H) -> unit", "type": "(bits_rm, bits_H) -> unit" } }, "extern_f16Sub": { "val": { "source": "val extern_f16Sub = {c: \"softfloat_f16sub\", ocaml: \"Softfloat.f16_sub\", lem: \"softfloat_f16_sub\"} : (bits_rm, bits_H, bits_H) -> unit", "type": "(bits_rm, bits_H, bits_H) -> unit" } }, "extern_f16ToF32": { "val": { "source": "val extern_f16ToF32 = {c: \"softfloat_f16tof32\", ocaml: \"Softfloat.f16_to_f32\", lem: \"softfloat_f16_to_f32\"} : (bits_rm, bits_H) -> unit", "type": "(bits_rm, bits_H) -> unit" } }, "extern_f16ToF64": { "val": { "source": "val extern_f16ToF64 = {c: \"softfloat_f16tof64\", ocaml: \"Softfloat.f16_to_f64\", lem: \"softfloat_f16_to_f64\"} : (bits_rm, bits_H) -> unit", "type": "(bits_rm, bits_H) -> unit" } }, "extern_f16ToI32": { "val": { "source": "val extern_f16ToI32 = {c: \"softfloat_f16toi32\", ocaml: \"Softfloat.f16_to_i32\", lem: \"softfloat_f16_to_i32\"} : (bits_rm, bits_H) -> unit", "type": "(bits_rm, bits_H) -> unit" } }, "extern_f16ToI64": { "val": { "source": "val extern_f16ToI64 = {c: \"softfloat_f16toi64\", ocaml: \"Softfloat.f16_to_i64\", lem: \"softfloat_f16_to_i64\"} : (bits_rm, bits_H) -> unit", "type": "(bits_rm, bits_H) -> unit" } }, "extern_f16ToUi32": { "val": { "source": "val extern_f16ToUi32 = {c: \"softfloat_f16toui32\", ocaml: \"Softfloat.f16_to_ui32\", lem: \"softfloat_f16_to_ui32\"} : (bits_rm, bits_H) -> unit", "type": "(bits_rm, bits_H) -> unit" } }, "extern_f16ToUi64": { "val": { "source": "val extern_f16ToUi64 = {c: \"softfloat_f16toui64\", ocaml: \"Softfloat.f16_to_ui64\", lem: \"softfloat_f16_to_ui64\"} : (bits_rm, bits_H) -> unit", "type": "(bits_rm, bits_H) -> unit" } }, "extern_f16roundToInt": { "val": { "source": "val extern_f16roundToInt = {c: \"softfloat_f16roundToInt\", ocaml: \"Softfloat.f16_round_to_int\", lem: \"softfloat_f16_round_to_int\"} : (bits_rm, bits_H, bool) -> unit", "type": "(bits_rm, bits_H, bool) -> unit" } }, "extern_f32Add": { "val": { "source": "val extern_f32Add = {c: \"softfloat_f32add\", ocaml: \"Softfloat.f32_add\", lem: \"softfloat_f32_add\"} : (bits_rm, bits_S, bits_S) -> unit", "type": "(bits_rm, bits_S, bits_S) -> unit" } }, "extern_f32Div": { "val": { "source": "val extern_f32Div = {c: \"softfloat_f32div\", ocaml: \"Softfloat.f32_div\", lem: \"softfloat_f32_div\"} : (bits_rm, bits_S, bits_S) -> unit", "type": "(bits_rm, bits_S, bits_S) -> unit" } }, "extern_f32Eq": { "val": { "source": "val extern_f32Eq = {c: \"softfloat_f32eq\", ocaml: \"Softfloat.f32_eq\", lem: \"softfloat_f32_eq\"} : (bits_S, bits_S) -> unit", "type": "(bits_S, bits_S) -> unit" } }, "extern_f32Le": { "val": { "source": "val extern_f32Le = {c: \"softfloat_f32le\", ocaml: \"Softfloat.f32_le\", lem: \"softfloat_f32_le\"} : (bits_S, bits_S) -> unit", "type": "(bits_S, bits_S) -> unit" } }, "extern_f32Le_quiet": { "val": { "source": "val extern_f32Le_quiet = {c: \"softfloat_f32le_quiet\", ocaml: \"Softfloat.f32_le_quiet\", lem: \"softfloat_f32_le_quiet\"} : (bits_S, bits_S) -> unit", "type": "(bits_S, bits_S) -> unit" } }, "extern_f32Lt": { "val": { "source": "val extern_f32Lt = {c: \"softfloat_f32lt\", ocaml: \"Softfloat.f32_lt\", lem: \"softfloat_f32_lt\"} : (bits_S, bits_S) -> unit", "type": "(bits_S, bits_S) -> unit" } }, "extern_f32Lt_quiet": { "val": { "source": "val extern_f32Lt_quiet = {c: \"softfloat_f32lt_quiet\", ocaml: \"Softfloat.f32_lt_quiet\", lem: \"softfloat_f32_lt_quiet\"} : (bits_S, bits_S) -> unit", "type": "(bits_S, bits_S) -> unit" } }, "extern_f32Mul": { "val": { "source": "val extern_f32Mul = {c: \"softfloat_f32mul\", ocaml: \"Softfloat.f32_mul\", lem: \"softfloat_f32_mul\"} : (bits_rm, bits_S, bits_S) -> unit", "type": "(bits_rm, bits_S, bits_S) -> unit" } }, "extern_f32MulAdd": { "val": { "source": "val extern_f32MulAdd = {c: \"softfloat_f32muladd\", ocaml: \"Softfloat.f32_muladd\", lem: \"softfloat_f32_muladd\"} : (bits_rm, bits_S, bits_S, bits_S) -> unit", "type": "(bits_rm, bits_S, bits_S, bits_S) -> unit" } }, "extern_f32Sqrt": { "val": { "source": "val extern_f32Sqrt = {c: \"softfloat_f32sqrt\", ocaml: \"Softfloat.f32_sqrt\", lem: \"softfloat_f32_sqrt\"} : (bits_rm, bits_S) -> unit", "type": "(bits_rm, bits_S) -> unit" } }, "extern_f32Sub": { "val": { "source": "val extern_f32Sub = {c: \"softfloat_f32sub\", ocaml: \"Softfloat.f32_sub\", lem: \"softfloat_f32_sub\"} : (bits_rm, bits_S, bits_S) -> unit", "type": "(bits_rm, bits_S, bits_S) -> unit" } }, "extern_f32ToF16": { "val": { "source": "val extern_f32ToF16 = {c: \"softfloat_f32tof16\", ocaml: \"Softfloat.f32_to_f16\", lem: \"softfloat_f32_to_f16\"} : (bits_rm, bits_S) -> unit", "type": "(bits_rm, bits_S) -> unit" } }, "extern_f32ToF64": { "val": { "source": "val extern_f32ToF64 = {c: \"softfloat_f32tof64\", ocaml: \"Softfloat.f32_to_f64\", lem: \"softfloat_f32_to_f64\"} : (bits_rm, bits_S) -> unit", "type": "(bits_rm, bits_S) -> unit" } }, "extern_f32ToI32": { "val": { "source": "val extern_f32ToI32 = {c: \"softfloat_f32toi32\", ocaml: \"Softfloat.f32_to_i32\", lem: \"softfloat_f32_to_i32\"} : (bits_rm, bits_S) -> unit", "type": "(bits_rm, bits_S) -> unit" } }, "extern_f32ToI64": { "val": { "source": "val extern_f32ToI64 = {c: \"softfloat_f32toi64\", ocaml: \"Softfloat.f32_to_i64\", lem: \"softfloat_f32_to_i64\"} : (bits_rm, bits_S) -> unit", "type": "(bits_rm, bits_S) -> unit" } }, "extern_f32ToUi32": { "val": { "source": "val extern_f32ToUi32 = {c: \"softfloat_f32toui32\", ocaml: \"Softfloat.f32_to_ui32\", lem: \"softfloat_f32_to_ui32\"} : (bits_rm, bits_S) -> unit", "type": "(bits_rm, bits_S) -> unit" } }, "extern_f32ToUi64": { "val": { "source": "val extern_f32ToUi64 = {c: \"softfloat_f32toui64\", ocaml: \"Softfloat.f32_to_ui64\", lem: \"softfloat_f32_to_ui64\"} : (bits_rm, bits_S) -> unit", "type": "(bits_rm, bits_S) -> unit" } }, "extern_f32roundToInt": { "val": { "source": "val extern_f32roundToInt = {c: \"softfloat_f32roundToInt\", ocaml: \"Softfloat.f32_round_to_int\", lem: \"softfloat_f32_round_to_int\"} : (bits_rm, bits_S, bool) -> unit", "type": "(bits_rm, bits_S, bool) -> unit" } }, "extern_f64Add": { "val": { "source": "val extern_f64Add = {c: \"softfloat_f64add\", ocaml: \"Softfloat.f64_add\", lem: \"softfloat_f64_add\"} : (bits_rm, bits_D, bits_D) -> unit", "type": "(bits_rm, bits_D, bits_D) -> unit" } }, "extern_f64Div": { "val": { "source": "val extern_f64Div = {c: \"softfloat_f64div\", ocaml: \"Softfloat.f64_div\", lem: \"softfloat_f64_div\"} : (bits_rm, bits_D, bits_D) -> unit", "type": "(bits_rm, bits_D, bits_D) -> unit" } }, "extern_f64Eq": { "val": { "source": "val extern_f64Eq = {c: \"softfloat_f64eq\", ocaml: \"Softfloat.f64_eq\", lem: \"softfloat_f64_eq\"} : (bits_D, bits_D) -> unit", "type": "(bits_D, bits_D) -> unit" } }, "extern_f64Le": { "val": { "source": "val extern_f64Le = {c: \"softfloat_f64le\", ocaml: \"Softfloat.f64_le\", lem: \"softfloat_f64_le\"} : (bits_D, bits_D) -> unit", "type": "(bits_D, bits_D) -> unit" } }, "extern_f64Le_quiet": { "val": { "source": "val extern_f64Le_quiet = {c: \"softfloat_f64le_quiet\", ocaml: \"Softfloat.f64_le_quiet\", lem: \"softfloat_f64_le_quiet\"} : (bits_D, bits_D) -> unit", "type": "(bits_D, bits_D) -> unit" } }, "extern_f64Lt": { "val": { "source": "val extern_f64Lt = {c: \"softfloat_f64lt\", ocaml: \"Softfloat.f64_lt\", lem: \"softfloat_f64_lt\"} : (bits_D, bits_D) -> unit", "type": "(bits_D, bits_D) -> unit" } }, "extern_f64Lt_quiet": { "val": { "source": "val extern_f64Lt_quiet = {c: \"softfloat_f64lt_quiet\", ocaml: \"Softfloat.f64_lt_quiet\", lem: \"softfloat_f64_lt_quiet\"} : (bits_D, bits_D) -> unit", "type": "(bits_D, bits_D) -> unit" } }, "extern_f64Mul": { "val": { "source": "val extern_f64Mul = {c: \"softfloat_f64mul\", ocaml: \"Softfloat.f64_mul\", lem: \"softfloat_f64_mul\"} : (bits_rm, bits_D, bits_D) -> unit", "type": "(bits_rm, bits_D, bits_D) -> unit" } }, "extern_f64MulAdd": { "val": { "source": "val extern_f64MulAdd = {c: \"softfloat_f64muladd\", ocaml: \"Softfloat.f64_muladd\", lem: \"softfloat_f64_muladd\"} : (bits_rm, bits_D, bits_D, bits_D) -> unit", "type": "(bits_rm, bits_D, bits_D, bits_D) -> unit" } }, "extern_f64Sqrt": { "val": { "source": "val extern_f64Sqrt = {c: \"softfloat_f64sqrt\", ocaml: \"Softfloat.f64_sqrt\", lem: \"softfloat_f64_sqrt\"} : (bits_rm, bits_D) -> unit", "type": "(bits_rm, bits_D) -> unit" } }, "extern_f64Sub": { "val": { "source": "val extern_f64Sub = {c: \"softfloat_f64sub\", ocaml: \"Softfloat.f64_sub\", lem: \"softfloat_f64_sub\"} : (bits_rm, bits_D, bits_D) -> unit", "type": "(bits_rm, bits_D, bits_D) -> unit" } }, "extern_f64ToF16": { "val": { "source": "val extern_f64ToF16 = {c: \"softfloat_f64tof16\", ocaml: \"Softfloat.f64_to_f16\", lem: \"softfloat_f64_to_f16\"} : (bits_rm, bits_D) -> unit", "type": "(bits_rm, bits_D) -> unit" } }, "extern_f64ToF32": { "val": { "source": "val extern_f64ToF32 = {c: \"softfloat_f64tof32\", ocaml: \"Softfloat.f64_to_f32\", lem: \"softfloat_f64_to_f32\"} : (bits_rm, bits_D) -> unit", "type": "(bits_rm, bits_D) -> unit" } }, "extern_f64ToI32": { "val": { "source": "val extern_f64ToI32 = {c: \"softfloat_f64toi32\", ocaml: \"Softfloat.f64_to_i32\", lem: \"softfloat_f64_to_i32\"} : (bits_rm, bits_D) -> unit", "type": "(bits_rm, bits_D) -> unit" } }, "extern_f64ToI64": { "val": { "source": "val extern_f64ToI64 = {c: \"softfloat_f64toi64\", ocaml: \"Softfloat.f64_to_i64\", lem: \"softfloat_f64_to_i64\"} : (bits_rm, bits_D) -> unit", "type": "(bits_rm, bits_D) -> unit" } }, "extern_f64ToUi32": { "val": { "source": "val extern_f64ToUi32 = {c: \"softfloat_f64toui32\", ocaml: \"Softfloat.f64_to_ui32\", lem: \"softfloat_f64_to_ui32\"} : (bits_rm, bits_D) -> unit", "type": "(bits_rm, bits_D) -> unit" } }, "extern_f64ToUi64": { "val": { "source": "val extern_f64ToUi64 = {c: \"softfloat_f64toui64\", ocaml: \"Softfloat.f64_to_ui64\", lem: \"softfloat_f64_to_ui64\"} : (bits_rm, bits_D) -> unit", "type": "(bits_rm, bits_D) -> unit" } }, "extern_f64roundToInt": { "val": { "source": "val extern_f64roundToInt = {c: \"softfloat_f64roundToInt\", ocaml: \"Softfloat.f64_round_to_int\", lem: \"softfloat_f64_round_to_int\"} : (bits_rm, bits_D, bool) -> unit", "type": "(bits_rm, bits_D, bool) -> unit" } }, "extern_i32ToF16": { "val": { "source": "val extern_i32ToF16 = {c: \"softfloat_i32tof16\", ocaml: \"Softfloat.i32_to_f16\", lem: \"softfloat_i32_to_f16\"} : (bits_rm, bits_W) -> unit", "type": "(bits_rm, bits_W) -> unit" } }, "extern_i32ToF32": { "val": { "source": "val extern_i32ToF32 = {c: \"softfloat_i32tof32\", ocaml: \"Softfloat.i32_to_f32\", lem: \"softfloat_i32_to_f32\"} : (bits_rm, bits_W) -> unit", "type": "(bits_rm, bits_W) -> unit" } }, "extern_i32ToF64": { "val": { "source": "val extern_i32ToF64 = {c: \"softfloat_i32tof64\", ocaml: \"Softfloat.i32_to_f64\", lem: \"softfloat_i32_to_f64\"} : (bits_rm, bits_W) -> unit", "type": "(bits_rm, bits_W) -> unit" } }, "extern_i64ToF16": { "val": { "source": "val extern_i64ToF16 = {c: \"softfloat_i64tof16\", ocaml: \"Softfloat.i64_to_f16\", lem: \"softfloat_i64_to_f16\"} : (bits_rm, bits_L) -> unit", "type": "(bits_rm, bits_L) -> unit" } }, "extern_i64ToF32": { "val": { "source": "val extern_i64ToF32 = {c: \"softfloat_i64tof32\", ocaml: \"Softfloat.i64_to_f32\", lem: \"softfloat_i64_to_f32\"} : (bits_rm, bits_L) -> unit", "type": "(bits_rm, bits_L) -> unit" } }, "extern_i64ToF64": { "val": { "source": "val extern_i64ToF64 = {c: \"softfloat_i64tof64\", ocaml: \"Softfloat.i64_to_f64\", lem: \"softfloat_i64_to_f64\"} : (bits_rm, bits_L) -> unit", "type": "(bits_rm, bits_L) -> unit" } }, "extern_ui32ToF16": { "val": { "source": "val extern_ui32ToF16 = {c: \"softfloat_ui32tof16\", ocaml: \"Softfloat.ui32_to_f16\", lem: \"softfloat_ui32_to_f16\"} : (bits_rm, bits_WU) -> unit", "type": "(bits_rm, bits_WU) -> unit" } }, "extern_ui32ToF32": { "val": { "source": "val extern_ui32ToF32 = {c: \"softfloat_ui32tof32\", ocaml: \"Softfloat.ui32_to_f32\", lem: \"softfloat_ui32_to_f32\"} : (bits_rm, bits_WU) -> unit", "type": "(bits_rm, bits_WU) -> unit" } }, "extern_ui32ToF64": { "val": { "source": "val extern_ui32ToF64 = {c: \"softfloat_ui32tof64\", ocaml: \"Softfloat.ui32_to_f64\", lem: \"softfloat_ui32_to_f64\"} : (bits_rm, bits_WU) -> unit", "type": "(bits_rm, bits_WU) -> unit" } }, "extern_ui64ToF16": { "val": { "source": "val extern_ui64ToF16 = {c: \"softfloat_ui64tof16\", ocaml: \"Softfloat.ui64_to_f16\", lem: \"softfloat_ui64_to_f16\"} : (bits_rm, bits_L) -> unit", "type": "(bits_rm, bits_L) -> unit" } }, "extern_ui64ToF32": { "val": { "source": "val extern_ui64ToF32 = {c: \"softfloat_ui64tof32\", ocaml: \"Softfloat.ui64_to_f32\", lem: \"softfloat_ui64_to_f32\"} : (bits_rm, bits_L) -> unit", "type": "(bits_rm, bits_L) -> unit" } }, "extern_ui64ToF64": { "val": { "source": "val extern_ui64ToF64 = {c: \"softfloat_ui64tof64\", ocaml: \"Softfloat.ui64_to_f64\", lem: \"softfloat_ui64_to_f64\"} : (bits_rm, bits_LU) -> unit", "type": "(bits_rm, bits_LU) -> unit" } }, "extop_zbb_of_num": { "val": { "source": "val extop_zbb_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> extop_zbb", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> extop_zbb" } }, "f_bin_op_D_of_num": { "val": { "source": "val f_bin_op_D_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> f_bin_op_D", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> f_bin_op_D" } }, "f_bin_op_H_of_num": { "val": { "source": "val f_bin_op_H_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> f_bin_op_H", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> f_bin_op_H" } }, "f_bin_op_S_of_num": { "val": { "source": "val f_bin_op_S_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> f_bin_op_S", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> f_bin_op_S" } }, "f_bin_rm_op_D_of_num": { "val": { "source": "val f_bin_rm_op_D_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_bin_rm_op_D", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_bin_rm_op_D" } }, "f_bin_rm_op_H_of_num": { "val": { "source": "val f_bin_rm_op_H_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_bin_rm_op_H", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_bin_rm_op_H" } }, "f_bin_rm_op_S_of_num": { "val": { "source": "val f_bin_rm_op_S_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_bin_rm_op_S", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_bin_rm_op_S" } }, "f_bin_rm_type_mnemonic_D": { "val": { "source": "val f_bin_rm_type_mnemonic_D : f_bin_rm_op_D <-> string", "type": "f_bin_rm_op_D <-> string" } }, "f_bin_rm_type_mnemonic_H": { "val": { "source": "val f_bin_rm_type_mnemonic_H : f_bin_rm_op_H <-> string", "type": "f_bin_rm_op_H <-> string" } }, "f_bin_rm_type_mnemonic_S": { "val": { "source": "val f_bin_rm_type_mnemonic_S : f_bin_rm_op_S <-> string", "type": "f_bin_rm_op_S <-> string" } }, "f_bin_type_mnemonic_D": { "val": { "source": "val f_bin_type_mnemonic_D : f_bin_op_D <-> string", "type": "f_bin_op_D <-> string" } }, "f_bin_type_mnemonic_H": { "val": { "source": "val f_bin_type_mnemonic_H : f_bin_op_H <-> string", "type": "f_bin_op_H <-> string" } }, "f_bin_type_mnemonic_S": { "val": { "source": "val f_bin_type_mnemonic_S : f_bin_op_S <-> string", "type": "f_bin_op_S <-> string" } }, "f_is_NaN": { "val": { "source": "val f_is_NaN : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_NaN_D": { "val": { "source": "val f_is_NaN_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_NaN_H": { "val": { "source": "val f_is_NaN_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_NaN_S": { "val": { "source": "val f_is_NaN_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_QNaN": { "val": { "source": "val f_is_QNaN : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_QNaN_D": { "val": { "source": "val f_is_QNaN_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_QNaN_H": { "val": { "source": "val f_is_QNaN_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_QNaN_S": { "val": { "source": "val f_is_QNaN_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_SNaN": { "val": { "source": "val f_is_SNaN : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_SNaN_D": { "val": { "source": "val f_is_SNaN_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_SNaN_H": { "val": { "source": "val f_is_SNaN_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_SNaN_S": { "val": { "source": "val f_is_SNaN_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_neg_inf": { "val": { "source": "val f_is_neg_inf : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_neg_inf_D": { "val": { "source": "val f_is_neg_inf_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_neg_inf_H": { "val": { "source": "val f_is_neg_inf_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_neg_inf_S": { "val": { "source": "val f_is_neg_inf_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_neg_norm": { "val": { "source": "val f_is_neg_norm : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_neg_norm_D": { "val": { "source": "val f_is_neg_norm_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_neg_norm_H": { "val": { "source": "val f_is_neg_norm_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_neg_norm_S": { "val": { "source": "val f_is_neg_norm_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_neg_subnorm": { "val": { "source": "val f_is_neg_subnorm : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_neg_subnorm_D": { "val": { "source": "val f_is_neg_subnorm_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_neg_subnorm_H": { "val": { "source": "val f_is_neg_subnorm_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_neg_subnorm_S": { "val": { "source": "val f_is_neg_subnorm_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_neg_zero": { "val": { "source": "val f_is_neg_zero : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_neg_zero_D": { "val": { "source": "val f_is_neg_zero_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_neg_zero_H": { "val": { "source": "val f_is_neg_zero_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_neg_zero_S": { "val": { "source": "val f_is_neg_zero_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_pos_inf": { "val": { "source": "val f_is_pos_inf : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_pos_inf_D": { "val": { "source": "val f_is_pos_inf_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_pos_inf_H": { "val": { "source": "val f_is_pos_inf_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_pos_inf_S": { "val": { "source": "val f_is_pos_inf_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_pos_norm": { "val": { "source": "val f_is_pos_norm : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_pos_norm_D": { "val": { "source": "val f_is_pos_norm_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_pos_norm_H": { "val": { "source": "val f_is_pos_norm_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_pos_norm_S": { "val": { "source": "val f_is_pos_norm_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_pos_subnorm": { "val": { "source": "val f_is_pos_subnorm : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_pos_subnorm_D": { "val": { "source": "val f_is_pos_subnorm_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_pos_subnorm_H": { "val": { "source": "val f_is_pos_subnorm_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_pos_subnorm_S": { "val": { "source": "val f_is_pos_subnorm_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_is_pos_zero": { "val": { "source": "val f_is_pos_zero : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bool" } }, "f_is_pos_zero_D": { "val": { "source": "val f_is_pos_zero_D : bits(64) -> bool", "type": "bits(64) -> bool" } }, "f_is_pos_zero_H": { "val": { "source": "val f_is_pos_zero_H : bits(16) -> bool", "type": "bits(16) -> bool" } }, "f_is_pos_zero_S": { "val": { "source": "val f_is_pos_zero_S : bits(32) -> bool", "type": "bits(32) -> bool" } }, "f_madd_op_D_of_num": { "val": { "source": "val f_madd_op_D_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_madd_op_D", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_madd_op_D" } }, "f_madd_op_H_of_num": { "val": { "source": "val f_madd_op_H_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_madd_op_H", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_madd_op_H" } }, "f_madd_op_S_of_num": { "val": { "source": "val f_madd_op_S_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_madd_op_S", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> f_madd_op_S" } }, "f_madd_type_mnemonic_D": { "val": { "source": "val f_madd_type_mnemonic_D : f_madd_op_D <-> string", "type": "f_madd_op_D <-> string" } }, "f_madd_type_mnemonic_H": { "val": { "source": "val f_madd_type_mnemonic_H : f_madd_op_H <-> string", "type": "f_madd_op_H <-> string" } }, "f_madd_type_mnemonic_S": { "val": { "source": "val f_madd_type_mnemonic_S : f_madd_op_S <-> string", "type": "f_madd_op_S <-> string" } }, "f_un_op_D_of_num": { "val": { "source": "val f_un_op_D_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> f_un_op_D", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> f_un_op_D" } }, "f_un_op_H_of_num": { "val": { "source": "val f_un_op_H_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> f_un_op_H", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> f_un_op_H" } }, "f_un_op_S_of_num": { "val": { "source": "val f_un_op_S_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> f_un_op_S", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> f_un_op_S" } }, "f_un_rm_op_D_of_num": { "val": { "source": "val f_un_rm_op_D_of_num : forall 'e, (0 <= 'e & 'e <= 10). int('e) -> f_un_rm_op_D", "type": "forall 'e, (0 <= 'e & 'e <= 10). int('e) -> f_un_rm_op_D" } }, "f_un_rm_op_H_of_num": { "val": { "source": "val f_un_rm_op_H_of_num : forall 'e, (0 <= 'e & 'e <= 12). int('e) -> f_un_rm_op_H", "type": "forall 'e, (0 <= 'e & 'e <= 12). int('e) -> f_un_rm_op_H" } }, "f_un_rm_op_S_of_num": { "val": { "source": "val f_un_rm_op_S_of_num : forall 'e, (0 <= 'e & 'e <= 8). int('e) -> f_un_rm_op_S", "type": "forall 'e, (0 <= 'e & 'e <= 8). int('e) -> f_un_rm_op_S" } }, "f_un_rm_type_mnemonic_D": { "val": { "source": "val f_un_rm_type_mnemonic_D : f_un_rm_op_D <-> string", "type": "f_un_rm_op_D <-> string" } }, "f_un_rm_type_mnemonic_H": { "val": { "source": "val f_un_rm_type_mnemonic_H : f_un_rm_op_H <-> string", "type": "f_un_rm_op_H <-> string" } }, "f_un_rm_type_mnemonic_S": { "val": { "source": "val f_un_rm_type_mnemonic_S : f_un_rm_op_S <-> string", "type": "f_un_rm_op_S <-> string" } }, "f_un_type_mnemonic_D": { "val": { "source": "val f_un_type_mnemonic_D : f_un_op_D <-> string", "type": "f_un_op_D <-> string" } }, "f_un_type_mnemonic_H": { "val": { "source": "val f_un_type_mnemonic_H : f_un_op_H <-> string", "type": "f_un_op_H <-> string" } }, "f_un_type_mnemonic_S": { "val": { "source": "val f_un_type_mnemonic_S : f_un_op_S <-> string", "type": "f_un_op_S <-> string" } }, "fcvtmod_helper": { "val": { "source": "val fcvtmod_helper : bits(64) -> (bits(5), bits(32))", "type": "bits(64) -> (bits(5), bits(32))" } }, "fdiv_int": { "val": { "source": "val fdiv_int : (int, int) -> int", "type": "(int, int) -> int" } }, "fence_bits": { "val": { "source": "val fence_bits : bitvector(4) <-> string", "type": "bitvector(4) <-> string" } }, "feq_quiet_D": { "val": { "source": "val feq_quiet_D : (bits(64), bits (64)) -> (bool, bits(5))", "type": "(bits(64), bits (64)) -> (bool, bits(5))" } }, "feq_quiet_S": { "val": { "source": "val feq_quiet_S : (bits(32), bits (32)) -> (bool, bits(5))", "type": "(bits(32), bits (32)) -> (bool, bits(5))" } }, "fetch": { "val": { "source": "val fetch : unit -> FetchResult", "type": "unit -> FetchResult" } }, "findPendingInterrupt": { "val": { "source": "val findPendingInterrupt : xlenbits -> option(InterruptType)", "type": "xlenbits -> option(InterruptType)" } }, "fle_D": { "val": { "source": "val fle_D : (bits(64), bits (64), bool) -> (bool, bits(5))", "type": "(bits(64), bits (64), bool) -> (bool, bits(5))" } }, "fle_H": { "val": { "source": "val fle_H : (bits(16), bits (16), bool) -> (bool, bits(5))", "type": "(bits(16), bits (16), bool) -> (bool, bits(5))" } }, "fle_S": { "val": { "source": "val fle_S : (bits(32), bits (32), bool) -> (bool, bits(5))", "type": "(bits(32), bits (32), bool) -> (bool, bits(5))" } }, "flt_D": { "val": { "source": "val flt_D : (bits(64), bits (64), bool) -> (bool, bits(5))", "type": "(bits(64), bits (64), bool) -> (bool, bits(5))" } }, "flt_S": { "val": { "source": "val flt_S : (bits(32), bits (32), bool) -> (bool, bits(5))", "type": "(bits(32), bits (32), bool) -> (bool, bits(5))" } }, "flush_TLB": { "val": { "source": "val flush_TLB : (option(xlenbits), option(xlenbits)) -> unit", "type": "(option(xlenbits), option(xlenbits)) -> unit" } }, "flush_TLB_Entry": { "val": { "source": "val flush_TLB_Entry : (TLB_Entry, option(asidbits), option(bits(64))) -> bool", "type": "(TLB_Entry, option(asidbits), option(bits(64))) -> bool" } }, "fmake_D": { "val": { "source": "val fmake_D : (bits(1), bits(11), bits(52)) -> bits(64)", "type": "(bits(1), bits(11), bits(52)) -> bits(64)" } }, "fmake_H": { "val": { "source": "val fmake_H : (bits(1), bits(5), bits(10)) -> bits(16)", "type": "(bits(1), bits(5), bits(10)) -> bits(16)" } }, "fmake_S": { "val": { "source": "val fmake_S : (bits(1), bits(8), bits(23)) -> bits(32)", "type": "(bits(1), bits(8), bits(23)) -> bits(32)" } }, "fmod_int": { "val": { "source": "val fmod_int : (int, int) -> int", "type": "(int, int) -> int" } }, "fp_add": { "val": { "source": "val fp_add: forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m)" } }, "fp_class": { "val": { "source": "val fp_class : forall 'm, 'm in {16, 32, 64}. bits('m) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bits('m)" } }, "fp_div": { "val": { "source": "val fp_div : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m)" } }, "fp_eq": { "val": { "source": "val fp_eq : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool" } }, "fp_ge": { "val": { "source": "val fp_ge : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool" } }, "fp_gt": { "val": { "source": "val fp_gt : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool" } }, "fp_le": { "val": { "source": "val fp_le : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool" } }, "fp_lt": { "val": { "source": "val fp_lt : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool" } }, "fp_max": { "val": { "source": "val fp_max : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bits('m)" } }, "fp_min": { "val": { "source": "val fp_min : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bits('m)" } }, "fp_mul": { "val": { "source": "val fp_mul : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m)" } }, "fp_muladd": { "val": { "source": "val fp_muladd : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m)" } }, "fp_mulsub": { "val": { "source": "val fp_mulsub : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m)" } }, "fp_nmuladd": { "val": { "source": "val fp_nmuladd : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m)" } }, "fp_nmulsub": { "val": { "source": "val fp_nmulsub : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m)" } }, "fp_sub": { "val": { "source": "val fp_sub: forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m)" } }, "fp_widen": { "val": { "source": "val fp_widen : forall 'm, 'm in {16, 32}. bits('m) -> bits('m * 2)", "type": "forall 'm, 'm in {16, 32}. bits('m) -> bits('m * 2)" } }, "freg_name": { "val": { "source": "val freg_name : bits(5) <-> string", "type": "bits(5) <-> string" } }, "freg_name_abi": { "val": { "source": "val freg_name_abi : regidx <-> string", "type": "regidx <-> string" } }, "freg_or_reg_name": { "val": { "source": "val freg_or_reg_name : bits(5) <-> string", "type": "bits(5) <-> string" } }, "fregval_from_freg": { "val": { "source": "val fregval_from_freg : fregtype -> flenbits", "type": "fregtype -> flenbits" } }, "fregval_into_freg": { "val": { "source": "val fregval_into_freg : flenbits -> fregtype", "type": "flenbits -> fregtype" } }, "frm_mnemonic": { "val": { "source": "val frm_mnemonic : rounding_mode <-> string", "type": "rounding_mode <-> string" } }, "fsplit_D": { "val": { "source": "val fsplit_D : bits(64) -> (bits(1), bits(11), bits(52))", "type": "bits(64) -> (bits(1), bits(11), bits(52))" } }, "fsplit_H": { "val": { "source": "val fsplit_H : bits(16) -> (bits(1), bits(5), bits(10))", "type": "bits(16) -> (bits(1), bits(5), bits(10))" } }, "fsplit_S": { "val": { "source": "val fsplit_S : bits(32) -> (bits(1), bits(8), bits(23))", "type": "bits(32) -> (bits(1), bits(8), bits(23))" } }, "fvffunct6_of_num": { "val": { "source": "val fvffunct6_of_num : forall 'e, (0 <= 'e & 'e <= 12). int('e) -> fvffunct6", "type": "forall 'e, (0 <= 'e & 'e <= 12). int('e) -> fvffunct6" } }, "fvfmafunct6_of_num": { "val": { "source": "val fvfmafunct6_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> fvfmafunct6", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> fvfmafunct6" } }, "fvfmatype_mnemonic": { "val": { "source": "val fvfmatype_mnemonic : fvfmafunct6 <-> string", "type": "fvfmafunct6 <-> string" } }, "fvfmfunct6_of_num": { "val": { "source": "val fvfmfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 5). int('e) -> fvfmfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 5). int('e) -> fvfmfunct6" } }, "fvfmtype_mnemonic": { "val": { "source": "val fvfmtype_mnemonic : fvfmfunct6 <-> string", "type": "fvfmfunct6 <-> string" } }, "fvftype_mnemonic": { "val": { "source": "val fvftype_mnemonic : fvffunct6 <-> string", "type": "fvffunct6 <-> string" } }, "fvvfunct6_of_num": { "val": { "source": "val fvvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 8). int('e) -> fvvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 8). int('e) -> fvvfunct6" } }, "fvvmafunct6_of_num": { "val": { "source": "val fvvmafunct6_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> fvvmafunct6", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> fvvmafunct6" } }, "fvvmatype_mnemonic": { "val": { "source": "val fvvmatype_mnemonic : fvvmafunct6 <-> string", "type": "fvvmafunct6 <-> string" } }, "fvvmfunct6_of_num": { "val": { "source": "val fvvmfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> fvvmfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> fvvmfunct6" } }, "fvvmtype_mnemonic": { "val": { "source": "val fvvmtype_mnemonic : fvvmfunct6 <-> string", "type": "fvvmfunct6 <-> string" } }, "fvvtype_mnemonic": { "val": { "source": "val fvvtype_mnemonic : fvvfunct6 <-> string", "type": "fvvfunct6 <-> string" } }, "fwffunct6_of_num": { "val": { "source": "val fwffunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> fwffunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> fwffunct6" } }, "fwftype_mnemonic": { "val": { "source": "val fwftype_mnemonic : fwffunct6 <-> string", "type": "fwffunct6 <-> string" } }, "fwvffunct6_of_num": { "val": { "source": "val fwvffunct6_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> fwvffunct6", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> fwvffunct6" } }, "fwvfmafunct6_of_num": { "val": { "source": "val fwvfmafunct6_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> fwvfmafunct6", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> fwvfmafunct6" } }, "fwvfmatype_mnemonic": { "val": { "source": "val fwvfmatype_mnemonic : fwvfmafunct6 <-> string", "type": "fwvfmafunct6 <-> string" } }, "fwvftype_mnemonic": { "val": { "source": "val fwvftype_mnemonic : fwvffunct6 <-> string", "type": "fwvffunct6 <-> string" } }, "fwvfunct6_of_num": { "val": { "source": "val fwvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> fwvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> fwvfunct6" } }, "fwvtype_mnemonic": { "val": { "source": "val fwvtype_mnemonic : fwvfunct6 <-> string", "type": "fwvfunct6 <-> string" } }, "fwvvfunct6_of_num": { "val": { "source": "val fwvvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> fwvvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> fwvvfunct6" } }, "fwvvmafunct6_of_num": { "val": { "source": "val fwvvmafunct6_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> fwvvmafunct6", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> fwvvmafunct6" } }, "fwvvmatype_mnemonic": { "val": { "source": "val fwvvmatype_mnemonic : fwvvmafunct6 <-> string", "type": "fwvvmafunct6 <-> string" } }, "fwvvtype_mnemonic": { "val": { "source": "val fwvvtype_mnemonic : fwvvfunct6 <-> string", "type": "fwvvfunct6 <-> string" } }, "getPendingSet": { "val": { "source": "val getPendingSet : Privilege -> option((xlenbits, Privilege))", "type": "Privilege -> option((xlenbits, Privilege))" } }, "get_16_random_bits": { "val": { "source": "val get_16_random_bits = {\n ocaml: \"Platform.get_16_random_bits\",\n interpreter: \"Platform.get_16_random_bits\",\n c: \"plat_get_16_random_bits\",\n lem: \"plat_get_16_random_bits\"\n} : unit -> bits(16)", "type": "unit -> bits(16)" } }, "get_arch_pc": { "val": { "source": "val get_arch_pc : unit -> xlenbits", "type": "unit -> xlenbits" } }, "get_config_print_instr": { "val": { "source": "val get_config_print_instr = {ocaml: \"Platform.get_config_print_instr\", c:\"get_config_print_instr\"} : unit -> bool", "type": "unit -> bool" } }, "get_config_print_mem": { "val": { "source": "val get_config_print_mem = {ocaml: \"Platform.get_config_print_mem\", c:\"get_config_print_mem\"} : unit -> bool", "type": "unit -> bool" } }, "get_config_print_platform": { "val": { "source": "val get_config_print_platform = {ocaml: \"Platform.get_config_print_platform\", c:\"get_config_print_platform\"} : unit -> bool", "type": "unit -> bool" } }, "get_config_print_reg": { "val": { "source": "val get_config_print_reg = {ocaml: \"Platform.get_config_print_reg\", c:\"get_config_print_reg\"} : unit -> bool", "type": "unit -> bool" } }, "get_elen_pow": { "val": { "source": "val get_elen_pow : unit -> {|5, 6|}", "type": "unit -> {|5, 6|}" } }, "get_end_element": { "val": { "source": "val get_end_element : unit -> int", "type": "unit -> int" } }, "get_fixed_rounding_incr": { "val": { "source": "val get_fixed_rounding_incr : forall ('m 'n : Int), ('m > 0 & 'n >= 0). (bits('m), int('n)) -> bits(1)", "type": "forall ('m 'n : Int), ('m > 0 & 'n >= 0). (bits('m), int('n)) -> bits(1)" } }, "get_fp_rounding_mode": { "val": { "source": "val get_fp_rounding_mode : unit -> rounding_mode", "type": "unit -> rounding_mode" } }, "get_lmul_pow": { "val": { "source": "val get_lmul_pow : unit -> {|-3, -2, -1, 0, 1, 2, 3|}", "type": "unit -> {|-3, -2, -1, 0, 1, 2, 3|}" } }, "get_mstatus_SXL": { "val": { "source": "val get_mstatus_SXL : Mstatus -> arch_xlen", "type": "Mstatus -> arch_xlen" } }, "get_mstatus_UXL": { "val": { "source": "val get_mstatus_UXL : Mstatus -> arch_xlen", "type": "Mstatus -> arch_xlen" } }, "get_mtvec": { "val": { "source": "val get_mtvec : unit -> xlenbits", "type": "unit -> xlenbits" } }, "get_next_pc": { "val": { "source": "val get_next_pc : unit -> xlenbits", "type": "unit -> xlenbits" } }, "get_num_elem": { "val": { "source": "val get_num_elem : (int, int) -> nat", "type": "(int, int) -> nat" } }, "get_scalar": { "val": { "source": "val get_scalar : forall 'm, 'm >= 8. (regidx, int('m)) -> bits('m)", "type": "forall 'm, 'm >= 8. (regidx, int('m)) -> bits('m)" } }, "get_scalar_fp": { "val": { "source": "val get_scalar_fp : forall 'n, 'n in {16, 32, 64}. (regidx, int('n)) -> bits('n)", "type": "forall 'n, 'n in {16, 32, 64}. (regidx, int('n)) -> bits('n)" } }, "get_sew": { "val": { "source": "val get_sew : unit -> {|8, 16, 32, 64|}", "type": "unit -> {|8, 16, 32, 64|}" } }, "get_sew_bytes": { "val": { "source": "val get_sew_bytes : unit -> {|1, 2, 4, 8|}", "type": "unit -> {|1, 2, 4, 8|}" } }, "get_sew_pow": { "val": { "source": "val get_sew_pow : unit -> {|3, 4, 5, 6|}", "type": "unit -> {|3, 4, 5, 6|}" } }, "get_shift_amount": { "val": { "source": "val get_shift_amount : forall 'n 'm, 0 <= 'n & 'm in {8, 16, 32, 64}. (bits('n), int('m)) -> nat", "type": "forall 'n 'm, 0 <= 'n & 'm in {8, 16, 32, 64}. (bits('n), int('m)) -> nat" } }, "get_slice_int": { "val": { "source": "val get_slice_int = pure {_: \"get_slice_int\"}: forall 'w. (int('w), int, int) -> bits('w)", "type": "forall 'w. (int('w), int, int) -> bits('w)" } }, "get_sstatus_UXL": { "val": { "source": "val get_sstatus_UXL : Sstatus -> arch_xlen", "type": "Sstatus -> arch_xlen" } }, "get_start_element": { "val": { "source": "val get_start_element : unit -> nat", "type": "unit -> nat" } }, "get_stvec": { "val": { "source": "val get_stvec : unit -> xlenbits", "type": "unit -> xlenbits" } }, "get_utvec": { "val": { "source": "val get_utvec : unit -> xlenbits", "type": "unit -> xlenbits" } }, "get_vlen_pow": { "val": { "source": "val get_vlen_pow : unit -> {|5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16|}", "type": "unit -> {|5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16|}" } }, "get_vtype_vma": { "val": { "source": "val get_vtype_vma : unit -> agtype", "type": "unit -> agtype" } }, "get_vtype_vta": { "val": { "source": "val get_vtype_vta : unit -> agtype", "type": "unit -> agtype" } }, "get_xret_target": { "val": { "source": "val get_xret_target : Privilege -> xlenbits", "type": "Privilege -> xlenbits" } }, "getbyte": { "val": { "source": "val getbyte : (bits(64), int) -> bits(8)", "type": "(bits(64), int) -> bits(8)" } }, "gfmul": { "val": { "source": "val gfmul : (bits(8), bits(4)) -> bits(8)", "type": "(bits(8), bits(4)) -> bits(8)" } }, "gt_int": { "val": { "source": "val gt_int = pure {coq: \"Z.gtb\", _: \"gt\"}: forall 'n 'm. (int('n), int('m)) -> bool('n > 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> bool('n > 'm)" } }, "gteq_int": { "val": { "source": "val gteq_int = pure {coq: \"Z.geb\", _: \"gteq\"}: forall 'n 'm. (int('n), int('m)) -> bool('n >= 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> bool('n >= 'm)" } }, "handle_exception": { "val": { "source": "val handle_exception : ExceptionType -> unit", "type": "ExceptionType -> unit" } }, "handle_illegal": { "val": { "source": "val handle_illegal : unit -> unit", "type": "unit -> unit" } }, "handle_interrupt": { "val": { "source": "val handle_interrupt : (InterruptType, Privilege) -> unit", "type": "(InterruptType, Privilege) -> unit" } }, "handle_mem_exception": { "val": { "source": "val handle_mem_exception : (xlenbits, ExceptionType) -> unit", "type": "(xlenbits, ExceptionType) -> unit" } }, "handle_trap_extension": { "val": { "source": "val handle_trap_extension : (Privilege, xlenbits, option(unit)) -> unit", "type": "(Privilege, xlenbits, option(unit)) -> unit" } }, "haveAtomics": { "val": { "source": "val haveAtomics : unit -> bool", "type": "unit -> bool" } }, "haveDExt": { "val": { "source": "val haveDExt : unit -> bool", "type": "unit -> bool" } }, "haveDoubleFPU": { "val": { "source": "val haveDoubleFPU : unit -> bool", "type": "unit -> bool" } }, "haveFExt": { "val": { "source": "val haveFExt : unit -> bool", "type": "unit -> bool" } }, "haveHalfFPU": { "val": { "source": "val haveHalfFPU : unit -> bool", "type": "unit -> bool" } }, "haveMulDiv": { "val": { "source": "val haveMulDiv : unit -> bool", "type": "unit -> bool" } }, "haveNExt": { "val": { "source": "val haveNExt : unit -> bool", "type": "unit -> bool" } }, "haveRVC": { "val": { "source": "val haveRVC : unit -> bool", "type": "unit -> bool" } }, "haveSingleFPU": { "val": { "source": "val haveSingleFPU : unit -> bool", "type": "unit -> bool" } }, "haveSupMode": { "val": { "source": "val haveSupMode : unit -> bool", "type": "unit -> bool" } }, "haveUsrMode": { "val": { "source": "val haveUsrMode : unit -> bool", "type": "unit -> bool" } }, "haveVExt": { "val": { "source": "val haveVExt : unit -> bool", "type": "unit -> bool" } }, "haveZba": { "val": { "source": "val haveZba : unit -> bool", "type": "unit -> bool" } }, "haveZbb": { "val": { "source": "val haveZbb : unit -> bool", "type": "unit -> bool" } }, "haveZbc": { "val": { "source": "val haveZbc : unit -> bool", "type": "unit -> bool" } }, "haveZbkb": { "val": { "source": "val haveZbkb : unit -> bool", "type": "unit -> bool" } }, "haveZbkc": { "val": { "source": "val haveZbkc : unit -> bool", "type": "unit -> bool" } }, "haveZbkx": { "val": { "source": "val haveZbkx : unit -> bool", "type": "unit -> bool" } }, "haveZbs": { "val": { "source": "val haveZbs : unit -> bool", "type": "unit -> bool" } }, "haveZdinx": { "val": { "source": "val haveZdinx : unit -> bool", "type": "unit -> bool" } }, "haveZfa": { "val": { "source": "val haveZfa : unit -> bool", "type": "unit -> bool" } }, "haveZfh": { "val": { "source": "val haveZfh : unit -> bool", "type": "unit -> bool" } }, "haveZfinx": { "val": { "source": "val haveZfinx : unit -> bool", "type": "unit -> bool" } }, "haveZhinx": { "val": { "source": "val haveZhinx : unit -> bool", "type": "unit -> bool" } }, "haveZicond": { "val": { "source": "val haveZicond : unit -> bool", "type": "unit -> bool" } }, "haveZknd": { "val": { "source": "val haveZknd : unit -> bool", "type": "unit -> bool" } }, "haveZkne": { "val": { "source": "val haveZkne : unit -> bool", "type": "unit -> bool" } }, "haveZknh": { "val": { "source": "val haveZknh : unit -> bool", "type": "unit -> bool" } }, "haveZkr": { "val": { "source": "val haveZkr : unit -> bool", "type": "unit -> bool" } }, "haveZksed": { "val": { "source": "val haveZksed : unit -> bool", "type": "unit -> bool" } }, "haveZksh": { "val": { "source": "val haveZksh : unit -> bool", "type": "unit -> bool" } }, "haveZmmul": { "val": { "source": "val haveZmmul : unit -> bool", "type": "unit -> bool" } }, "hex_bits": { "val": { "source": "val hex_bits : forall 'n, 'n > 0. bits('n) <-> (int('n), string)", "type": "forall 'n, 'n > 0. bits('n) <-> (int('n), string)" } }, "hex_bits_1": { "val": { "source": "val hex_bits_1 : bitvector(1) <-> string", "type": "bitvector(1) <-> string" } }, "hex_bits_10": { "val": { "source": "val hex_bits_10 : bitvector(10) <-> string", "type": "bitvector(10) <-> string" } }, "hex_bits_11": { "val": { "source": "val hex_bits_11 : bitvector(11) <-> string", "type": "bitvector(11) <-> string" } }, "hex_bits_12": { "val": { "source": "val hex_bits_12 : bitvector(12) <-> string", "type": "bitvector(12) <-> string" } }, "hex_bits_13": { "val": { "source": "val hex_bits_13 : bitvector(13) <-> string", "type": "bitvector(13) <-> string" } }, "hex_bits_14": { "val": { "source": "val hex_bits_14 : bitvector(14) <-> string", "type": "bitvector(14) <-> string" } }, "hex_bits_15": { "val": { "source": "val hex_bits_15 : bitvector(15) <-> string", "type": "bitvector(15) <-> string" } }, "hex_bits_16": { "val": { "source": "val hex_bits_16 : bitvector(16) <-> string", "type": "bitvector(16) <-> string" } }, "hex_bits_17": { "val": { "source": "val hex_bits_17 : bitvector(17) <-> string", "type": "bitvector(17) <-> string" } }, "hex_bits_18": { "val": { "source": "val hex_bits_18 : bitvector(18) <-> string", "type": "bitvector(18) <-> string" } }, "hex_bits_19": { "val": { "source": "val hex_bits_19 : bitvector(19) <-> string", "type": "bitvector(19) <-> string" } }, "hex_bits_2": { "val": { "source": "val hex_bits_2 : bitvector(2) <-> string", "type": "bitvector(2) <-> string" } }, "hex_bits_20": { "val": { "source": "val hex_bits_20 : bitvector(20) <-> string", "type": "bitvector(20) <-> string" } }, "hex_bits_21": { "val": { "source": "val hex_bits_21 : bitvector(21) <-> string", "type": "bitvector(21) <-> string" } }, "hex_bits_22": { "val": { "source": "val hex_bits_22 : bitvector(22) <-> string", "type": "bitvector(22) <-> string" } }, "hex_bits_23": { "val": { "source": "val hex_bits_23 : bitvector(23) <-> string", "type": "bitvector(23) <-> string" } }, "hex_bits_24": { "val": { "source": "val hex_bits_24 : bitvector(24) <-> string", "type": "bitvector(24) <-> string" } }, "hex_bits_25": { "val": { "source": "val hex_bits_25 : bitvector(25) <-> string", "type": "bitvector(25) <-> string" } }, "hex_bits_26": { "val": { "source": "val hex_bits_26 : bitvector(26) <-> string", "type": "bitvector(26) <-> string" } }, "hex_bits_27": { "val": { "source": "val hex_bits_27 : bitvector(27) <-> string", "type": "bitvector(27) <-> string" } }, "hex_bits_28": { "val": { "source": "val hex_bits_28 : bitvector(28) <-> string", "type": "bitvector(28) <-> string" } }, "hex_bits_29": { "val": { "source": "val hex_bits_29 : bitvector(29) <-> string", "type": "bitvector(29) <-> string" } }, "hex_bits_3": { "val": { "source": "val hex_bits_3 : bitvector(3) <-> string", "type": "bitvector(3) <-> string" } }, "hex_bits_30": { "val": { "source": "val hex_bits_30 : bitvector(30) <-> string", "type": "bitvector(30) <-> string" } }, "hex_bits_31": { "val": { "source": "val hex_bits_31 : bitvector(31) <-> string", "type": "bitvector(31) <-> string" } }, "hex_bits_32": { "val": { "source": "val hex_bits_32 : bitvector(32) <-> string", "type": "bitvector(32) <-> string" } }, "hex_bits_4": { "val": { "source": "val hex_bits_4 : bitvector(4) <-> string", "type": "bitvector(4) <-> string" } }, "hex_bits_5": { "val": { "source": "val hex_bits_5 : bitvector(5) <-> string", "type": "bitvector(5) <-> string" } }, "hex_bits_6": { "val": { "source": "val hex_bits_6 : bitvector(6) <-> string", "type": "bitvector(6) <-> string" } }, "hex_bits_7": { "val": { "source": "val hex_bits_7 : bitvector(7) <-> string", "type": "bitvector(7) <-> string" } }, "hex_bits_8": { "val": { "source": "val hex_bits_8 : bitvector(8) <-> string", "type": "bitvector(8) <-> string" } }, "hex_bits_9": { "val": { "source": "val hex_bits_9 : bitvector(9) <-> string", "type": "bitvector(9) <-> string" } }, "hex_str": { "val": { "source": "val hex_str = pure {_: \"hex_str\"}: int -> string", "type": "int -> string" } }, "hex_str_upper": { "val": { "source": "val hex_str_upper = pure {_: \"hex_str_upper\"}: int -> string", "type": "int -> string" } }, "htif_load": { "val": { "source": "val htif_load : forall 'n, 'n > 0. (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n))", "type": "forall 'n, 'n > 0. (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n))" } }, "htif_store": { "val": { "source": "val htif_store: forall 'n, 0 < 'n <= 8. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool)", "type": "forall 'n, 0 < 'n <= 8. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool)" } }, "htif_tick": { "val": { "source": "val htif_tick : unit -> unit", "type": "unit -> unit" } }, "illegal_fp_normal": { "val": { "source": "val illegal_fp_normal : (regidx, bits(1), {|8, 16, 32, 64|}, bits(3)) -> bool", "type": "(regidx, bits(1), {|8, 16, 32, 64|}, bits(3)) -> bool" } }, "illegal_fp_reduction": { "val": { "source": "val illegal_fp_reduction : ({|8, 16, 32, 64|}, bits(3)) -> bool", "type": "({|8, 16, 32, 64|}, bits(3)) -> bool" } }, "illegal_fp_reduction_widen": { "val": { "source": "val illegal_fp_reduction_widen : ({|8, 16, 32, 64|}, bits(3), int, int) -> bool", "type": "({|8, 16, 32, 64|}, bits(3), int, int) -> bool" } }, "illegal_fp_variable_width": { "val": { "source": "val illegal_fp_variable_width : (regidx, bits(1), {|8, 16, 32, 64|}, bits(3), int, int) -> bool", "type": "(regidx, bits(1), {|8, 16, 32, 64|}, bits(3), int, int) -> bool" } }, "illegal_fp_vd_masked": { "val": { "source": "val illegal_fp_vd_masked : (regidx, {|8, 16, 32, 64|}, bits(3)) -> bool", "type": "(regidx, {|8, 16, 32, 64|}, bits(3)) -> bool" } }, "illegal_fp_vd_unmasked": { "val": { "source": "val illegal_fp_vd_unmasked : ({|8, 16, 32, 64|}, bits(3)) -> bool", "type": "({|8, 16, 32, 64|}, bits(3)) -> bool" } }, "illegal_indexed_load": { "val": { "source": "val illegal_indexed_load : (regidx, bits(1), int, int, int, int) -> bool", "type": "(regidx, bits(1), int, int, int, int) -> bool" } }, "illegal_indexed_store": { "val": { "source": "val illegal_indexed_store : (int, int, int, int) -> bool", "type": "(int, int, int, int) -> bool" } }, "illegal_load": { "val": { "source": "val illegal_load : (regidx, bits(1), int, int, int) -> bool", "type": "(regidx, bits(1), int, int, int) -> bool" } }, "illegal_normal": { "val": { "source": "val illegal_normal : (regidx, bits(1)) -> bool", "type": "(regidx, bits(1)) -> bool" } }, "illegal_reduction": { "val": { "source": "val illegal_reduction : unit -> bool", "type": "unit -> bool" } }, "illegal_reduction_widen": { "val": { "source": "val illegal_reduction_widen : (int, int) -> bool", "type": "(int, int) -> bool" } }, "illegal_store": { "val": { "source": "val illegal_store : (int, int, int) -> bool", "type": "(int, int, int) -> bool" } }, "illegal_variable_width": { "val": { "source": "val illegal_variable_width : (regidx, bits(1), int, int) -> bool", "type": "(regidx, bits(1), int, int) -> bool" } }, "illegal_vd_masked": { "val": { "source": "val illegal_vd_masked : regidx -> bool", "type": "regidx -> bool" } }, "illegal_vd_unmasked": { "val": { "source": "val illegal_vd_unmasked : unit -> bool", "type": "unit -> bool" } }, "in32BitMode": { "val": { "source": "val in32BitMode : unit -> bool", "type": "unit -> bool" } }, "init_TLB": { "val": { "source": "val init_TLB : unit -> unit", "type": "unit -> unit" } }, "init_base_regs": { "val": { "source": "val init_base_regs : unit -> unit", "type": "unit -> unit" } }, "init_fdext_regs": { "val": { "source": "val init_fdext_regs : unit -> unit", "type": "unit -> unit" } }, "init_masked_result": { "val": { "source": "val init_masked_result : forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), vector('n, dec, bits('m)), vector('n, dec, bool)) -> (vector('n, dec, bits('m)), vector('n, dec, bool))", "type": "forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), vector('n, dec, bits('m)), vector('n, dec, bool)) -> (vector('n, dec, bits('m)), vector('n, dec, bool))" } }, "init_masked_result_carry": { "val": { "source": "val init_masked_result_carry : forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), vector('n, dec, bool)) -> (vector('n, dec, bool), vector('n, dec, bool))", "type": "forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), vector('n, dec, bool)) -> (vector('n, dec, bool), vector('n, dec, bool))" } }, "init_masked_result_cmp": { "val": { "source": "val init_masked_result_cmp : forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), vector('n, dec, bool), vector('n, dec, bool)) -> (vector('n, dec, bool), vector('n, dec, bool))", "type": "forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), vector('n, dec, bool), vector('n, dec, bool)) -> (vector('n, dec, bool), vector('n, dec, bool))" } }, "init_masked_source": { "val": { "source": "val init_masked_source : forall 'n 'p, 'n >= 0. (int('n), int('p), vector('n, dec, bool)) -> vector('n, dec, bool)", "type": "forall 'n 'p, 'n >= 0. (int('n), int('p), vector('n, dec, bool)) -> vector('n, dec, bool)" } }, "init_model": { "val": { "source": "val init_model : unit -> unit", "type": "unit -> unit" } }, "init_platform": { "val": { "source": "val init_platform : unit -> unit", "type": "unit -> unit" } }, "init_pmp": { "val": { "source": "val init_pmp : unit -> unit", "type": "unit -> unit" } }, "init_sys": { "val": { "source": "val init_sys : unit -> unit", "type": "unit -> unit" } }, "init_vmem": { "val": { "source": "val init_vmem : unit -> unit", "type": "unit -> unit" } }, "init_vregs": { "val": { "source": "val init_vregs : unit -> unit", "type": "unit -> unit" } }, "initial_analysis": { "val": { "source": "val initial_analysis : ast -> (regfps, regfps, regfps, niafps, diafp, instruction_kind)", "type": "ast -> (regfps, regfps, regfps, niafps, diafp, instruction_kind)" } }, "int_power": { "val": { "source": "val int_power = {ocaml: \"int_power\", interpreter: \"int_power\", lem: \"pow\", coq: \"pow\", c: \"pow_int\"} : (int, int) -> int", "type": "(int, int) -> int" } }, "internal_error": { "val": { "source": "val internal_error : forall ('a : Type). (string, int, string) -> 'a", "type": "forall ('a : Type). (string, int, string) -> 'a" } }, "interruptType_to_bits": { "val": { "source": "val interruptType_to_bits : InterruptType -> exc_code", "type": "InterruptType -> exc_code" } }, "iop_of_num": { "val": { "source": "val iop_of_num : forall 'e, (0 <= 'e & 'e <= 5). int('e) -> iop", "type": "forall 'e, (0 <= 'e & 'e <= 5). int('e) -> iop" } }, "isRVC": { "val": { "source": "val isRVC : half -> bool", "type": "half -> bool" } }, "is_CSR_defined": { "val": { "source": "val is_CSR_defined : (csreg, Privilege) -> bool", "type": "(csreg, Privilege) -> bool" } }, "is_aligned_addr": { "val": { "source": "val is_aligned_addr : forall 'n. (xlenbits, int('n)) -> bool", "type": "forall 'n. (xlenbits, int('n)) -> bool" } }, "is_fiom_active": { "val": { "source": "val is_fiom_active : unit -> bool", "type": "unit -> bool" } }, "is_none": { "val": { "source": "val is_none : forall ('a : Type). option('a) -> bool", "type": "forall ('a : Type). option('a) -> bool" } }, "is_some": { "val": { "source": "val is_some : forall ('a : Type). option('a) -> bool", "type": "forall ('a : Type). option('a) -> bool" } }, "is_valid_vAddr": { "val": { "source": "val is_valid_vAddr : (SV_Params, bits(64)) -> bool", "type": "(SV_Params, bits(64)) -> bool" } }, "itype_mnemonic": { "val": { "source": "val itype_mnemonic : iop <-> string", "type": "iop <-> string" } }, "legalize_mcounteren": { "val": { "source": "val legalize_mcounteren : (Counteren, xlenbits) -> Counteren", "type": "(Counteren, xlenbits) -> Counteren" } }, "legalize_mcountinhibit": { "val": { "source": "val legalize_mcountinhibit : (Counterin, xlenbits) -> Counterin", "type": "(Counterin, xlenbits) -> Counterin" } }, "legalize_medeleg": { "val": { "source": "val legalize_medeleg : (Medeleg, xlenbits) -> Medeleg", "type": "(Medeleg, xlenbits) -> Medeleg" } }, "legalize_menvcfg": { "val": { "source": "val legalize_menvcfg : (MEnvcfg, bits(64)) -> MEnvcfg", "type": "(MEnvcfg, bits(64)) -> MEnvcfg" } }, "legalize_mideleg": { "val": { "source": "val legalize_mideleg : (Minterrupts, xlenbits) -> Minterrupts", "type": "(Minterrupts, xlenbits) -> Minterrupts" } }, "legalize_mie": { "val": { "source": "val legalize_mie : (Minterrupts, xlenbits) -> Minterrupts", "type": "(Minterrupts, xlenbits) -> Minterrupts" } }, "legalize_mip": { "val": { "source": "val legalize_mip : (Minterrupts, xlenbits) -> Minterrupts", "type": "(Minterrupts, xlenbits) -> Minterrupts" } }, "legalize_misa": { "val": { "source": "val legalize_misa : (Misa, xlenbits) -> Misa", "type": "(Misa, xlenbits) -> Misa" } }, "legalize_mstatus": { "val": { "source": "val legalize_mstatus : (Mstatus, xlenbits) -> Mstatus", "type": "(Mstatus, xlenbits) -> Mstatus" } }, "legalize_satp": { "val": { "source": "val legalize_satp : (Architecture, xlenbits, xlenbits) -> xlenbits", "type": "(Architecture, xlenbits, xlenbits) -> xlenbits" } }, "legalize_satp32": { "val": { "source": "val legalize_satp32 : (Architecture, bits(32), bits(32)) -> bits(32)", "type": "(Architecture, bits(32), bits(32)) -> bits(32)" } }, "legalize_satp64": { "val": { "source": "val legalize_satp64 : (Architecture, bits(64), bits(64)) -> bits(64)", "type": "(Architecture, bits(64), bits(64)) -> bits(64)" } }, "legalize_scounteren": { "val": { "source": "val legalize_scounteren : (Counteren, xlenbits) -> Counteren", "type": "(Counteren, xlenbits) -> Counteren" } }, "legalize_sedeleg": { "val": { "source": "val legalize_sedeleg : (Sedeleg, xlenbits) -> Sedeleg", "type": "(Sedeleg, xlenbits) -> Sedeleg" } }, "legalize_senvcfg": { "val": { "source": "val legalize_senvcfg : (SEnvcfg, xlenbits) -> SEnvcfg", "type": "(SEnvcfg, xlenbits) -> SEnvcfg" } }, "legalize_sie": { "val": { "source": "val legalize_sie : (Minterrupts, Minterrupts, xlenbits) -> Minterrupts", "type": "(Minterrupts, Minterrupts, xlenbits) -> Minterrupts" } }, "legalize_sip": { "val": { "source": "val legalize_sip : (Minterrupts, Minterrupts, xlenbits) -> Minterrupts", "type": "(Minterrupts, Minterrupts, xlenbits) -> Minterrupts" } }, "legalize_sstatus": { "val": { "source": "val legalize_sstatus : (Mstatus, xlenbits) -> Mstatus", "type": "(Mstatus, xlenbits) -> Mstatus" } }, "legalize_tvec": { "val": { "source": "val legalize_tvec : (Mtvec, xlenbits) -> Mtvec", "type": "(Mtvec, xlenbits) -> Mtvec" } }, "legalize_uie": { "val": { "source": "val legalize_uie : (Sinterrupts, Sinterrupts, xlenbits) -> Sinterrupts", "type": "(Sinterrupts, Sinterrupts, xlenbits) -> Sinterrupts" } }, "legalize_uip": { "val": { "source": "val legalize_uip : (Sinterrupts, Sinterrupts, xlenbits) -> Sinterrupts", "type": "(Sinterrupts, Sinterrupts, xlenbits) -> Sinterrupts" } }, "legalize_ustatus": { "val": { "source": "val legalize_ustatus : (Mstatus, xlenbits) -> Mstatus", "type": "(Mstatus, xlenbits) -> Mstatus" } }, "legalize_xepc": { "val": { "source": "val legalize_xepc : xlenbits -> xlenbits", "type": "xlenbits -> xlenbits" } }, "lift_sie": { "val": { "source": "val lift_sie : (Minterrupts, Minterrupts, Sinterrupts) -> Minterrupts", "type": "(Minterrupts, Minterrupts, Sinterrupts) -> Minterrupts" } }, "lift_sip": { "val": { "source": "val lift_sip : (Minterrupts, Minterrupts, Sinterrupts) -> Minterrupts", "type": "(Minterrupts, Minterrupts, Sinterrupts) -> Minterrupts" } }, "lift_sstatus": { "val": { "source": "val lift_sstatus : (Mstatus, Sstatus) -> Mstatus", "type": "(Mstatus, Sstatus) -> Mstatus" } }, "lift_uie": { "val": { "source": "val lift_uie : (Sinterrupts, Sinterrupts, Uinterrupts) -> Sinterrupts", "type": "(Sinterrupts, Sinterrupts, Uinterrupts) -> Sinterrupts" } }, "lift_uip": { "val": { "source": "val lift_uip : (Sinterrupts, Sinterrupts, Uinterrupts) -> Sinterrupts", "type": "(Sinterrupts, Sinterrupts, Uinterrupts) -> Sinterrupts" } }, "lift_ustatus": { "val": { "source": "val lift_ustatus : (Sstatus, Ustatus) -> Sstatus", "type": "(Sstatus, Ustatus) -> Sstatus" } }, "load_reservation": { "val": { "source": "val load_reservation = {ocaml: \"Platform.load_reservation\", interpreter: \"Platform.load_reservation\", c: \"load_reservation\", lem: \"load_reservation\"} : xlenbits -> unit", "type": "xlenbits -> unit" } }, "log2": { "val": { "source": "val log2 : forall 'n, 'n in {1, 2, 4, 8, 16, 32, 64}. int('n) -> int", "type": "forall 'n, 'n in {1, 2, 4, 8, 16, 32, 64}. int('n) -> int" } }, "lookup_TLB": { "val": { "source": "val lookup_TLB : (asidbits, bits(64)) -> option((nat, TLB_Entry))", "type": "(asidbits, bits(64)) -> option((nat, TLB_Entry))" } }, "loop": { "val": { "source": "val loop : unit -> unit", "type": "unit -> unit" } }, "lower_mie": { "val": { "source": "val lower_mie : (Minterrupts, Minterrupts) -> Sinterrupts", "type": "(Minterrupts, Minterrupts) -> Sinterrupts" } }, "lower_mip": { "val": { "source": "val lower_mip : (Minterrupts, Minterrupts) -> Sinterrupts", "type": "(Minterrupts, Minterrupts) -> Sinterrupts" } }, "lower_mstatus": { "val": { "source": "val lower_mstatus : Mstatus -> Sstatus", "type": "Mstatus -> Sstatus" } }, "lower_sie": { "val": { "source": "val lower_sie : (Sinterrupts, Sinterrupts) -> Uinterrupts", "type": "(Sinterrupts, Sinterrupts) -> Uinterrupts" } }, "lower_sip": { "val": { "source": "val lower_sip : (Sinterrupts, Sinterrupts) -> Uinterrupts", "type": "(Sinterrupts, Sinterrupts) -> Uinterrupts" } }, "lower_sstatus": { "val": { "source": "val lower_sstatus : Sstatus -> Ustatus", "type": "Sstatus -> Ustatus" } }, "lrsc_width_str": { "val": { "source": "val lrsc_width_str : word_width -> string", "type": "word_width -> string" } }, "lt_int": { "val": { "source": "val lt_int = pure {coq: \"Z.ltb\", _: \"lt\"}: forall 'n 'm. (int('n), int('m)) -> bool('n < 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> bool('n < 'm)" } }, "lteq_int": { "val": { "source": "val lteq_int = pure {coq: \"Z.leb\", _: \"lteq\"}: forall 'n 'm. (int('n), int('m)) -> bool('n <= 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> bool('n <= 'm)" } }, "main": { "val": { "source": "val main : unit -> unit", "type": "unit -> unit" } }, "maskfunct3_of_num": { "val": { "source": "val maskfunct3_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> maskfunct3", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> maskfunct3" } }, "match_TLB_Entry": { "val": { "source": "val match_TLB_Entry : (TLB_Entry, asidbits, bits(64)) -> bool", "type": "(TLB_Entry, asidbits, bits(64)) -> bool" } }, "match_reservation": { "val": { "source": "val match_reservation = {ocaml: \"Platform.match_reservation\", interpreter: \"Platform.match_reservation\", lem: \"match_reservation\", c: \"match_reservation\"} : xlenbits -> bool", "type": "xlenbits -> bool" } }, "max_int": { "val": { "source": "val max_int = {ocaml: \"max_int\", interpreter: \"max_int\", lem: \"max\", coq: \"max_atom\", c: \"max_int\"} : forall 'x 'y.\n (int('x), int('y)) -> {'z, ('x >= 'y & 'z == 'x) | ('x < 'y & 'z == 'y). int('z)}", "type": "forall 'x 'y.\n (int('x), int('y)) -> {'z, ('x >= 'y & 'z == 'x) | ('x < 'y & 'z == 'y). int('z)}" } }, "maybe_aq": { "val": { "source": "val maybe_aq : bool <-> string", "type": "bool <-> string" } }, "maybe_i": { "val": { "source": "val maybe_i : bool <-> string", "type": "bool <-> string" } }, "maybe_lmul_flag": { "val": { "source": "val maybe_lmul_flag : string <-> bitvector(3)", "type": "string <-> bitvector(3)" } }, "maybe_ma_flag": { "val": { "source": "val maybe_ma_flag : string <-> bitvector(1)", "type": "string <-> bitvector(1)" } }, "maybe_not_u": { "val": { "source": "val maybe_not_u : bool <-> string", "type": "bool <-> string" } }, "maybe_rl": { "val": { "source": "val maybe_rl : bool <-> string", "type": "bool <-> string" } }, "maybe_ta_flag": { "val": { "source": "val maybe_ta_flag : string <-> bitvector(1)", "type": "string <-> bitvector(1)" } }, "maybe_u": { "val": { "source": "val maybe_u : bool <-> string", "type": "bool <-> string" } }, "maybe_vmask": { "val": { "source": "val maybe_vmask : string <-> bitvector(1)", "type": "string <-> bitvector(1)" } }, "mem_read": { "val": { "source": "val mem_read : forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n))", "type": "forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n))" } }, "mem_read_meta": { "val": { "source": "val mem_read_meta : forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))", "type": "forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))" } }, "mem_read_priv": { "val": { "source": "val mem_read_priv : forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), Privilege, xlenbits, int('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n))", "type": "forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), Privilege, xlenbits, int('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n))" } }, "mem_read_priv_meta": { "val": { "source": "val mem_read_priv_meta : forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), Privilege, xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))", "type": "forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), Privilege, xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))" } }, "mem_write_ea": { "val": { "source": "val mem_write_ea : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bool, bool, bool) -> MemoryOpResult(unit)", "type": "forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bool, bool, bool) -> MemoryOpResult(unit)" } }, "mem_write_value": { "val": { "source": "val mem_write_value : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(bool)", "type": "forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(bool)" } }, "mem_write_value_meta": { "val": { "source": "val mem_write_value_meta : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bits(8 * 'n), ext_access_type, mem_meta, bool, bool, bool) -> MemoryOpResult(bool)", "type": "forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bits(8 * 'n), ext_access_type, mem_meta, bool, bool, bool) -> MemoryOpResult(bool)" } }, "mem_write_value_priv": { "val": { "source": "val mem_write_value_priv : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bits(8 * 'n), Privilege, bool, bool, bool) -> MemoryOpResult(bool)", "type": "forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bits(8 * 'n), Privilege, bool, bool, bool) -> MemoryOpResult(bool)" } }, "mem_write_value_priv_meta": { "val": { "source": "val mem_write_value_priv_meta : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bits(8 * 'n), AccessType(ext_access_type), Privilege, mem_meta, bool, bool, bool) -> MemoryOpResult(bool)", "type": "forall 'n, 0 < 'n <= max_mem_access . (xlenbits, int('n), bits(8 * 'n), AccessType(ext_access_type), Privilege, mem_meta, bool, bool, bool) -> MemoryOpResult(bool)" } }, "min_int": { "val": { "source": "val min_int = {ocaml: \"min_int\", interpreter: \"min_int\", lem: \"min\", coq: \"min_atom\", c: \"min_int\"} : forall 'x 'y.\n (int('x), int('y)) -> {'z, ('x <= 'y & 'z == 'x) | ('x > 'y & 'z == 'y). int('z)}", "type": "forall 'x 'y.\n (int('x), int('y)) -> {'z, ('x <= 'y & 'z == 'x) | ('x > 'y & 'z == 'y). int('z)}" } }, "mmfunct6_of_num": { "val": { "source": "val mmfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> mmfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> mmfunct6" } }, "mmio_read": { "val": { "source": "val mmio_read : forall 'n, (0 < 'n & 'n <= max_mem_access).\n (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n))", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access).\n (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n))" } }, "mmio_write": { "val": { "source": "val mmio_write : forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool)", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool)" } }, "mmtype_mnemonic": { "val": { "source": "val mmtype_mnemonic : mmfunct6 <-> string", "type": "mmfunct6 <-> string" } }, "msbs_of_PTE": { "val": { "source": "val msbs_of_PTE : (SV_Params, bits(64)) -> bits(64)", "type": "(SV_Params, bits(64)) -> bits(64)" } }, "mul_mnemonic": { "val": { "source": "val mul_mnemonic : (bool, bool, bool) <-> string", "type": "(bool, bool, bool) <-> string" } }, "mult_atom": { "val": { "source": "val mult_atom = pure {ocaml: \"mult\", interpreter: \"mult\", lem: \"integerMult\", c: \"mult_int\", coq: \"Z.mul\"}: forall 'n 'm.\n (int('n), int('m)) -> int('n * 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> int('n * 'm)" } }, "mult_int": { "val": { "source": "val mult_int = pure {ocaml: \"mult\", interpreter: \"mult\", lem: \"integerMult\", c: \"mult_int\", coq: \"Z.mul\"}: (int, int) -> int", "type": "(int, int) -> int" } }, "mvvfunct6_of_num": { "val": { "source": "val mvvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 11). int('e) -> mvvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 11). int('e) -> mvvfunct6" } }, "mvvmafunct6_of_num": { "val": { "source": "val mvvmafunct6_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> mvvmafunct6", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> mvvmafunct6" } }, "mvvmatype_mnemonic": { "val": { "source": "val mvvmatype_mnemonic : mvvmafunct6 <-> string", "type": "mvvmafunct6 <-> string" } }, "mvvtype_mnemonic": { "val": { "source": "val mvvtype_mnemonic : mvvfunct6 <-> string", "type": "mvvfunct6 <-> string" } }, "mvxfunct6_of_num": { "val": { "source": "val mvxfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 13). int('e) -> mvxfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 13). int('e) -> mvxfunct6" } }, "mvxmafunct6_of_num": { "val": { "source": "val mvxmafunct6_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> mvxmafunct6", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> mvxmafunct6" } }, "mvxmatype_mnemonic": { "val": { "source": "val mvxmatype_mnemonic : mvxmafunct6 <-> string", "type": "mvxmafunct6 <-> string" } }, "mvxtype_mnemonic": { "val": { "source": "val mvxtype_mnemonic : mvxfunct6 <-> string", "type": "mvxfunct6 <-> string" } }, "n_leading_spaces": { "val": { "source": "val n_leading_spaces = pure { coq: \"n_leading_spaces_Z\" } : string -> nat", "type": "string -> nat" } }, "nan_box_H": { "val": { "source": "val nan_box_H : bits(16) -> flenbits", "type": "bits(16) -> flenbits" } }, "nan_box_S": { "val": { "source": "val nan_box_S : bits(32) -> flenbits", "type": "bits(32) -> flenbits" } }, "nan_unbox_H": { "val": { "source": "val nan_unbox_H : flenbits -> bits(16)", "type": "flenbits -> bits(16)" } }, "nan_unbox_S": { "val": { "source": "val nan_unbox_S : flenbits -> bits(32)", "type": "flenbits -> bits(32)" } }, "negate_D": { "val": { "source": "val negate_D : bits(64) -> bits(64)", "type": "bits(64) -> bits(64)" } }, "negate_H": { "val": { "source": "val negate_H : bits(16) -> bits(16)", "type": "bits(16) -> bits(16)" } }, "negate_S": { "val": { "source": "val negate_S : bits(32) -> bits(32)", "type": "bits(32) -> bits(32)" } }, "negate_atom": { "val": { "source": "val negate_atom = pure {ocaml: \"negate\", interpreter: \"negate\", lem: \"integerNegate\", c: \"neg_int\", coq: \"Z.opp\"}: forall 'n.\n int('n) -> int(- 'n)", "type": "forall 'n. int('n) -> int(- 'n)" } }, "negate_fp": { "val": { "source": "val negate_fp : forall 'm, 'm in {16, 32, 64}. bits('m) -> bits('m)", "type": "forall 'm, 'm in {16, 32, 64}. bits('m) -> bits('m)" } }, "negate_int": { "val": { "source": "val negate_int = pure {ocaml: \"negate\", interpreter: \"negate\", lem: \"integerNegate\", c: \"neg_int\", coq: \"Z.opp\"}: int -> int", "type": "int -> int" } }, "neq_anything": { "val": { "source": "val neq_anything = pure {lem: \"neq\", coq: \"generic_neq\"}: forall ('a : Type). ('a, 'a) -> bool", "type": "forall ('a : Type). ('a, 'a) -> bool" } }, "neq_bits": { "val": { "source": "val neq_bits = pure {lem: \"neq_vec\", c: \"neq_bits\", coq: \"neq_vec\"}: forall 'n. (bits('n), bits('n)) -> bool", "type": "forall 'n. (bits('n), bits('n)) -> bool" } }, "neq_bool": { "val": { "source": "val neq_bool : (bool, bool) -> bool", "type": "(bool, bool) -> bool" } }, "neq_int": { "val": { "source": "val neq_int = pure {lem: \"neq\"}: forall 'n 'm. (int('n), int('m)) -> bool('n != 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> bool('n != 'm)" } }, "nfields_int": { "val": { "source": "val nfields_int : bitvector(3) <-> {1, 2, 3, 4, 5, 6, 7, 8}", "type": "bitvector(3) <-> {1, 2, 3, 4, 5, 6, 7, 8}" } }, "nfields_string": { "val": { "source": "val nfields_string : bitvector(3) <-> string", "type": "bitvector(3) <-> string" } }, "nifunct6_of_num": { "val": { "source": "val nifunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nifunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nifunct6" } }, "nisfunct6_of_num": { "val": { "source": "val nisfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nisfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nisfunct6" } }, "nistype_mnemonic": { "val": { "source": "val nistype_mnemonic : nisfunct6 <-> string", "type": "nisfunct6 <-> string" } }, "nitype_mnemonic": { "val": { "source": "val nitype_mnemonic : nifunct6 <-> string", "type": "nifunct6 <-> string" } }, "not": { "val": { "source": "val not : forall ('p : Bool). bool('p) -> bool(not('p))", "type": "forall ('p : Bool). bool('p) -> bool(not('p))" } }, "not_bit": { "val": { "source": "val not_bit : bit -> bit", "type": "bit -> bit" } }, "not_bool": { "val": { "source": "val not_bool = pure {coq: \"negb\", _: \"not\"}: forall ('p : Bool). bool('p) -> bool(not('p))", "type": "forall ('p : Bool). bool('p) -> bool(not('p))" } }, "not_implemented": { "val": { "source": "val not_implemented : forall ('a : Type). string -> 'a", "type": "forall ('a : Type). string -> 'a" } }, "not_vec": { "val": { "source": "val not_vec = pure {c: \"not_bits\", _: \"not_vec\"}: forall 'n. bits('n) -> bits('n)", "type": "forall 'n. bits('n) -> bits('n)" } }, "num_of_Architecture": { "val": { "source": "val num_of_Architecture : Architecture -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "Architecture -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_ExceptionType": { "val": { "source": "val num_of_ExceptionType : ExceptionType -> {'n, (0 <= 'n < xlen). int('n)}", "type": "ExceptionType -> {'n, (0 <= 'n < xlen). int('n)}" } }, "num_of_ExtStatus": { "val": { "source": "val num_of_ExtStatus : ExtStatus -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "ExtStatus -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_InterruptType": { "val": { "source": "val num_of_InterruptType : InterruptType -> {'e, (0 <= 'e & 'e <= 8). int('e)}", "type": "InterruptType -> {'e, (0 <= 'e & 'e <= 8). int('e)}" } }, "num_of_PmpAddrMatchType": { "val": { "source": "val num_of_PmpAddrMatchType : PmpAddrMatchType -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "PmpAddrMatchType -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_Privilege": { "val": { "source": "val num_of_Privilege : Privilege -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "Privilege -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_Retired": { "val": { "source": "val num_of_Retired : Retired -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "Retired -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_SATPMode": { "val": { "source": "val num_of_SATPMode : SATPMode -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "SATPMode -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_TrapVectorMode": { "val": { "source": "val num_of_TrapVectorMode : TrapVectorMode -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "TrapVectorMode -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_a64_barrier_domain": { "val": { "source": "val num_of_a64_barrier_domain : a64_barrier_domain -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "a64_barrier_domain -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_a64_barrier_type": { "val": { "source": "val num_of_a64_barrier_type : a64_barrier_type -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "a64_barrier_type -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_agtype": { "val": { "source": "val num_of_agtype : agtype -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "agtype -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_amoop": { "val": { "source": "val num_of_amoop : amoop -> {'e, (0 <= 'e & 'e <= 8). int('e)}", "type": "amoop -> {'e, (0 <= 'e & 'e <= 8). int('e)}" } }, "num_of_biop_zbs": { "val": { "source": "val num_of_biop_zbs : biop_zbs -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "biop_zbs -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_bop": { "val": { "source": "val num_of_bop : bop -> {'e, (0 <= 'e & 'e <= 5). int('e)}", "type": "bop -> {'e, (0 <= 'e & 'e <= 5). int('e)}" } }, "num_of_brop_zba": { "val": { "source": "val num_of_brop_zba : brop_zba -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "brop_zba -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_brop_zbb": { "val": { "source": "val num_of_brop_zbb : brop_zbb -> {'e, (0 <= 'e & 'e <= 8). int('e)}", "type": "brop_zbb -> {'e, (0 <= 'e & 'e <= 8). int('e)}" } }, "num_of_brop_zbkb": { "val": { "source": "val num_of_brop_zbkb : brop_zbkb -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "brop_zbkb -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_brop_zbs": { "val": { "source": "val num_of_brop_zbs : brop_zbs -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "brop_zbs -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_bropw_zba": { "val": { "source": "val num_of_bropw_zba : bropw_zba -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "bropw_zba -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_bropw_zbb": { "val": { "source": "val num_of_bropw_zbb : bropw_zbb -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "bropw_zbb -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_cache_op_kind": { "val": { "source": "val num_of_cache_op_kind : cache_op_kind -> {'e, (0 <= 'e & 'e <= 10). int('e)}", "type": "cache_op_kind -> {'e, (0 <= 'e & 'e <= 10). int('e)}" } }, "num_of_csrop": { "val": { "source": "val num_of_csrop : csrop -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "csrop -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_ext_exc_type": { "val": { "source": "val num_of_ext_exc_type : ext_exc_type -> {'n, (0 <= 'n < xlen). int('n)}", "type": "ext_exc_type -> {'n, (0 <= 'n < xlen). int('n)}" } }, "num_of_extop_zbb": { "val": { "source": "val num_of_extop_zbb : extop_zbb -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "extop_zbb -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_f_bin_op_D": { "val": { "source": "val num_of_f_bin_op_D : f_bin_op_D -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "f_bin_op_D -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_f_bin_op_H": { "val": { "source": "val num_of_f_bin_op_H : f_bin_op_H -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "f_bin_op_H -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_f_bin_op_S": { "val": { "source": "val num_of_f_bin_op_S : f_bin_op_S -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "f_bin_op_S -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_f_bin_rm_op_D": { "val": { "source": "val num_of_f_bin_rm_op_D : f_bin_rm_op_D -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "f_bin_rm_op_D -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_f_bin_rm_op_H": { "val": { "source": "val num_of_f_bin_rm_op_H : f_bin_rm_op_H -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "f_bin_rm_op_H -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_f_bin_rm_op_S": { "val": { "source": "val num_of_f_bin_rm_op_S : f_bin_rm_op_S -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "f_bin_rm_op_S -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_f_madd_op_D": { "val": { "source": "val num_of_f_madd_op_D : f_madd_op_D -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "f_madd_op_D -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_f_madd_op_H": { "val": { "source": "val num_of_f_madd_op_H : f_madd_op_H -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "f_madd_op_H -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_f_madd_op_S": { "val": { "source": "val num_of_f_madd_op_S : f_madd_op_S -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "f_madd_op_S -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_f_un_op_D": { "val": { "source": "val num_of_f_un_op_D : f_un_op_D -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "f_un_op_D -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_f_un_op_H": { "val": { "source": "val num_of_f_un_op_H : f_un_op_H -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "f_un_op_H -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_f_un_op_S": { "val": { "source": "val num_of_f_un_op_S : f_un_op_S -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "f_un_op_S -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_f_un_rm_op_D": { "val": { "source": "val num_of_f_un_rm_op_D : f_un_rm_op_D -> {'e, (0 <= 'e & 'e <= 10). int('e)}", "type": "f_un_rm_op_D -> {'e, (0 <= 'e & 'e <= 10). int('e)}" } }, "num_of_f_un_rm_op_H": { "val": { "source": "val num_of_f_un_rm_op_H : f_un_rm_op_H -> {'e, (0 <= 'e & 'e <= 12). int('e)}", "type": "f_un_rm_op_H -> {'e, (0 <= 'e & 'e <= 12). int('e)}" } }, "num_of_f_un_rm_op_S": { "val": { "source": "val num_of_f_un_rm_op_S : f_un_rm_op_S -> {'e, (0 <= 'e & 'e <= 8). int('e)}", "type": "f_un_rm_op_S -> {'e, (0 <= 'e & 'e <= 8). int('e)}" } }, "num_of_fvffunct6": { "val": { "source": "val num_of_fvffunct6 : fvffunct6 -> {'e, (0 <= 'e & 'e <= 12). int('e)}", "type": "fvffunct6 -> {'e, (0 <= 'e & 'e <= 12). int('e)}" } }, "num_of_fvfmafunct6": { "val": { "source": "val num_of_fvfmafunct6 : fvfmafunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "fvfmafunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_fvfmfunct6": { "val": { "source": "val num_of_fvfmfunct6 : fvfmfunct6 -> {'e, (0 <= 'e & 'e <= 5). int('e)}", "type": "fvfmfunct6 -> {'e, (0 <= 'e & 'e <= 5). int('e)}" } }, "num_of_fvvfunct6": { "val": { "source": "val num_of_fvvfunct6 : fvvfunct6 -> {'e, (0 <= 'e & 'e <= 8). int('e)}", "type": "fvvfunct6 -> {'e, (0 <= 'e & 'e <= 8). int('e)}" } }, "num_of_fvvmafunct6": { "val": { "source": "val num_of_fvvmafunct6 : fvvmafunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "fvvmafunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_fvvmfunct6": { "val": { "source": "val num_of_fvvmfunct6 : fvvmfunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "fvvmfunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_fwffunct6": { "val": { "source": "val num_of_fwffunct6 : fwffunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "fwffunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_fwvffunct6": { "val": { "source": "val num_of_fwvffunct6 : fwvffunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "fwvffunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_fwvfmafunct6": { "val": { "source": "val num_of_fwvfmafunct6 : fwvfmafunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "fwvfmafunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_fwvfunct6": { "val": { "source": "val num_of_fwvfunct6 : fwvfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "fwvfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_fwvvfunct6": { "val": { "source": "val num_of_fwvvfunct6 : fwvvfunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "fwvvfunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_fwvvmafunct6": { "val": { "source": "val num_of_fwvvmafunct6 : fwvvmafunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "fwvvmafunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_iop": { "val": { "source": "val num_of_iop : iop -> {'e, (0 <= 'e & 'e <= 5). int('e)}", "type": "iop -> {'e, (0 <= 'e & 'e <= 5). int('e)}" } }, "num_of_maskfunct3": { "val": { "source": "val num_of_maskfunct3 : maskfunct3 -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "maskfunct3 -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_mmfunct6": { "val": { "source": "val num_of_mmfunct6 : mmfunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "mmfunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_mvvfunct6": { "val": { "source": "val num_of_mvvfunct6 : mvvfunct6 -> {'e, (0 <= 'e & 'e <= 11). int('e)}", "type": "mvvfunct6 -> {'e, (0 <= 'e & 'e <= 11). int('e)}" } }, "num_of_mvvmafunct6": { "val": { "source": "val num_of_mvvmafunct6 : mvvmafunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "mvvmafunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_mvxfunct6": { "val": { "source": "val num_of_mvxfunct6 : mvxfunct6 -> {'e, (0 <= 'e & 'e <= 13). int('e)}", "type": "mvxfunct6 -> {'e, (0 <= 'e & 'e <= 13). int('e)}" } }, "num_of_mvxmafunct6": { "val": { "source": "val num_of_mvxmafunct6 : mvxmafunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "mvxmafunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_nifunct6": { "val": { "source": "val num_of_nifunct6 : nifunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "nifunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_nisfunct6": { "val": { "source": "val num_of_nisfunct6 : nisfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "nisfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_nvfunct6": { "val": { "source": "val num_of_nvfunct6 : nvfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "nvfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_nvsfunct6": { "val": { "source": "val num_of_nvsfunct6 : nvsfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "nvsfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_nxfunct6": { "val": { "source": "val num_of_nxfunct6 : nxfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "nxfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_nxsfunct6": { "val": { "source": "val num_of_nxsfunct6 : nxsfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "nxsfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_pmpAddrMatch": { "val": { "source": "val num_of_pmpAddrMatch : pmpAddrMatch -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "pmpAddrMatch -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_pmpMatch": { "val": { "source": "val num_of_pmpMatch : pmpMatch -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "pmpMatch -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_read_kind": { "val": { "source": "val num_of_read_kind : read_kind -> {'e, (0 <= 'e & 'e <= 12). int('e)}", "type": "read_kind -> {'e, (0 <= 'e & 'e <= 12). int('e)}" } }, "num_of_rfvvfunct6": { "val": { "source": "val num_of_rfvvfunct6 : rfvvfunct6 -> {'e, (0 <= 'e & 'e <= 5). int('e)}", "type": "rfvvfunct6 -> {'e, (0 <= 'e & 'e <= 5). int('e)}" } }, "num_of_rivvfunct6": { "val": { "source": "val num_of_rivvfunct6 : rivvfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "rivvfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_rmvvfunct6": { "val": { "source": "val num_of_rmvvfunct6 : rmvvfunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "rmvvfunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_rop": { "val": { "source": "val num_of_rop : rop -> {'e, (0 <= 'e & 'e <= 9). int('e)}", "type": "rop -> {'e, (0 <= 'e & 'e <= 9). int('e)}" } }, "num_of_ropw": { "val": { "source": "val num_of_ropw : ropw -> {'e, (0 <= 'e & 'e <= 4). int('e)}", "type": "ropw -> {'e, (0 <= 'e & 'e <= 4). int('e)}" } }, "num_of_rounding_mode": { "val": { "source": "val num_of_rounding_mode : rounding_mode -> {'e, (0 <= 'e & 'e <= 5). int('e)}", "type": "rounding_mode -> {'e, (0 <= 'e & 'e <= 5). int('e)}" } }, "num_of_seed_opst": { "val": { "source": "val num_of_seed_opst : seed_opst -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "seed_opst -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_sop": { "val": { "source": "val num_of_sop : sop -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "sop -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_sopw": { "val": { "source": "val num_of_sopw : sopw -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "sopw -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_trans_kind": { "val": { "source": "val num_of_trans_kind : trans_kind -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "trans_kind -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_uop": { "val": { "source": "val num_of_uop : uop -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "uop -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vext2funct6": { "val": { "source": "val num_of_vext2funct6 : vext2funct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vext2funct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vext4funct6": { "val": { "source": "val num_of_vext4funct6 : vext4funct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vext4funct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vext8funct6": { "val": { "source": "val num_of_vext8funct6 : vext8funct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vext8funct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vfnunary0": { "val": { "source": "val num_of_vfnunary0 : vfnunary0 -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "vfnunary0 -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_vfunary0": { "val": { "source": "val num_of_vfunary0 : vfunary0 -> {'e, (0 <= 'e & 'e <= 5). int('e)}", "type": "vfunary0 -> {'e, (0 <= 'e & 'e <= 5). int('e)}" } }, "num_of_vfunary1": { "val": { "source": "val num_of_vfunary1 : vfunary1 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "vfunary1 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_vfwunary0": { "val": { "source": "val num_of_vfwunary0 : vfwunary0 -> {'e, (0 <= 'e & 'e <= 6). int('e)}", "type": "vfwunary0 -> {'e, (0 <= 'e & 'e <= 6). int('e)}" } }, "num_of_vicmpfunct6": { "val": { "source": "val num_of_vicmpfunct6 : vicmpfunct6 -> {'e, (0 <= 'e & 'e <= 5). int('e)}", "type": "vicmpfunct6 -> {'e, (0 <= 'e & 'e <= 5). int('e)}" } }, "num_of_vifunct6": { "val": { "source": "val num_of_vifunct6 : vifunct6 -> {'e, (0 <= 'e & 'e <= 11). int('e)}", "type": "vifunct6 -> {'e, (0 <= 'e & 'e <= 11). int('e)}" } }, "num_of_vimcfunct6": { "val": { "source": "val num_of_vimcfunct6 : vimcfunct6 -> {'e, (0 <= 'e & 'e <= 0). int('e)}", "type": "vimcfunct6 -> {'e, (0 <= 'e & 'e <= 0). int('e)}" } }, "num_of_vimfunct6": { "val": { "source": "val num_of_vimfunct6 : vimfunct6 -> {'e, (0 <= 'e & 'e <= 0). int('e)}", "type": "vimfunct6 -> {'e, (0 <= 'e & 'e <= 0). int('e)}" } }, "num_of_vimsfunct6": { "val": { "source": "val num_of_vimsfunct6 : vimsfunct6 -> {'e, (0 <= 'e & 'e <= 0). int('e)}", "type": "vimsfunct6 -> {'e, (0 <= 'e & 'e <= 0). int('e)}" } }, "num_of_visgfunct6": { "val": { "source": "val num_of_visgfunct6 : visgfunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "visgfunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_vlewidth": { "val": { "source": "val num_of_vlewidth : vlewidth -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "vlewidth -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_vmlsop": { "val": { "source": "val num_of_vmlsop : vmlsop -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vmlsop -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vsetop": { "val": { "source": "val num_of_vsetop : vsetop -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vsetop -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vvcmpfunct6": { "val": { "source": "val num_of_vvcmpfunct6 : vvcmpfunct6 -> {'e, (0 <= 'e & 'e <= 5). int('e)}", "type": "vvcmpfunct6 -> {'e, (0 <= 'e & 'e <= 5). int('e)}" } }, "num_of_vvfunct6": { "val": { "source": "val num_of_vvfunct6 : vvfunct6 -> {'e, (0 <= 'e & 'e <= 20). int('e)}", "type": "vvfunct6 -> {'e, (0 <= 'e & 'e <= 20). int('e)}" } }, "num_of_vvmcfunct6": { "val": { "source": "val num_of_vvmcfunct6 : vvmcfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vvmcfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vvmfunct6": { "val": { "source": "val num_of_vvmfunct6 : vvmfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vvmfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vvmsfunct6": { "val": { "source": "val num_of_vvmsfunct6 : vvmsfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vvmsfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vxcmpfunct6": { "val": { "source": "val num_of_vxcmpfunct6 : vxcmpfunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}", "type": "vxcmpfunct6 -> {'e, (0 <= 'e & 'e <= 7). int('e)}" } }, "num_of_vxfunct6": { "val": { "source": "val num_of_vxfunct6 : vxfunct6 -> {'e, (0 <= 'e & 'e <= 19). int('e)}", "type": "vxfunct6 -> {'e, (0 <= 'e & 'e <= 19). int('e)}" } }, "num_of_vxmcfunct6": { "val": { "source": "val num_of_vxmcfunct6 : vxmcfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vxmcfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vxmfunct6": { "val": { "source": "val num_of_vxmfunct6 : vxmfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vxmfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vxmsfunct6": { "val": { "source": "val num_of_vxmsfunct6 : vxmsfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "vxmsfunct6 -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "num_of_vxsgfunct6": { "val": { "source": "val num_of_vxsgfunct6 : vxsgfunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "vxsgfunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_wmvvfunct6": { "val": { "source": "val num_of_wmvvfunct6 : wmvvfunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}", "type": "wmvvfunct6 -> {'e, (0 <= 'e & 'e <= 2). int('e)}" } }, "num_of_wmvxfunct6": { "val": { "source": "val num_of_wmvxfunct6 : wmvxfunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "wmvxfunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_word_width": { "val": { "source": "val num_of_word_width : word_width -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "word_width -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_write_kind": { "val": { "source": "val num_of_write_kind : write_kind -> {'e, (0 <= 'e & 'e <= 10). int('e)}", "type": "write_kind -> {'e, (0 <= 'e & 'e <= 10). int('e)}" } }, "num_of_wvfunct6": { "val": { "source": "val num_of_wvfunct6 : wvfunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "wvfunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_wvvfunct6": { "val": { "source": "val num_of_wvvfunct6 : wvvfunct6 -> {'e, (0 <= 'e & 'e <= 6). int('e)}", "type": "wvvfunct6 -> {'e, (0 <= 'e & 'e <= 6). int('e)}" } }, "num_of_wvxfunct6": { "val": { "source": "val num_of_wvxfunct6 : wvxfunct6 -> {'e, (0 <= 'e & 'e <= 6). int('e)}", "type": "wvxfunct6 -> {'e, (0 <= 'e & 'e <= 6). int('e)}" } }, "num_of_wxfunct6": { "val": { "source": "val num_of_wxfunct6 : wxfunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}", "type": "wxfunct6 -> {'e, (0 <= 'e & 'e <= 3). int('e)}" } }, "num_of_zicondop": { "val": { "source": "val num_of_zicondop : zicondop -> {'e, (0 <= 'e & 'e <= 1). int('e)}", "type": "zicondop -> {'e, (0 <= 'e & 'e <= 1). int('e)}" } }, "nvFlag": { "val": { "source": "val nvFlag : unit -> bits(5)", "type": "unit -> bits(5)" } }, "nvfunct6_of_num": { "val": { "source": "val nvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nvfunct6" } }, "nvsfunct6_of_num": { "val": { "source": "val nvsfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nvsfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nvsfunct6" } }, "nvstype_mnemonic": { "val": { "source": "val nvstype_mnemonic : nvsfunct6 <-> string", "type": "nvsfunct6 <-> string" } }, "nvtype_mnemonic": { "val": { "source": "val nvtype_mnemonic : nvfunct6 <-> string", "type": "nvfunct6 <-> string" } }, "nxFlag": { "val": { "source": "val nxFlag : unit -> bits(5)", "type": "unit -> bits(5)" } }, "nxfunct6_of_num": { "val": { "source": "val nxfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nxfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nxfunct6" } }, "nxsfunct6_of_num": { "val": { "source": "val nxsfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nxsfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> nxsfunct6" } }, "nxstype_mnemonic": { "val": { "source": "val nxstype_mnemonic : nxsfunct6 <-> string", "type": "nxsfunct6 <-> string" } }, "nxtype_mnemonic": { "val": { "source": "val nxtype_mnemonic : nxfunct6 <-> string", "type": "nxfunct6 <-> string" } }, "ofFlag": { "val": { "source": "val ofFlag : unit -> bits(5)", "type": "unit -> bits(5)" } }, "offset_of_va": { "val": { "source": "val offset_of_va : bits(64) -> bits(PAGESIZE_BITS)", "type": "bits(64) -> bits(PAGESIZE_BITS)" } }, "ones": { "val": { "source": "val ones : forall 'n, 'n >= 0 . implicit('n) -> bits('n)", "type": "forall 'n, 'n >= 0 . implicit('n) -> bits('n)" } }, "opst_code": { "val": { "source": "val opst_code : seed_opst <-> bitvector(2)", "type": "seed_opst <-> bitvector(2)" } }, "opt_spc": { "val": { "source": "val opt_spc : unit <-> string", "type": "unit <-> string" } }, "or_bool": { "val": { "source": "val or_bool = pure {coq: \"orb\", _: \"or_bool\"}: forall ('p : Bool) ('q : Bool). (bool('p), bool('q)) -> bool(('p | 'q))", "type": "forall ('p : Bool) ('q : Bool). (bool('p), bool('q)) -> bool(('p | 'q))" } }, "or_vec": { "val": { "source": "val or_vec = pure {lem: \"or_vec\", c: \"or_bits\", coq: \"or_vec\", ocaml: \"or_vec\", interpreter: \"or_vec\"}: forall 'n.\n (bits('n), bits('n)) -> bits('n)", "type": "forall 'n. (bits('n), bits('n)) -> bits('n)" } }, "parse_hex_bits": { "val": { "source": "val \"parse_hex_bits\" : forall 'n, 'n > 0. (int('n), string) -> bits('n)", "type": "forall 'n, 'n > 0. (int('n), string) -> bits('n)" } }, "pc_alignment_mask": { "val": { "source": "val pc_alignment_mask : unit -> xlenbits", "type": "unit -> xlenbits" } }, "phys_mem_read": { "val": { "source": "val phys_mem_read : forall 'n, (0 < 'n & 'n <= max_mem_access).\n (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access).\n (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))" } }, "phys_mem_segments": { "val": { "source": "val phys_mem_segments : unit -> list((xlenbits, xlenbits))", "type": "unit -> list((xlenbits, xlenbits))" } }, "phys_mem_write": { "val": { "source": "val phys_mem_write : forall 'n, (0 < 'n & 'n <= max_mem_access).\n (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> MemoryOpResult(bool)", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access).\n (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> MemoryOpResult(bool)" } }, "plain_vector_access": { "val": { "source": "val plain_vector_access = pure {ocaml: \"access\", interpreter: \"access\", lem: \"access_list_dec\", coq: \"vec_access_dec\", c: \"vector_access\"}: forall 'n 'm ('a : Type), (0 <= 'm & 'm < 'n).\n (vector('n, 'a), int('m)) -> 'a", "type": "forall 'n 'm ('a : Type), (0 <= 'm & 'm < 'n). (vector('n, 'a), int('m)) -> 'a" } }, "plain_vector_update": { "val": { "source": "val plain_vector_update = pure {ocaml: \"update\", interpreter: \"update\", lem: \"update_list_dec\", coq: \"vec_update_dec\", c: \"vector_update\"}: forall 'n 'm ('a : Type), (0 <= 'm & 'm < 'n).\n (vector('n, 'a), int('m), 'a) -> vector('n, 'a)", "type": "forall 'n 'm ('a : Type), (0 <= 'm & 'm < 'n). (vector('n, 'a), int('m), 'a) -> vector('n, 'a)" } }, "plat_clint_base": { "val": { "source": "val plat_clint_base = {ocaml: \"Platform.clint_base\", interpreter: \"Platform.clint_base\", c: \"plat_clint_base\", lem: \"plat_clint_base\"} : unit -> xlenbits", "type": "unit -> xlenbits" } }, "plat_clint_size": { "val": { "source": "val plat_clint_size = {ocaml: \"Platform.clint_size\", interpreter: \"Platform.clint_size\", c: \"plat_clint_size\", lem: \"plat_clint_size\"} : unit -> xlenbits", "type": "unit -> xlenbits" } }, "plat_enable_dirty_update": { "val": { "source": "val plat_enable_dirty_update = {ocaml: \"Platform.enable_dirty_update\",\n interpreter: \"Platform.enable_dirty_update\",\n c: \"plat_enable_dirty_update\",\n lem: \"plat_enable_dirty_update\"} : unit -> bool", "type": "unit -> bool" } }, "plat_enable_misaligned_access": { "val": { "source": "val plat_enable_misaligned_access = {ocaml: \"Platform.enable_misaligned_access\",\n interpreter: \"Platform.enable_misaligned_access\",\n c: \"plat_enable_misaligned_access\",\n lem: \"plat_enable_misaligned_access\"} : unit -> bool", "type": "unit -> bool" } }, "plat_htif_tohost": { "val": { "source": "val plat_htif_tohost = {ocaml: \"Platform.htif_tohost\", c: \"plat_htif_tohost\", lem: \"plat_htif_tohost\"} : unit -> xlenbits", "type": "unit -> xlenbits" } }, "plat_insns_per_tick": { "val": { "source": "val plat_insns_per_tick = {ocaml: \"Platform.insns_per_tick\", interpreter: \"Platform.insns_per_tick\", c: \"plat_insns_per_tick\", lem: \"plat_insns_per_tick\"} : unit -> int", "type": "unit -> int" } }, "plat_mtval_has_illegal_inst_bits": { "val": { "source": "val plat_mtval_has_illegal_inst_bits = {ocaml: \"Platform.mtval_has_illegal_inst_bits\",\n interpreter: \"Platform.mtval_has_illegal_inst_bits\",\n c: \"plat_mtval_has_illegal_inst_bits\",\n lem: \"plat_mtval_has_illegal_inst_bits\"} : unit -> bool", "type": "unit -> bool" } }, "plat_ram_base": { "val": { "source": "val plat_ram_base = {c: \"plat_ram_base\", ocaml: \"Platform.dram_base\", interpreter: \"Platform.dram_base\", lem: \"plat_ram_base\"} : unit -> xlenbits", "type": "unit -> xlenbits" } }, "plat_ram_size": { "val": { "source": "val plat_ram_size = {c: \"plat_ram_size\", ocaml: \"Platform.dram_size\", interpreter: \"Platform.dram_size\", lem: \"plat_ram_size\"} : unit -> xlenbits", "type": "unit -> xlenbits" } }, "plat_rom_base": { "val": { "source": "val plat_rom_base = {ocaml: \"Platform.rom_base\", interpreter: \"Platform.rom_base\", c: \"plat_rom_base\", lem: \"plat_rom_base\"} : unit -> xlenbits", "type": "unit -> xlenbits" } }, "plat_rom_size": { "val": { "source": "val plat_rom_size = {ocaml: \"Platform.rom_size\", interpreter: \"Platform.rom_size\", c: \"plat_rom_size\", lem: \"plat_rom_size\"} : unit -> xlenbits", "type": "unit -> xlenbits" } }, "plat_term_read": { "val": { "source": "val plat_term_read = {ocaml: \"Platform.term_read\", c: \"plat_term_read\", lem: \"plat_term_read\"} : unit -> bits(8)", "type": "unit -> bits(8)" } }, "plat_term_write": { "val": { "source": "val plat_term_write = {ocaml: \"Platform.term_write\", c: \"plat_term_write\", lem: \"plat_term_write\"} : bits(8) -> unit", "type": "bits(8) -> unit" } }, "platform_wfi": { "val": { "source": "val platform_wfi : unit -> unit", "type": "unit -> unit" } }, "pmpAddrMatchType_of_bits": { "val": { "source": "val pmpAddrMatchType_of_bits : bits(2) -> PmpAddrMatchType", "type": "bits(2) -> PmpAddrMatchType" } }, "pmpAddrMatchType_to_bits": { "val": { "source": "val pmpAddrMatchType_to_bits : PmpAddrMatchType -> bits(2)", "type": "PmpAddrMatchType -> bits(2)" } }, "pmpAddrMatch_of_num": { "val": { "source": "val pmpAddrMatch_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> pmpAddrMatch", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> pmpAddrMatch" } }, "pmpAddrRange": { "val": { "source": "val pmpAddrRange : (Pmpcfg_ent, xlenbits, xlenbits) -> pmp_addr_range", "type": "(Pmpcfg_ent, xlenbits, xlenbits) -> pmp_addr_range" } }, "pmpCheck": { "val": { "source": "val pmpCheck : forall 'n, 'n > 0. (xlenbits, int('n), AccessType(ext_access_type), Privilege) -> option(ExceptionType)", "type": "forall 'n, 'n > 0. (xlenbits, int('n), AccessType(ext_access_type), Privilege) -> option(ExceptionType)" } }, "pmpCheckPerms": { "val": { "source": "val pmpCheckPerms: (Pmpcfg_ent, AccessType(ext_access_type), Privilege) -> bool", "type": "(Pmpcfg_ent, AccessType(ext_access_type), Privilege) -> bool" } }, "pmpCheckRWX": { "val": { "source": "val pmpCheckRWX: (Pmpcfg_ent, AccessType(ext_access_type)) -> bool", "type": "(Pmpcfg_ent, AccessType(ext_access_type)) -> bool" } }, "pmpLocked": { "val": { "source": "val pmpLocked : Pmpcfg_ent -> bool", "type": "Pmpcfg_ent -> bool" } }, "pmpMatchAddr": { "val": { "source": "val pmpMatchAddr : (xlenbits, xlenbits, pmp_addr_range) -> pmpAddrMatch", "type": "(xlenbits, xlenbits, pmp_addr_range) -> pmpAddrMatch" } }, "pmpMatchEntry": { "val": { "source": "val pmpMatchEntry : (xlenbits, xlenbits, AccessType(ext_access_type), Privilege, Pmpcfg_ent, xlenbits, xlenbits) -> pmpMatch", "type": "(xlenbits, xlenbits, AccessType(ext_access_type), Privilege, Pmpcfg_ent, xlenbits, xlenbits) -> pmpMatch" } }, "pmpMatch_of_num": { "val": { "source": "val pmpMatch_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> pmpMatch", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> pmpMatch" } }, "pmpReadAddrReg": { "val": { "source": "val pmpReadAddrReg : range(0, 63) -> xlenbits", "type": "range(0, 63) -> xlenbits" } }, "pmpReadCfgReg": { "val": { "source": "val pmpReadCfgReg : range(0, 15) -> xlenbits", "type": "range(0, 15) -> xlenbits" } }, "pmpTORLocked": { "val": { "source": "val pmpTORLocked : Pmpcfg_ent -> bool", "type": "Pmpcfg_ent -> bool" } }, "pmpWriteAddr": { "val": { "source": "val pmpWriteAddr : (bool, bool, xlenbits, xlenbits) -> xlenbits", "type": "(bool, bool, xlenbits, xlenbits) -> xlenbits" } }, "pmpWriteAddrReg": { "val": { "source": "val pmpWriteAddrReg : (range(0, 63), xlenbits) -> unit", "type": "(range(0, 63), xlenbits) -> unit" } }, "pmpWriteCfg": { "val": { "source": "val pmpWriteCfg : (range(0, 63), Pmpcfg_ent, bits(8)) -> Pmpcfg_ent", "type": "(range(0, 63), Pmpcfg_ent, bits(8)) -> Pmpcfg_ent" } }, "pmpWriteCfgReg": { "val": { "source": "val pmpWriteCfgReg : (range(0, 15), xlenbits) -> unit", "type": "(range(0, 15), xlenbits) -> unit" } }, "pmp_mem_read": { "val": { "source": "val pmp_mem_read : forall 'n, (0 < 'n & 'n <= max_mem_access).\n (AccessType(ext_access_type), Privilege, xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access).\n (AccessType(ext_access_type), Privilege, xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta))" } }, "pmp_mem_write": { "val": { "source": "val pmp_mem_write : forall 'n, (0 < 'n & 'n <= max_mem_access).\n (write_kind, xlenbits, int('n), bits(8 * 'n), AccessType(ext_access_type), Privilege, mem_meta) -> MemoryOpResult(bool)", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access).\n (write_kind, xlenbits, int('n), bits(8 * 'n), AccessType(ext_access_type), Privilege, mem_meta) -> MemoryOpResult(bool)" } }, "pow2": { "val": { "source": "val pow2 = \"pow2\" : forall 'n. int('n) -> int(2 ^ 'n)", "type": "forall 'n. int('n) -> int(2 ^ 'n)" } }, "prepare_trap_vector": { "val": { "source": "val prepare_trap_vector : (Privilege, Mcause) -> xlenbits", "type": "(Privilege, Mcause) -> xlenbits" } }, "prepare_xret_target": { "val": { "source": "val prepare_xret_target : (Privilege) -> xlenbits", "type": "(Privilege) -> xlenbits" } }, "prerr": { "val": { "source": "val prerr = pure {_: \"prerr\"}: string -> unit", "type": "string -> unit" } }, "prerr_bits": { "val": { "source": "val prerr_bits = pure {_: \"prerr_bits\"}: forall 'n. (string, bits('n)) -> unit", "type": "forall 'n. (string, bits('n)) -> unit" } }, "prerr_endline": { "val": { "source": "val prerr_endline = pure {_: \"prerr_endline\"}: string -> unit", "type": "string -> unit" } }, "prerr_int": { "val": { "source": "val prerr_int = pure {_: \"prerr_int\"}: (string, int) -> unit", "type": "(string, int) -> unit" } }, "print": { "val": { "source": "val print = \"print_endline\" : string -> unit", "type": "string -> unit" } }, "print_bits": { "val": { "source": "val print_bits = pure {_: \"print_bits\"}: forall 'n. (string, bits('n)) -> unit", "type": "forall 'n. (string, bits('n)) -> unit" } }, "print_endline": { "val": { "source": "val print_endline = pure {_: \"print_endline\"}: string -> unit", "type": "string -> unit" } }, "print_insn": { "val": { "source": "val print_insn : ast -> string", "type": "ast -> string" } }, "print_instr": { "val": { "source": "val print_instr = {ocaml: \"Platform.print_instr\", interpreter: \"print_endline\", c: \"print_instr\", lem: \"print_dbg\", _: \"print_endline\"} : string -> unit", "type": "string -> unit" } }, "print_int": { "val": { "source": "val print_int = pure {_: \"print_int\"}: (string, int) -> unit", "type": "(string, int) -> unit" } }, "print_mem": { "val": { "source": "val print_mem = {ocaml: \"Platform.print_mem_access\", interpreter: \"print_endline\", c: \"print_mem_access\", lem: \"print_dbg\", _: \"print_endline\"} : string -> unit", "type": "string -> unit" } }, "print_platform": { "val": { "source": "val print_platform = {ocaml: \"Platform.print_platform\", interpreter: \"print_endline\", c: \"print_platform\", lem: \"print_dbg\", _: \"print_endline\"} : string -> unit", "type": "string -> unit" } }, "print_reg": { "val": { "source": "val print_reg = {ocaml: \"Platform.print_reg\", interpreter: \"print_endline\", c: \"print_reg\", lem: \"print_dbg\", _: \"print_endline\"} : string -> unit", "type": "string -> unit" } }, "print_string": { "val": { "source": "val print_string = \"print_string\" : (string, string) -> unit", "type": "(string, string) -> unit" } }, "privLevel_of_bits": { "val": { "source": "val privLevel_of_bits : priv_level -> Privilege", "type": "priv_level -> Privilege" } }, "privLevel_to_bits": { "val": { "source": "val privLevel_to_bits : Privilege -> priv_level", "type": "Privilege -> priv_level" } }, "privLevel_to_str": { "val": { "source": "val privLevel_to_str : Privilege -> string", "type": "Privilege -> string" } }, "processPending": { "val": { "source": "val processPending : (Minterrupts, Minterrupts, xlenbits, bool) -> interrupt_set", "type": "(Minterrupts, Minterrupts, xlenbits, bool) -> interrupt_set" } }, "process_fload16": { "val": { "source": "val process_fload16 : (regidx, xlenbits, MemoryOpResult(bits(16)))\n -> Retired", "type": "(regidx, xlenbits, MemoryOpResult(bits(16)))\n -> Retired" } }, "process_fload32": { "val": { "source": "val process_fload32 : (regidx, xlenbits, MemoryOpResult(bits(32)))\n -> Retired", "type": "(regidx, xlenbits, MemoryOpResult(bits(32)))\n -> Retired" } }, "process_fload64": { "val": { "source": "val process_fload64 : (regidx, xlenbits, MemoryOpResult(bits(64)))\n -> Retired", "type": "(regidx, xlenbits, MemoryOpResult(bits(64)))\n -> Retired" } }, "process_fstore": { "val": { "source": "val process_fstore : (xlenbits, MemoryOpResult(bool)) -> Retired", "type": "(xlenbits, MemoryOpResult(bool)) -> Retired" } }, "process_load": { "val": { "source": "val process_load : forall 'n, 0 < 'n <= xlen_bytes. (regidx, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> Retired", "type": "forall 'n, 0 < 'n <= xlen_bytes. (regidx, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> Retired" } }, "process_loadres": { "val": { "source": "val process_loadres : forall 'n, 0 < 'n <= xlen_bytes. (regidx, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> Retired", "type": "forall 'n, 0 < 'n <= xlen_bytes. (regidx, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> Retired" } }, "process_rfvv_single": { "val": { "source": "val process_rfvv_single: forall 'n 'm 'p, 'n >= 0 & 'm in {8, 16, 32, 64}. (rfvvfunct6, bits(1), regidx, regidx, regidx, int('n), int('m), int('p)) -> Retired", "type": "forall 'n 'm 'p, 'n >= 0 & 'm in {8, 16, 32, 64}. (rfvvfunct6, bits(1), regidx, regidx, regidx, int('n), int('m), int('p)) -> Retired" } }, "process_rfvv_widen": { "val": { "source": "val process_rfvv_widen: forall 'n 'm 'p, 'n >= 0 & 'm in {8, 16, 32, 64}. (rfvvfunct6, bits(1), regidx, regidx, regidx, int('n), int('m), int('p)) -> Retired", "type": "forall 'n 'm 'p, 'n >= 0 & 'm in {8, 16, 32, 64}. (rfvvfunct6, bits(1), regidx, regidx, regidx, int('n), int('m), int('p)) -> Retired" } }, "process_vlre": { "val": { "source": "val process_vlre : forall 'f 'b 'n, ('f in {1, 2, 4, 8}) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), regidx, int('b), regidx, int('n)) -> Retired", "type": "forall 'f 'b 'n, ('f in {1, 2, 4, 8}) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), regidx, int('b), regidx, int('n)) -> Retired" } }, "process_vlseg": { "val": { "source": "val process_vlseg : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired", "type": "forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired" } }, "process_vlsegff": { "val": { "source": "val process_vlsegff : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired", "type": "forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired" } }, "process_vlsseg": { "val": { "source": "val process_vlsseg : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, regidx, int('p), int('n)) -> Retired", "type": "forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, regidx, int('p), int('n)) -> Retired" } }, "process_vlxseg": { "val": { "source": "val process_vlxseg : forall 'f 'ib 'db 'ip 'dp 'n, (0 < 'f & 'f <= 8) & ('ib in {1, 2, 4, 8}) & ('db in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('ib), int('db), int('ip), int('dp), regidx, regidx, int('n), int) -> Retired", "type": "forall 'f 'ib 'db 'ip 'dp 'n, (0 < 'f & 'f <= 8) & ('ib in {1, 2, 4, 8}) & ('db in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('ib), int('db), int('ip), int('dp), regidx, regidx, int('n), int) -> Retired" } }, "process_vm": { "val": { "source": "val process_vm : forall 'n 'l, ('n >= 0 & 'l >= 0). (regidx, regidx, int('n), int('l), vmlsop) -> Retired", "type": "forall 'n 'l, ('n >= 0 & 'l >= 0). (regidx, regidx, int('n), int('l), vmlsop) -> Retired" } }, "process_vsre": { "val": { "source": "val process_vsre : forall 'f 'b 'n, ('f in {1, 2, 4, 8}) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), int('b), regidx, regidx, int('n)) -> Retired", "type": "forall 'f 'b 'n, ('f in {1, 2, 4, 8}) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), int('b), regidx, regidx, int('n)) -> Retired" } }, "process_vsseg": { "val": { "source": "val process_vsseg : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired", "type": "forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired" } }, "process_vssseg": { "val": { "source": "val process_vssseg : forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, regidx, int('p), int('n)) -> Retired", "type": "forall 'f 'b 'n 'p, (0 < 'f & 'f <= 8) & ('b in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('b), regidx, regidx, int('p), int('n)) -> Retired" } }, "process_vsxseg": { "val": { "source": "val process_vsxseg : forall 'f 'ib 'db 'ip 'dp 'n, (0 < 'f & 'f <= 8) & ('ib in {1, 2, 4, 8}) & ('db in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('ib), int('db), int('ip), int('dp), regidx, regidx, int('n), int) -> Retired", "type": "forall 'f 'ib 'db 'ip 'dp 'n, (0 < 'f & 'f <= 8) & ('ib in {1, 2, 4, 8}) & ('db in {1, 2, 4, 8}) & ('n >= 0). (int('f), bits(1), regidx, int('ib), int('db), int('ip), int('dp), regidx, regidx, int('n), int) -> Retired" } }, "pt_walk": { "val": { "source": "val pt_walk : (SV_Params,\n bits(64), // virtual addr\n AccessType(ext_access_type), // Read/Write/ReadWrite/Execute\n Privilege, // User/Supervisor/Machine\n bool, // mstatus.MXR\n bool, // do_sum\n bits(64), // PT base addr\n PTW_Level, // tree level for this recursive call\n bool, // global translation,\n ext_ptw) // ext_ptw\n -> PTW_Result", "type": "(SV_Params,\n bits(64), // virtual addr\n AccessType(ext_access_type), // Read/Write/ReadWrite/Execute\n Privilege, // User/Supervisor/Machine\n bool, // mstatus.MXR\n bool, // do_sum\n bits(64), // PT base addr\n PTW_Level, // tree level for this recursive call\n bool, // global translation,\n ext_ptw) // ext_ptw\n -> PTW_Result" } }, "pte_is_invalid": { "val": { "source": "val pte_is_invalid : PTE_Flags -> bool", "type": "PTE_Flags -> bool" } }, "pte_is_ptr": { "val": { "source": "val pte_is_ptr : PTE_Flags -> bool", "type": "PTE_Flags -> bool" } }, "ptw_error_to_str": { "val": { "source": "val ptw_error_to_str : PTW_Error -> string", "type": "PTW_Error -> string" } }, "quot_round_zero": { "val": { "source": "val quot_round_zero = {ocaml: \"quot_round_zero\", interpreter: \"quot_round_zero\", lem: \"hardware_quot\", c: \"tdiv_int\", coq: \"Z.quot\"} : (int, int) -> int", "type": "(int, int) -> int" } }, "rF": { "val": { "source": "val rF : forall 'n, 0 <= 'n < 32. regno('n) -> flenbits", "type": "forall 'n, 0 <= 'n < 32. regno('n) -> flenbits" } }, "rF_D": { "val": { "source": "val rF_D : bits(5) -> bits(64)", "type": "bits(5) -> bits(64)" } }, "rF_H": { "val": { "source": "val rF_H : bits(5) -> bits(16)", "type": "bits(5) -> bits(16)" } }, "rF_S": { "val": { "source": "val rF_S : bits(5) -> bits(32)", "type": "bits(5) -> bits(32)" } }, "rF_bits": { "val": { "source": "val rF_bits : bits(5) -> flenbits", "type": "bits(5) -> flenbits" } }, "rF_or_X_D": { "val": { "source": "val rF_or_X_D : bits(5) -> bits(64)", "type": "bits(5) -> bits(64)" } }, "rF_or_X_H": { "val": { "source": "val rF_or_X_H : bits(5) -> bits(16)", "type": "bits(5) -> bits(16)" } }, "rF_or_X_S": { "val": { "source": "val rF_or_X_S : bits(5) -> bits(32)", "type": "bits(5) -> bits(32)" } }, "rV": { "val": { "source": "val rV : forall 'n, 0 <= 'n < 32. regno('n) -> vregtype", "type": "forall 'n, 0 <= 'n < 32. regno('n) -> vregtype" } }, "rV_bits": { "val": { "source": "val rV_bits : bits(5) -> vregtype", "type": "bits(5) -> vregtype" } }, "rX": { "val": { "source": "val rX : forall 'n, 0 <= 'n < 32. regno('n) -> xlenbits", "type": "forall 'n, 0 <= 'n < 32. regno('n) -> xlenbits" } }, "rX_bits": { "val": { "source": "val rX_bits : bits(5) -> xlenbits", "type": "bits(5) -> xlenbits" } }, "readCSR": { "val": { "source": "val readCSR : csreg -> xlenbits", "type": "csreg -> xlenbits" } }, "read_kind_of_flags": { "val": { "source": "val read_kind_of_flags : (bool, bool, bool) -> option(read_kind)", "type": "(bool, bool, bool) -> option(read_kind)" } }, "read_kind_of_num": { "val": { "source": "val read_kind_of_num : forall 'e, (0 <= 'e & 'e <= 12). int('e) -> read_kind", "type": "forall 'e, (0 <= 'e & 'e <= 12). int('e) -> read_kind" } }, "read_ram": { "val": { "source": "val read_ram = {lem: \"read_ram\", coq: \"read_ram\"} : forall 'n, 0 < 'n <= max_mem_access . (read_kind, xlenbits, int('n), bool) -> (bits(8 * 'n), mem_meta)", "type": "forall 'n, 0 < 'n <= max_mem_access . (read_kind, xlenbits, int('n), bool) -> (bits(8 * 'n), mem_meta)" } }, "read_seed_csr": { "val": { "source": "val read_seed_csr : unit -> xlenbits", "type": "unit -> xlenbits" } }, "read_single_element": { "val": { "source": "val read_single_element : forall 'm 'x, 8 <= 'm <= 128. (int('m), int('x), regidx) -> bits('m)", "type": "forall 'm 'x, 8 <= 'm <= 128. (int('m), int('x), regidx) -> bits('m)" } }, "read_single_vreg": { "val": { "source": "val read_single_vreg : forall 'n 'm, 'n >= 0. (int('n), int('m), regidx) -> vector('n, dec, bits('m))", "type": "forall 'n 'm, 'n >= 0. (int('n), int('m), regidx) -> vector('n, dec, bits('m))" } }, "read_vmask": { "val": { "source": "val read_vmask : forall 'n, 'n >= 0. (int('n), bits(1), regidx) -> vector('n, dec, bool)", "type": "forall 'n, 'n >= 0. (int('n), bits(1), regidx) -> vector('n, dec, bool)" } }, "read_vmask_carry": { "val": { "source": "val read_vmask_carry : forall 'n, 'n >= 0. (int('n), bits(1), regidx) -> vector('n, dec, bool)", "type": "forall 'n, 'n >= 0. (int('n), bits(1), regidx) -> vector('n, dec, bool)" } }, "read_vreg": { "val": { "source": "val read_vreg : forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), regidx) -> vector('n, dec, bits('m))", "type": "forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), regidx) -> vector('n, dec, bits('m))" } }, "read_vreg_seg": { "val": { "source": "val read_vreg_seg : forall 'n 'm 'p 'q, 'n >= 0 & 'q >= 0. (int('n), int('m), int('p), int('q), regidx) -> vector('n, dec, bits('q * 'm))", "type": "forall 'n 'm 'p 'q, 'n >= 0 & 'q >= 0. (int('n), int('m), int('p), int('q), regidx) -> vector('n, dec, bits('q * 'm))" } }, "recip7": { "val": { "source": "val recip7 : forall 'm, 'm in {16, 32, 64}. (bits('m), bits(3), bool) -> (bool, bits_D)", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bits(3), bool) -> (bool, bits_D)" } }, "reg_name": { "val": { "source": "val reg_name : bits(5) <-> string", "type": "bits(5) <-> string" } }, "reg_name_abi": { "val": { "source": "val reg_name_abi : regidx -> string", "type": "regidx -> string" } }, "regidx_to_regno": { "val": { "source": "val regidx_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)}", "type": "bits(5) -> {'n, 0 <= 'n < 32. regno('n)}" } }, "regval_from_reg": { "val": { "source": "val regval_from_reg : regtype -> xlenbits", "type": "regtype -> xlenbits" } }, "regval_into_reg": { "val": { "source": "val regval_into_reg : xlenbits -> regtype", "type": "xlenbits -> regtype" } }, "rem_round_zero": { "val": { "source": "val rem_round_zero = {ocaml: \"rem_round_zero\", interpreter: \"rem_round_zero\", lem: \"hardware_mod\", c: \"tmod_int\", coq: \"Z.rem\"} : (int, int) -> int", "type": "(int, int) -> int" } }, "replicate_bits": { "val": { "source": "val replicate_bits = pure {_: \"replicate_bits\"}: forall 'n 'm. (bits('n), int('m)) -> bits('n * 'm)", "type": "forall 'n 'm. (bits('n), int('m)) -> bits('n * 'm)" } }, "report_invalid_width": { "val": { "source": "val report_invalid_width : forall ('a : Type). (string, int, word_width, string) -> 'a", "type": "forall ('a : Type). (string, int, word_width, string) -> 'a" } }, "reset_htif": { "val": { "source": "val reset_htif : unit -> unit", "type": "unit -> unit" } }, "retire_instruction": { "val": { "source": "val retire_instruction : unit -> unit", "type": "unit -> unit" } }, "reverse_bits_in_byte": { "val": { "source": "val reverse_bits_in_byte : bits(8) -> bits(8)", "type": "bits(8) -> bits(8)" } }, "rfvvfunct6_of_num": { "val": { "source": "val rfvvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 5). int('e) -> rfvvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 5). int('e) -> rfvvfunct6" } }, "rfvvtype_mnemonic": { "val": { "source": "val rfvvtype_mnemonic : rfvvfunct6 <-> string", "type": "rfvvfunct6 <-> string" } }, "riscv_f16Add": { "val": { "source": "val riscv_f16Add : (bits_rm, bits_H, bits_H) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H, bits_H) -> (bits_fflags, bits_H)" } }, "riscv_f16Div": { "val": { "source": "val riscv_f16Div : (bits_rm, bits_H, bits_H) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H, bits_H) -> (bits_fflags, bits_H)" } }, "riscv_f16Eq": { "val": { "source": "val riscv_f16Eq : (bits_H, bits_H) -> (bits_fflags, bool)", "type": "(bits_H, bits_H) -> (bits_fflags, bool)" } }, "riscv_f16Le": { "val": { "source": "val riscv_f16Le : (bits_H, bits_H) -> (bits_fflags, bool)", "type": "(bits_H, bits_H) -> (bits_fflags, bool)" } }, "riscv_f16Le_quiet": { "val": { "source": "val riscv_f16Le_quiet : (bits_H, bits_H) -> (bits_fflags, bool)", "type": "(bits_H, bits_H) -> (bits_fflags, bool)" } }, "riscv_f16Lt": { "val": { "source": "val riscv_f16Lt : (bits_H, bits_H) -> (bits_fflags, bool)", "type": "(bits_H, bits_H) -> (bits_fflags, bool)" } }, "riscv_f16Lt_quiet": { "val": { "source": "val riscv_f16Lt_quiet : (bits_H, bits_H) -> (bits_fflags, bool)", "type": "(bits_H, bits_H) -> (bits_fflags, bool)" } }, "riscv_f16Mul": { "val": { "source": "val riscv_f16Mul : (bits_rm, bits_H, bits_H) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H, bits_H) -> (bits_fflags, bits_H)" } }, "riscv_f16MulAdd": { "val": { "source": "val riscv_f16MulAdd : (bits_rm, bits_H, bits_H, bits_H) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H, bits_H, bits_H) -> (bits_fflags, bits_H)" } }, "riscv_f16Recip7": { "val": { "source": "val riscv_f16Recip7 : (bits_rm, bits_H) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_H)" } }, "riscv_f16Rsqrte7": { "val": { "source": "val riscv_f16Rsqrte7 : (bits_rm, bits_H) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_H)" } }, "riscv_f16Sqrt": { "val": { "source": "val riscv_f16Sqrt : (bits_rm, bits_H) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_H)" } }, "riscv_f16Sub": { "val": { "source": "val riscv_f16Sub : (bits_rm, bits_H, bits_H) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H, bits_H) -> (bits_fflags, bits_H)" } }, "riscv_f16ToF32": { "val": { "source": "val riscv_f16ToF32 : (bits_rm, bits_H) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_S)" } }, "riscv_f16ToF64": { "val": { "source": "val riscv_f16ToF64 : (bits_rm, bits_H) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_D)" } }, "riscv_f16ToI16": { "val": { "source": "val riscv_f16ToI16 : (bits_rm, bits_H) -> (bits_fflags, bits(16))", "type": "(bits_rm, bits_H) -> (bits_fflags, bits(16))" } }, "riscv_f16ToI32": { "val": { "source": "val riscv_f16ToI32 : (bits_rm, bits_H) -> (bits_fflags, bits_W)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_W)" } }, "riscv_f16ToI64": { "val": { "source": "val riscv_f16ToI64 : (bits_rm, bits_H) -> (bits_fflags, bits_L)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_L)" } }, "riscv_f16ToI8": { "val": { "source": "val riscv_f16ToI8 : (bits_rm, bits_H) -> (bits_fflags, bits(8))", "type": "(bits_rm, bits_H) -> (bits_fflags, bits(8))" } }, "riscv_f16ToUi16": { "val": { "source": "val riscv_f16ToUi16 : (bits_rm, bits_H) -> (bits_fflags, bits(16))", "type": "(bits_rm, bits_H) -> (bits_fflags, bits(16))" } }, "riscv_f16ToUi32": { "val": { "source": "val riscv_f16ToUi32 : (bits_rm, bits_H) -> (bits_fflags, bits_WU)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_WU)" } }, "riscv_f16ToUi64": { "val": { "source": "val riscv_f16ToUi64 : (bits_rm, bits_H) -> (bits_fflags, bits_LU)", "type": "(bits_rm, bits_H) -> (bits_fflags, bits_LU)" } }, "riscv_f16ToUi8": { "val": { "source": "val riscv_f16ToUi8 : (bits_rm, bits_H) -> (bits_fflags, bits(8))", "type": "(bits_rm, bits_H) -> (bits_fflags, bits(8))" } }, "riscv_f16roundToInt": { "val": { "source": "val riscv_f16roundToInt : (bits_rm, bits_H, bool) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_H, bool) -> (bits_fflags, bits_H)" } }, "riscv_f32Add": { "val": { "source": "val riscv_f32Add : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S)" } }, "riscv_f32Div": { "val": { "source": "val riscv_f32Div : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S)" } }, "riscv_f32Eq": { "val": { "source": "val riscv_f32Eq : (bits_S, bits_S) -> (bits_fflags, bool)", "type": "(bits_S, bits_S) -> (bits_fflags, bool)" } }, "riscv_f32Le": { "val": { "source": "val riscv_f32Le : (bits_S, bits_S) -> (bits_fflags, bool)", "type": "(bits_S, bits_S) -> (bits_fflags, bool)" } }, "riscv_f32Le_quiet": { "val": { "source": "val riscv_f32Le_quiet : (bits_S, bits_S) -> (bits_fflags, bool)", "type": "(bits_S, bits_S) -> (bits_fflags, bool)" } }, "riscv_f32Lt": { "val": { "source": "val riscv_f32Lt : (bits_S, bits_S) -> (bits_fflags, bool)", "type": "(bits_S, bits_S) -> (bits_fflags, bool)" } }, "riscv_f32Lt_quiet": { "val": { "source": "val riscv_f32Lt_quiet : (bits_S, bits_S) -> (bits_fflags, bool)", "type": "(bits_S, bits_S) -> (bits_fflags, bool)" } }, "riscv_f32Mul": { "val": { "source": "val riscv_f32Mul : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S)" } }, "riscv_f32MulAdd": { "val": { "source": "val riscv_f32MulAdd : (bits_rm, bits_S, bits_S, bits_S) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S, bits_S, bits_S) -> (bits_fflags, bits_S)" } }, "riscv_f32Recip7": { "val": { "source": "val riscv_f32Recip7 : (bits_rm, bits_S) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_S)" } }, "riscv_f32Rsqrte7": { "val": { "source": "val riscv_f32Rsqrte7 : (bits_rm, bits_S) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_S)" } }, "riscv_f32Sqrt": { "val": { "source": "val riscv_f32Sqrt : (bits_rm, bits_S) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_S)" } }, "riscv_f32Sub": { "val": { "source": "val riscv_f32Sub : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S)" } }, "riscv_f32ToF16": { "val": { "source": "val riscv_f32ToF16 : (bits_rm, bits_S) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_H)" } }, "riscv_f32ToF64": { "val": { "source": "val riscv_f32ToF64 : (bits_rm, bits_S) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_D)" } }, "riscv_f32ToI16": { "val": { "source": "val riscv_f32ToI16 : (bits_rm, bits_S) -> (bits_fflags, bits(16))", "type": "(bits_rm, bits_S) -> (bits_fflags, bits(16))" } }, "riscv_f32ToI32": { "val": { "source": "val riscv_f32ToI32 : (bits_rm, bits_S) -> (bits_fflags, bits_W)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_W)" } }, "riscv_f32ToI64": { "val": { "source": "val riscv_f32ToI64 : (bits_rm, bits_S) -> (bits_fflags, bits_L)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_L)" } }, "riscv_f32ToUi16": { "val": { "source": "val riscv_f32ToUi16 : (bits_rm, bits_S) -> (bits_fflags, bits(16))", "type": "(bits_rm, bits_S) -> (bits_fflags, bits(16))" } }, "riscv_f32ToUi32": { "val": { "source": "val riscv_f32ToUi32 : (bits_rm, bits_S) -> (bits_fflags, bits_WU)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_WU)" } }, "riscv_f32ToUi64": { "val": { "source": "val riscv_f32ToUi64 : (bits_rm, bits_S) -> (bits_fflags, bits_LU)", "type": "(bits_rm, bits_S) -> (bits_fflags, bits_LU)" } }, "riscv_f32roundToInt": { "val": { "source": "val riscv_f32roundToInt : (bits_rm, bits_S, bool) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_S, bool) -> (bits_fflags, bits_S)" } }, "riscv_f64Add": { "val": { "source": "val riscv_f64Add : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D)" } }, "riscv_f64Div": { "val": { "source": "val riscv_f64Div : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D)" } }, "riscv_f64Eq": { "val": { "source": "val riscv_f64Eq : (bits_D, bits_D) -> (bits_fflags, bool)", "type": "(bits_D, bits_D) -> (bits_fflags, bool)" } }, "riscv_f64Le": { "val": { "source": "val riscv_f64Le : (bits_D, bits_D) -> (bits_fflags, bool)", "type": "(bits_D, bits_D) -> (bits_fflags, bool)" } }, "riscv_f64Le_quiet": { "val": { "source": "val riscv_f64Le_quiet : (bits_D, bits_D) -> (bits_fflags, bool)", "type": "(bits_D, bits_D) -> (bits_fflags, bool)" } }, "riscv_f64Lt": { "val": { "source": "val riscv_f64Lt : (bits_D, bits_D) -> (bits_fflags, bool)", "type": "(bits_D, bits_D) -> (bits_fflags, bool)" } }, "riscv_f64Lt_quiet": { "val": { "source": "val riscv_f64Lt_quiet : (bits_D, bits_D) -> (bits_fflags, bool)", "type": "(bits_D, bits_D) -> (bits_fflags, bool)" } }, "riscv_f64Mul": { "val": { "source": "val riscv_f64Mul : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D)" } }, "riscv_f64MulAdd": { "val": { "source": "val riscv_f64MulAdd : (bits_rm, bits_D, bits_D, bits_D) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D, bits_D, bits_D) -> (bits_fflags, bits_D)" } }, "riscv_f64Recip7": { "val": { "source": "val riscv_f64Recip7 : (bits_rm, bits_D) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_D)" } }, "riscv_f64Rsqrte7": { "val": { "source": "val riscv_f64Rsqrte7 : (bits_rm, bits_D) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_D)" } }, "riscv_f64Sqrt": { "val": { "source": "val riscv_f64Sqrt : (bits_rm, bits_D) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_D)" } }, "riscv_f64Sub": { "val": { "source": "val riscv_f64Sub : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D)" } }, "riscv_f64ToF16": { "val": { "source": "val riscv_f64ToF16 : (bits_rm, bits_D) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_H)" } }, "riscv_f64ToF32": { "val": { "source": "val riscv_f64ToF32 : (bits_rm, bits_D) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_S)" } }, "riscv_f64ToI32": { "val": { "source": "val riscv_f64ToI32 : (bits_rm, bits_D) -> (bits_fflags, bits_W)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_W)" } }, "riscv_f64ToI64": { "val": { "source": "val riscv_f64ToI64 : (bits_rm, bits_D) -> (bits_fflags, bits_L)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_L)" } }, "riscv_f64ToUi32": { "val": { "source": "val riscv_f64ToUi32 : (bits_rm, bits_D) -> (bits_fflags, bits_WU)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_WU)" } }, "riscv_f64ToUi64": { "val": { "source": "val riscv_f64ToUi64 : (bits_rm, bits_D) -> (bits_fflags, bits_LU)", "type": "(bits_rm, bits_D) -> (bits_fflags, bits_LU)" } }, "riscv_f64roundToInt": { "val": { "source": "val riscv_f64roundToInt : (bits_rm, bits_D, bool) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_D, bool) -> (bits_fflags, bits_D)" } }, "riscv_i32ToF16": { "val": { "source": "val riscv_i32ToF16 : (bits_rm, bits_W) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_W) -> (bits_fflags, bits_H)" } }, "riscv_i32ToF32": { "val": { "source": "val riscv_i32ToF32 : (bits_rm, bits_W) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_W) -> (bits_fflags, bits_S)" } }, "riscv_i32ToF64": { "val": { "source": "val riscv_i32ToF64 : (bits_rm, bits_W) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_W) -> (bits_fflags, bits_D)" } }, "riscv_i64ToF16": { "val": { "source": "val riscv_i64ToF16 : (bits_rm, bits_L) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_L) -> (bits_fflags, bits_H)" } }, "riscv_i64ToF32": { "val": { "source": "val riscv_i64ToF32 : (bits_rm, bits_L) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_L) -> (bits_fflags, bits_S)" } }, "riscv_i64ToF64": { "val": { "source": "val riscv_i64ToF64 : (bits_rm, bits_L) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_L) -> (bits_fflags, bits_D)" } }, "riscv_ui32ToF16": { "val": { "source": "val riscv_ui32ToF16 : (bits_rm, bits_WU) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_WU) -> (bits_fflags, bits_H)" } }, "riscv_ui32ToF32": { "val": { "source": "val riscv_ui32ToF32 : (bits_rm, bits_WU) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_WU) -> (bits_fflags, bits_S)" } }, "riscv_ui32ToF64": { "val": { "source": "val riscv_ui32ToF64 : (bits_rm, bits_WU) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_WU) -> (bits_fflags, bits_D)" } }, "riscv_ui64ToF16": { "val": { "source": "val riscv_ui64ToF16 : (bits_rm, bits_LU) -> (bits_fflags, bits_H)", "type": "(bits_rm, bits_LU) -> (bits_fflags, bits_H)" } }, "riscv_ui64ToF32": { "val": { "source": "val riscv_ui64ToF32 : (bits_rm, bits_LU) -> (bits_fflags, bits_S)", "type": "(bits_rm, bits_LU) -> (bits_fflags, bits_S)" } }, "riscv_ui64ToF64": { "val": { "source": "val riscv_ui64ToF64 : (bits_rm, bits_LU) -> (bits_fflags, bits_D)", "type": "(bits_rm, bits_LU) -> (bits_fflags, bits_D)" } }, "rivvfunct6_of_num": { "val": { "source": "val rivvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> rivvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> rivvfunct6" } }, "rivvtype_mnemonic": { "val": { "source": "val rivvtype_mnemonic : rivvfunct6 <-> string", "type": "rivvfunct6 <-> string" } }, "rmvvfunct6_of_num": { "val": { "source": "val rmvvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> rmvvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> rmvvfunct6" } }, "rmvvtype_mnemonic": { "val": { "source": "val rmvvtype_mnemonic : rmvvfunct6 <-> string", "type": "rmvvfunct6 <-> string" } }, "rop_of_num": { "val": { "source": "val rop_of_num : forall 'e, (0 <= 'e & 'e <= 9). int('e) -> rop", "type": "forall 'e, (0 <= 'e & 'e <= 9). int('e) -> rop" } }, "ropw_of_num": { "val": { "source": "val ropw_of_num : forall 'e, (0 <= 'e & 'e <= 4). int('e) -> ropw", "type": "forall 'e, (0 <= 'e & 'e <= 4). int('e) -> ropw" } }, "rotate_bits_left": { "val": { "source": "val rotate_bits_left : forall 'n 'm, 'm >= 0. (bits('n), bits('m)) -> bits('n)", "type": "forall 'n 'm, 'm >= 0. (bits('n), bits('m)) -> bits('n)" } }, "rotate_bits_right": { "val": { "source": "val rotate_bits_right : forall 'n 'm, 'm >= 0. (bits('n), bits('m)) -> bits('n)", "type": "forall 'n 'm, 'm >= 0. (bits('n), bits('m)) -> bits('n)" } }, "rotatel": { "val": { "source": "val rotatel : forall 'm 'n, 'm >= 'n >= 0. (bits('m), int('n)) -> bits('m)", "type": "forall 'm 'n, 'm >= 'n >= 0. (bits('m), int('n)) -> bits('m)" } }, "rotater": { "val": { "source": "val rotater : forall 'm 'n, 'm >= 'n >= 0. (bits('m), int('n)) -> bits('m)", "type": "forall 'm 'n, 'm >= 'n >= 0. (bits('m), int('n)) -> bits('m)" } }, "rounding_mode_of_num": { "val": { "source": "val rounding_mode_of_num : forall 'e, (0 <= 'e & 'e <= 5). int('e) -> rounding_mode", "type": "forall 'e, (0 <= 'e & 'e <= 5). int('e) -> rounding_mode" } }, "rsqrt7": { "val": { "source": "val rsqrt7 : forall 'm, 'm in {16, 32, 64}. (bits('m), bool) -> bits_D", "type": "forall 'm, 'm in {16, 32, 64}. (bits('m), bool) -> bits_D" } }, "rtype_mnemonic": { "val": { "source": "val rtype_mnemonic : rop <-> string", "type": "rop <-> string" } }, "rtypew_mnemonic": { "val": { "source": "val rtypew_mnemonic : ropw <-> string", "type": "ropw <-> string" } }, "rvfi_read": { "val": { "source": "val rvfi_read : forall 'n, 'n > 0. (xlenbits, int('n), MemoryOpResult((bits(8 * 'n), mem_meta))) -> unit", "type": "forall 'n, 'n > 0. (xlenbits, int('n), MemoryOpResult((bits(8 * 'n), mem_meta))) -> unit" } }, "rvfi_trap": { "val": { "source": "val rvfi_trap : unit -> unit", "type": "unit -> unit" } }, "rvfi_wX": { "val": { "source": "val rvfi_wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit", "type": "forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit" } }, "rvfi_write": { "val": { "source": "val rvfi_write : forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n), mem_meta, MemoryOpResult(bool)) -> unit", "type": "forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n), mem_meta, MemoryOpResult(bool)) -> unit" } }, "sail_arith_shiftright": { "val": { "source": "val sail_arith_shiftright = pure {_: \"arith_shiftr\"}: forall 'n. (bitvector('n), int) -> bitvector('n)", "type": "forall 'n. (bitvector('n), int) -> bitvector('n)" } }, "sail_mask": { "val": { "source": "val sail_mask : forall 'len 'v, ('len >= 0 & 'v >= 0). (int('len), bits('v)) -> bits('len)", "type": "forall 'len 'v, ('len >= 0 & 'v >= 0). (int('len), bits('v)) -> bits('len)" } }, "sail_ones": { "val": { "source": "val sail_ones : forall 'n, 'n >= 0. int('n) -> bits('n)", "type": "forall 'n, 'n >= 0. int('n) -> bits('n)" } }, "sail_shiftleft": { "val": { "source": "val sail_shiftleft = pure {_: \"shiftl\"}: forall 'n. (bitvector('n), int) -> bitvector('n)", "type": "forall 'n. (bitvector('n), int) -> bitvector('n)" } }, "sail_shiftright": { "val": { "source": "val sail_shiftright = pure {_: \"shiftr\"}: forall 'n. (bitvector('n), int) -> bitvector('n)", "type": "forall 'n. (bitvector('n), int) -> bitvector('n)" } }, "sail_sign_extend": { "val": { "source": "val sail_sign_extend = pure {_: \"sign_extend\"}: forall 'n 'm, 'm >= 'n. (bits('n), int('m)) -> bits('m)", "type": "forall 'n 'm, 'm >= 'n. (bits('n), int('m)) -> bits('m)" } }, "sail_zero_extend": { "val": { "source": "val sail_zero_extend = pure {_: \"zero_extend\"}: forall 'n 'm, 'm >= 'n. (bits('n), int('m)) -> bits('m)", "type": "forall 'n 'm, 'm >= 'n. (bits('n), int('m)) -> bits('m)" } }, "sail_zeros": { "val": { "source": "val sail_zeros = pure {_: \"zeros\"}: forall 'n, 'n >= 0. int('n) -> bits('n)", "type": "forall 'n, 'n >= 0. int('n) -> bits('n)" } }, "satp64Mode_of_bits": { "val": { "source": "val satp64Mode_of_bits : (Architecture, satp_mode) -> option(SATPMode)", "type": "(Architecture, satp_mode) -> option(SATPMode)" } }, "satp_to_PT_base": { "val": { "source": "val satp_to_PT_base : xlenbits -> bits(64)", "type": "xlenbits -> bits(64)" } }, "satp_to_asid": { "val": { "source": "val satp_to_asid : xlenbits -> asidbits", "type": "xlenbits -> asidbits" } }, "sbox_lookup": { "val": { "source": "val sbox_lookup : (bits(8), vector(256, bits(8))) -> bits(8)", "type": "(bits(8), vector(256, bits(8))) -> bits(8)" } }, "seed_opst_of_num": { "val": { "source": "val seed_opst_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> seed_opst", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> seed_opst" } }, "select_instr_or_fcsr_rm": { "val": { "source": "val select_instr_or_fcsr_rm : rounding_mode -> option(rounding_mode)", "type": "rounding_mode -> option(rounding_mode)" } }, "sep": { "val": { "source": "val sep : unit <-> string", "type": "unit <-> string" } }, "set_mstatus_SXL": { "val": { "source": "val set_mstatus_SXL : (Mstatus, arch_xlen) -> Mstatus", "type": "(Mstatus, arch_xlen) -> Mstatus" } }, "set_mstatus_UXL": { "val": { "source": "val set_mstatus_UXL : (Mstatus, arch_xlen) -> Mstatus", "type": "(Mstatus, arch_xlen) -> Mstatus" } }, "set_mtvec": { "val": { "source": "val set_mtvec : xlenbits -> xlenbits", "type": "xlenbits -> xlenbits" } }, "set_next_pc": { "val": { "source": "val set_next_pc : xlenbits -> unit", "type": "xlenbits -> unit" } }, "set_slice_bits": { "val": { "source": "val set_slice_bits = pure {_: \"set_slice\"}: forall 'n 'm. (implicit('n), int('m), bits('n), int, bits('m)) -> bits('n)", "type": "forall 'n 'm. (implicit('n), int('m), bits('n), int, bits('m)) -> bits('n)" } }, "set_slice_int": { "val": { "source": "val set_slice_int = pure {_: \"set_slice_int\"}: forall 'w. (int('w), int, int, bits('w)) -> int", "type": "forall 'w. (int('w), int, int, bits('w)) -> int" } }, "set_sstatus_UXL": { "val": { "source": "val set_sstatus_UXL : (Sstatus, arch_xlen) -> Sstatus", "type": "(Sstatus, arch_xlen) -> Sstatus" } }, "set_stvec": { "val": { "source": "val set_stvec : xlenbits -> xlenbits", "type": "xlenbits -> xlenbits" } }, "set_utvec": { "val": { "source": "val set_utvec : xlenbits -> xlenbits", "type": "xlenbits -> xlenbits" } }, "set_xret_target": { "val": { "source": "val set_xret_target : (Privilege, xlenbits) -> xlenbits", "type": "(Privilege, xlenbits) -> xlenbits" } }, "sew_flag": { "val": { "source": "val sew_flag : string <-> bitvector(3)", "type": "string <-> bitvector(3)" } }, "shift_bits_left": { "val": { "source": "val \"shift_bits_left\" : forall 'n 'm. (bits('n), bits('m)) -> bits('n)", "type": "forall 'n 'm. (bits('n), bits('m)) -> bits('n)" } }, "shift_bits_right": { "val": { "source": "val \"shift_bits_right\" : forall 'n 'm. (bits('n), bits('m)) -> bits('n)", "type": "forall 'n 'm. (bits('n), bits('m)) -> bits('n)" } }, "shift_right_arith32": { "val": { "source": "val shift_right_arith32 : (bits(32), bits(5)) -> bits(32)", "type": "(bits(32), bits(5)) -> bits(32)" } }, "shift_right_arith64": { "val": { "source": "val shift_right_arith64 : (bits(64), bits(6)) -> bits(64)", "type": "(bits(64), bits(6)) -> bits(64)" } }, "shiftiop_mnemonic": { "val": { "source": "val shiftiop_mnemonic : sop <-> string", "type": "sop <-> string" } }, "shiftiwop_mnemonic": { "val": { "source": "val shiftiwop_mnemonic : sopw <-> string", "type": "sopw <-> string" } }, "shiftl": { "val": { "source": "val \"shiftl\" : forall 'm 'n, 'n >= 0. (bits('m), int('n)) -> bits('m)", "type": "forall 'm 'n, 'n >= 0. (bits('m), int('n)) -> bits('m)" } }, "shiftr": { "val": { "source": "val \"shiftr\" : forall 'm 'n, 'n >= 0. (bits('m), int('n)) -> bits('m)", "type": "forall 'm 'n, 'n >= 0. (bits('m), int('n)) -> bits('m)" } }, "sign_extend": { "val": { "source": "val sign_extend : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)", "type": "forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)" } }, "signed": { "val": { "source": "val signed = pure {c: \"sail_signed\", _: \"sint\"}: forall 'n, 'n > 0.\n bits('n) -> range(- (2 ^ ('n - 1)), 2 ^ ('n - 1) - 1)", "type": "forall 'n, 'n > 0. bits('n) -> range(- (2 ^ ('n - 1)), 2 ^ ('n - 1) - 1)" } }, "signed_saturation": { "val": { "source": "val signed_saturation : forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m)", "type": "forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m)" } }, "simm_string": { "val": { "source": "val simm_string : bitvector(5) <-> string", "type": "bitvector(5) <-> string" } }, "size_bits": { "val": { "source": "val size_bits : word_width <-> bitvector(2)", "type": "word_width <-> bitvector(2)" } }, "size_mnemonic": { "val": { "source": "val size_mnemonic : word_width <-> string", "type": "word_width <-> string" } }, "slice": { "val": { "source": "val slice = pure {_: \"slice\"}: forall 'n 'm 'o, (0 <= 'm & 0 <= 'n). (bits('m), int('o), int('n)) -> bits('n)", "type": "forall 'n 'm 'o, (0 <= 'm & 0 <= 'n). (bits('m), int('o), int('n)) -> bits('n)" } }, "slice_mask": { "val": { "source": "val slice_mask : forall 'n, 'n >= 0. (implicit('n), int, int) -> bits('n)", "type": "forall 'n, 'n >= 0. (implicit('n), int, int) -> bits('n)" } }, "sm4_sbox": { "val": { "source": "val sm4_sbox : bits(8) -> bits(8)", "type": "bits(8) -> bits(8)" } }, "sop_of_num": { "val": { "source": "val sop_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> sop", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> sop" } }, "sopw_of_num": { "val": { "source": "val sopw_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> sopw", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> sopw" } }, "spc": { "val": { "source": "val spc : unit <-> string", "type": "unit <-> string" } }, "speculate_conditional": { "val": { "source": "val speculate_conditional = monadic {ocaml: \"Platform.speculate_conditional\", interpreter: \"excl_res\", c: \"speculate_conditional\", lem: \"speculate_conditional_success\"} : unit -> bool", "type": "unit -> bool" } }, "step": { "val": { "source": "val step : int -> bool", "type": "int -> bool" } }, "string_append": { "val": { "source": "val string_append = pure {coq: \"String.append\", c: \"concat_str\", _: \"string_append\"} : (string, string) -> string", "type": "(string, string) -> string" } }, "string_drop": { "val": { "source": "val string_drop = pure \"string_drop\" : (string, nat) -> string", "type": "(string, nat) -> string" } }, "string_length": { "val": { "source": "val string_length = pure \"string_length\" : string -> nat", "type": "string -> nat" } }, "string_startswith": { "val": { "source": "val string_startswith = pure \"string_startswith\" : (string, string) -> bool", "type": "(string, string) -> bool" } }, "string_take": { "val": { "source": "val string_take = pure \"string_take\" : (string, nat) -> string", "type": "(string, nat) -> string" } }, "sub_atom": { "val": { "source": "val sub_atom = pure {ocaml: \"sub_int\", interpreter: \"sub_int\", lem: \"integerMinus\", c: \"sub_int\", coq: \"Z.sub\"}: forall 'n 'm.\n (int('n), int('m)) -> int('n - 'm)", "type": "forall 'n 'm. (int('n), int('m)) -> int('n - 'm)" } }, "sub_bits": { "val": { "source": "val sub_bits = pure {ocaml: \"sub_vec\", interpreter: \"sub_vec\", lem: \"sub_vec\", c: \"sub_bits\", coq: \"sub_vec\"}: forall 'n.\n (bits('n), bits('n)) -> bits('n)", "type": "forall 'n. (bits('n), bits('n)) -> bits('n)" } }, "sub_int": { "val": { "source": "val sub_int = pure {ocaml: \"sub_int\", interpreter: \"sub_int\", lem: \"integerMinus\", c: \"sub_int\", coq: \"Z.sub\"}: (int, int) -> int", "type": "(int, int) -> int" } }, "sub_nat": { "val": { "source": "val sub_nat = pure {ocaml: \"(fun (x,y) -> let n = sub_int (x,y) in if Big_int.less_equal n Big_int.zero then Big_int.zero else n)\", lem: \"integerMinus\", coq: \"Z.sub\", _: \"sub_nat\"}: (nat, nat) -> nat", "type": "(nat, nat) -> nat" } }, "sub_vec": { "val": { "source": "val sub_vec = {c: \"sub_bits\", _: \"sub_vec\"} : forall 'n. (bits('n), bits('n)) -> bits('n)", "type": "forall 'n. (bits('n), bits('n)) -> bits('n)" } }, "sub_vec_int": { "val": { "source": "val sub_vec_int = {c: \"sub_bits_int\", _: \"sub_vec_int\"} : forall 'n. (bits('n), int) -> bits('n)", "type": "forall 'n. (bits('n), int) -> bits('n)" } }, "subrange_bits": { "val": { "source": "val subrange_bits = pure {ocaml: \"subrange\", interpreter: \"subrange\", lem: \"subrange_vec_dec\", c: \"vector_subrange\", coq: \"subrange_vec_dec\"}: forall 'n 'm 'o, (0 <= 'o & 'o <= 'm & 'm < 'n).\n (bits('n), int('m), int('o)) -> bits('m - 'o + 1)", "type": "forall 'n 'm 'o, (0 <= 'o & 'o <= 'm & 'm < 'n). (bits('n), int('m), int('o)) -> bits('m - 'o + 1)" } }, "sys_enable_fdext": { "val": { "source": "val sys_enable_fdext = {c: \"sys_enable_fdext\", ocaml: \"Platform.enable_fdext\", _: \"sys_enable_fdext\"} : unit -> bool", "type": "unit -> bool" } }, "sys_enable_next": { "val": { "source": "val sys_enable_next = {c: \"sys_enable_next\", ocaml: \"Platform.enable_next\", _: \"sys_enable_next\"} : unit -> bool", "type": "unit -> bool" } }, "sys_enable_rvc": { "val": { "source": "val sys_enable_rvc = {c: \"sys_enable_rvc\", ocaml: \"Platform.enable_rvc\", _: \"sys_enable_rvc\"} : unit -> bool", "type": "unit -> bool" } }, "sys_enable_vext": { "val": { "source": "val sys_enable_vext = {c: \"sys_enable_vext\", ocaml: \"Platform.enable_vext\", _: \"sys_enable_vext\"} : unit -> bool", "type": "unit -> bool" } }, "sys_enable_writable_fiom": { "val": { "source": "val sys_enable_writable_fiom = {c: \"sys_enable_writable_fiom\", ocaml: \"Platform.enable_writable_fiom\", _: \"sys_enable_writable_fiom\"} : unit -> bool", "type": "unit -> bool" } }, "sys_enable_writable_misa": { "val": { "source": "val sys_enable_writable_misa = {c: \"sys_enable_writable_misa\", ocaml: \"Platform.enable_writable_misa\", _: \"sys_enable_writable_misa\"} : unit -> bool", "type": "unit -> bool" } }, "sys_enable_zfinx": { "val": { "source": "val sys_enable_zfinx = {c: \"sys_enable_zfinx\", ocaml: \"Platform.enable_zfinx\", _: \"sys_enable_zfinx\"} : unit -> bool", "type": "unit -> bool" } }, "sys_pmp_count": { "val": { "source": "val sys_pmp_count = {c: \"sys_pmp_count\", ocaml: \"Platform.pmp_count\", _: \"sys_pmp_count\"} : unit -> range(0, 64)", "type": "unit -> range(0, 64)" } }, "sys_pmp_grain": { "val": { "source": "val sys_pmp_grain = {c: \"sys_pmp_grain\", ocaml: \"Platform.pmp_grain\", _: \"sys_pmp_grain\"} : unit -> range(0, 63)", "type": "unit -> range(0, 63)" } }, "tdiv_int": { "val": { "source": "val tdiv_int = pure {ocaml: \"tdiv_int\", interpreter: \"tdiv_int\", lem: \"tdiv_int\", c: \"tdiv_int\", coq: \"Z.quot\"}: (int, int) -> int", "type": "(int, int) -> int" } }, "tick_clock": { "val": { "source": "val tick_clock : unit -> unit", "type": "unit -> unit" } }, "tick_pc": { "val": { "source": "val tick_pc : unit -> unit", "type": "unit -> unit" } }, "tick_platform": { "val": { "source": "val tick_platform : unit -> unit", "type": "unit -> unit" } }, "to_bits": { "val": { "source": "val to_bits : forall 'l, 'l >= 0.(int('l), int) -> bits('l)", "type": "forall 'l, 'l >= 0.(int('l), int) -> bits('l)" } }, "trans_kind_of_num": { "val": { "source": "val trans_kind_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> trans_kind", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> trans_kind" } }, "translate": { "val": { "source": "val translate : (SV_Params, asidbits, bits(64), bits(64), AccessType(ext_access_type), Privilege, bool, bool, ext_ptw) -> TR_Result(bits(64), PTW_Error)", "type": "(SV_Params, asidbits, bits(64), bits(64), AccessType(ext_access_type), Privilege, bool, bool, ext_ptw) -> TR_Result(bits(64), PTW_Error)" } }, "translateAddr": { "val": { "source": "val translateAddr : (xlenbits, AccessType(ext_access_type)) -> TR_Result(xlenbits, ExceptionType)", "type": "(xlenbits, AccessType(ext_access_type)) -> TR_Result(xlenbits, ExceptionType)" } }, "translate_TLB_hit": { "val": { "source": "val translate_TLB_hit : (SV_Params, asidbits, bits(64), bits(64), AccessType(ext_access_type), Privilege, bool, bool, ext_ptw, nat, TLB_Entry) -> TR_Result(bits(64), PTW_Error)", "type": "(SV_Params, asidbits, bits(64), bits(64), AccessType(ext_access_type), Privilege, bool, bool, ext_ptw, nat, TLB_Entry) -> TR_Result(bits(64), PTW_Error)" } }, "translate_TLB_miss": { "val": { "source": "val translate_TLB_miss : (SV_Params, asidbits, bits(64), bits(64), AccessType(ext_access_type), Privilege, bool, bool, ext_ptw) -> TR_Result(bits(64), PTW_Error)", "type": "(SV_Params, asidbits, bits(64), bits(64), AccessType(ext_access_type), Privilege, bool, bool, ext_ptw) -> TR_Result(bits(64), PTW_Error)" } }, "translationException": { "val": { "source": "val translationException : (AccessType(ext_access_type), PTW_Error) -> ExceptionType", "type": "(AccessType(ext_access_type), PTW_Error) -> ExceptionType" } }, "translationMode": { "val": { "source": "val translationMode : Privilege -> SATPMode", "type": "Privilege -> SATPMode" } }, "trapVectorMode_of_bits": { "val": { "source": "val trapVectorMode_of_bits : tv_mode -> TrapVectorMode", "type": "tv_mode -> TrapVectorMode" } }, "trap_handler": { "val": { "source": "val trap_handler : (Privilege, bool, exc_code, xlenbits, option(xlenbits), option(ext_exception)) -> xlenbits", "type": "(Privilege, bool, exc_code, xlenbits, option(xlenbits), option(ext_exception)) -> xlenbits" } }, "truncate": { "val": { "source": "val truncate = pure {ocaml: \"vector_truncate\", interpreter: \"vector_truncate\", lem: \"vector_truncate\", coq: \"vector_truncate\", c: \"sail_truncate\"}: forall 'm 'n, ('m >= 0 & 'm <= 'n).\n (bits('n), int('m)) -> bits('m)", "type": "forall 'm 'n, ('m >= 0 & 'm <= 'n). (bits('n), int('m)) -> bits('m)" } }, "truncateLSB": { "val": { "source": "val truncateLSB = pure {ocaml: \"vector_truncateLSB\", interpreter: \"vector_truncateLSB\", lem: \"vector_truncateLSB\", coq: \"vector_truncateLSB\", c: \"sail_truncateLSB\"}: forall 'm 'n, ('m >= 0 & 'm <= 'n).\n (bits('n), int('m)) -> bits('m)", "type": "forall 'm 'n, ('m >= 0 & 'm <= 'n). (bits('n), int('m)) -> bits('m)" } }, "tval": { "val": { "source": "val tval : option(xlenbits) -> xlenbits", "type": "option(xlenbits) -> xlenbits" } }, "tvec_addr": { "val": { "source": "val tvec_addr : (Mtvec, Mcause) -> option(xlenbits)", "type": "(Mtvec, Mcause) -> option(xlenbits)" } }, "ufFlag": { "val": { "source": "val ufFlag : unit -> bits(5)", "type": "unit -> bits(5)" } }, "undefined_SV_Params": { "val": { "source": "val undefined_SV_Params : unit -> SV_Params", "type": "unit -> SV_Params" } }, "unsigned": { "val": { "source": "val unsigned = pure {ocaml: \"uint\", lem: \"uint\", interpreter: \"uint\", c: \"sail_unsigned\", coq: \"uint\"}: forall 'n.\n bits('n) -> range(0, 2 ^ 'n - 1)", "type": "forall 'n. bits('n) -> range(0, 2 ^ 'n - 1)" } }, "unsigned_saturation": { "val": { "source": "val unsigned_saturation : forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m)", "type": "forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m)" } }, "uop_of_num": { "val": { "source": "val uop_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> uop", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> uop" } }, "update_PTE_Bits": { "val": { "source": "val update_PTE_Bits : (SV_Params, bits(64), AccessType(ext_access_type)) -> option(bits(64))", "type": "(SV_Params, bits(64), AccessType(ext_access_type)) -> option(bits(64))" } }, "update_subrange_bits": { "val": { "source": "val update_subrange_bits = pure {ocaml: \"update_subrange\", interpreter: \"update_subrange\", lem: \"update_subrange_vec_dec\", c: \"vector_update_subrange\", coq: \"update_subrange_vec_dec\"}: forall 'n 'm 'o, (0 <= 'o & 'o <= 'm & 'm < 'n).\n (bits('n), int('m), int('o), bits('m - ('o - 1))) -> bits('n)", "type": "forall 'n 'm 'o, (0 <= 'o & 'o <= 'm & 'm < 'n). (bits('n), int('m), int('o), bits('m - ('o - 1))) -> bits('n)" } }, "utype_mnemonic": { "val": { "source": "val utype_mnemonic : uop <-> string", "type": "uop <-> string" } }, "validDoubleRegs": { "val": { "source": "val validDoubleRegs : forall 'n, 'n > 0. (implicit('n), vector('n, dec, regidx)) -> bool", "type": "forall 'n, 'n > 0. (implicit('n), vector('n, dec, regidx)) -> bool" } }, "valid_eew_emul": { "val": { "source": "val valid_eew_emul : (int, int) -> bool", "type": "(int, int) -> bool" } }, "valid_fp_op": { "val": { "source": "val valid_fp_op : ({|8, 16, 32, 64|}, bits(3)) -> bool", "type": "({|8, 16, 32, 64|}, bits(3)) -> bool" } }, "valid_hex_bits": { "val": { "source": "val \"valid_hex_bits\" : forall 'n, 'n > 0. (int('n), string) -> bool", "type": "forall 'n, 'n > 0. (int('n), string) -> bool" } }, "valid_rd_mask": { "val": { "source": "val valid_rd_mask : (regidx, bits(1)) -> bool", "type": "(regidx, bits(1)) -> bool" } }, "valid_reg_overlap": { "val": { "source": "val valid_reg_overlap : (regidx, regidx, int, int) -> bool", "type": "(regidx, regidx, int, int) -> bool" } }, "valid_rounding_mode": { "val": { "source": "val valid_rounding_mode : bits(3) -> bool", "type": "bits(3) -> bool" } }, "valid_segment": { "val": { "source": "val valid_segment : (int, int) -> bool", "type": "(int, int) -> bool" } }, "valid_vtype": { "val": { "source": "val valid_vtype : unit -> bool", "type": "unit -> bool" } }, "vector_length": { "val": { "source": "val vector_length = pure {ocaml: \"length\", interpreter: \"length\", lem: \"length_list\", c: \"length\", coq: \"vec_length\"}: forall 'n ('a : Type).\n vector('n, 'a) -> int('n)", "type": "forall 'n ('a : Type). vector('n, 'a) -> int('n)" } }, "vext2_vs1": { "val": { "source": "val vext2_vs1 : vext2funct6 <-> bitvector(5)", "type": "vext2funct6 <-> bitvector(5)" } }, "vext2funct6_of_num": { "val": { "source": "val vext2funct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vext2funct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vext2funct6" } }, "vext2type_mnemonic": { "val": { "source": "val vext2type_mnemonic : vext2funct6 <-> string", "type": "vext2funct6 <-> string" } }, "vext4_vs1": { "val": { "source": "val vext4_vs1 : vext4funct6 <-> bitvector(5)", "type": "vext4funct6 <-> bitvector(5)" } }, "vext4funct6_of_num": { "val": { "source": "val vext4funct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vext4funct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vext4funct6" } }, "vext4type_mnemonic": { "val": { "source": "val vext4type_mnemonic : vext4funct6 <-> string", "type": "vext4funct6 <-> string" } }, "vext8_vs1": { "val": { "source": "val vext8_vs1 : vext8funct6 <-> bitvector(5)", "type": "vext8funct6 <-> bitvector(5)" } }, "vext8funct6_of_num": { "val": { "source": "val vext8funct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vext8funct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vext8funct6" } }, "vext8type_mnemonic": { "val": { "source": "val vext8type_mnemonic : vext8funct6 <-> string", "type": "vext8funct6 <-> string" } }, "vfnunary0_mnemonic": { "val": { "source": "val vfnunary0_mnemonic : vfnunary0 <-> string", "type": "vfnunary0 <-> string" } }, "vfnunary0_of_num": { "val": { "source": "val vfnunary0_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> vfnunary0", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> vfnunary0" } }, "vfunary0_mnemonic": { "val": { "source": "val vfunary0_mnemonic : vfunary0 <-> string", "type": "vfunary0 <-> string" } }, "vfunary0_of_num": { "val": { "source": "val vfunary0_of_num : forall 'e, (0 <= 'e & 'e <= 5). int('e) -> vfunary0", "type": "forall 'e, (0 <= 'e & 'e <= 5). int('e) -> vfunary0" } }, "vfunary1_mnemonic": { "val": { "source": "val vfunary1_mnemonic : vfunary1 <-> string", "type": "vfunary1 <-> string" } }, "vfunary1_of_num": { "val": { "source": "val vfunary1_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> vfunary1", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> vfunary1" } }, "vfwunary0_mnemonic": { "val": { "source": "val vfwunary0_mnemonic : vfwunary0 <-> string", "type": "vfwunary0 <-> string" } }, "vfwunary0_of_num": { "val": { "source": "val vfwunary0_of_num : forall 'e, (0 <= 'e & 'e <= 6). int('e) -> vfwunary0", "type": "forall 'e, (0 <= 'e & 'e <= 6). int('e) -> vfwunary0" } }, "vicmpfunct6_of_num": { "val": { "source": "val vicmpfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 5). int('e) -> vicmpfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 5). int('e) -> vicmpfunct6" } }, "vicmptype_mnemonic": { "val": { "source": "val vicmptype_mnemonic : vicmpfunct6 <-> string", "type": "vicmpfunct6 <-> string" } }, "vifunct6_of_num": { "val": { "source": "val vifunct6_of_num : forall 'e, (0 <= 'e & 'e <= 11). int('e) -> vifunct6", "type": "forall 'e, (0 <= 'e & 'e <= 11). int('e) -> vifunct6" } }, "vimcfunct6_of_num": { "val": { "source": "val vimcfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 0). int('e) -> vimcfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 0). int('e) -> vimcfunct6" } }, "vimctype_mnemonic": { "val": { "source": "val vimctype_mnemonic : vimcfunct6 <-> string", "type": "vimcfunct6 <-> string" } }, "vimfunct6_of_num": { "val": { "source": "val vimfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 0). int('e) -> vimfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 0). int('e) -> vimfunct6" } }, "vimsfunct6_of_num": { "val": { "source": "val vimsfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 0). int('e) -> vimsfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 0). int('e) -> vimsfunct6" } }, "vimstype_mnemonic": { "val": { "source": "val vimstype_mnemonic : vimsfunct6 <-> string", "type": "vimsfunct6 <-> string" } }, "vimtype_mnemonic": { "val": { "source": "val vimtype_mnemonic : vimfunct6 <-> string", "type": "vimfunct6 <-> string" } }, "visg_mnemonic": { "val": { "source": "val visg_mnemonic : visgfunct6 <-> string", "type": "visgfunct6 <-> string" } }, "visgfunct6_of_num": { "val": { "source": "val visgfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> visgfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> visgfunct6" } }, "vitype_mnemonic": { "val": { "source": "val vitype_mnemonic : vifunct6 <-> string", "type": "vifunct6 <-> string" } }, "vlewidth_bitsnumberstr": { "val": { "source": "val vlewidth_bitsnumberstr : vlewidth <-> string", "type": "vlewidth <-> string" } }, "vlewidth_bytesnumber": { "val": { "source": "val vlewidth_bytesnumber : vlewidth <-> {1, 2, 4, 8}", "type": "vlewidth <-> {1, 2, 4, 8}" } }, "vlewidth_of_num": { "val": { "source": "val vlewidth_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> vlewidth", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> vlewidth" } }, "vlewidth_pow": { "val": { "source": "val vlewidth_pow : vlewidth <-> {3, 4, 5, 6}", "type": "vlewidth <-> {3, 4, 5, 6}" } }, "vmlsop_of_num": { "val": { "source": "val vmlsop_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vmlsop", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vmlsop" } }, "vmtype_mnemonic": { "val": { "source": "val vmtype_mnemonic : vmlsop <-> string", "type": "vmlsop <-> string" } }, "vpn_j_of_va": { "val": { "source": "val vpn_j_of_va : (SV_Params, bits(64), PTW_Level) -> bits(64)", "type": "(SV_Params, bits(64), PTW_Level) -> bits(64)" } }, "vpns_of_va": { "val": { "source": "val vpns_of_va : (SV_Params, bits(64)) -> bits(64)", "type": "(SV_Params, bits(64)) -> bits(64)" } }, "vreg_name": { "val": { "source": "val vreg_name : bits(5) <-> string", "type": "bits(5) <-> string" } }, "vsetop_of_num": { "val": { "source": "val vsetop_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vsetop", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vsetop" } }, "vsettype_mnemonic": { "val": { "source": "val vsettype_mnemonic : vsetop <-> string", "type": "vsetop <-> string" } }, "vvcmpfunct6_of_num": { "val": { "source": "val vvcmpfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 5). int('e) -> vvcmpfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 5). int('e) -> vvcmpfunct6" } }, "vvcmptype_mnemonic": { "val": { "source": "val vvcmptype_mnemonic : vvcmpfunct6 <-> string", "type": "vvcmpfunct6 <-> string" } }, "vvfunct6_of_num": { "val": { "source": "val vvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 20). int('e) -> vvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 20). int('e) -> vvfunct6" } }, "vvmcfunct6_of_num": { "val": { "source": "val vvmcfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vvmcfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vvmcfunct6" } }, "vvmctype_mnemonic": { "val": { "source": "val vvmctype_mnemonic : vvmcfunct6 <-> string", "type": "vvmcfunct6 <-> string" } }, "vvmfunct6_of_num": { "val": { "source": "val vvmfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vvmfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vvmfunct6" } }, "vvmsfunct6_of_num": { "val": { "source": "val vvmsfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vvmsfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vvmsfunct6" } }, "vvmstype_mnemonic": { "val": { "source": "val vvmstype_mnemonic : vvmsfunct6 <-> string", "type": "vvmsfunct6 <-> string" } }, "vvmtype_mnemonic": { "val": { "source": "val vvmtype_mnemonic : vvmfunct6 <-> string", "type": "vvmfunct6 <-> string" } }, "vvtype_mnemonic": { "val": { "source": "val vvtype_mnemonic : vvfunct6 <-> string", "type": "vvfunct6 <-> string" } }, "vxcmpfunct6_of_num": { "val": { "source": "val vxcmpfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 7). int('e) -> vxcmpfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 7). int('e) -> vxcmpfunct6" } }, "vxcmptype_mnemonic": { "val": { "source": "val vxcmptype_mnemonic : vxcmpfunct6 <-> string", "type": "vxcmpfunct6 <-> string" } }, "vxfunct6_of_num": { "val": { "source": "val vxfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 19). int('e) -> vxfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 19). int('e) -> vxfunct6" } }, "vxmcfunct6_of_num": { "val": { "source": "val vxmcfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vxmcfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vxmcfunct6" } }, "vxmctype_mnemonic": { "val": { "source": "val vxmctype_mnemonic : vxmcfunct6 <-> string", "type": "vxmcfunct6 <-> string" } }, "vxmfunct6_of_num": { "val": { "source": "val vxmfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vxmfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vxmfunct6" } }, "vxmsfunct6_of_num": { "val": { "source": "val vxmsfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vxmsfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> vxmsfunct6" } }, "vxmstype_mnemonic": { "val": { "source": "val vxmstype_mnemonic : vxmsfunct6 <-> string", "type": "vxmsfunct6 <-> string" } }, "vxmtype_mnemonic": { "val": { "source": "val vxmtype_mnemonic : vxmfunct6 <-> string", "type": "vxmfunct6 <-> string" } }, "vxsg_mnemonic": { "val": { "source": "val vxsg_mnemonic : vxsgfunct6 <-> string", "type": "vxsgfunct6 <-> string" } }, "vxsgfunct6_of_num": { "val": { "source": "val vxsgfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> vxsgfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> vxsgfunct6" } }, "vxtype_mnemonic": { "val": { "source": "val vxtype_mnemonic : vxfunct6 <-> string", "type": "vxfunct6 <-> string" } }, "wF": { "val": { "source": "val wF : forall 'n, 0 <= 'n < 32. (regno('n), flenbits) -> unit", "type": "forall 'n, 0 <= 'n < 32. (regno('n), flenbits) -> unit" } }, "wF_D": { "val": { "source": "val wF_D : (bits(5), bits(64)) -> unit", "type": "(bits(5), bits(64)) -> unit" } }, "wF_H": { "val": { "source": "val wF_H : (bits(5), bits(16)) -> unit", "type": "(bits(5), bits(16)) -> unit" } }, "wF_S": { "val": { "source": "val wF_S : (bits(5), bits(32)) -> unit", "type": "(bits(5), bits(32)) -> unit" } }, "wF_bits": { "val": { "source": "val wF_bits : (bits(5), flenbits) -> unit", "type": "(bits(5), flenbits) -> unit" } }, "wF_or_X_D": { "val": { "source": "val wF_or_X_D : (bits(5), bits(64)) -> unit", "type": "(bits(5), bits(64)) -> unit" } }, "wF_or_X_H": { "val": { "source": "val wF_or_X_H : (bits(5), bits(16)) -> unit", "type": "(bits(5), bits(16)) -> unit" } }, "wF_or_X_S": { "val": { "source": "val wF_or_X_S : (bits(5), bits(32)) -> unit", "type": "(bits(5), bits(32)) -> unit" } }, "wV": { "val": { "source": "val wV : forall 'n, 0 <= 'n < 32. (regno('n), vregtype) -> unit", "type": "forall 'n, 0 <= 'n < 32. (regno('n), vregtype) -> unit" } }, "wV_bits": { "val": { "source": "val wV_bits : (bits(5), vregtype) -> unit", "type": "(bits(5), vregtype) -> unit" } }, "wX": { "val": { "source": "val wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit", "type": "forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit" } }, "wX_bits": { "val": { "source": "val wX_bits : (bits(5), xlenbits) -> unit", "type": "(bits(5), xlenbits) -> unit" } }, "within_clint": { "val": { "source": "val within_clint : forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool" } }, "within_htif_readable": { "val": { "source": "val within_htif_readable : forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool" } }, "within_htif_writable": { "val": { "source": "val within_htif_writable : forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool" } }, "within_mmio_readable": { "val": { "source": "val within_mmio_readable : forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool" } }, "within_mmio_writable": { "val": { "source": "val within_mmio_writable : forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool", "type": "forall 'n, (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool" } }, "within_phys_mem": { "val": { "source": "val within_phys_mem : forall 'n, 'n <= max_mem_access. (xlenbits, int('n)) -> bool", "type": "forall 'n, 'n <= max_mem_access. (xlenbits, int('n)) -> bool" } }, "wmvvfunct6_of_num": { "val": { "source": "val wmvvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 2). int('e) -> wmvvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 2). int('e) -> wmvvfunct6" } }, "wmvvtype_mnemonic": { "val": { "source": "val wmvvtype_mnemonic : wmvvfunct6 <-> string", "type": "wmvvfunct6 <-> string" } }, "wmvxfunct6_of_num": { "val": { "source": "val wmvxfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> wmvxfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> wmvxfunct6" } }, "wmvxtype_mnemonic": { "val": { "source": "val wmvxtype_mnemonic : wmvxfunct6 <-> string", "type": "wmvxfunct6 <-> string" } }, "word_width_bytes": { "val": { "source": "val word_width_bytes : word_width -> {'s, 's == 1 | 's == 2 | 's == 4 | 's == 8 . int('s)}", "type": "word_width -> {'s, 's == 1 | 's == 2 | 's == 4 | 's == 8 . int('s)}" } }, "word_width_of_num": { "val": { "source": "val word_width_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> word_width", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> word_width" } }, "writeCSR": { "val": { "source": "val writeCSR : (csreg, xlenbits) -> unit", "type": "(csreg, xlenbits) -> unit" } }, "write_TLB": { "val": { "source": "val write_TLB : (nat, TLB_Entry) -> unit", "type": "(nat, TLB_Entry) -> unit" } }, "write_kind_of_num": { "val": { "source": "val write_kind_of_num : forall 'e, (0 <= 'e & 'e <= 10). int('e) -> write_kind", "type": "forall 'e, (0 <= 'e & 'e <= 10). int('e) -> write_kind" } }, "write_ram": { "val": { "source": "val write_ram = {lem: \"write_ram\", coq: \"write_ram\"} : forall 'n, 0 < 'n <= max_mem_access . (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> bool", "type": "forall 'n, 0 < 'n <= max_mem_access . (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> bool" } }, "write_ram_ea": { "val": { "source": "val write_ram_ea : forall 'n, 0 < 'n <= max_mem_access . (write_kind, xlenbits, int('n)) -> unit", "type": "forall 'n, 0 < 'n <= max_mem_access . (write_kind, xlenbits, int('n)) -> unit" } }, "write_seed_csr": { "val": { "source": "val write_seed_csr : unit -> option(xlenbits)", "type": "unit -> option(xlenbits)" } }, "write_single_element": { "val": { "source": "val write_single_element : forall 'm 'x, 8 <= 'm <= 128. (int('m), int('x), regidx, bits('m)) -> unit", "type": "forall 'm 'x, 8 <= 'm <= 128. (int('m), int('x), regidx, bits('m)) -> unit" } }, "write_single_vreg": { "val": { "source": "val write_single_vreg : forall 'n 'm, 'n >= 0. (int('n), int('m), regidx, vector('n, dec, bits('m))) -> unit", "type": "forall 'n 'm, 'n >= 0. (int('n), int('m), regidx, vector('n, dec, bits('m))) -> unit" } }, "write_vmask": { "val": { "source": "val write_vmask : forall 'n, 'n >= 0. (int('n), regidx, vector('n, dec, bool)) -> unit", "type": "forall 'n, 'n >= 0. (int('n), regidx, vector('n, dec, bool)) -> unit" } }, "write_vreg": { "val": { "source": "val write_vreg : forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), regidx, vector('n, dec, bits('m))) -> unit", "type": "forall 'n 'm 'p, 'n >= 0. (int('n), int('m), int('p), regidx, vector('n, dec, bits('m))) -> unit" } }, "wvfunct6_of_num": { "val": { "source": "val wvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> wvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> wvfunct6" } }, "wvtype_mnemonic": { "val": { "source": "val wvtype_mnemonic : wvfunct6 <-> string", "type": "wvfunct6 <-> string" } }, "wvvfunct6_of_num": { "val": { "source": "val wvvfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 6). int('e) -> wvvfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 6). int('e) -> wvvfunct6" } }, "wvvtype_mnemonic": { "val": { "source": "val wvvtype_mnemonic : wvvfunct6 <-> string", "type": "wvvfunct6 <-> string" } }, "wvxfunct6_of_num": { "val": { "source": "val wvxfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 6). int('e) -> wvxfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 6). int('e) -> wvxfunct6" } }, "wvxtype_mnemonic": { "val": { "source": "val wvxtype_mnemonic : wvxfunct6 <-> string", "type": "wvxfunct6 <-> string" } }, "wxfunct6_of_num": { "val": { "source": "val wxfunct6_of_num : forall 'e, (0 <= 'e & 'e <= 3). int('e) -> wxfunct6", "type": "forall 'e, (0 <= 'e & 'e <= 3). int('e) -> wxfunct6" } }, "wxtype_mnemonic": { "val": { "source": "val wxtype_mnemonic : wxfunct6 <-> string", "type": "wxfunct6 <-> string" } }, "xor_vec": { "val": { "source": "val xor_vec = pure {lem: \"xor_vec\", c: \"xor_bits\", coq: \"xor_vec\", ocaml: \"xor_vec\", interpreter: \"xor_vec\"}: forall 'n.\n (bits('n), bits('n)) -> bits('n)", "type": "forall 'n. (bits('n), bits('n)) -> bits('n)" } }, "xt2": { "val": { "source": "val xt2 : bits(8) -> bits(8)", "type": "bits(8) -> bits(8)" } }, "xt3": { "val": { "source": "val xt3 : bits(8) -> bits(8)", "type": "bits(8) -> bits(8)" } }, "zba_rtype_mnemonic": { "val": { "source": "val zba_rtype_mnemonic : brop_zba <-> string", "type": "brop_zba <-> string" } }, "zba_rtypeuw_mnemonic": { "val": { "source": "val zba_rtypeuw_mnemonic : bropw_zba <-> string", "type": "bropw_zba <-> string" } }, "zbb_extop_mnemonic": { "val": { "source": "val zbb_extop_mnemonic : extop_zbb <-> string", "type": "extop_zbb <-> string" } }, "zbb_rtype_mnemonic": { "val": { "source": "val zbb_rtype_mnemonic : brop_zbb <-> string", "type": "brop_zbb <-> string" } }, "zbb_rtypew_mnemonic": { "val": { "source": "val zbb_rtypew_mnemonic : bropw_zbb <-> string", "type": "bropw_zbb <-> string" } }, "zbkb_rtype_mnemonic": { "val": { "source": "val zbkb_rtype_mnemonic : brop_zbkb <-> string", "type": "brop_zbkb <-> string" } }, "zbs_iop_mnemonic": { "val": { "source": "val zbs_iop_mnemonic : biop_zbs <-> string", "type": "biop_zbs <-> string" } }, "zbs_rtype_mnemonic": { "val": { "source": "val zbs_rtype_mnemonic : brop_zbs <-> string", "type": "brop_zbs <-> string" } }, "zero_extend": { "val": { "source": "val zero_extend : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)", "type": "forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)" } }, "zeros_implicit": { "val": { "source": "val zeros_implicit : forall 'n, 'n >= 0 . implicit('n) -> bits('n)", "type": "forall 'n, 'n >= 0 . implicit('n) -> bits('n)" } }, "zicond_mnemonic": { "val": { "source": "val zicond_mnemonic : zicondop <-> string", "type": "zicondop <-> string" } }, "zicondop_of_num": { "val": { "source": "val zicondop_of_num : forall 'e, (0 <= 'e & 'e <= 1). int('e) -> zicondop", "type": "forall 'e, (0 <= 'e & 'e <= 1). int('e) -> zicondop" } }, "(operator <=_s)": { "val": { "source": "val operator <=_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool", "type": "forall 'n, 'n > 0. (bits('n), bits('n)) -> bool" } }, "(operator <=_u)": { "val": { "source": "val operator <=_u : forall 'n. (bits('n), bits('n)) -> bool", "type": "forall 'n. (bits('n), bits('n)) -> bool" } }, "(operator <_s)": { "val": { "source": "val operator <_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool", "type": "forall 'n, 'n > 0. (bits('n), bits('n)) -> bool" } }, "(operator <_u)": { "val": { "source": "val operator <_u : forall 'n. (bits('n), bits('n)) -> bool", "type": "forall 'n. (bits('n), bits('n)) -> bool" } }, "(operator >=_s)": { "val": { "source": "val operator >=_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool", "type": "forall 'n, 'n > 0. (bits('n), bits('n)) -> bool" } }, "(operator >=_u)": { "val": { "source": "val operator >=_u : forall 'n. (bits('n), bits('n)) -> bool", "type": "forall 'n. (bits('n), bits('n)) -> bool" } }, "(operator >_s)": { "val": { "source": "val operator >_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool", "type": "forall 'n, 'n > 0. (bits('n), bits('n)) -> bool" } }, "(operator >_u)": { "val": { "source": "val operator >_u : forall 'n. (bits('n), bits('n)) -> bool", "type": "forall 'n. (bits('n), bits('n)) -> bool" } } }, "types": { "AccessType": { "type": "union AccessType ('a : Type) = {\n Read : 'a,\n Write : 'a,\n ReadWrite : ('a, 'a),\n Execute : unit\n}" }, "Architecture": { "type": "enum Architecture = {RV32, RV64, RV128}" }, "Counteren": { "type": "bitfield Counteren : bits(32) = {\n HPM : 31 .. 3,\n IR : 2,\n TM : 1,\n CY : 0\n}" }, "Counterin": { "type": "bitfield Counterin : bits(32) = {\n /* no HPM counters yet */\n IR : 2,\n CY : 0\n}" }, "ExceptionType": { "type": "union ExceptionType = {\n E_Fetch_Addr_Align : unit,\n E_Fetch_Access_Fault : unit,\n E_Illegal_Instr : unit,\n E_Breakpoint : unit,\n E_Load_Addr_Align : unit,\n E_Load_Access_Fault : unit,\n E_SAMO_Addr_Align : unit,\n E_SAMO_Access_Fault : unit,\n E_U_EnvCall : unit,\n E_S_EnvCall : unit,\n E_Reserved_10 : unit,\n E_M_EnvCall : unit,\n E_Fetch_Page_Fault : unit,\n E_Load_Page_Fault : unit,\n E_Reserved_14 : unit,\n E_SAMO_Page_Fault : unit,\n\n /* extensions */\n E_Extension : ext_exc_type\n}" }, "ExtStatus": { "type": "enum ExtStatus = {Off, Initial, Clean, Dirty}" }, "Ext_ControlAddr_Check": { "type": "union Ext_ControlAddr_Check ('a : Type) = {\n Ext_ControlAddr_OK : xlenbits, /* PC value to use for the target of the control operation */\n Ext_ControlAddr_Error : 'a\n}" }, "Ext_DataAddr_Check": { "type": "union Ext_DataAddr_Check ('a : Type) = {\n Ext_DataAddr_OK : xlenbits, /* Address to use for the data access */\n Ext_DataAddr_Error : 'a\n}" }, "Ext_FetchAddr_Check": { "type": "union Ext_FetchAddr_Check ('a : Type) = {\n Ext_FetchAddr_OK : xlenbits, /* PC value to use for the actual fetch */\n Ext_FetchAddr_Error : 'a\n}" }, "Ext_PhysAddr_Check": { "type": "union Ext_PhysAddr_Check = {\n Ext_PhysAddr_OK : unit,\n Ext_PhysAddr_Error : ExceptionType\n}" }, "Fcsr": { "type": "bitfield Fcsr : bits(32) = {\n FRM : 7 .. 5,\n FFLAGS : 4 .. 0,\n}" }, "FetchResult": { "type": "union FetchResult = {\n F_Ext_Error : ext_fetch_addr_error, /* For extensions */\n F_Base : word, /* Base ISA */\n F_RVC : half, /* Compressed ISA */\n F_Error : (ExceptionType, xlenbits) /* standard exception and PC */\n}" }, "InterruptType": { "type": "enum InterruptType = {\n I_U_Software,\n I_S_Software,\n I_M_Software,\n I_U_Timer,\n I_S_Timer,\n I_M_Timer,\n I_U_External,\n I_S_External,\n I_M_External\n}" }, "MEnvcfg": { "type": "bitfield MEnvcfg : bits(64) = {\n // Supervisor TimeCmp Extension\n STCE : 63,\n // Page Based Memory Types Extension\n PBMTE : 62,\n // Reserved WPRI bits.\n wpri_1 : 61 .. 8,\n // Cache Block Zero instruction Enable\n CBZE : 7,\n // Cache Block Clean and Flush instruction Enable\n CBCFE : 6,\n // Cache Block Invalidate instruction Enable\n CBIE : 5 .. 4,\n // Reserved WPRI bits.\n wpri_0 : 3 .. 1,\n // Fence of I/O implies Memory\n FIOM : 0,\n}" }, "Mcause": { "type": "bitfield Mcause : xlenbits = {\n IsInterrupt : xlen - 1,\n Cause : xlen - 2 .. 0\n}" }, "Medeleg": { "type": "bitfield Medeleg : xlenbits = {\n SAMO_Page_Fault : 15,\n Load_Page_Fault : 13,\n Fetch_Page_Fault : 12,\n MEnvCall : 11,\n SEnvCall : 9,\n UEnvCall : 8,\n SAMO_Access_Fault : 7,\n SAMO_Addr_Align : 6,\n Load_Access_Fault : 5,\n Load_Addr_Align : 4,\n Breakpoint : 3,\n Illegal_Instr : 2,\n Fetch_Access_Fault: 1,\n Fetch_Addr_Align : 0\n}" }, "MemoryOpResult": { "type": "union MemoryOpResult ('a : Type) = {\n MemValue : 'a,\n MemException : ExceptionType\n}" }, "Minterrupts": { "type": "bitfield Minterrupts : xlenbits = {\n MEI : 11, /* external interrupts */\n SEI : 9,\n UEI : 8,\n\n MTI : 7, /* timers interrupts */\n STI : 5,\n UTI : 4,\n\n MSI : 3, /* software interrupts */\n SSI : 1,\n USI : 0,\n}" }, "Misa": { "type": "bitfield Misa : xlenbits = {\n MXL : xlen - 1 .. xlen - 2,\n\n Z : 25,\n Y : 24,\n X : 23,\n W : 22,\n V : 21,\n U : 20,\n T : 19,\n S : 18,\n R : 17,\n Q : 16,\n P : 15,\n O : 14,\n N : 13,\n M : 12,\n L : 11,\n K : 10,\n J : 9,\n I : 8,\n H : 7,\n G : 6,\n F : 5,\n E : 4,\n D : 3,\n C : 2,\n B : 1,\n A : 0\n}" }, "Mstatus": { "type": "bitfield Mstatus : xlenbits = {\n SD : xlen - 1,\n\n // The MBE and SBE fields are in mstatus in RV64 and absent in RV32.\n // On RV32, they are in mstatush, which doesn't exist in RV64. For now,\n // they are handled in an ad-hoc way.\n // MBE : 37\n // SBE : 36\n\n // The SXL and UXL fields don't exist on RV32, so they are modelled\n // via explicit getters and setters; see below.\n // SXL : 35 .. 34,\n // UXL : 33 .. 32,\n\n TSR : 22,\n TW : 21,\n TVM : 20,\n MXR : 19,\n SUM : 18,\n MPRV : 17,\n\n XS : 16 .. 15,\n FS : 14 .. 13,\n\n MPP : 12 .. 11,\n VS : 10 .. 9,\n SPP : 8,\n\n MPIE : 7,\n SPIE : 5,\n UPIE : 4,\n\n MIE : 3,\n SIE : 1,\n UIE : 0\n}" }, "Mstatush": { "type": "bitfield Mstatush : bits(32) = {\n MBE : 5,\n SBE : 4\n}" }, "Mtvec": { "type": "bitfield Mtvec : xlenbits = {\n Base : xlen - 1 .. 2,\n Mode : 1 .. 0\n}" }, "PAGESIZE_BITS": { "type": "type PAGESIZE_BITS : Int = 12" }, "PTE_Check": { "type": "union PTE_Check = {\n PTE_Check_Success : ext_ptw,\n PTE_Check_Failure : (ext_ptw, ext_ptw_fail)\n}" }, "PTE_Flags": { "type": "bitfield PTE_Flags : pte_flags_bits = {\n D : 7, // dirty\n A : 6, // accessed\n G : 5, // global\n U : 4, // User\n X : 3, // Execute permission\n W : 2, // Write permission\n R : 1, // Read permission\n V : 0 // Valid\n}" }, "PTW_Error": { "type": "union PTW_Error = {\n PTW_Invalid_Addr : unit, // invalid source address\n PTW_Access : unit, // physical memory access error for a PTE\n PTW_Invalid_PTE : unit,\n PTW_No_Permission : unit,\n PTW_Misaligned : unit, // misaligned superpage\n PTW_PTE_Update : unit, // PTE update needed but not enabled\n PTW_Ext_Error : ext_ptw_error // parameterized for errors from extensions\n}" }, "PTW_Level": { "type": "type PTW_Level = range(0,3)" }, "PTW_Result": { "type": "union PTW_Result = {\n PTW_Success: (bits(64), bits(64), bits(64), nat, bool, ext_ptw),\n PTW_Failure: (PTW_Error, ext_ptw)\n}" }, "PmpAddrMatchType": { "type": "enum PmpAddrMatchType = {OFF, TOR, NA4, NAPOT}" }, "Pmpcfg_ent": { "type": "bitfield Pmpcfg_ent : bits(8) = {\n L : 7, /* locking */\n A : 4 .. 3, /* address match type, encoded as above */\n\n /* permissions */\n X : 2, /* execute */\n W : 1, /* write */\n R : 0 /* read */\n}" }, "Privilege": { "type": "enum Privilege = {User, Supervisor, Machine}" }, "Retired": { "type": "enum Retired = {RETIRE_SUCCESS, RETIRE_FAIL}" }, "SATPMode": { "type": "enum SATPMode = {Sbare, Sv32, Sv39, Sv48}" }, "SEnvcfg": { "type": "bitfield SEnvcfg : xlenbits = {\n // Cache Block Zero instruction Enable\n CBZE : 7,\n // Cache Block Clean and Flush instruction Enable\n CBCFE : 6,\n // Cache Block Invalidate instruction Enable\n CBIE : 5 .. 4,\n // Reserved WPRI bits.\n wpri_0 : 3 .. 1,\n // Fence of I/O implies Memory\n FIOM : 0,\n}" }, "SV_Params": { "type": "struct SV_Params = {\n // VA\n va_size_bits : {32, 39, 48}, // 32 39 48\n vpn_size_bits : {10, 9}, // 10 9 9\n\n // PTE\n levels : { 2, 3, 4}, // 2 3 4\n log_pte_size_bytes : { 2, 3}, // 2 3 3\n pte_msbs_lsb_index : {32, 54}, // 32 54 54\n pte_msbs_size_bits : { 0, 10}, // 0 10 10\n pte_PPNs_lsb_index : {10}, // 10 10 10\n pte_PPNs_size_bits : {22, 44}, // 22 44 44\n pte_PPN_j_size_bits : {10, 9} // 10 9 9\n}" }, "Satp32": { "type": "bitfield Satp32 : bits(32) = {\n Mode : 31,\n Asid : 30 .. 22,\n PPN : 21 .. 0\n}" }, "Satp64": { "type": "bitfield Satp64 : bits(64) = {\n Mode : 63 .. 60,\n Asid : 59 .. 44,\n PPN : 43 .. 0\n}" }, "Sedeleg": { "type": "bitfield Sedeleg : xlenbits = {\n UEnvCall : 8,\n SAMO_Access_Fault : 7,\n SAMO_Addr_Align : 6,\n Load_Access_Fault : 5,\n Load_Addr_Align : 4,\n Breakpoint : 3,\n Illegal_Instr : 2,\n Fetch_Access_Fault: 1,\n Fetch_Addr_Align : 0\n}" }, "Sinterrupts": { "type": "bitfield Sinterrupts : xlenbits = {\n SEI : 9, /* external interrupts */\n UEI : 8,\n\n STI : 5, /* timers interrupts */\n UTI : 4,\n\n SSI : 1, /* software interrupts */\n USI : 0\n}" }, "Sstatus": { "type": "bitfield Sstatus : xlenbits = {\n SD : xlen - 1,\n // The UXL field does not exist on RV32, so we define an explicit\n // getter and setter below.\n // UXL : 30 .. 29,\n MXR : 19,\n SUM : 18,\n XS : 16 .. 15,\n FS : 14 .. 13,\n VS : 10 .. 9,\n SPP : 8,\n SPIE : 5,\n UPIE : 4,\n SIE : 1,\n UIE : 0\n}" }, "TLB_Entry": { "type": "struct TLB_Entry = {\n asid : asidbits, // address-space id\n global : bool, // global translation\n vAddr : bits(64), // VPN\n pAddr : bits(64), // ppn\n vMatchMask : bits(64), // matching mask for superpages\n vAddrMask : bits(64), // selection mask for superpages\n pte : bits(64), // PTE\n pteAddr : bits(64), // for dirty writeback\n age : bits(64) // for replacement policy?\n}" }, "TR_Result": { "type": "union TR_Result('paddr : Type, 'failure : Type) = {\n TR_Address : ('paddr, ext_ptw),\n TR_Failure : ('failure, ext_ptw)\n}" }, "TrapVectorMode": { "type": "enum TrapVectorMode = {TV_Direct, TV_Vector, TV_Reserved}" }, "Uinterrupts": { "type": "bitfield Uinterrupts : xlenbits = {\n UEI : 8, /* external interrupt */\n UTI : 4, /* timer interrupt */\n USI : 0 /* software interrupt */\n}" }, "Ustatus": { "type": "bitfield Ustatus : xlenbits = {\n UPIE : 4,\n UIE : 0\n}" }, "Vcsr": { "type": "bitfield Vcsr : bits(3) = {\n vxrm : 2 .. 1,\n vxsat : 0\n}" }, "Vtype": { "type": "bitfield Vtype : xlenbits = {\n vill : xlen - 1,\n reserved : xlen - 2 .. 8,\n vma : 7,\n vta : 6,\n vsew : 5 .. 3,\n vlmul : 2 .. 0\n}" }, "a64_barrier_domain": { "type": "enum a64_barrier_domain = {A64_FullShare, A64_InnerShare, A64_OuterShare, A64_NonShare}" }, "a64_barrier_type": { "type": "enum a64_barrier_type = {A64_barrier_all, A64_barrier_LD, A64_barrier_ST}" }, "agtype": { "type": "enum agtype = { UNDISTURBED, AGNOSTIC }" }, "amo": { "type": "type amo = bits(1)" }, "amoop": { "type": "enum amoop = {AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR,\n AMOMIN, AMOMAX, AMOMINU, AMOMAXU}" }, "arch_xlen": { "type": "type arch_xlen = bits(2)" }, "asidbits": { "type": "type asidbits = bits(16)" }, "ast": { "type": "scattered union ast" }, "barrier_kind": { "type": "union barrier_kind = {\n Barrier_Sync : unit,\n Barrier_LwSync : unit,\n Barrier_Eieio : unit,\n Barrier_Isync : unit,\n Barrier_DMB : (a64_barrier_domain, a64_barrier_type),\n Barrier_DSB : (a64_barrier_domain, a64_barrier_type),\n Barrier_ISB : unit,\n Barrier_MIPS_SYNC : unit,\n Barrier_RISCV_rw_rw : unit,\n Barrier_RISCV_r_rw : unit,\n Barrier_RISCV_r_r : unit,\n Barrier_RISCV_rw_w : unit,\n Barrier_RISCV_w_w : unit,\n Barrier_RISCV_w_rw : unit,\n Barrier_RISCV_rw_r : unit,\n Barrier_RISCV_r_w : unit,\n Barrier_RISCV_w_r : unit,\n Barrier_RISCV_tso : unit,\n Barrier_RISCV_i : unit,\n Barrier_x86_MFENCE : unit\n}" }, "biop_zbs": { "type": "enum biop_zbs = {RISCV_BCLRI, RISCV_BEXTI, RISCV_BINVI, RISCV_BSETI}" }, "bits": { "type": "type bits('n: Int) = bitvector('n)" }, "bits_D": { "type": "type bits_D = bits(64)" }, "bits_H": { "type": "type bits_H = bits(16)" }, "bits_L": { "type": "type bits_L = bits(64)" }, "bits_LU": { "type": "type bits_LU = bits(64)" }, "bits_S": { "type": "type bits_S = bits(32)" }, "bits_W": { "type": "type bits_W = bits(32)" }, "bits_WU": { "type": "type bits_WU = bits(32)" }, "bits_fflags": { "type": "type bits_fflags = bits(5)" }, "bits_rm": { "type": "type bits_rm = bits(3)" }, "bop": { "type": "enum bop = {RISCV_BEQ, RISCV_BNE, RISCV_BLT,\n RISCV_BGE, RISCV_BLTU, RISCV_BGEU}" }, "brop_zba": { "type": "enum brop_zba = {RISCV_SH1ADD, RISCV_SH2ADD, RISCV_SH3ADD}" }, "brop_zbb": { "type": "enum brop_zbb = {RISCV_ANDN, RISCV_ORN, RISCV_XNOR, RISCV_MAX,\n RISCV_MAXU, RISCV_MIN, RISCV_MINU, RISCV_ROL,\n RISCV_ROR}" }, "brop_zbkb": { "type": "enum brop_zbkb = {RISCV_PACK, RISCV_PACKH}" }, "brop_zbs": { "type": "enum brop_zbs = {RISCV_BCLR, RISCV_BEXT, RISCV_BINV, RISCV_BSET}" }, "bropw_zba": { "type": "enum bropw_zba = {RISCV_ADDUW, RISCV_SH1ADDUW, RISCV_SH2ADDUW,\n RISCV_SH3ADDUW}" }, "bropw_zbb": { "type": "enum bropw_zbb = {RISCV_ROLW, RISCV_RORW}" }, "cache_op_kind": { "type": "enum cache_op_kind = {\n Cache_op_D_IVAC,\n Cache_op_D_ISW,\n Cache_op_D_CSW,\n Cache_op_D_CISW,\n Cache_op_D_ZVA,\n Cache_op_D_CVAC,\n Cache_op_D_CVAU,\n Cache_op_D_CIVAC,\n Cache_op_I_IALLUIS,\n Cache_op_I_IALLU,\n Cache_op_I_IVAU\n}" }, "cregidx": { "type": "type cregidx = bits(3)" }, "csrRW": { "type": "type csrRW = bits(2)" }, "csreg": { "type": "type csreg = bits(12)" }, "csrop": { "type": "enum csrop = {CSRRW, CSRRS, CSRRC}" }, "ctl_result": { "type": "union ctl_result = {\n CTL_TRAP : sync_exception,\n CTL_SRET : unit,\n CTL_MRET : unit,\n CTL_URET : unit\n}" }, "diafp": { "type": "union diafp = {DIAFP_none : unit, DIAFP_concrete : bits(64), DIAFP_reg : regfp}" }, "exc_code": { "type": "type exc_code = bits(8)" }, "exception": { "type": "union exception = {\n Error_not_implemented : string,\n Error_internal_error : unit\n}" }, "extPte": { "type": "type extPte = bits(64)" }, "ext_access_type": { "type": "type ext_access_type = unit" }, "ext_control_addr_error": { "type": "type ext_control_addr_error = unit" }, "ext_data_addr_error": { "type": "type ext_data_addr_error = unit" }, "ext_exc_type": { "type": "type ext_exc_type = unit" }, "ext_exception": { "type": "type ext_exception = unit" }, "ext_fetch_addr_error": { "type": "type ext_fetch_addr_error = unit" }, "ext_ptw": { "type": "type ext_ptw = unit" }, "ext_ptw_error": { "type": "type ext_ptw_error = unit" }, "ext_ptw_fail": { "type": "type ext_ptw_fail = unit" }, "ext_status": { "type": "type ext_status = bits(2)" }, "extop_zbb": { "type": "enum extop_zbb = {RISCV_SEXTB, RISCV_SEXTH, RISCV_ZEXTH}" }, "f_bin_op_D": { "type": "enum f_bin_op_D = {FSGNJ_D, FSGNJN_D, FSGNJX_D, FMIN_D, FMAX_D, FEQ_D, FLT_D, FLE_D}" }, "f_bin_op_H": { "type": "enum f_bin_op_H = {FSGNJ_H, FSGNJN_H, FSGNJX_H, FMIN_H, FMAX_H, FEQ_H, FLT_H, FLE_H}" }, "f_bin_op_S": { "type": "enum f_bin_op_S = {FSGNJ_S, FSGNJN_S, FSGNJX_S, FMIN_S, FMAX_S, FEQ_S, FLT_S, FLE_S}" }, "f_bin_rm_op_D": { "type": "enum f_bin_rm_op_D = {FADD_D, FSUB_D, FMUL_D, FDIV_D}" }, "f_bin_rm_op_H": { "type": "enum f_bin_rm_op_H = {FADD_H, FSUB_H, FMUL_H, FDIV_H}" }, "f_bin_rm_op_S": { "type": "enum f_bin_rm_op_S = {FADD_S, FSUB_S, FMUL_S, FDIV_S}" }, "f_madd_op_D": { "type": "enum f_madd_op_D = {FMADD_D, FMSUB_D, FNMSUB_D, FNMADD_D}" }, "f_madd_op_H": { "type": "enum f_madd_op_H = {FMADD_H, FMSUB_H, FNMSUB_H, FNMADD_H}" }, "f_madd_op_S": { "type": "enum f_madd_op_S = {FMADD_S, FMSUB_S, FNMSUB_S, FNMADD_S}" }, "f_un_op_D": { "type": "enum f_un_op_D = {FCLASS_D, /* RV32 and RV64 */\n FMV_X_D, FMV_D_X}" }, "f_un_op_H": { "type": "enum f_un_op_H = {FCLASS_H, FMV_X_H, FMV_H_X}" }, "f_un_op_S": { "type": "enum f_un_op_S = {FCLASS_S, FMV_X_W, FMV_W_X}" }, "f_un_rm_op_D": { "type": "enum f_un_rm_op_D = {FSQRT_D, FCVT_W_D, FCVT_WU_D, FCVT_D_W, FCVT_D_WU, // RV32 and RV64\n FCVT_S_D, FCVT_D_S,\n FCVT_L_D, FCVT_LU_D, FCVT_D_L, FCVT_D_LU}" }, "f_un_rm_op_H": { "type": "enum f_un_rm_op_H = {FSQRT_H, FCVT_W_H, FCVT_WU_H, FCVT_H_W, FCVT_H_WU, // RV32 and RV64\n FCVT_H_S, FCVT_H_D, FCVT_S_H, FCVT_D_H,\n FCVT_L_H, FCVT_LU_H, FCVT_H_L, FCVT_H_LU}" }, "f_un_rm_op_S": { "type": "enum f_un_rm_op_S = {FSQRT_S, FCVT_W_S, FCVT_WU_S, FCVT_S_W, FCVT_S_WU, // RV32 and RV64\n FCVT_L_S, FCVT_LU_S, FCVT_S_L, FCVT_S_LU}" }, "flen": { "type": "type flen : Int = 64" }, "flen_bytes": { "type": "type flen_bytes : Int = 8" }, "flenbits": { "type": "type flenbits = bits(flen)" }, "fregtype": { "type": "type fregtype = flenbits" }, "fvffunct6": { "type": "enum fvffunct6 = { VF_VADD, VF_VSUB, VF_VMIN, VF_VMAX, VF_VSGNJ, VF_VSGNJN, VF_VSGNJX,\n VF_VDIV, VF_VRDIV, VF_VMUL, VF_VRSUB, VF_VSLIDE1UP, VF_VSLIDE1DOWN }" }, "fvfmafunct6": { "type": "enum fvfmafunct6 = { VF_VMADD, VF_VNMADD, VF_VMSUB, VF_VNMSUB, VF_VMACC, VF_VNMACC, VF_VMSAC, VF_VNMSAC }" }, "fvfmfunct6": { "type": "enum fvfmfunct6 = { VFM_VMFEQ, VFM_VMFLE, VFM_VMFLT, VFM_VMFNE, VFM_VMFGT, VFM_VMFGE }" }, "fvvfunct6": { "type": "enum fvvfunct6 = { FVV_VADD, FVV_VSUB, FVV_VMIN, FVV_VMAX, FVV_VSGNJ, FVV_VSGNJN, FVV_VSGNJX,\n FVV_VDIV, FVV_VMUL }" }, "fvvmafunct6": { "type": "enum fvvmafunct6 = { FVV_VMADD, FVV_VNMADD, FVV_VMSUB, FVV_VNMSUB, FVV_VMACC, FVV_VNMACC, FVV_VMSAC, FVV_VNMSAC }" }, "fvvmfunct6": { "type": "enum fvvmfunct6 = { FVVM_VMFEQ, FVVM_VMFLE, FVVM_VMFLT, FVVM_VMFNE }" }, "fwffunct6": { "type": "enum fwffunct6 = { FWF_VADD, FWF_VSUB }" }, "fwvffunct6": { "type": "enum fwvffunct6 = { FWVF_VADD, FWVF_VSUB, FWVF_VMUL }" }, "fwvfmafunct6": { "type": "enum fwvfmafunct6 = { FWVF_VMACC, FWVF_VNMACC, FWVF_VMSAC, FWVF_VNMSAC }" }, "fwvfunct6": { "type": "enum fwvfunct6 = { FWV_VADD, FWV_VSUB }" }, "fwvvfunct6": { "type": "enum fwvvfunct6 = { FWVV_VADD, FWVV_VSUB, FWVV_VMUL }" }, "fwvvmafunct6": { "type": "enum fwvvmafunct6 = { FWVV_VMACC, FWVV_VNMACC, FWVV_VMSAC, FWVV_VNMSAC }" }, "half": { "type": "type half = bits(16)" }, "htif_cmd": { "type": "bitfield htif_cmd : bits(64) = {\n device : 63 .. 56,\n cmd : 55 .. 48,\n payload : 47 .. 0\n}" }, "imm12": { "type": "type imm12 = bits(12)" }, "imm20": { "type": "type imm20 = bits(20)" }, "instruction_kind": { "type": "union instruction_kind = {\n IK_barrier : barrier_kind,\n IK_mem_read : read_kind,\n IK_mem_write : write_kind,\n IK_mem_rmw : (read_kind, write_kind),\n IK_branch : unit,\n IK_trans : trans_kind,\n IK_simple : unit,\n IK_cache_op : cache_op_kind\n}" }, "interrupt_set": { "type": "union interrupt_set = {\n Ints_Pending : xlenbits,\n Ints_Delegated : xlenbits,\n Ints_Empty : unit\n}" }, "iop": { "type": "enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU,\n RISCV_XORI, RISCV_ORI, RISCV_ANDI}" }, "maskfunct3": { "type": "enum maskfunct3 = { VV_VMERGE, VI_VMERGE, VX_VMERGE }" }, "max_mem_access": { "type": "type max_mem_access : Int = 16" }, "mem_meta": { "type": "type mem_meta = unit" }, "mmfunct6": { "type": "enum mmfunct6 = { MM_VMAND, MM_VMNAND, MM_VMANDNOT, MM_VMXOR, MM_VMOR, MM_VMNOR, MM_VMORNOT, MM_VMXNOR }" }, "mvvfunct6": { "type": "enum mvvfunct6 = { MVV_VAADDU, MVV_VAADD, MVV_VASUBU, MVV_VASUB, MVV_VMUL, MVV_VMULH,\n MVV_VMULHU, MVV_VMULHSU, MVV_VDIVU, MVV_VDIV, MVV_VREMU, MVV_VREM }" }, "mvvmafunct6": { "type": "enum mvvmafunct6 = { MVV_VMACC, MVV_VNMSAC, MVV_VMADD, MVV_VNMSUB }" }, "mvxfunct6": { "type": "enum mvxfunct6 = { MVX_VAADDU, MVX_VAADD, MVX_VASUBU, MVX_VASUB, MVX_VSLIDE1UP, MVX_VSLIDE1DOWN,\n\tMVX_VMUL, MVX_VMULH, MVX_VMULHU, MVX_VMULHSU, MVX_VDIVU, MVX_VDIV, MVX_VREMU, MVX_VREM }" }, "mvxmafunct6": { "type": "enum mvxmafunct6 = { MVX_VMACC, MVX_VNMSAC, MVX_VMADD, MVX_VNMSUB }" }, "niafp": { "type": "union niafp = {NIAFP_successor : unit, NIAFP_concrete_address : bits(64), NIAFP_indirect_address : unit}" }, "niafps": { "type": "type niafps = list(niafp)" }, "nifunct6": { "type": "enum nifunct6 = { NI_VNCLIPU, NI_VNCLIP }" }, "nisfunct6": { "type": "enum nisfunct6 = { NIS_VNSRL, NIS_VNSRA }" }, "nvfunct6": { "type": "enum nvfunct6 = { NV_VNCLIPU, NV_VNCLIP }" }, "nvsfunct6": { "type": "enum nvsfunct6 = { NVS_VNSRL, NVS_VNSRA }" }, "nxfunct6": { "type": "enum nxfunct6 = { NX_VNCLIPU, NX_VNCLIP}" }, "nxsfunct6": { "type": "enum nxsfunct6 = { NXS_VNSRL, NXS_VNSRA }" }, "opcode": { "type": "type opcode = bits(7)" }, "option": { "type": "union option ('a: Type) = {Some : 'a, None : unit}" }, "pmpAddrMatch": { "type": "enum pmpAddrMatch = {PMP_NoMatch, PMP_PartialMatch, PMP_Match}" }, "pmpMatch": { "type": "enum pmpMatch = {PMP_Success, PMP_Continue, PMP_Fail}" }, "pmp_addr_range": { "type": "type pmp_addr_range = option((xlenbits, xlenbits))" }, "priv_level": { "type": "type priv_level = bits(2)" }, "pte_flags_bits": { "type": "type pte_flags_bits = bits(8)" }, "read_kind": { "type": "enum read_kind = {\n Read_plain,\n Read_reserve,\n Read_acquire,\n Read_exclusive,\n Read_exclusive_acquire,\n Read_stream,\n Read_ifetch,\n Read_RISCV_acquire,\n Read_RISCV_strong_acquire,\n Read_RISCV_reserved,\n Read_RISCV_reserved_acquire,\n Read_RISCV_reserved_strong_acquire,\n Read_X86_locked\n}" }, "regfp": { "type": "union regfp = {RFull : string, RSlice : (string, nat, nat), RSliceBit : (string, nat), RField : (string, string)}" }, "regfps": { "type": "type regfps = list(regfp)" }, "regidx": { "type": "type regidx = bits(5)" }, "regno": { "type": "type regno ('n : Int), 0 <= 'n < 32 = int('n)" }, "regtype": { "type": "type regtype = xlenbits" }, "rfvvfunct6": { "type": "enum rfvvfunct6 = { FVV_VFREDOSUM, FVV_VFREDUSUM, FVV_VFREDMAX, FVV_VFREDMIN,\n FVV_VFWREDOSUM, FVV_VFWREDUSUM }" }, "rivvfunct6": { "type": "enum rivvfunct6 = { IVV_VWREDSUMU, IVV_VWREDSUM }" }, "rmvvfunct6": { "type": "enum rmvvfunct6 = { MVV_VREDSUM, MVV_VREDAND, MVV_VREDOR, MVV_VREDXOR,\n MVV_VREDMINU, MVV_VREDMIN, MVV_VREDMAXU, MVV_VREDMAX }" }, "rop": { "type": "enum rop = {RISCV_ADD, RISCV_SUB, RISCV_SLL, RISCV_SLT,\n RISCV_SLTU, RISCV_XOR, RISCV_SRL, RISCV_SRA,\n RISCV_OR, RISCV_AND}" }, "ropw": { "type": "enum ropw = {RISCV_ADDW, RISCV_SUBW, RISCV_SLLW,\n RISCV_SRLW, RISCV_SRAW}" }, "rounding_mode": { "type": "enum rounding_mode = {RM_RNE, RM_RTZ, RM_RDN, RM_RUP, RM_RMM, RM_DYN}" }, "satp_mode": { "type": "type satp_mode = bits(4)" }, "seed_opst": { "type": "enum seed_opst = {\n BIST, // Built-in-self-test. No randomness sampled.\n ES16, // Entropy-sample-16. Valid 16-bits of randomness sampled.\n WAIT, // Device still gathering entropy.\n DEAD // Fatal device compromise. No randomness sampled.\n}" }, "sop": { "type": "enum sop = {RISCV_SLLI, RISCV_SRLI, RISCV_SRAI}" }, "sopw": { "type": "enum sopw = {RISCV_SLLIW, RISCV_SRLIW,\n RISCV_SRAIW}" }, "sync_exception": { "type": "struct sync_exception = {\n trap : ExceptionType,\n excinfo : option(xlenbits),\n ext : option(ext_exception) /* for extensions */\n}" }, "trans_kind": { "type": "enum trans_kind = {Transaction_start, Transaction_commit, Transaction_abort}" }, "tv_mode": { "type": "type tv_mode = bits(2)" }, "uop": { "type": "enum uop = {RISCV_LUI, RISCV_AUIPC}" }, "vext2funct6": { "type": "enum vext2funct6 = { VEXT2_ZVF2, VEXT2_SVF2 }" }, "vext4funct6": { "type": "enum vext4funct6 = { VEXT4_ZVF4, VEXT4_SVF4 }" }, "vext8funct6": { "type": "enum vext8funct6 = { VEXT8_ZVF8, VEXT8_SVF8 }" }, "vfnunary0": { "type": "enum vfnunary0 = { FNV_CVT_XU_F, FNV_CVT_X_F, FNV_CVT_F_XU, FNV_CVT_F_X, FNV_CVT_F_F,\n FNV_CVT_ROD_F_F, FNV_CVT_RTZ_XU_F, FNV_CVT_RTZ_X_F}" }, "vfunary0": { "type": "enum vfunary0 = { FV_CVT_XU_F, FV_CVT_X_F, FV_CVT_F_XU, FV_CVT_F_X, FV_CVT_RTZ_XU_F, FV_CVT_RTZ_X_F }" }, "vfunary1": { "type": "enum vfunary1 = { FVV_VSQRT, FVV_VRSQRT7, FVV_VREC7, FVV_VCLASS }" }, "vfwunary0": { "type": "enum vfwunary0 = { FWV_CVT_XU_F, FWV_CVT_X_F, FWV_CVT_F_XU, FWV_CVT_F_X, FWV_CVT_F_F,\n FWV_CVT_RTZ_XU_F, FWV_CVT_RTZ_X_F }" }, "vicmpfunct6": { "type": "enum vicmpfunct6 = { VICMP_VMSEQ, VICMP_VMSNE, VICMP_VMSLEU, VICMP_VMSLE, VICMP_VMSGTU, VICMP_VMSGT }" }, "vifunct6": { "type": "enum vifunct6 = { VI_VADD, VI_VRSUB, VI_VAND, VI_VOR, VI_VXOR, VI_VSADDU, VI_VSADD,\n VI_VSLL, VI_VSRL, VI_VSRA, VI_VSSRL, VI_VSSRA }" }, "vimcfunct6": { "type": "enum vimcfunct6 = { VIMC_VMADC }" }, "vimfunct6": { "type": "enum vimfunct6 = { VIM_VMADC }" }, "vimsfunct6": { "type": "enum vimsfunct6 = { VIMS_VADC }" }, "visgfunct6": { "type": "enum visgfunct6 = { VI_VSLIDEUP, VI_VSLIDEDOWN, VI_VRGATHER }" }, "vlenmax": { "type": "type vlenmax : Int = 65536" }, "vlewidth": { "type": "enum vlewidth = { VLE8, VLE16, VLE32, VLE64 }" }, "vmlsop": { "type": "enum vmlsop = { VLM, VSM }" }, "vreglenbits": { "type": "type vreglenbits = bits(vlenmax)" }, "vregtype": { "type": "type vregtype = vreglenbits" }, "vsetop": { "type": "enum vsetop = { VSETVLI, VSETVL }" }, "vvcmpfunct6": { "type": "enum vvcmpfunct6 = { VVCMP_VMSEQ, VVCMP_VMSNE, VVCMP_VMSLTU, VVCMP_VMSLT, VVCMP_VMSLEU, VVCMP_VMSLE }" }, "vvfunct6": { "type": "enum vvfunct6 = { VV_VADD, VV_VSUB, VV_VMINU, VV_VMIN, VV_VMAXU, VV_VMAX, VV_VAND, VV_VOR, VV_VXOR,\n VV_VRGATHER, VV_VRGATHEREI16, VV_VSADDU, VV_VSADD, VV_VSSUBU, VV_VSSUB, VV_VSLL, VV_VSMUL,\n VV_VSRL, VV_VSRA, VV_VSSRL, VV_VSSRA }" }, "vvmcfunct6": { "type": "enum vvmcfunct6 = { VVMC_VMADC, VVMC_VMSBC }" }, "vvmfunct6": { "type": "enum vvmfunct6 = { VVM_VMADC, VVM_VMSBC }" }, "vvmsfunct6": { "type": "enum vvmsfunct6 = { VVMS_VADC, VVMS_VSBC }" }, "vxcmpfunct6": { "type": "enum vxcmpfunct6 = { VXCMP_VMSEQ, VXCMP_VMSNE, VXCMP_VMSLTU, VXCMP_VMSLT, VXCMP_VMSLEU, VXCMP_VMSLE,\n VXCMP_VMSGTU, VXCMP_VMSGT }" }, "vxfunct6": { "type": "enum vxfunct6 = { VX_VADD, VX_VSUB, VX_VRSUB, VX_VMINU, VX_VMIN, VX_VMAXU, VX_VMAX,\n VX_VAND, VX_VOR, VX_VXOR, VX_VSADDU, VX_VSADD, VX_VSSUBU, VX_VSSUB,\n VX_VSLL, VX_VSMUL, VX_VSRL, VX_VSRA, VX_VSSRL, VX_VSSRA }" }, "vxmcfunct6": { "type": "enum vxmcfunct6 = { VXMC_VMADC, VXMC_VMSBC }" }, "vxmfunct6": { "type": "enum vxmfunct6 = { VXM_VMADC, VXM_VMSBC }" }, "vxmsfunct6": { "type": "enum vxmsfunct6 = { VXMS_VADC, VXMS_VSBC }" }, "vxsgfunct6": { "type": "enum vxsgfunct6 = { VX_VSLIDEUP, VX_VSLIDEDOWN, VX_VRGATHER }" }, "wmvvfunct6": { "type": "enum wmvvfunct6 = { WMVV_VWMACCU, WMVV_VWMACC, WMVV_VWMACCSU }" }, "wmvxfunct6": { "type": "enum wmvxfunct6 = { WMVX_VWMACCU, WMVX_VWMACC, WMVX_VWMACCUS, WMVX_VWMACCSU }" }, "word": { "type": "type word = bits(32)" }, "word_width": { "type": "enum word_width = {BYTE, HALF, WORD, DOUBLE}" }, "write_kind": { "type": "enum write_kind = {\n Write_plain,\n Write_conditional,\n Write_release,\n Write_exclusive,\n Write_exclusive_release,\n Write_RISCV_release,\n Write_RISCV_strong_release,\n Write_RISCV_conditional,\n Write_RISCV_conditional_release,\n Write_RISCV_conditional_strong_release,\n Write_X86_locked\n}" }, "wvfunct6": { "type": "enum wvfunct6 = { WV_VADD, WV_VSUB, WV_VADDU, WV_VSUBU }" }, "wvvfunct6": { "type": "enum wvvfunct6 = { WVV_VADD, WVV_VSUB, WVV_VADDU, WVV_VSUBU, WVV_VWMUL, WVV_VWMULU, WVV_VWMULSU }" }, "wvxfunct6": { "type": "enum wvxfunct6 = { WVX_VADD, WVX_VSUB, WVX_VADDU, WVX_VSUBU, WVX_VWMUL, WVX_VWMULU, WVX_VWMULSU }" }, "wxfunct6": { "type": "enum wxfunct6 = { WX_VADD, WX_VSUB, WX_VADDU, WX_VSUBU }" }, "xlen": { "type": "type xlen : Int = 64" }, "xlen_bytes": { "type": "type xlen_bytes : Int = 8" }, "xlenbits": { "type": "type xlenbits = bits(xlen)" }, "zicondop": { "type": "enum zicondop = {RISCV_CZERO_EQZ, RISCV_CZERO_NEZ}" } }, "registers": { "PC": { "register": { "source": "register PC : xlenbits", "type": "xlenbits" } }, "cur_inst": { "register": { "source": "register cur_inst : xlenbits", "type": "xlenbits" } }, "cur_privilege": { "register": { "source": "register cur_privilege : Privilege", "type": "Privilege" } }, "elen": { "register": { "source": "register elen : bits(1)", "type": "bits(1)" } }, "f0": { "register": { "source": "register f0 : fregtype", "type": "fregtype" } }, "f1": { "register": { "source": "register f1 : fregtype", "type": "fregtype" } }, "f10": { "register": { "source": "register f10 : fregtype", "type": "fregtype" } }, "f11": { "register": { "source": "register f11 : fregtype", "type": "fregtype" } }, "f12": { "register": { "source": "register f12 : fregtype", "type": "fregtype" } }, "f13": { "register": { "source": "register f13 : fregtype", "type": "fregtype" } }, "f14": { "register": { "source": "register f14 : fregtype", "type": "fregtype" } }, "f15": { "register": { "source": "register f15 : fregtype", "type": "fregtype" } }, "f16": { "register": { "source": "register f16 : fregtype", "type": "fregtype" } }, "f17": { "register": { "source": "register f17 : fregtype", "type": "fregtype" } }, "f18": { "register": { "source": "register f18 : fregtype", "type": "fregtype" } }, "f19": { "register": { "source": "register f19 : fregtype", "type": "fregtype" } }, "f2": { "register": { "source": "register f2 : fregtype", "type": "fregtype" } }, "f20": { "register": { "source": "register f20 : fregtype", "type": "fregtype" } }, "f21": { "register": { "source": "register f21 : fregtype", "type": "fregtype" } }, "f22": { "register": { "source": "register f22 : fregtype", "type": "fregtype" } }, "f23": { "register": { "source": "register f23 : fregtype", "type": "fregtype" } }, "f24": { "register": { "source": "register f24 : fregtype", "type": "fregtype" } }, "f25": { "register": { "source": "register f25 : fregtype", "type": "fregtype" } }, "f26": { "register": { "source": "register f26 : fregtype", "type": "fregtype" } }, "f27": { "register": { "source": "register f27 : fregtype", "type": "fregtype" } }, "f28": { "register": { "source": "register f28 : fregtype", "type": "fregtype" } }, "f29": { "register": { "source": "register f29 : fregtype", "type": "fregtype" } }, "f3": { "register": { "source": "register f3 : fregtype", "type": "fregtype" } }, "f30": { "register": { "source": "register f30 : fregtype", "type": "fregtype" } }, "f31": { "register": { "source": "register f31 : fregtype", "type": "fregtype" } }, "f4": { "register": { "source": "register f4 : fregtype", "type": "fregtype" } }, "f5": { "register": { "source": "register f5 : fregtype", "type": "fregtype" } }, "f6": { "register": { "source": "register f6 : fregtype", "type": "fregtype" } }, "f7": { "register": { "source": "register f7 : fregtype", "type": "fregtype" } }, "f8": { "register": { "source": "register f8 : fregtype", "type": "fregtype" } }, "f9": { "register": { "source": "register f9 : fregtype", "type": "fregtype" } }, "fcsr": { "register": { "source": "register fcsr : Fcsr", "type": "Fcsr" } }, "float_fflags": { "register": { "source": "register float_fflags : bits(64)", "type": "bits(64)" } }, "float_result": { "register": { "source": "register float_result : bits(64)", "type": "bits(64)" } }, "htif_cmd_write": { "register": { "source": "register htif_cmd_write : bit", "type": "bit" } }, "htif_done": { "register": { "source": "register htif_done : bool", "type": "bool" } }, "htif_exit_code": { "register": { "source": "register htif_exit_code : bits(64)", "type": "bits(64)" } }, "htif_payload_writes": { "register": { "source": "register htif_payload_writes : bits(4)", "type": "bits(4)" } }, "htif_tohost": { "register": { "source": "register htif_tohost : bits(64)", "type": "bits(64)" } }, "instbits": { "register": { "source": "register instbits : xlenbits", "type": "xlenbits" } }, "marchid": { "register": { "source": "register marchid : xlenbits", "type": "xlenbits" } }, "mcause": { "register": { "source": "register mcause : Mcause", "type": "Mcause" } }, "mcounteren": { "register": { "source": "register mcounteren : Counteren", "type": "Counteren" } }, "mcountinhibit": { "register": { "source": "register mcountinhibit : Counterin", "type": "Counterin" } }, "mcycle": { "register": { "source": "register mcycle : bits(64)", "type": "bits(64)" } }, "medeleg": { "register": { "source": "register medeleg : Medeleg", "type": "Medeleg" } }, "menvcfg": { "register": { "source": "register menvcfg : MEnvcfg", "type": "MEnvcfg" } }, "mepc": { "register": { "source": "register mepc : xlenbits", "type": "xlenbits" } }, "mhartid": { "register": { "source": "register mhartid : xlenbits", "type": "xlenbits" } }, "mideleg": { "register": { "source": "register mideleg : Minterrupts", "type": "Minterrupts" } }, "mie": { "register": { "source": "register mie : Minterrupts", "type": "Minterrupts" } }, "mimpid": { "register": { "source": "register mimpid : xlenbits", "type": "xlenbits" } }, "minstret": { "register": { "source": "register minstret : bits(64)", "type": "bits(64)" } }, "minstret_increment": { "register": { "source": "register minstret_increment : bool", "type": "bool" } }, "mip": { "register": { "source": "register mip : Minterrupts", "type": "Minterrupts" } }, "misa": { "register": { "source": "register misa : Misa", "type": "Misa" } }, "mscratch": { "register": { "source": "register mscratch : xlenbits", "type": "xlenbits" } }, "mstatus": { "register": { "source": "register mstatus : Mstatus", "type": "Mstatus" } }, "mstatush": { "register": { "source": "register mstatush : Mstatush", "type": "Mstatush" } }, "mtime": { "register": { "source": "register mtime : bits(64)", "type": "bits(64)" } }, "mtimecmp": { "register": { "source": "register mtimecmp : bits(64)", "type": "bits(64)" } }, "mtval": { "register": { "source": "register mtval : xlenbits", "type": "xlenbits" } }, "mtvec": { "register": { "source": "register mtvec : Mtvec", "type": "Mtvec" } }, "mvendorid": { "register": { "source": "register mvendorid : bits(32)", "type": "bits(32)" } }, "nextPC": { "register": { "source": "register nextPC : xlenbits", "type": "xlenbits" } }, "pmpaddr_n": { "register": { "source": "register pmpaddr_n : vector(64, dec, xlenbits)", "type": "vector(64, dec, xlenbits)" } }, "pmpcfg_n": { "register": { "source": "register pmpcfg_n : vector(64, dec, Pmpcfg_ent)", "type": "vector(64, dec, Pmpcfg_ent)" } }, "satp": { "register": { "source": "register satp : xlenbits", "type": "xlenbits" } }, "scause": { "register": { "source": "register scause : Mcause", "type": "Mcause" } }, "scounteren": { "register": { "source": "register scounteren : Counteren", "type": "Counteren" } }, "sedeleg": { "register": { "source": "register sedeleg : Sedeleg", "type": "Sedeleg" } }, "senvcfg": { "register": { "source": "register senvcfg : SEnvcfg", "type": "SEnvcfg" } }, "sepc": { "register": { "source": "register sepc : xlenbits", "type": "xlenbits" } }, "sideleg": { "register": { "source": "register sideleg : Sinterrupts", "type": "Sinterrupts" } }, "sscratch": { "register": { "source": "register sscratch : xlenbits", "type": "xlenbits" } }, "stval": { "register": { "source": "register stval : xlenbits", "type": "xlenbits" } }, "stvec": { "register": { "source": "register stvec : Mtvec", "type": "Mtvec" } }, "tlb": { "register": { "source": "register tlb : option(TLB_Entry) = None()", "type": "option(TLB_Entry)", "exp": "None()" }, "links": [ { "type": "function", "id": "None", "file": "model/riscv_vmem_tlb.sail", "loc": [ 1562, 1566 ] } ] }, "tselect": { "register": { "source": "register tselect : xlenbits", "type": "xlenbits" } }, "ucause": { "register": { "source": "register ucause : Mcause", "type": "Mcause" } }, "uepc": { "register": { "source": "register uepc : xlenbits", "type": "xlenbits" } }, "uscratch": { "register": { "source": "register uscratch : xlenbits", "type": "xlenbits" } }, "utval": { "register": { "source": "register utval : xlenbits", "type": "xlenbits" } }, "utvec": { "register": { "source": "register utvec : Mtvec", "type": "Mtvec" } }, "vcsr": { "register": { "source": "register vcsr : Vcsr", "type": "Vcsr" } }, "vl": { "register": { "source": "register vl : xlenbits", "type": "xlenbits" } }, "vlen": { "register": { "source": "register vlen : bits(4)", "type": "bits(4)" } }, "vlenb": { "register": { "source": "register vlenb : xlenbits", "type": "xlenbits" } }, "vr0": { "register": { "source": "register vr0 : vregtype", "type": "vregtype" } }, "vr1": { "register": { "source": "register vr1 : vregtype", "type": "vregtype" } }, "vr10": { "register": { "source": "register vr10 : vregtype", "type": "vregtype" } }, "vr11": { "register": { "source": "register vr11 : vregtype", "type": "vregtype" } }, "vr12": { "register": { "source": "register vr12 : vregtype", "type": "vregtype" } }, "vr13": { "register": { "source": "register vr13 : vregtype", "type": "vregtype" } }, "vr14": { "register": { "source": "register vr14 : vregtype", "type": "vregtype" } }, "vr15": { "register": { "source": "register vr15 : vregtype", "type": "vregtype" } }, "vr16": { "register": { "source": "register vr16 : vregtype", "type": "vregtype" } }, "vr17": { "register": { "source": "register vr17 : vregtype", "type": "vregtype" } }, "vr18": { "register": { "source": "register vr18 : vregtype", "type": "vregtype" } }, "vr19": { "register": { "source": "register vr19 : vregtype", "type": "vregtype" } }, "vr2": { "register": { "source": "register vr2 : vregtype", "type": "vregtype" } }, "vr20": { "register": { "source": "register vr20 : vregtype", "type": "vregtype" } }, "vr21": { "register": { "source": "register vr21 : vregtype", "type": "vregtype" } }, "vr22": { "register": { "source": "register vr22 : vregtype", "type": "vregtype" } }, "vr23": { "register": { "source": "register vr23 : vregtype", "type": "vregtype" } }, "vr24": { "register": { "source": "register vr24 : vregtype", "type": "vregtype" } }, "vr25": { "register": { "source": "register vr25 : vregtype", "type": "vregtype" } }, "vr26": { "register": { "source": "register vr26 : vregtype", "type": "vregtype" } }, "vr27": { "register": { "source": "register vr27 : vregtype", "type": "vregtype" } }, "vr28": { "register": { "source": "register vr28 : vregtype", "type": "vregtype" } }, "vr29": { "register": { "source": "register vr29 : vregtype", "type": "vregtype" } }, "vr3": { "register": { "source": "register vr3 : vregtype", "type": "vregtype" } }, "vr30": { "register": { "source": "register vr30 : vregtype", "type": "vregtype" } }, "vr31": { "register": { "source": "register vr31 : vregtype", "type": "vregtype" } }, "vr4": { "register": { "source": "register vr4 : vregtype", "type": "vregtype" } }, "vr5": { "register": { "source": "register vr5 : vregtype", "type": "vregtype" } }, "vr6": { "register": { "source": "register vr6 : vregtype", "type": "vregtype" } }, "vr7": { "register": { "source": "register vr7 : vregtype", "type": "vregtype" } }, "vr8": { "register": { "source": "register vr8 : vregtype", "type": "vregtype" } }, "vr9": { "register": { "source": "register vr9 : vregtype", "type": "vregtype" } }, "vstart": { "register": { "source": "register vstart : bits(16)", "type": "bits(16)" } }, "vtype": { "register": { "source": "register vtype : Vtype", "type": "Vtype" } }, "vxrm": { "register": { "source": "register vxrm : bits(2)", "type": "bits(2)" } }, "vxsat": { "register": { "source": "register vxsat : bits(1)", "type": "bits(1)" } }, "x1": { "register": { "source": "register x1 : regtype", "type": "regtype" } }, "x10": { "register": { "source": "register x10 : regtype", "type": "regtype" } }, "x11": { "register": { "source": "register x11 : regtype", "type": "regtype" } }, "x12": { "register": { "source": "register x12 : regtype", "type": "regtype" } }, "x13": { "register": { "source": "register x13 : regtype", "type": "regtype" } }, "x14": { "register": { "source": "register x14 : regtype", "type": "regtype" } }, "x15": { "register": { "source": "register x15 : regtype", "type": "regtype" } }, "x16": { "register": { "source": "register x16 : regtype", "type": "regtype" } }, "x17": { "register": { "source": "register x17 : regtype", "type": "regtype" } }, "x18": { "register": { "source": "register x18 : regtype", "type": "regtype" } }, "x19": { "register": { "source": "register x19 : regtype", "type": "regtype" } }, "x2": { "register": { "source": "register x2 : regtype", "type": "regtype" } }, "x20": { "register": { "source": "register x20 : regtype", "type": "regtype" } }, "x21": { "register": { "source": "register x21 : regtype", "type": "regtype" } }, "x22": { "register": { "source": "register x22 : regtype", "type": "regtype" } }, "x23": { "register": { "source": "register x23 : regtype", "type": "regtype" } }, "x24": { "register": { "source": "register x24 : regtype", "type": "regtype" } }, "x25": { "register": { "source": "register x25 : regtype", "type": "regtype" } }, "x26": { "register": { "source": "register x26 : regtype", "type": "regtype" } }, "x27": { "register": { "source": "register x27 : regtype", "type": "regtype" } }, "x28": { "register": { "source": "register x28 : regtype", "type": "regtype" } }, "x29": { "register": { "source": "register x29 : regtype", "type": "regtype" } }, "x3": { "register": { "source": "register x3 : regtype", "type": "regtype" } }, "x30": { "register": { "source": "register x30 : regtype", "type": "regtype" } }, "x31": { "register": { "source": "register x31 : regtype", "type": "regtype" } }, "x4": { "register": { "source": "register x4 : regtype", "type": "regtype" } }, "x5": { "register": { "source": "register x5 : regtype", "type": "regtype" } }, "x6": { "register": { "source": "register x6 : regtype", "type": "regtype" } }, "x7": { "register": { "source": "register x7 : regtype", "type": "regtype" } }, "x8": { "register": { "source": "register x8 : regtype", "type": "regtype" } }, "x9": { "register": { "source": "register x9 : regtype", "type": "regtype" } } }, "lets": { "CIA_fp": { "let": { "source": "CIA_fp = RFull(\"CIA\")", "exp": "RFull(\"CIA\")" }, "links": [ { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 1075, 1080 ] } ] }, "Data": { "let": { "source": "Data : ext_access_type = ()", "exp": "()" } }, "GPRstrs": { "let": { "source": "GPRstrs : vector(32, dec, string) = [ \"x31\", \"x30\", \"x29\", \"x28\", \"x27\", \"x26\", \"x25\", \"x24\", \"x23\", \"x22\", \"x21\",\n \"x20\", \"x19\", \"x18\", \"x17\", \"x16\", \"x15\", \"x14\", \"x13\", \"x12\", \"x11\",\n \"x10\", \"x9\", \"x8\", \"x7\", \"x6\", \"x5\", \"x4\", \"x3\", \"x2\", \"x1\", \"x0\"\n ]", "exp": "[ \"x31\", \"x30\", \"x29\", \"x28\", \"x27\", \"x26\", \"x25\", \"x24\", \"x23\", \"x22\", \"x21\",\n \"x20\", \"x19\", \"x18\", \"x17\", \"x16\", \"x15\", \"x14\", \"x13\", \"x12\", \"x11\",\n \"x10\", \"x9\", \"x8\", \"x7\", \"x6\", \"x5\", \"x4\", \"x3\", \"x2\", \"x1\", \"x0\"\n ]" } }, "MSIP_BASE": { "let": { "source": "MSIP_BASE : xlenbits = zero_extend(0x00000)", "exp": "zero_extend(0x00000)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 6961, 6972 ] } ] }, "MTIMECMP_BASE": { "let": { "source": "MTIMECMP_BASE : xlenbits = zero_extend(0x04000)", "exp": "zero_extend(0x04000)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 7016, 7027 ] } ] }, "MTIMECMP_BASE_HI": { "let": { "source": "MTIMECMP_BASE_HI : xlenbits = zero_extend(0x04004)", "exp": "zero_extend(0x04004)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 7071, 7082 ] } ] }, "MTIME_BASE": { "let": { "source": "MTIME_BASE : xlenbits = zero_extend(0x0bff8)", "exp": "zero_extend(0x0bff8)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 7126, 7137 ] } ] }, "MTIME_BASE_HI": { "let": { "source": "MTIME_BASE_HI : xlenbits = zero_extend(0x0bffc)", "exp": "zero_extend(0x0bffc)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_platform.sail", "loc": [ 7181, 7192 ] } ] }, "NIA_fp": { "let": { "source": "NIA_fp = RFull(\"NIA\")", "exp": "RFull(\"NIA\")" }, "links": [ { "type": "function", "id": "RFull", "file": "model/riscv_analysis.sail", "loc": [ 1101, 1106 ] } ] }, "aes_sbox_fwd_table": { "let": { "source": "aes_sbox_fwd_table : vector(256, bits(8)) = [\n0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe,\n0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4,\n0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7,\n0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3,\n0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09,\n0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3,\n0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe,\n0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,\n0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92,\n0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c,\n0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19,\n0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14,\n0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2,\n0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5,\n0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25,\n0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,\n0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86,\n0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e,\n0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42,\n0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16\n]", "exp": "[\n0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe,\n0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4,\n0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7,\n0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3,\n0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09,\n0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3,\n0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe,\n0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,\n0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92,\n0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c,\n0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19,\n0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14,\n0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2,\n0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5,\n0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25,\n0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,\n0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86,\n0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e,\n0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42,\n0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16\n]" } }, "aes_sbox_inv_table": { "let": { "source": "aes_sbox_inv_table : vector(256, bits(8)) = [\n0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81,\n0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e,\n0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23,\n0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66,\n0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72,\n0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65,\n0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46,\n0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a,\n0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca,\n0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91,\n0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6,\n0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8,\n0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f,\n0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2,\n0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8,\n0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,\n0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93,\n0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb,\n0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6,\n0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d\n]", "exp": "[\n0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81,\n0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e,\n0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23,\n0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66,\n0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72,\n0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65,\n0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46,\n0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a,\n0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca,\n0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91,\n0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6,\n0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8,\n0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f,\n0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2,\n0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8,\n0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,\n0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93,\n0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb,\n0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6,\n0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d\n]" } }, "default_meta": { "let": { "source": "default_meta : mem_meta = ()", "exp": "()" } }, "default_write_acc": { "let": { "source": "default_write_acc : ext_access_type = Data", "exp": "Data" } }, "init_ext_ptw": { "let": { "source": "init_ext_ptw : ext_ptw = ()", "exp": "()" } }, "pagesize_bits": { "let": { "source": "pagesize_bits = sizeof(PAGESIZE_BITS)", "exp": "sizeof(PAGESIZE_BITS)" } }, "ra": { "let": { "source": "ra : regidx = 0b00001", "exp": "0b00001" } }, "sm4_sbox_table": { "let": { "source": "sm4_sbox_table : vector(256, bits(8)) = [\n0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28,\n0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44,\n0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98,\n0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, 0xE4, 0xB3, 0x1C, 0xA9,\n0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, 0x47,\n0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85,\n0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F,\n0x4B, 0x70, 0x56, 0x9D, 0x35, 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2,\n0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F,\n0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF,\n0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15,\n0xA1, 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30,\n0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0,\n0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD,\n0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, 0x8D, 0x1B, 0xAF,\n0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,\n0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8,\n0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9,\n0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D,\n0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48\n]", "exp": "[\n0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28,\n0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44,\n0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98,\n0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, 0xE4, 0xB3, 0x1C, 0xA9,\n0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, 0x47,\n0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85,\n0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F,\n0x4B, 0x70, 0x56, 0x9D, 0x35, 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2,\n0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F,\n0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF,\n0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15,\n0xA1, 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30,\n0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0,\n0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD,\n0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, 0x8D, 0x1B, 0xAF,\n0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8,\n0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8,\n0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9,\n0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D,\n0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48\n]" } }, "sp": { "let": { "source": "sp : regidx = 0b00010", "exp": "0b00010" } }, "sv32_params": { "let": { "source": "sv32_params : SV_Params = struct {\n // VA\n va_size_bits = 32,\n vpn_size_bits = 10,\n\n // PTE\n levels = 2,\n log_pte_size_bytes = 2, // 4 Bytes\n pte_msbs_lsb_index = 32,\n pte_msbs_size_bits = 0,\n pte_PPNs_lsb_index = 10,\n pte_PPNs_size_bits = 22,\n pte_PPN_j_size_bits = 10\n}", "exp": "struct {\n // VA\n va_size_bits = 32,\n vpn_size_bits = 10,\n\n // PTE\n levels = 2,\n log_pte_size_bytes = 2, // 4 Bytes\n pte_msbs_lsb_index = 32,\n pte_msbs_size_bits = 0,\n pte_PPNs_lsb_index = 10,\n pte_PPNs_size_bits = 22,\n pte_PPN_j_size_bits = 10\n}" } }, "sv39_params": { "let": { "source": "sv39_params : SV_Params = struct {\n // VA\n va_size_bits = 39,\n vpn_size_bits = 9,\n\n // PTE\n levels = 3,\n log_pte_size_bytes = 3, // 8 Bytes\n pte_msbs_lsb_index = 54,\n pte_msbs_size_bits = 10,\n pte_PPNs_lsb_index = 10,\n pte_PPNs_size_bits = 44,\n pte_PPN_j_size_bits = 9\n}", "exp": "struct {\n // VA\n va_size_bits = 39,\n vpn_size_bits = 9,\n\n // PTE\n levels = 3,\n log_pte_size_bytes = 3, // 8 Bytes\n pte_msbs_lsb_index = 54,\n pte_msbs_size_bits = 10,\n pte_PPNs_lsb_index = 10,\n pte_PPNs_size_bits = 44,\n pte_PPN_j_size_bits = 9\n}" } }, "sv48_params": { "let": { "source": "sv48_params : SV_Params = struct {\n // VA\n va_size_bits = 48,\n vpn_size_bits = 9,\n\n // PTE\n levels = 4,\n log_pte_size_bytes = 3, // 8 Bytes\n pte_msbs_lsb_index = 54,\n pte_msbs_size_bits = 10,\n pte_PPNs_lsb_index = 10,\n pte_PPNs_size_bits = 44,\n pte_PPN_j_size_bits = 9\n}", "exp": "struct {\n // VA\n va_size_bits = 48,\n vpn_size_bits = 9,\n\n // PTE\n levels = 4,\n log_pte_size_bytes = 3, // 8 Bytes\n pte_msbs_lsb_index = 54,\n pte_msbs_size_bits = 10,\n pte_PPNs_lsb_index = 10,\n pte_PPNs_size_bits = 44,\n pte_PPN_j_size_bits = 9\n}" } }, "xlen_max_signed": { "let": { "source": "xlen_max_signed = 2 ^ (sizeof(xlen) - 1) - 1", "exp": "2 ^ (sizeof(xlen) - 1) - 1" }, "links": [ { "type": "function", "id": "pow2", "file": "model/riscv_types.sail", "loc": [ 928, 931 ] } ] }, "xlen_max_unsigned": { "let": { "source": "xlen_max_unsigned = 2 ^ sizeof(xlen) - 1", "exp": "2 ^ sizeof(xlen) - 1" }, "links": [ { "type": "function", "id": "pow2", "file": "model/riscv_types.sail", "loc": [ 885, 888 ] } ] }, "xlen_min_signed": { "let": { "source": "xlen_min_signed = 0 - 2 ^ (sizeof(xlen) - 1)", "exp": "0 - 2 ^ (sizeof(xlen) - 1)" }, "links": [ { "type": "function", "id": "pow2", "file": "model/riscv_types.sail", "loc": [ 981, 984 ] } ] }, "xlen_val": { "let": { "source": "xlen_val = sizeof(xlen)", "exp": "sizeof(xlen)" } }, "zero_freg": { "let": { "source": "zero_freg : fregtype = zero_extend(0x0)", "exp": "zero_extend(0x0)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_freg_type.sail", "loc": [ 823, 834 ] } ] }, "zero_reg": { "let": { "source": "zero_reg : regtype = zero_extend(0x0)", "exp": "zero_extend(0x0)" }, "links": [ { "type": "function", "id": "zero_extend", "file": "model/riscv_reg_type.sail", "loc": [ 751, 762 ] } ] }, "zreg": { "let": { "source": "zreg : regidx = 0b00000", "exp": "0b00000" } } }, "anchors": {}, "spans": {} }