\chapter{RV32E Base Integer Instruction Set, Version 1.9}
\label{rv32e}

This chapter describes the RV32E base integer instruction set, which
is a reduced version of RV32I designed for embedded systems.  The main
change is to reduce the number of integer registers to 16, and to
remove the counters that are mandatory in RV32I.  This chapter only
outlines the differences between RV32E and RV32I, and so should be
read after Chapter~\ref{rv32}.

\begin{commentary}
RV32E was designed to provide an even smaller base core for embedded
microcontrollers.  Although we had mentioned this possibility in
version 2.0 of this document, we initially resisted defining this
subset. However, given the demand for the smallest possible 32-bit
microcontroller, and in the interests of preempting fragmentation in
this space, we have now defined RV32E as a fourth standard base ISA in
addition to RV32I, RV64I, and RV128I.  The E variant is only
standardized for the 32-bit address space width.
\end{commentary}

\section{RV32E Programmers' Model}

RV32E reduces the integer register count to 16 general-purpose
registers, ({\tt x0}--{\tt x15}), where {\tt x0} is a dedicated zero
register.

\begin{commentary}
We have found that in the small RV32I core designs, the upper 16
registers consume around one quarter of the total area of the core
excluding memories, thus their removal saves around 25\% core area
with a corresponding core power reduction.
\end{commentary}

\begin{commentary}
This change requires a different calling convention and ABI.  In
particular, RV32E is only used with a soft-float calling convention.
Systems with hardware floating-point must use an I base.
\end{commentary}

\section{RV32E Instruction Set}

RV32E uses the same instruction set encoding as RV32I, except that use
of register specifiers {\tt x16}--{\tt x31} in an instruction will
result in an illegal instruction exception being raised.

\begin{commentary}
Any future standard extensions will not make use of the instruction
bits freed up by the reduced register-specifier fields and so these
are available for non-standard extensions.
\end{commentary}

A further simplification is that the counter instructions ({\tt
  rdcycle[h]},{\tt rdtime[h]}, {\tt rdinstret[h]}) are no longer
mandatory.

\begin{commentary}
The mandatory counters require additional registers and logic, and can
be replaced with more application-specific facilities.
\end{commentary}

\section{RV32E Extensions}

RV32E can be extended with the M, A, and C user-level standard extensions.

\begin{commentary}
We do not intend to support hardware floating-point with the RV32E
subset.  The savings from reduced register count become negligible in
the context of a hardware floating-point unit, and we wish to reduce
the proliferation of ABIs.
\end{commentary}

The privileged architecture of an RV32E system can include user mode
as well as machine mode, and the Mbare, Mbb, and Mbbid memory
management schemes described in Volume II.

\begin{commentary}
We do not intend to support full Unix-style operating systems with the
RV32E subset.  The savings from reduced register count become
negligible in the context of an OS-capable core, and we wish to avoid
OS fragmentation.
\end{commentary}