[[rv32-64g]]
== RV32/64G Instruction Set Listings

One goal of the RISC-V project is that it be used as a stable software
development target. For this purpose, we define a combination of a base
ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,
Zifencei) as a ``general-purpose`` ISA, and we use the abbreviation G
for the IMAFDZicsr_Zifencei combination of instruction-set extensions.
This chapter presents opcode maps and instruction-set listings for RV32G
and RV64G.

// note: ≥ is unicode for >=
[[opcodemap]]
.RISC-V base opcode map, inst[1:0]=11
[cols=  ">.^4m,  ^.^4m,    ^.^4m,      ^.^4m,    ^.^4m,  ^.^4m,      ^.^4m,           ^.^6m, ^.^4m"]
|===
|inst[4:2] .2+|000 .2+|001   .2+|010     .2+|011   .2+|100 .2+|101     .2+|110          .2+|111 (>32b)
|inst[6:5]
|00           |LOAD   |LOAD-FP  |_custom-0_ |MISC-MEM |OP-IMM |AUIPC      |OP-IMM-32       |48b
|01           |STORE  |STORE-FP |_custom-1_ |AMO      |OP     |LUI        |OP-32           |64b
|10           |MADD   |MSUB     |NMSUB      |NMADD    |OP-FP  |_reserved_ |_custom-2/rv128_|48b
|11           |BRANCH |JALR     |_reserved_ |JAL      |SYSTEM |_reserved_ |_custom-3/rv128_|≥80b
|===

<<opcodemap>> shows a map of the major opcodes for
RVG. Major opcodes with 3 or more lower bits set are reserved for
instruction lengths greater than 32 bits. Opcodes marked as _reserved_
should be avoided for custom instruction-set extensions as they might be
used by future standard extensions. Major opcodes marked as _custom-0_
and _custom-1_ will be avoided by future standard extensions and are
recommended for use by custom instruction-set extensions within the base
32-bit instruction format. The opcodes marked _custom-2/rv128_ and
_custom-3/rv128_ are reserved for future use by RV128, but will
otherwise be avoided for standard extensions and so can also be used for
custom instruction-set extensions in RV32 and RV64.

We believe RV32G and RV64G provide simple but complete instruction sets
for a broad range of general-purpose computing. The optional compressed
instruction set described in <<compressed>> can
be added (forming RV32GC and RV64GC) to improve performance, code size,
and energy efficiency, though with some additional hardware complexity.

As we move beyond IMAFDC into further instruction-set extensions, the
added instructions tend to be more domain-specific and only provide
benefits to a restricted class of applications, e.g., for multimedia or
security. Unlike most commercial ISAs, the RISC-V ISA design clearly
separates the base ISA and broadly applicable standard extensions from
these more specialized additions. <<extensions>>
has a more extensive discussion of ways to add extensions to the RISC-V
ISA.

[cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"]
|===
    |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |   0|
 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
 6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
 4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
 4+^|imm[12\|10:5]  2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:1\|11] 2+^|opcode  <|B-type
10+^|imm[31:12]                                    2+^|rd           2+^|opcode  <|U-type
10+^|imm[20\|10:1\|11\|19:12]                      2+^|rd           2+^|opcode  <|J-type
15+^|
15+^|*RV32I Base Instruction Set*
10+^|imm[31:12]                                    2+^|rd           2+^|0110111 <|LUI
10+^|imm[31:12]                                    2+^|rd           2+^|0010111 <|AUIPC
10+^|imm[20\|10:1\|11\|19:12]                      2+^|rd           2+^|1101111 <|JAL
 6+^|imm[11:0]                2+^|rs1   2+^|000    2+^|rd           2+^|1100111 <|JALR
 4+^|imm[12\|10:5]  2+^|rs2   2+^|rs1   2+^|000    2+^|imm[4:1\|11] 2+^|1100011 <|BEQ
 4+^|imm[12\|10:5]  2+^|rs2   2+^|rs1   2+^|001    2+^|imm[4:1\|11] 2+^|1100011 <|BNE
 4+^|imm[12\|10:5]  2+^|rs2   2+^|rs1   2+^|100    2+^|imm[4:1\|11] 2+^|1100011 <|BLT
 4+^|imm[12\|10:5]  2+^|rs2   2+^|rs1   2+^|101    2+^|imm[4:1\|11] 2+^|1100011 <|BGE
 4+^|imm[12\|10:5]  2+^|rs2   2+^|rs1   2+^|110    2+^|imm[4:1\|11] 2+^|1100011 <|BLTU
 4+^|imm[12\|10:5]  2+^|rs2   2+^|rs1   2+^|111    2+^|imm[4:1\|11] 2+^|1100011 <|BGEU
 6+^|imm[11:0]                2+^|rs1   2+^|000    2+^|rd           2+^|0000011 <|LB
 6+^|imm[11:0]                2+^|rs1   2+^|001    2+^|rd           2+^|0000011 <|LH
 6+^|imm[11:0]                2+^|rs1   2+^|010    2+^|rd           2+^|0000011 <|LW
 6+^|imm[11:0]                2+^|rs1   2+^|100    2+^|rd           2+^|0000011 <|LBU
 6+^|imm[11:0]                2+^|rs1   2+^|101    2+^|rd           2+^|0000011 <|LHU
 4+^|imm[11:5]      2+^|rs2   2+^|rs1   2+^|000    2+^|imm[4:0]     2+^|0100011 <|SB
 4+^|imm[11:5]      2+^|rs2   2+^|rs1   2+^|001    2+^|imm[4:0]     2+^|0100011 <|SH
 4+^|imm[11:5]      2+^|rs2   2+^|rs1   2+^|010    2+^|imm[4:0]     2+^|0100011 <|SW
 6+^|imm[11:0]                2+^|rs1   2+^|000    2+^|rd           2+^|0010011 <|ADDI
 6+^|imm[11:0]                2+^|rs1   2+^|010    2+^|rd           2+^|0010011 <|SLTI
 6+^|imm[11:0]                2+^|rs1   2+^|011    2+^|rd           2+^|0010011 <|SLTIU
 6+^|imm[11:0]                2+^|rs1   2+^|100    2+^|rd           2+^|0010011 <|XORI
 6+^|imm[11:0]                2+^|rs1   2+^|110    2+^|rd           2+^|0010011 <|ORI
 6+^|imm[11:0]                2+^|rs1   2+^|111    2+^|rd           2+^|0010011 <|ANDI
 4+^|0000000        2+^|shamt 2+^|rs1   2+^|001    2+^|rd           2+^|0010011 <|SLLI
 4+^|0000000        2+^|shamt 2+^|rs1   2+^|101    2+^|rd           2+^|0010011 <|SRLI
 4+^|0100000        2+^|shamt 2+^|rs1   2+^|101    2+^|rd           2+^|0010011 <|SRAI
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|000    2+^|rd           2+^|0110011 <|ADD
 4+^|0100000        2+^|rs2   2+^|rs1   2+^|000    2+^|rd           2+^|0110011 <|SUB
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|001    2+^|rd           2+^|0110011 <|SLL
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|010    2+^|rd           2+^|0110011 <|SLT
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|011    2+^|rd           2+^|0110011 <|SLTU
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|100    2+^|rd           2+^|0110011 <|XOR
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|101    2+^|rd           2+^|0110011 <|SRL
 4+^|0100000        2+^|rs2   2+^|rs1   2+^|101    2+^|rd           2+^|0110011 <|SRA
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|110    2+^|rd           2+^|0110011 <|OR
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|111    2+^|rd           2+^|0110011 <|AND
 3+^|fm   2+^|pred  1+^|succ  2+^|rs1   2+^|000    2+^|rd           2+^|0001111 <|FENCE
 3+^|1000 2+^|0011  1+^|0011  2+^|00000 2+^|000    2+^|00000        2+^|0001111 <|FENCE.TSO
 3+^|0000 2+^|0001  1+^|0000  2+^|00000 2+^|000    2+^|00000        2+^|0001111 <|PAUSE
 6+^|000000000000             2+^|00000 2+^|000    2+^|00000        2+^|1110011 <|ECALL
 6+^|000000000001             2+^|00000 2+^|000    2+^|00000        2+^|1110011 <|EBREAK
15+^|
    |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
 6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
 4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
15+^|
15+^|*RV64I Base Instruction Set (in addition to RV32I)*
 6+^|imm[11:0]                2+^|rs1   2+^|110    2+^|rd           2+^|0000011 <|LWU
 6+^|imm[11:0]                2+^|rs1   2+^|011    2+^|rd           2+^|0000011 <|LD
 4+^|imm[11:5]      2+^|rs2   2+^|rs1   2+^|011    2+^|imm[4:0]     2+^|0100011 <|SD
 3+^|000000         3+^|shamt 2+^|rs1   2+^|001    2+^|rd           2+^|0010011 <|SLLI
 3+^|000000         3+^|shamt 2+^|rs1   2+^|101    2+^|rd           2+^|0010011 <|SRLI
 3+^|010000         3+^|shamt 2+^|rs1   2+^|101    2+^|rd           2+^|0010011 <|SRAI
 6+^|imm[11:0]                2+^|rs1   2+^|000    2+^|rd           2+^|0011011 <|ADDIW
 4+^|0000000        2+^|shamt 2+^|rs1   2+^|001    2+^|rd           2+^|0011011 <|SLLIW
 4+^|0000000        2+^|shamt 2+^|rs1   2+^|101    2+^|rd           2+^|0011011 <|SRLIW
 4+^|0100000        2+^|shamt 2+^|rs1   2+^|101    2+^|rd           2+^|0011011 <|SRAIW
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|000    2+^|rd           2+^|0111011 <|ADDW
 4+^|0100000        2+^|rs2   2+^|rs1   2+^|000    2+^|rd           2+^|0111011 <|SUBW
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|001    2+^|rd           2+^|0111011 <|SLLW
 4+^|0000000        2+^|rs2   2+^|rs1   2+^|101    2+^|rd           2+^|0111011 <|SRLW
 4+^|0100000        2+^|rs2   2+^|rs1   2+^|101    2+^|rd           2+^|0111011 <|SRAW
15+^|
15+^|*RV32/RV64 _Zifencei_ Standard Extension*
 6+^|imm[11:0]                2+^|rs1   2+^|001    2+^|rd           2+^|0001111 <|FENCE.I
15+^|
15+^|*RV32/RV64 _Zicsr_ Standard Extension*
 6+^|csr                      2+^|rs1   2+^|001    2+^|rd           2+^|1110011 <|CSRRW
 6+^|csr                      2+^|rs1   2+^|010    2+^|rd           2+^|1110011 <|CSRRS
 6+^|csr                      2+^|rs1   2+^|011    2+^|rd           2+^|1110011 <|CSRRC
 6+^|csr                      2+^|uimm  2+^|101    2+^|rd           2+^|1110011 <|CSRRWI
 6+^|csr                      2+^|uimm  2+^|110    2+^|rd           2+^|1110011 <|CSRRSI
 6+^|csr                      2+^|uimm  2+^|111    2+^|rd           2+^|1110011 <|CSRRCI
15+^|
15+^|*RV32M Standard Extension*
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|000    2+^|rd           2+^|0110011 <|MUL
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|001    2+^|rd           2+^|0110011 <|MULH
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|010    2+^|rd           2+^|0110011 <|MULHSU
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|011    2+^|rd           2+^|0110011 <|MULHU
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|100    2+^|rd           2+^|0110011 <|DIV
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|101    2+^|rd           2+^|0110011 <|DIVU
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|110    2+^|rd           2+^|0110011 <|REM
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|111    2+^|rd           2+^|0110011 <|REMU
15+^|
15+^|*RV64M Standard Extension (in addition to RV32M)*
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|000    2+^|rd           2+^|0111011 <|MULW
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|100    2+^|rd           2+^|0111011 <|DIVW
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|101    2+^|rd           2+^|0111011 <|DIVUW
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|110    2+^|rd           2+^|0111011 <|REMW
 4+^|0000001        2+^|rs2   2+^|rs1   2+^|111    2+^|rd           2+^|0111011 <|REMUW
15+^|
    |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
15+^|
15+^|*RV32A Standard Extension*
 2+^|00010 ^|aq ^|rl 2+^|00000 2+^|rs1  2+^|010    2+^|rd           2+^|0101111 <|LR.W
 2+^|00011 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|SC.W
 2+^|00001 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOSWAP.W
 2+^|00000 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOADD.W
 2+^|00100 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOXOR.W
 2+^|01100 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOAND.W
 2+^|01000 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOOR.W
 2+^|10000 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOMIN.W
 2+^|10100 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOMAX.W
 2+^|11000 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOMINU.W
 2+^|11100 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|010    2+^|rd           2+^|0101111 <|AMOMAXU.W
15+^|
15+^|*RV64A Standard Extension (in addition to RV32A)*
 2+^|00010 ^|aq ^|rl 2+^|00000 2+^|rs1  2+^|011    2+^|rd           2+^|0101111 <|LR.D
 2+^|00011 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|SC.D
 2+^|00001 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOSWAP.D
 2+^|00000 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOADD.D
 2+^|00100 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOXOR.D
 2+^|01100 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOAND.D
 2+^|01000 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOOR.D
 2+^|10000 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOMIN.D
 2+^|10100 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOMAX.D
 2+^|11000 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOMINU.D
 2+^|11100 ^|aq ^|rl 2+^|rs2  2+^|rs1   2+^|011    2+^|rd           2+^|0101111 <|AMOMAXU.D
15+^|
    |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
 2+^|rs3 2+^|funct2 2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R4-type
 6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
 4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
15+^|
15+^|*RV32F Standard Extension*
 6+^|imm[11:0]               2+^|rs1    2+^|010    2+^|rd           2+^|0000111 <|FLW
 4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|010    2+^|imm[4:0]     2+^|0100111 <|FSW
 2+^|rs3 2+^|00     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1000011 <|FMADD.S
 2+^|rs3 2+^|00     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1000111 <|FMSUB.S
 2+^|rs3 2+^|00     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1001011 <|FNMSUB.S
 2+^|rs3 2+^|00     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1001111 <|FNMADD.S
 4+^|0000000        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FADD.S
 4+^|0000100        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FSUB.S
 4+^|0001000        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FMUL.S
 4+^|0001100        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FDIV.S
 4+^|0101100        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FSQRT.S
 4+^|0010000        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FSGNJ.S
 4+^|0010000        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FSGNJN.S
 4+^|0010000        2+^|rs2  2+^|rs1    2+^|010    2+^|rd           2+^|1010011 <|FSGNJX.S
 4+^|0010100        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FMIN.S
 4+^|0010100        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FMAX.S
 4+^|1100000        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.W.S
 4+^|1100000        2+^|00001 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.WU.S
 4+^|1110000        2+^|00000 2+^|rs1   2+^|000    2+^|rd           2+^|1010011 <|FMV.X.W
 4+^|1010000        2+^|rs2  2+^|rs1    2+^|010    2+^|rd           2+^|1010011 <|FEQ.S
 4+^|1010000        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FLT.S
 4+^|1010000        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FLE.S
 4+^|1110000        2+^|00000 2+^|rs1   2+^|001    2+^|rd           2+^|1010011 <|FCLASS.S
 4+^|1101000        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.S.W
 4+^|1101000        2+^|00001 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.S.WU
 4+^|1111000        2+^|00000 2+^|rs1   2+^|000    2+^|rd           2+^|1010011 <|FMV.W.X
15+^|
15+^|*RV64F Standard Extension (in addition to RV32F)*
 4+^|1100000        2+^|00010 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.L.S
 4+^|1100000        2+^|00011 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.LU.S
 4+^|1101000        2+^|00010 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.S.L
 4+^|1101000        2+^|00011 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.S.LU
15+^|
    |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
 2+^|rs3 2+^|funct2 2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R4-type
 6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
 4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
15+^|
15+|*RV32D Standard Extension*
 6+^|imm[11:0]               2+^|rs1    2+^|011    2+^|rd           2+^|0000111 <|FLD
 4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|011    2+^|imm[4:0]     2+^|0100111 <|FSD
 2+^|rs3 2+^|01     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1000011 <|FMADD.D
 2+^|rs3 2+^|01     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1000111 <|FMSUB.D
 2+^|rs3 2+^|01     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1001011 <|FNMSUB.D
 2+^|rs3 2+^|01     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1001111 <|FNMADD.D
 4+^|0000001        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FADD.D
 4+^|0000101        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FSUB.D
 4+^|0001001        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FMUL.D
 4+^|0001101        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FDIV.D
 4+^|0101101        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FSQRT.D
 4+^|0010001        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FSGNJ.D
 4+^|0010001        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FSGNJN.D
 4+^|0010001        2+^|rs2  2+^|rs1    2+^|010    2+^|rd           2+^|1010011 <|FSGNJX.D
 4+^|0010101        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FMIN.D
 4+^|0010101        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FMAX.D
 4+^|0100000        2+^|00001 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.S.D
 4+^|0100001        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.D.S
 4+^|1010001        2+^|rs2  2+^|rs1    2+^|010    2+^|rd           2+^|1010011 <|FEQ.D
 4+^|1010001        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FLT.D
 4+^|1010001        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FLE.D
 4+^|1110001        2+^|00000 2+^|rs1   2+^|001    2+^|rd           2+^|1010011 <|FCLASS.D
 4+^|1100001        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.W.D
 4+^|1100001        2+^|00001 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.WU.D
 4+^|1101001        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.D.W
 4+^|1101001        2+^|00001 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.D.WU
15+^|
15+^|*RV64D Standard Extension (in addition to RV32D)*
 4+^|1100001        2+^|00010 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.L.D
 4+^|1100001        2+^|00011 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.LU.D
 4+^|1110001        2+^|00000 2+^|rs1   2+^|000    2+^|rd           2+^|1010011 <|FMV.X.D
 4+^|1101001        2+^|00010 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.D.L
 4+^|1101001        2+^|00011 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.D.LU
 4+^|1111001        2+^|00000 2+^|rs1   2+^|000    2+^|rd           2+^|1010011 <|FMV.D.X
15+^|
    |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
 2+^|rs3 2+^|funct2 2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R4-type
 6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
 4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
 6+^|imm[11:0]               2+^|rs1    2+^|100    2+^|rd           2+^|0000111 <|FLQ
15+^|
15+^|*RV32Q Standard Extension*
 4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|100    2+^|imm[4:0]     2+^|0100111 <|FSQ
 2+^|rs3 2+^|11     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1000011 <|FMADD.Q
 2+^|rs3 2+^|11     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1000111 <|FMSUB.Q
 2+^|rs3 2+^|11     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1001011 <|FNMSUB.Q
 2+^|rs3 2+^|11     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1001111 <|FNMADD.Q
 4+^|0000011        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FADD.Q
 4+^|0000111        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FSUB.Q
 4+^|0001011        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FMUL.Q
 4+^|0001111        2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1010011 <|FDIV.Q
 4+^|0101111        2+^|00000  2+^|rs1  2+^|rm     2+^|rd           2+^|1010011 <|FSQRT.Q
 4+^|0010011        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FSGNJ.Q
 4+^|0010011        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FSGNJN.Q
 4+^|0010011        2+^|rs2  2+^|rs1    2+^|010    2+^|rd           2+^|1010011 <|FSGNJX.Q
 4+^|0010111        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FMIN.Q
 4+^|0010111        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FMAX.Q
 4+^|0100000        2+^|00011 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.S.Q
 4+^|0100011        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.Q.S
 4+^|0100001        2+^|00011 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.D.Q
 4+^|0100011        2+^|00001 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.Q.D
 4+^|1010011        2+^|rs2  2+^|rs1    2+^|010    2+^|rd           2+^|1010011 <|FEQ.Q
 4+^|1010011        2+^|rs2  2+^|rs1    2+^|001    2+^|rd           2+^|1010011 <|FLT.Q
 4+^|1010011        2+^|rs2  2+^|rs1    2+^|000    2+^|rd           2+^|1010011 <|FLE.Q
 4+^|1110011        2+^|00000 2+^|rs1   2+^|001    2+^|rd           2+^|1010011 <|FCLASS.Q
 4+^|1100011        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.W.Q
 4+^|1100011        2+^|00001 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.WU.Q
 4+^|1101011        2+^|00000 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.Q.W
 4+^|1101011        2+^|00001 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.Q.WU
15+^|
15+^|*RV64Q Standard Extension (in addition to RV32Q)*
 4+^|1100011        2+^|00010 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.L.Q
 4+^|1100011        2+^|00011 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.LU.Q
 4+^|1101011        2+^|00010 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.Q.L
 4+^|1101011        2+^|00011 2+^|rs1   2+^|rm     2+^|rd           2+^|1010011 <|FCVT.Q.LU
|===

<<rvgcsrnames>> lists the CSRs that have currently been
allocated CSR addresses. The timers, counters, and floating-point CSRs
are the only CSRs defined in this specification.
[[rvgcsrnames]]
.RISC-V control and status register (CSR) address map.
[cols="1,1,1,4", frame=all, grid=cols]
|===
^|Number ^|Privilege  ^|Name      ^|Description
4+^|[underline]#Floating-Point Control and Status Registers#
^|`0x001` ^|Read/write |`fflags`   |Floating-Point Accrued Exceptions.
^|`0x002` ^|Read/write |`frm`      |Floating-Point Dynamic Rounding Mode.
^|`0x003` ^|Read/write |`fcsr`     |Floating-Point Control and Status Register (`frm` + `fflags`).
4+^|[underline]#Counters and Timers#
^|`0xC00` ^|Read-only  |`cycle`    |Cycle counter for RDCYCLE instruction.
^|`0xC01` ^|Read-only  |`time`     |Timer for RDTIME instruction.
^|`0xC02` ^|Read-only  |`instret`  |Instructions-retired counter for RDINSTRET instruction.
^|`0xC80` ^|Read-only  |`cycleh`   |Upper 32 bits of `cycle`, RV32I only.
^|`0xC81` ^|Read-only  |`timeh`    |Upper 32 bits of `time`, RV32I only.
^|`0xC82` ^|Read-only  |`instreth` |Upper 32 bits of `instret`, RV32I only.
|===