\chapter{Preface}

This document describes the RISC-V unprivileged architecture.  This
release \specrev\ will be used in ratifying the base and standard
extensions described below.

The RISC-V RVWMO memory model has been ratified at this time.  The ISA
modules marked {\bf Ratification} are scheduled for ratification with
this release of the specification.  The modules marked {\em Frozen}
are not expected to change before being put up for ratification.  The
modules marked {\em Draft} are expected to change before ratification.

The document contains the following versions of the RISC-V ISA
modules:

{
\begin{table}[hbt]
  \centering
  \begin{tabular}{|c|l|c|}
    \hline
    Base           & Version & Status\\
    \hline
    RVWMO          & 2.0 & Ratified   \\
    \bf RV32I      & \bf 2.1 & \bf Ratification \\
    \bf RV64I      & \bf 2.1 & \bf Ratification \\
    \em RV32E      & \em 1.9 & \em Draft \\
    \em RV128I     & \em 1.7 & \em Draft \\
    \hline
    Extension      & Version & Status \\
    \hline
    \bf Zifencei   & \bf 2.0 & \bf Ratification \\
    \bf Zicsr      & \bf 2.0 & \bf Ratification \\
    \bf M          & \bf 2.0 & \bf Ratification \\
    \em A          & \em 2.0 &  Frozen \\
    \bf F          & \bf 2.2 & \bf Ratification \\
    \bf D          & \bf 2.2 & \bf Ratification \\
    \bf Q          & \bf 2.2 & \bf Ratification \\
    \bf C          & \bf 2.0 & \bf Ratification \\
    \em Ztso       & \em 0.1 & \em Frozen \\
    \em Counters   & \em 2.0 & \em Draft \\
    \em L          & \em 0.0 & \em Draft \\
    \em B          & \em 0.0 & \em Draft \\
    \em J          & \em 0.0 & \em Draft \\
    \em T          & \em 0.0 & \em Draft \\
    \em P          & \em 0.2 & \em Draft \\
    \em V          & \em 0.7 & \em Draft \\
    \em N          & \em 1.1 & \em Draft \\
    \em Zam        & \em 0.1 & \em Draft \\
    \hline
  \end{tabular}
\end{table}
}

The changes in this version of the document include:
\vspace{-0.2in}
\begin{itemize}
\parskip 0pt
\itemsep 1pt
\item Removed the A extension from ratification.
\item Changed document version scheme to avoid confusion with versions
  of the ISA modules.
\item Incremented the version numbers of the base integer ISA to 2.1,
  reflecting the presence of the ratified RVWMO memory model and
  exclusion of FENCE.I, counters, and CSR instructions that were in
  previous base ISA.
\item Incremented the version numbers of the F and D extensions to 2.2,
  reflecting that version 2.1 changed the canonical NaN, and version
  2.2 defined the NaN-boxing scheme and changed the definition of the
  FMIN and FMAX instructions.
\item Changed name of document to refer to ``unprivileged''
  instructions as part of move to separate ISA specifications from
  platform profile mandates.
\item Added clearer and more precise definitions of execution
  environments, harts, traps, and memory accesses.
\item Defined instruction-set categories: {\em standard}, {\em
  reserved}, {\em custom}, {\em non-standard}, and {\em
  non-conforming}.
\item Removed text implying operation under alternate endianness, as
  alternate-endianness operation has not yet been defined for RISC-V.
\item Changed description of misaligned load and store behavior.  The
  specification now allows visible misaligned address traps in
  execution environment interfaces, rather than just mandating
  invisible handling of misaligned loads and stores in user mode.
  Also, now allows access exceptions to be reported for misaligned
  accesses (including atomics) that should not be emulated. 
\item Moved FENCE.I out of the mandatory base and into a separate extension,
  with Zifencei ISA name.  FENCE.I was removed from the Linux user ABI and is
  problematic in implementations with large incoherent instruction and
  data caches.  However, it remains the only standard
  instruction-fetch coherence mechanism.
\item Removed prohibitions on using RV32E with other extensions.
\item Removed platform-specific mandates that certain encodings
  produce illegal instruction exceptions in RV32E and RV64I chapters.
\item Counter/timer instructions are now not considered part of the
  mandatory base ISA, and so CSR instructions were moved into separate
  chapter and marked as version 2.0, with the unprivileged counters
  moved into another separate chapter.  The counters are not ready for
  ratification as there are outstanding issues, including counter
  inaccuracies.
\item A CSR-access ordering model has been added.
\item Explicitly defined the 16-bit half-precision floating-point
  format for floating-point instructions in the 2-bit {\em fmt field.}
\item Defined the signed-zero behavior of FMIN.{\em fmt} and FMAX.{\em fmt},
  and changed their behavior on signaling-NaN inputs to conform to the
  minimumNumber and maximumNumber operations in the proposed IEEE 754-201x
  specification.
\item The memory consistency model, RVWMO, has been defined.
\item The ``Zam'' extension, which permits misaligned AMOs and specifies their semantics, has been defined.
\item The ``Ztso'' extension, which enforces a stricter memory consistency model than RVWMO, has been defined.
\item Improvements to the description and commentary.
\item Defined the term IALIGN as shorthand to describe the instruction-address
  alignment constraint.
\item Removed text of P extension chapter as now superceded by active task
  group documents.
\item Removed text of V extension chapter as now superceded by separate vector
  extension draft document.
\end{itemize}

\section*{Preface to Document Version 2.2}

This is version 2.2 of the document describing the RISC-V
user-level architecture.  The document contains the following
versions of the RISC-V ISA modules:
\begin{table}[hbt]
  \centering
  \begin{tabular}{|c|l|c|}
    \hline
    Base     & \em Version & \em Draft Frozen? \\
    \hline
    RV32I    & 2.0 & Y \\
    RV32E    & 1.9 & N \\
    RV64I    & 2.0 & Y \\
    RV128I   & 1.7 & N \\
    \hline
    Extension & Version & Frozen? \\
    \hline
    M        & 2.0 & Y \\
    A        & 2.0 & Y \\
    F        & 2.0 & Y \\
    D        & 2.0 & Y \\
    Q        & 2.0 & Y \\
    L        & 0.0 & N \\
    C        & 2.0 & Y \\
    B        & 0.0 & N \\
    J        & 0.0 & N \\
    T        & 0.0 & N \\
    P        & 0.1 & N \\
    V        & 0.7 & N \\
    N        & 1.1 & N \\
    \hline
  \end{tabular}
\end{table}

To date, no parts of the standard have been officially ratified by the
RISC-V Foundation, but the components labeled ``frozen'' above are not
expected to change during the ratification process beyond resolving
ambiguities and holes in the specification.

The major changes in this version of the document include:
\begin{itemize}
\parskip 0pt
\itemsep 1pt
\item The previous version of this document was released under a
  Creative Commons Attribution 4.0 International License by the
  original authors, and this and future versions of this document will
  be released under the same license.
\item Rearranged chapters to put all extensions first in canonical order.
\item Improvements to the description and commentary.
\item Modified implicit hinting suggestion on JALR to support more efficient
  macro-op fusion of LUI/JALR and AUIPC/JALR pairs.
\item Clarification of constraints on load-reserved/store-conditional sequences.
\item A new table of control and status register (CSR) mappings.
\item Clarified purpose and behavior of high-order bits of {\tt fcsr}.
\item Corrected the description of the FNMADD.{\em fmt} and FNMSUB.{\em fmt}
      instructions, which had suggested the incorrect sign of a zero result.
\item Instructions FMV.S.X and FMV.X.S were renamed to FMV.W.X and
  FMV.X.W respectively to be more consistent with their
  semantics, which did not change.
  The old names will continue to be supported in the tools.
\item Specified behavior of narrower ($<$FLEN) floating-point values held in
  wider {\tt f} registers using NaN-boxing model.
\item Defined the exception behavior of FMA($\infty$, 0, qNaN).
\item Added note indicating that the P extension might be reworked
  into an integer packed-SIMD proposal for fixed-point operations
  using the integer registers.
\item A draft proposal of the V vector instruction-set extension.
\item An early draft proposal of the N user-level traps extension.
\item An expanded pseudoinstruction listing.
\item Removal of the calling convention chapter, which has been superseded by
      the RISC-V ELF psABI Specification~\cite{riscv-elf-psabi}.
\item The C extension has been frozen and renumbered version 2.0.
\end{itemize}

\section*{Preface to Document Version 2.1}

This is version 2.1 of the document describing the RISC-V user-level
architecture.  Note the frozen user-level ISA base and extensions
IMAFDQ version 2.0 have not changed from the previous version of this
document~\cite{riscvtr2}, but some specification holes have been fixed
and the documentation has been improved.  Some changes have been made
to the software conventions.
\begin{itemize}
\parskip 0pt
\itemsep 1pt
\item Numerous additions and improvements to the commentary sections.
\item Separate version numbers for each chapter.
\item Modification to long instruction encodings $>$64 bits to avoid
  moving the {\em rd} specifier in very long instruction formats.
\item CSR instructions are now described in the base integer format
  where the counter registers are introduced, as opposed to only being
  introduced later in the floating-point section (and the companion
  privileged architecture manual).
\item The SCALL and SBREAK instructions have been renamed to ECALL and
  EBREAK, respectively.  Their encoding and functionality are unchanged.
\item Clarification of floating-point NaN handling, and a new canonical NaN
  value.
\item Clarification of values returned by floating-point to integer
  conversions that overflow.
\item Clarification of LR/SC allowed successes and required failures,
  including use of compressed instructions in the sequence.
\item A new RV32E base ISA proposal for reduced integer register
  counts, supports MAC extensions.
\item A revised calling convention.
\item Relaxed stack alignment for soft-float calling convention, and
  description of the RV32E calling convention.
\item A revised proposal for the C compressed extension, version 1.9.
\end{itemize}

\section*{Preface to Version 2.0}

This is the second release of the user ISA specification, and we
intend the specification of the base user ISA plus general extensions
(i.e., IMAFD) to remain fixed for future development.  The following
changes have been made since Version 1.0~\cite{riscvtr} of this ISA
specification.

\vspace{-0.1in}
\begin{itemize}
\parskip 0pt
\itemsep 1pt
\item The ISA has been divided into an integer base with several
  standard extensions.
\item The instruction formats have been rearranged to make immediate
  encoding more efficient.
\item The base ISA has been defined to have a little-endian memory system, with
  big-endian or bi-endian as non-standard variants.
\item Load-Reserved/Store-Conditional (LR/SC) instructions have been added in
  the atomic instruction extension.
\item AMOs and LR/SC can support the release consistency model.
\item The FENCE instruction provides finer-grain memory and I/O
  orderings. 
\item An AMO for fetch-and-XOR (AMOXOR) has been added, and the
  encoding for AMOSWAP has been changed to make room.
\item The AUIPC instruction, which adds a 20-bit upper immediate to
  the PC, replaces the RDNPC instruction, which only read the current
  PC value.  This results in significant savings for position-independent
  code.
\item The JAL instruction has now moved to the U-Type format with an
  explicit destination register, and the J instruction has been
  dropped being replaced by JAL with {\em rd}={\tt x0}.  This removes
  the only instruction with an implicit destination register and
  removes the J-Type instruction format from the base ISA.  There is
  an accompanying reduction in JAL reach, but a significant reduction
  in base ISA complexity.
\item The static hints on the JALR instruction have been dropped. The
  hints are redundant with the {\em rd} and {\em rs1} register
  specifiers for code compliant with the standard calling convention.
\item The JALR instruction now clears the lowest bit of the calculated
  target address, to simplify hardware and to allow auxiliary information
  to be stored in function pointers.
\item The MFTX.S and MFTX.D instructions have been renamed to FMV.X.S and
FMV.X.D, respectively.  Similarly, MXTF.S and MXTF.D instructions have been
renamed to FMV.S.X and FMV.D.X, respectively.
\item The MFFSR and MTFSR instructions have been renamed to FRCSR and FSCSR,
respectively.  FRRM, FSRM, FRFLAGS, and FSFLAGS instructions have been added
to individually access the rounding mode and exception flags subfields of
the {\tt fcsr}.
\item The FMV.X.S and FMV.X.D instructions now source their operands
from {\em rs1}, instead of {\em rs2}.  This change simplifies datapath
design.
\item FCLASS.S and FCLASS.D floating-point classify instructions have been
added.
\item A simpler NaN generation and propagation scheme has been
  adopted.
\item For RV32I, the system performance counters have been extended to
  64-bits wide, with separate read access to the upper and lower 32 bits.
\item Canonical NOP and MV encodings have been defined.
\item Standard instruction-length encodings have been defined for 48-bit,
  64-bit, and $>$64-bit instructions.
\item Description of a 128-bit address space variant, RV128, has been added.
\item Major opcodes in the 32-bit base instruction format have been
  allocated for user-defined custom extensions.
\item A typographical error that suggested that stores source their
  data from {\em rd} has been corrected to refer to {\em rs2}.
\end{itemize}
\vspace{-0.1in}