[wavedrom, ,svg]
....
{reg: [
  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'],    type: 8},
  {bits: 5, name: 'rd',     attr: ['5','dest'],     type: 2},
  {bits: 3, name: 'rm',     attr: ['3','RM'],       type: 8},
  {bits: 5, name: 'rs1',    attr: ['5','src1'],     type: 4},
  {bits: 5, name: 'rs2',    attr: ['5','src2'],     type: 4},
  {bits: 2, name: 'fmt',    attr: ['2','H'],        type: 8},
  {bits: 5, name: 'rs3', attr: ['5','src3'], type: 4},
]}
....