//# 10 "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
//## 10.1 CSR Instructions

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'], type: 8},
  {bits: 5,  name: 'rd',     attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2},
  {bits: 3,  name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8},
  {bits: 5,  name: 'rs1',    attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'], type: 4},
  {bits: 12, name: 'csr',    attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], type: 4},
]}
....

//[wavedrom, ,]
//....
//{reg: [
//  {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'],     type: 8},
//  {bits: 5,  name: 'rd',     attr: ['3', 'dest','dest', 'dest' ],       type: 2},
//  {bits: 3,  name: 'funct3',  attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8},
//  {bits: 5,  name: 'rs1',    attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'],   type: 3},
//  {bits: 12, name: 'csr',    attr: ['12', 'source/dest','source/dest','source/dest'], type: 4},
//]}
//....
