//

[wavedrom, ,svg]
....
{reg: [
  {bits: 2, name: 'op', type: 3, attr: ['2', 'C2']},
  {bits: 5, name: 'shamt[4:0]',    type: 1, attr: ['5', 'shamt[4:0]']},
  {bits: 5, name: 'rd/rs1',     type: 5, attr: ['5', 'dest != 0']},
  {bits: 1, name: 'shamt[5]',    type: 5, attr: ['1', 'shamt[5]']},
  {bits: 3, name: 'funct3',    type: 5, attr: ['3', 'C.SLLI']},
]}
....

