From 830229b0259d55d3a98b6d2f5a9cd436df4c040c Mon Sep 17 00:00:00 2001 From: Paul Donahue Date: Wed, 1 May 2019 10:46:18 -0700 Subject: Introduce the term UNSPECIFIED. --- src/intro.tex | 19 +++++++++++++++++++ src/machine.tex | 2 +- src/rv32.tex | 2 ++ src/supervisor.tex | 4 ++-- 4 files changed, 24 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/intro.tex b/src/intro.tex index 2629f6e..303930b 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -711,3 +711,22 @@ defined solely to cause requested traps are documented here. Invisible traps are, by their nature, out of scope for this document. Instruction encodings that are not defined here and not defined by some other means may cause a fatal trap. + +\section{Unspecified Behavior} + +The architecture fully describes what implementations must do and any +constraints on what they may do. In cases where the architecture +intentionally does not constrain implementations, the term UNSPECIFIED +is explicitly used. + +The term UNSPECIFIED refers to a behavior or value that is +intentionally unconstrained. The definition of these behaviors or +values is open to extensions, platform standards, or implementations. +Extensions or platform standards may provide normative content to +further constrain cases that the base architecture defines as +UNSPECIFIED. + +Like the base architecture, extensions should fully describe allowable +behavior and values and use the term UNSPECIFIED for cases that are +intentionally unconstrained. These cases may be constrained or defined +by other extensions, platform standards, or implementations. diff --git a/src/machine.tex b/src/machine.tex index 18aeedf..8048692 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2336,7 +2336,7 @@ extensions and widest MXLEN, as described in Section~\ref{sec:misa}. The {\tt pc} is set to an implementation-defined reset vector. The {\tt mcause} register is set to a value indicating the cause of the reset. Writable PMP registers' A and L fields are set to 0. All -other hart state is unspecified. +other hart state is UNSPECIFIED. The {\tt mcause} values after reset have implementation-specific interpretation, but the value 0 should be returned on implementations diff --git a/src/rv32.tex b/src/rv32.tex index b6885cb..98a9d7a 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -162,6 +162,8 @@ and to simplify hardware design for systems with IALIGN=32, where these are the only places where misalignment can occur. \end{commentary} +The behavior when decoding a reserved instruction is UNSPECIFIED. + \vspace{-0.2in} \begin{figure}[h] \begin{center} diff --git a/src/supervisor.tex b/src/supervisor.tex index 503c8bd..fa11abb 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -852,9 +852,9 @@ Value & Name & Description \\ \label{tab:satp-mode} \end{table} -The number of supervisor physical address bits is implementation-defined; any +The number of supervisor physical address bits is UNSPECIFIED; any unimplemented address bits are hardwired to zero in the {\tt satp} register. -The number of ASID bits is also implementation-defined and may be zero. The +The number of ASID bits is also UNSPECIFIED and may be zero. The number of implemented ASID bits, termed {\mbox {\em ASIDLEN}}, may be determined by writing one to every bit position in the ASID field, then reading back the value in {\tt satp} to see which bit positions in the ASID -- cgit v1.1 From 436c637d506d4843ce7fd23d6430a3bb4907bed9 Mon Sep 17 00:00:00 2001 From: Paul Donahue Date: Fri, 3 May 2019 16:54:23 -0700 Subject: Added UNSPECIFIED --- src/intro.tex | 14 +++++++------- src/machine.tex | 2 +- src/preamble.tex | 1 + src/rv32.tex | 2 +- src/supervisor.tex | 4 ++-- 5 files changed, 12 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/intro.tex b/src/intro.tex index 303930b..c5f23e4 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -712,21 +712,21 @@ Invisible traps are, by their nature, out of scope for this document. Instruction encodings that are not defined here and not defined by some other means may cause a fatal trap. -\section{Unspecified Behavior} +\section{UNSPECIFIED Behaviors and Values} The architecture fully describes what implementations must do and any constraints on what they may do. In cases where the architecture -intentionally does not constrain implementations, the term UNSPECIFIED +intentionally does not constrain implementations, the term \unspecified\ is explicitly used. -The term UNSPECIFIED refers to a behavior or value that is +The term \unspecified\ refers to a behavior or value that is intentionally unconstrained. The definition of these behaviors or values is open to extensions, platform standards, or implementations. -Extensions or platform standards may provide normative content to -further constrain cases that the base architecture defines as -UNSPECIFIED. +Extensions, platform standards, or implementation documentation may +provide normative content to further constrain cases that the base +architecture defines as \unspecified. Like the base architecture, extensions should fully describe allowable -behavior and values and use the term UNSPECIFIED for cases that are +behavior and values and use the term \unspecified\ for cases that are intentionally unconstrained. These cases may be constrained or defined by other extensions, platform standards, or implementations. diff --git a/src/machine.tex b/src/machine.tex index 8048692..56298d1 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2336,7 +2336,7 @@ extensions and widest MXLEN, as described in Section~\ref{sec:misa}. The {\tt pc} is set to an implementation-defined reset vector. The {\tt mcause} register is set to a value indicating the cause of the reset. Writable PMP registers' A and L fields are set to 0. All -other hart state is UNSPECIFIED. +other hart state is \unspecified. The {\tt mcause} values after reset have implementation-specific interpretation, but the value 0 should be returned on implementations diff --git a/src/preamble.tex b/src/preamble.tex index cb66be4..e2bda0d 100644 --- a/src/preamble.tex +++ b/src/preamble.tex @@ -137,3 +137,4 @@ \newcommand{\wlrl}{\textbf{WLRL}} \newcommand{\warl}{\textbf{WARL}} +\newcommand{\unspecified}{\textsc{unspecified}} diff --git a/src/rv32.tex b/src/rv32.tex index 98a9d7a..feb6bed 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -162,7 +162,7 @@ and to simplify hardware design for systems with IALIGN=32, where these are the only places where misalignment can occur. \end{commentary} -The behavior when decoding a reserved instruction is UNSPECIFIED. +The behavior upon decoding a reserved instruction is \unspecified. \vspace{-0.2in} \begin{figure}[h] diff --git a/src/supervisor.tex b/src/supervisor.tex index fa11abb..e48c4ee 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -852,9 +852,9 @@ Value & Name & Description \\ \label{tab:satp-mode} \end{table} -The number of supervisor physical address bits is UNSPECIFIED; any +The number of supervisor physical address bits is \unspecified; any unimplemented address bits are hardwired to zero in the {\tt satp} register. -The number of ASID bits is also UNSPECIFIED and may be zero. The +The number of ASID bits is also \unspecified\ and may be zero. The number of implemented ASID bits, termed {\mbox {\em ASIDLEN}}, may be determined by writing one to every bit position in the ASID field, then reading back the value in {\tt satp} to see which bit positions in the ASID -- cgit v1.1