From 085aac67a7ffd3c0581eda69fd6418bef3bce79d Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Thu, 27 Jun 2024 11:40:21 -0500 Subject: Updated SDT and MDT clearing --- src/hypervisor.adoc | 4 ++++ src/machine.adoc | 16 +++++++++------- src/supervisor.adoc | 14 +++++++------- 3 files changed, 20 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 3a3a3a9..d8a77e0 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -2544,3 +2544,7 @@ privilege mode as previously determined, and sets `pc`=`sepc`. When executed in VS-mode (i.e., V=1), SRET sets the privilege mode according to <>, in `vsstatus` sets SPP=0, SIE=SPIE, and SPIE=1, and lastly sets `pc`=`vsepc`. + +If the Ssdbltrp extension is implemented, when `SRET` is executed in HS-mode, +if the new privilege mode is VU, the `SRET` instruction sets `vsstatus.SDT` +to 0. When executed in VS-mode, `vsstatus.SDT` is set to 0. diff --git a/src/machine.adoc b/src/machine.adoc index cd2159b..8358279 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -589,26 +589,28 @@ In the event of a _unexpected trap_, the handling is as follows: [NOTE] ==== The consequence of this specification is that on occurrence of double trap the -RNMI handler is not provided with information that a trap would report in the -`mtval` and the `mtval2` registers. This information, if needed, may be obtained +RNMI handler is not provided with information that a trap reports in the +`mtval` and the `mtval2` registers. This information, if needed, can be obtained by the RNMI handler by decoding the instruction at the address in `mnepc` and examining its source register contents. ==== * When the Smrnmi extension is not implemented, or if the Smrnmi extension is implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state - without updating any architectural state including the `pc`. This state + without updating any architectural state, including the `pc`. This state involves ceasing execution, disabling all interrupts (including NMIs), and asserting a `critical-error` signal to the platform. [NOTE] ==== -The actions performed by the platform on assertion of a `critical-error` signal -by a hart are platform specific. The range of possible actions include restarting -the affected hart or restarting the entire platform among others. +The actions performed by the platform when a hart asserts a `critical-error` signal +are platform-specific. The range of possible actions include restarting +the affected hart or restarting the entire platform, among others. ==== -An `MRET` instruction sets the `MDT` bit to 0. +The `MRET` and `SRET` instructions, when executed in M-mode, set the `MDT` bit +to 0. If the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set +to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0. [[xlen-control]] ===== Base ISA Control in `mstatus` Register diff --git a/src/supervisor.adoc b/src/supervisor.adoc index b212620..daecbc2 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -253,13 +253,13 @@ An `SRET` instruction sets the `SDT` bit to 0. [NOTE] ==== -A trap handler after saving the state needed for resuming from the trap, -including `scause`, `sepc`, and `stval` among others, should clear the `SDT` bit -when it is reentrant. +After a trap handler has saved the state, such as `scause`, `sepc`, +and `stval`, needed for resuming from the trap and is reentrant, it +should clear the `SDT` bit. -Resetting of the `SDT` by an `SRET` enables the trap handler to detect double -trap occuring during the tail phase, where it restores critical state to return -from a trap. +Resetting the `SDT` by an `SRET` enables the trap handler to detect a double +trap that may occur during the tail phase, where it restores critical state +to return from a trap. The consequence of this specification is that if a critical error condition was caused by a guest page-fault, then the GPA will not be available in `mtval2` @@ -270,7 +270,7 @@ instruction in this phase of trap handling is not common. However, not recording the GPA is considered benign because, if required, it can still be obtained -- albeit with added effort -- through the process of walking the page tables. -For a double trap originating in VS-mode, M-mode should redirect the exception +For a double trap that originates in VS-mode, M-mode should redirect the exception to HS-mode by copying the values of M-mode CSRs updated by the trap to HS-mode CSRs and should use an `MRET` to resume execution at the address in `stvec`. -- cgit v1.1