From 0b7756c337891ea2af90fc9a124917a3696f7a6a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 9 Nov 2017 16:28:38 -0800 Subject: Specify meaning of R/W/X bits in PTE --- src/supervisor.tex | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src') diff --git a/src/supervisor.tex b/src/supervisor.tex index d10cf0a..3bd0c8b 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1119,6 +1119,19 @@ X & W & R & Meaning \\ \label{pteperm} \end{table*} +Attempting to fetch an instruction from a page that does not have execute +permissions raises a fetch page-fault exception. Attempting to execute +a load or load-reserved instruction whose effective address lies within +a page without read permissions raises a load page-fault exception. +Attempting to execute a store, store-conditional (regardless of success), +or AMO instruction whose effective address lies within a page without +write permissions raises a store page-fault exception. +\begin{commentary} +AMOs never raise load page-fault exceptions. Since any unreadable page is +also unwritable, attempting to perform an AMO on an unreadable page always +raises a store page-fault exception. +\end{commentary} + The U bit indicates whether the page is accessible to user mode. U-mode software may only access the page when U=1. If the SUM bit in the {\tt sstatus} register is -- cgit v1.1 From af4a2da4bcf6e6aff62f6e615b4cecbcb395c71b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 9 Nov 2017 16:55:04 -0800 Subject: Specify meaning of R/W/X bits in PMP --- src/machine.tex | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/machine.tex b/src/machine.tex index 6055ee6..c8079c2 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2699,6 +2699,14 @@ described in the following sections. \label{pmpcfg} \end{figure} +Attempting to fetch an instruction from a PMP region that does not have execute +permissions raises a fetch access exception. Attempting to execute +a load or load-reserved instruction whose effective address lies within +a PMP region without read permissions raises a load access exception. +Attempting to execute a store, store-conditional (regardless of success), +or AMO instruction whose effective address lies within a PMP region without +write permissions raises a store access exception. + \subsubsection*{Address Matching} The A field in a PMP entry's configuration register encodes the -- cgit v1.1 From 059f64c941856f249d8a0647e23e150dbdb1f62c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 9 Nov 2017 16:55:13 -0800 Subject: State that writable-but-not-readable PMPs are reserved --- src/machine.tex | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/machine.tex b/src/machine.tex index c8079c2..fdff47f 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2668,7 +2668,8 @@ space, so the RV64 PMP address registers impose the same limit. Figure~\ref{pmpcfg} shows the layout of a PMP configuration register. The R, W, and X bits, when set, indicate that the PMP entry permits read, write, and instruction execution, respectively. When one of these bits is clear, the -corresponding access type is denied. The remaining two fields, A and L, are +corresponding access type is denied. The combination R=0 and W=1 is reserved +for future use. The remaining two fields, A and L, are described in the following sections. \begin{figure}[h!] -- cgit v1.1 From 32b74b7a02e492c48a910ba0d20bcc52155b0616 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 9 Nov 2017 17:20:29 -0800 Subject: Make MPP/SPP WARL fields --- src/machine.tex | 9 ++++++--- src/priv-preface.tex | 1 + 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/machine.tex b/src/machine.tex index fdff47f..e22c4f4 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -543,11 +543,14 @@ value {\em y}, {\em x}\,IE is set to {\em x}\,PIE; the privilege mode is changed to {\em y}; {\em x}\,PIE is set to 1; and {\em x}\,PP is set to U (or M if user-mode is not supported). -{\em x}\,PP fields are \wlrl\ fields that need only be able to store -supported privilege modes, including {\em x} and any implemented -privilege mode lower than {\em x}. +{\em x}\,PP fields are \warl\ fields that can hold only privilege mode {\em x} +and any implemented privilege mode lower than {\em x}. If privilege mode {\em +x} is not implemented, then {\em x}\,PP must be hardwired to 0. \begin{commentary} +M-mode software can determine whether a privilege mode is implemented +by writing that mode to MPP then reading it back. + If the machine provides only U and M modes, then only a single hardware storage bit is required to represent either 00 or 11 in MPP. \end{commentary} diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 5e04665..095e374 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -11,6 +11,7 @@ architecture proposal. Changes from version 1.10 include: \item Specified which interrupt sources are reserved for standard use. \item The virtual-memory system no longer permits supervisor mode to execute instructions from user pages, regardless of the SUM setting. +\item Made the {\tt mstatus}.MPP field \warl, rather than \wlrl. \end{itemize} \newpage -- cgit v1.1 From 9c5a2d47f029b1982410658c421b9866d251ca52 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 12 Nov 2017 01:00:59 -0800 Subject: Mark useless PMP NAPOT case as reserved --- src/machine.tex | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/machine.tex b/src/machine.tex index e22c4f4..eec2aee 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2755,6 +2755,7 @@ to encode the size of the range, as shown in Table~\ref{pmpcfg-napot}. \tt aa01...1111 & NAPOT & $2^{XLEN}$-byte NAPOT range \\ \tt a011...1111 & NAPOT & $2^{XLEN+1}$-byte NAPOT range \\ \tt 0111...1111 & NAPOT & $2^{XLEN+2}$-byte NAPOT range \\ + \tt 1111...1111 & NAPOT & {\em Reserved} \\ \hline \end{tabular} \end{center} -- cgit v1.1 From 1b74dd69a400a1e9244e9a9f48174d38ec1b3a7e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 12 Nov 2017 01:01:33 -0800 Subject: Clarify WLRL semantics --- src/priv-csrs.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index c027bc2..e13e96a 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -416,7 +416,7 @@ instruction exception if an instruction attempts to write a non-supported value to a CSR field. Hardware implementations can return arbitrary bit patterns on the read of a CSR field when the last write was of an illegal value, but the value returned should -deterministically depend on the previous written value. +deterministically depend on the illegal written value. \subsection*{Write Any Values, Reads Legal Values (WARL)} -- cgit v1.1 From 9f22e9a9d7b3e3d9649fb0a9d1d0b48821037222 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 27 Nov 2017 15:07:54 -0800 Subject: Add R-type format to priv-instr-table Closes #115 --- src/priv-instr-table.tex | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src') diff --git a/src/priv-instr-table.tex b/src/priv-instr-table.tex index 653a94a..4d33a4e 100644 --- a/src/priv-instr-table.tex +++ b/src/priv-instr-table.tex @@ -21,6 +21,16 @@ & +\multicolumn{4}{|c|}{funct7} & +\multicolumn{2}{c|}{rs2} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{funct3} & +\multicolumn{1}{c|}{rd} & +\multicolumn{1}{c|}{opcode} & R-type \\ +\cline{2-11} + + +& \multicolumn{6}{|c|}{imm[11:0]} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{funct3} & -- cgit v1.1