From 073d6371a4989c58330ba6c8c6ba3c508381e08e Mon Sep 17 00:00:00 2001
From: John Hauser <31252952+jhauser-us@users.noreply.github.com>
Date: Wed, 15 Sep 2021 15:24:46 -0700
Subject: mip.MSIP and mie.MSIE may be hardwired zeros (#738)

---
 src/machine.tex | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src')

diff --git a/src/machine.tex b/src/machine.tex
index ca8f7a1..5d0d60e 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1528,6 +1528,10 @@ to memory-mapped control registers, which are used by remote harts to
 provide machine-level interprocessor interrupts.
 A hart can write its
 own MSIP bit using the same memory-mapped control register.
+If a system has only one hart, or if a platform standard supports the
+delivery of machine-level interprocessor interrupts through external
+interrupts (MEI) instead, then {\tt mip}.MSIP and {\tt mie}.MSIE may
+both be hardwired to zeros.
 
 If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of
 {\tt mip} and SEIE, STIE, and SSIE of {\tt mie} are hardwired to zeros.
-- 
cgit v1.1