From 0472bcdd166f45712492829a250e228bb45fa5e7 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 21 Mar 2018 13:16:20 -0700
Subject: John Hauser's alternative writable-misa.C proposal

This one removes implementation-defined behavior but is still sane
to implement.
---
 src/supervisor.tex | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'src/supervisor.tex')

diff --git a/src/supervisor.tex b/src/supervisor.tex
index e443612..975d7ba 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -538,8 +538,14 @@ XLEN \\
 
 {\tt sepc} is an XLEN-bit read/write register formatted as shown in
 Figure~\ref{epcreg}.  The low bit of {\tt sepc} ({\tt sepc[0]}) is
-always zero.  Implementations with IALIGN=32 may additionally
-hardwire {\tt sepc[1]} to zero.
+always zero.  On implementations that support only IALIGN=32, the two low bits
+({\tt sepc[1:0]}) are always zero.
+
+If an implementation allows IALIGN to be either 16 or 32 (by
+changing CSR {\tt misa}, for example), then, whenever IALIGN=32, bit
+{\tt sepc[1]} is masked on reads so that it appears to be 0.  This
+masking occurs also for the implicit read by the SRET instruction.
+Though masked, {\tt sepc[1]} remains writable when IALIGN=32.
 
 {\tt sepc} is a \warl\ register that must be able to hold all valid physical
 and virtual addresses.  It need not be capable of holding all possible invalid
-- 
cgit v1.1

