From c0dc4b4b839d70cf430ea7cf1d70864b188aa6bb Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 26 Apr 2023 17:59:07 -0700
Subject: Fix typos

---
 src/supervisor.adoc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/supervisor.adoc')

diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index 14755e4..a7297b9 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -302,7 +302,7 @@ in `sie`, then reading back to see which bit positions hold a one.
 
 [NOTE]
 ====
-The `sip` and `sie` registers are subsets of the `mip` and ` mie`
+The `sip` and `sie` registers are subsets of the `mip` and `mie`
 registers. Reading any implemented field, or writing any writable field,
 of `sip`/`sie` effects a read or write of the homonymous field of
 `mip`/`mie`.
@@ -351,7 +351,7 @@ an exception when executing in U-mode. Hence, they are effectively
 ====
 The setting of a bit in `mcounteren` does not affect whether the
 corresponding bit in `scounteren` is writable. However, U-mode may only
-access a counter if the corresponding bits in ` scounteren` and
+access a counter if the corresponding bits in `scounteren` and
 `mcounteren` are both set.
 ====
 
@@ -360,7 +360,7 @@ access a counter if the corresponding bits in ` scounteren` and
 The `sscratch` register is an SXLEN-bit read/write register, dedicated
 for use by the supervisor. Typically, `sscratch` is used to hold a
 pointer to the hart-local supervisor context while the hart is executing
-user code. At the beginning of a trap handler, ` sscratch` is swapped
+user code. At the beginning of a trap handler, `sscratch` is swapped
 with a user register to provide an initial working register.
 
 .Supervisor Scratch Register
@@ -397,7 +397,7 @@ include::images/bytefield/epcreg.edn[]
 
 The `scause` register is an SXLEN-bit read-write register formatted as
 shown in <<scausereg>>. When a trap is taken into
-S-mode, ` scause` is written with a code indicating the event that
+S-mode, `scause` is written with a code indicating the event that
 caused the trap. Otherwise, `scause` is never written by the
 implementation, though it may be explicitly written by software.
 
@@ -556,7 +556,7 @@ addresses and the value 0. It need not be capable of holding all
 possible invalid addresses. Prior to writing `stval`, implementations
 may convert an invalid address into some other invalid address that
 `stval` is capable of holding. If the feature to return the faulting
-instruction bits is implemented, ` stval` must also be able to hold all
+instruction bits is implemented, `stval` must also be able to hold all
 values less than latexmath:[$2^N$], where latexmath:[$N$] is the smaller
 of SXLEN and ILEN.
 
-- 
cgit v1.1

