From b170645fa6f8143b5927cccb27a740064589ba35 Mon Sep 17 00:00:00 2001
From: Daniel Lustig <dlustig@nvidia.com>
Date: Thu, 5 Jul 2018 15:53:28 -0700
Subject: FLD and FST are not atomic unless XLEN>=64

---
 src/rvwmo.tex | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'src/rvwmo.tex')

diff --git a/src/rvwmo.tex b/src/rvwmo.tex
index 1a7096c..8dd97c3 100644
--- a/src/rvwmo.tex
+++ b/src/rvwmo.tex
@@ -37,16 +37,18 @@ Memory-accessing instructions give rise to {\em memory operations}.
 A memory operation can be either a {\em load operation}, a {\em store operation}, or both simultaneously.
 All memory operations are single-copy atomic: they can never be observed in a partially-complete state.
 
-Among instructions in RV32GC and RV64GC, each aligned memory instruction other than an unsuccessful SC instruction gives rise to exactly one memory operation.
+Among instructions in RV32GC and RV64GC, each aligned memory instruction gives rise to exactly one memory operation, with two exceptions.
+First, an unsuccessful SC instruction does not give rise to any memory operations.
+Second, FLD and FST instructions may each give rise to multiple memory operations if XLEN$<$64, as stated in Section~\ref{fld_fst} and clarified below.
 An aligned AMO gives rise to a single memory operation that is both a load operation and a store operation simultaneously.
-Unsuccessful SC instructions do not generate architecturally-visible memory operations.
 
 \begin{commentary}
   Instructions in the RV128 base instruction set and in future ISA extensions such as V (vector) and P (SIMD) may give rise to multiple memory operations.  However, the memory model for these extensions has not yet been formalized.
 \end{commentary}
 
 A misaligned load or store instruction may be decomposed into a set of component memory operations of any granularity.
-The memory operations generated by a misaligned instruction are not ordered with respect to each other in program order, but they are ordered normally with respect to the memory operations generated by preceding and subsequent instructions in program order.
+An FLD or FST instruction for which XLEN$<$64 may also be decomposed into a set of component memory operations of any granularity.
+The memory operations generated by such instructions are not ordered with respect to each other in program order, but they are ordered normally with respect to the memory operations generated by preceding and subsequent instructions in program order.
 The atomics extension ``A'' does not require execution environments to support misaligned atomic instructions at all; however, if misaligned atomics are supported via the ``Zam'' extension, LRs, SCs, and AMOs may be decomposed subject to the constraints of the atomicity axiom for misaligned atomics, which is defined in Chapter~\ref{sec:zam}.
 
 \begin{commentary}
-- 
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