From 825c9395021ad25ae0726afa91a9a4f27daec2dc Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 25 Mar 2019 01:46:28 -0700
Subject: Change "pc" to "address" for clarity

Resolves #356
---
 src/rv32.tex | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'src/rv32.tex')

diff --git a/src/rv32.tex b/src/rv32.tex
index 7a676a4..b6885cb 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -569,7 +569,7 @@ bits with zeros.
 AUIPC (add upper immediate to {\tt pc}) is used to build {\tt pc}-relative
 addresses and uses the U-type format.  AUIPC forms a 32-bit offset from the
 20-bit U-immediate, filling in the lowest 12 bits with zeros, adds this offset
-to the {\tt pc} of the AUIPC instruction, then places the result in register {\em rd}.
+to the address of the AUIPC instruction, then places the result in register {\em rd}.
 
 \begin{commentary}
 The AUIPC instruction supports two-instruction sequences to access
@@ -690,7 +690,8 @@ slots.
 
 \vspace{-0.1in} The jump and link (JAL) instruction uses the J-type
 format, where the J-immediate encodes a signed offset in multiples of
-2 bytes.  The offset is sign-extended and added to the {\tt pc}
+2 bytes.  The offset is sign-extended and added to the address of
+the jump instruction
 to form the jump target address.  Jumps can therefore target a
 $\pm$\wunits{1}{MiB} range. JAL stores the address of the instruction
 following the jump ({\tt pc}+4) into register {\em rd}.  The standard
@@ -848,7 +849,7 @@ enable macro-op fusion of the sequences:\linebreak
 All branch instructions use the B-type instruction format.  The
 12-bit B-immediate encodes signed offsets in multiples of 2 bytes.
 The offset is sign-extended and added
-to the current {\tt pc} to give the target address.  The
+to the address of the branch instruction to give the target address.  The
 conditional branch range is $\pm$\wunits{4}{KiB}.
 
 \vspace{-0.2in}
-- 
cgit v1.1

