From 4e2aa61f692c16ac5ffc502bf04f980099863a0e Mon Sep 17 00:00:00 2001
From: Bill Traynor <wmat@riscv.org>
Date: Thu, 5 Jan 2023 12:25:58 -0500
Subject: Added missing table values.

Added missing first line to RV32Q table.
---
 src/rv-32-64g.adoc | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'src/rv-32-64g.adoc')

diff --git a/src/rv-32-64g.adoc b/src/rv-32-64g.adoc
index 7a08da1..5344e48 100644
--- a/src/rv-32-64g.adoc
+++ b/src/rv-32-64g.adoc
@@ -52,7 +52,7 @@ ISA.
 [%autowidth,float="center",align="center",cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"]
 |===
     |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |   0|
- 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
+ 4+^|funct7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
  6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
  4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
  4+^|imm[12\|10:5]  2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:1\|11] 2+^|opcode  <|B-type
@@ -107,7 +107,7 @@ ISA.
  6+^|000000000001             2+^|00000 2+^|000    2+^|00000        2+^|1110011 <|EBREAK
 15+^|
     |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
- 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
+ 4+^|funct7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
  6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
  4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
 |===
@@ -171,7 +171,7 @@ ISA.
  4+^|0000001        2+^|rs2   2+^|rs1   2+^|111    2+^|rd           2+^|0111011 <|REMUW
 15+^|
     |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
- 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
+ 4+^|funct7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
 |===
 
 [%autowidth,float="center",align="center",cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"]
@@ -209,7 +209,7 @@ ISA.
 [%autowidth,float="center",align="center",cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"]
 |===
     |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
- 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
+ 4+^|funct7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
  2+^|rs3 2+^|funct2 2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R4-type
  6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
  4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
@@ -258,7 +258,7 @@ ISA.
 [%autowidth,float="center",align="center",cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"]
 |===    
     |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
- 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
+ 4+^|funct7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
  2+^|rs3 2+^|funct2 2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R4-type
  6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
  4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
@@ -306,16 +306,16 @@ ISA.
  4+^|1111001        2+^|00000 2+^|rs1   2+^|000    2+^|rd           2+^|1010011 <|FMV.D.X
 15+^|
     |31 |27 |26  |25    |24 |  20|19  |  15| 14  |  12|11      |      7|6   |     0|
- 4+^|funt7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
+ 4+^|funct7          2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R-type
  2+^|rs3 2+^|funct2 2+^|rs2  2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|R4-type
  6+^|imm[11:0]               2+^|rs1    2+^|funct3 2+^|rd           2+^|opcode  <|I-type
  4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|funct3 2+^|imm[4:0]     2+^|opcode  <|S-type
- 6+^|imm[11:0]               2+^|rs1    2+^|100    2+^|rd           2+^|0000111 <|FLQ
 |===
 
 [%autowidth,float="center",align="center",cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"]
 |===
 15+^|*RV32Q Standard Extension*
+ 4+^|imm[11:0]      2+^|     2+^|rs1    2+^|100    2+^|rd           2+^|0000111 <|FLQ
  4+^|imm[11:5]      2+^|rs2  2+^|rs1    2+^|100    2+^|imm[4:0]     2+^|0100111 <|FSQ
  2+^|rs3 2+^|11     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1000011 <|FMADD.Q
  2+^|rs3 2+^|11     2+^|rs2  2+^|rs1    2+^|rm     2+^|rd           2+^|1000111 <|FMSUB.Q
-- 
cgit v1.1

