From abe428aa690233cd601402533ce65ee1bbd4503d Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com>
Date: Wed, 10 Apr 2024 19:22:32 -0500
Subject: Editorial updates to Smstateen (#1342)

* editorial updates to Smstateen

* editorial updates to Smstateen

* update1
---
 src/priv-csrs.adoc | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 89 insertions(+), 2 deletions(-)

(limited to 'src/priv-csrs.adoc')

diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc
index ac9432e..e799b51 100644
--- a/src/priv-csrs.adoc
+++ b/src/priv-csrs.adoc
@@ -282,8 +282,26 @@ Supervisor count overflow.
 
 |`0x5A8` |SRW |`scontext` |Supervisor-mode context register.
 
-4+^|Supervisor Resource Management Configuration
-|`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration.
+//4+^|Supervisor Resource Management Configuration
+//|`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration.
+
+4+^|Supervisor State Enable Registers
+|`0x10C` +
+ `0x10D` +
+ `0x10E` +
+ `0x10F`
+|SRW +
+ SRW +
+ SRW +
+ SRW
+|`sstateen0` +
+ `sstateen1` +
+ `sstateen2` +
+ `sstateen3`
+|Supervisor State Enable 0 Register. +
+ Supervisor State Enable 1 Register. +
+ Supervisor State Enable 2 Register. +
+ Supervisor State Enable 3 Register.
 
 |===
 
@@ -378,6 +396,40 @@ HRW
 |Delta for VS/VU-mode timer. +
 Upper 32 bits of `htimedelta`, RV32 only.
 
+4+^|Hypervisor State Enable Registers
+|`0x60C` +
+ `0x60D` +
+ `0x60E` +
+ `0x60F` +
+ `0x61C` +
+ `0x61D` +
+ `0x61E` +
+ `0x61F`
+|HRW +
+ HRW +
+ HRW +
+ HRW +
+ HRW +
+ HRW +
+ HRW +
+ HRW
+|`hstateen0`  +
+ `hstateen1`  +
+ `hstateen2`  +
+ `hstateen3`  +
+ `hstateen0h` +
+ `hstateen1h` +
+ `hstateen2h` +
+ `hstateen3h`
+|Hypervisor State Enable 0 Register. +
+ Hypervisor State Enable 1 Register. +
+ Hypervisor State Enable 2 Register. +
+ Hypervisor State Enable 3 Register. +
+ Upper 32 bits of Hypervisor State Enable 0 Register, RV32 only. +
+ Upper 32 bits of Hypervisor State Enable 1 Register, RV32 only. +
+ Upper 32 bits of Hypervisor State Enable 2 Register, RV32 only. +
+ Upper 32 bits of Hypervisor State Enable 3 Register, RV32 only.
+
 4+^|Virtual Supervisor Registers
 
 |`0x200` +
@@ -416,6 +468,7 @@ Virtual supervisor trap cause. +
 Virtual supervisor bad address or instruction. +
 Virtual supervisor interrupt pending. +
 Virtual supervisor address translation and protection.
+
 |===
 
 <<<
@@ -584,6 +637,40 @@ Physical memory protection address register. +
 Physical memory protection address register. +
 &#160; +
 Physical memory protection address register.
+
+4+^|Machine State Enable Registers
+|`0x30C` +
+ `0x30D` +
+ `0x30E` +
+ `0x30F` +
+ `0x31C` +
+ `0x31D` +
+ `0x31E` +
+ `0x31F`
+|MRW +
+ MRW +
+ MRW +
+ MRW +
+ MRW +
+ MRW +
+ MRW +
+ MRW
+|`mstateen0`  +
+ `mstateen1`  +
+ `mstateen2`  +
+ `mstateen3`  +
+ `mstateen0h` +
+ `mstateen1h` +
+ `mstateen2h` +
+ `mstateen3h`
+|Machine State Enable 0 Register. +
+ Machine State Enable 1 Register. +
+ Machine State Enable 2 Register. +
+ Machine State Enable 3 Register. +
+ Upper 32 bits of Machine State Enable 0 Register, RV32 only. +
+ Upper 32 bits of Machine State Enable 1 Register, RV32 only. +
+ Upper 32 bits of Machine State Enable 2 Register, RV32 only. +
+ Upper 32 bits of Machine State Enable 3 Register, RV32 only.
 |===
 
 <<<
-- 
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