From fc41db64f3cf618534adf02422db1ea4deb3ce4f Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 2 Dec 2018 22:15:02 -0800
Subject: WIP on M-mode chapter

---
 src/machine.tex | 39 ++++++++++-----------------------------
 1 file changed, 10 insertions(+), 29 deletions(-)

(limited to 'src/machine.tex')

diff --git a/src/machine.tex b/src/machine.tex
index a22d076..ccf2ace 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -3,8 +3,7 @@
 
 This chapter describes the machine-level operations available in
 machine-mode (M-mode), which is the highest privilege mode in a RISC-V
-system.  M-mode is the only mandatory privilege mode in a RISC-V
-hardware implementation.  M-mode is used for low-level access to a
+system.  M-mode is used for low-level access to a
 hardware platform and is the first mode entered at reset.  M-mode can
 also be used to implement features that are too difficult or expensive
 to implement in hardware directly.  The RISC-V machine-level ISA
@@ -88,17 +87,6 @@ at a time.  If zero after one shift, then the machine is RV32.  If
 zero after two shifts, then the machine is RV64, else RV128.
 \end{commentary}
 
-When MXL is set to a value less than the widest supported XLEN, all
-operations must ignore source operand register bits above the
-configured XLEN, and must sign-extend results to fill the entire
-widest supported XLEN in the destination register.
-
-\begin{commentary}
-We require that operations always fill the entire underlying hardware
-registers with defined values to avoid implementation-defined
-behavior.
-\end{commentary}
-
 The Extensions field encodes the presence of the standard extensions,
 with a single bit per letter of the alphabet (bit 0 encodes presence
 of extension ``A'' , bit 1 encodes presence of extension ``B'',
@@ -129,7 +117,7 @@ The ``X'' bit will be set if there are any non-standard extensions.
 Bit & Character  & Description \\
 \hline	 
   0 & A & Atomic extension \\
-  1 & B & {\em Tentatively reserved for Bit operations extension} \\
+  1 & B & {\em Tentatively reserved for Bit-Manipulation extension} \\
   2 & C & Compressed extension \\
   3 & D & Double-precision floating-point extension \\
   4 & E & RV32E base ISA \\
@@ -196,8 +184,6 @@ If an instruction that would write {\tt misa} increases IALIGN, and
 the subsequent instruction's address is not IALIGN-bit aligned, the
 write to {\tt misa} is suppressed, leaving {\tt misa} unchanged.
 
-\clearpage
-
 \subsection{Machine Vendor ID Register {\tt mvendorid}}
 
 The {\tt mvendorid} CSR is a 32-bit read-only register providing
@@ -603,13 +589,6 @@ supported in systems running Unix-like operating systems to support
 user-level trap handling.
 \end{commentary}
 
-\begin{commentary}
-Fields that were previously allocated for H-mode support in {\tt
-  mstatus} have now been reserved as \wpri\ fields.  To reduce
-backwards incompatibility with existing implementations, we did not
-compact the register after removing these fields.
-\end{commentary}
-
 \subsection{Base ISA Control in {\tt mstatus} Register}
 \label{xlen-control}
 
@@ -637,8 +616,11 @@ Whenever XLEN in any mode is set to a value less than the widest
 supported XLEN, all operations must ignore source operand register
 bits above the configured XLEN, and must sign-extend results to fill
 the entire widest supported XLEN in the destination register.
-
 \begin{commentary}
+We require that operations always fill the entire underlying hardware
+registers with defined values to avoid implementation-defined
+behavior.
+
 To reduce hardware complexity, the architecture imposes no checks that
 lower-privilege modes have XLEN settings less than or equal to the
 next-higher privilege mode.  In practice, such settings would almost
@@ -741,7 +723,7 @@ operation is permitted in S-mode.  TSR is hard-wired to 0 when S-mode is not
 supported.
 
 \begin{commentary}
-Trapping SRET is necessary to emulate the Augmented Virtualization mechanism
+Trapping SRET is necessary to emulate the hypervisor extension
 (see Chapter~\ref{hypervisor}) on implementations that do not provide it.
 \end{commentary}
 
@@ -1717,10 +1699,9 @@ read-only shadows of {\tt mcycle}, {\tt minstret}, and {\tt mhpmcounter{\em
 n}}, respectively.  The {\tt time} CSR is a read-only shadow of the
 memory-mapped {\tt mtime} register.
 \begin{commentary}
-Implementations can convert reads of the {\tt time} CSR into loads to
-the memory-mapped {\tt mtime} register, or hard-wire the TM bit in
-{\tt mcounteren} to 0
-and emulate this functionality in M-mode software.
+Implementations can convert reads of the {\tt time} CSR into loads to the
+memory-mapped {\tt mtime} register, or emulate this functionality in M-mode
+software.
 \end{commentary}
 
 \subsection{Machine Counter-Inhibit CSR ({\tt mcountinhibit})}
-- 
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