From d7b5caa893ecd40d295f5ae9831a055dcd1d0b70 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 29 Aug 2021 19:56:38 -0700
Subject: Add henvcfg/senvcfg CSRs

---
 src/machine.tex | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)

(limited to 'src/machine.tex')

diff --git a/src/machine.tex b/src/machine.tex
index 5368b4a..4ecc7ec 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2305,6 +2305,98 @@ register that is programmed by the platform or by M-mode software towards the
 beginning of the boot process.
 \end{commentary}
 
+\subsection{%
+ Machine Environment Configuration Registers
+ ({\tt menvcfg} and {\tt menvcfgh})%
+}
+
+The {\tt menvcfg} CSR is an MXLEN-bit read/write register,
+formatted for MXLEN=64 as shown in Figure~\ref{fig:menvcfg},
+that controls certain characteristics of the execution environment
+for modes less privileged than M.
+
+\begin{figure}[h!]
+{\footnotesize
+\begin{center}
+\begin{tabular}{c@{}Kcc@{}W@{}Wc}
+\instbit{63} &
+\instbitrange{62}{8} &
+\instbit{7} &
+\instbit{6} &
+\instbitrange{5}{4} &
+\instbitrange{3}{1} &
+\instbit{0} \\
+\hline
+\multicolumn{1}{|c|}{STCD} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{CBZE} &
+\multicolumn{1}{c|}{CBCFE} &
+\multicolumn{1}{c|}{CBIE} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{FIOM} \\
+\hline
+1 & 55 & 1 & 1 & 2 & 3 & 1 \\
+\end{tabular}
+\end{center}
+}
+\vspace{-0.1in}
+\caption{Machine environment configuration register ({\tt menvcfg}) for MXLEN=64.}
+\label{fig:menvcfg}
+\end{figure}
+
+If bit FIOM (Fence of I/O implies Memory) is set to one in {\tt menvcfg},
+FENCE instructions executed in modes less privileged than M are modified so
+the requirement to order accesses to device I/O implies also the requirement
+to order main memory accesses.
+Table~\ref{tab:menvcfg-FIOM} details the modified interpretation of
+FENCE instruction bits PI, PO, SI, and SO for modes less privileged than M
+when FIOM=1.
+If U-mode is not supported, FIOM is hardwired to zero.
+
+\begin{table}[h!]
+\begin{center}
+\begin{tabular}{|c|l|}
+\hline
+Instruction bit & Meaning when set \\
+\hline
+PI & Predecessor device input and memory reads   (PR implied) \\
+PO & Predecessor device output and memory writes (PW implied) \\
+\hline
+SI & Successor device input and memory reads     (SR implied) \\
+SO & Successor device output and memory writes   (SW implied) \\
+\hline
+\end{tabular}
+\end{center}
+\vspace{-0.1in}
+\caption{%
+Modified interpretation of FENCE predecessor and successor sets
+for modes less privileged than M when FIOM=1.%
+}
+\label{tab:menvcfg-FIOM}
+\end{table}
+
+The definition of the STCD field will be furnished by the
+forthcoming Sstc extension.
+Its allocation within {\tt menvcfg} may change prior to the ratification
+of that extension.
+
+The definition of the CBZE field will be furnished by the
+forthcoming Zicboz extension.
+Its allocation within {\tt menvcfg} may change prior to the ratification
+of that extension.
+
+The definitions of the CBCFE and CBIE fields will be furnished by the
+forthcoming Zicbom extension.
+Their allocations within {\tt menvcfg} may change prior to the ratification
+of that extension.
+
+When MXLEN=32, {\tt menvcfg} contains the same fields as bits 31:0
+of {\tt menvcfg} when MXLEN=64.
+Additionally, when MXLEN=32, {\tt menvcfgh} is a 32-bit read/write register that
+contains the same fields as bits 63:32 of {\tt menvcfg} when
+MXLEN=64.
+Register {\tt menvcfgh} does not exist when MXLEN=64.
+
 \subsection{Machine Security Configuration Register ({\tt mseccfg})}
 \label{sec:mseccfg}
 
-- 
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