From 8e52ffa49d09437c69fec6e173dfbddeb9e8ea1a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 3 Dec 2018 23:49:01 -0800 Subject: Mostly remove RV128 from priv spec, for now --- src/machine.tex | 56 ++++++++++++++++++++++++++++++-------------------------- 1 file changed, 30 insertions(+), 26 deletions(-) (limited to 'src/machine.tex') diff --git a/src/machine.tex b/src/machine.tex index c43a9b8..b130421 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -97,6 +97,10 @@ where the implementation allows the supported ISA to be modified. At reset, the Extension field should contain the maximal set of supported extensions, and I should be selected over E if both are available. +The RV128I base ISA is not yet frozen, and while much of the remainder of this +specification is expected to apply to RV128, this version of the document +focuses only on RV32 and RV64. + The ``G'' bit is used as an escape to allow expansion to a larger space of standard extension names. \begin{commentary} @@ -354,7 +358,7 @@ of the largest hart ID used in a system. The {\tt mstatus} register is an MXLEN-bit read/write register formatted as shown in Figure~\ref{mstatusreg-rv32} for RV32 and -Figure~\ref{mstatusreg} for RV64 and RV128. The {\tt mstatus} +Figure~\ref{mstatusreg} for RV64. The {\tt mstatus} register keeps track of and controls the hart's current operating state. Restricted views of the {\tt mstatus} register appear as the {\tt sstatus} and {\tt ustatus} registers in the S-level and U-level @@ -500,7 +504,7 @@ ISAs respectively. \end{center} } \vspace{-0.1in} -\caption{Machine-mode status register ({\tt mstatus}) for RV64 and RV128.} +\caption{Machine-mode status register ({\tt mstatus}) for RV64.} \label{mstatusreg} \end{figure*} @@ -591,7 +595,7 @@ user-level trap handling. \subsection{Base ISA Control in {\tt mstatus} Register} \label{xlen-control} -For RV64 and RV128 systems, the SXL and UXL fields are \warl\ fields +For RV64 systems, the SXL and UXL fields are \warl\ fields that control the value of XLEN for S-mode and U-mode, respectively. The encoding of these fields is the same as the MXL field of {\tt misa}, shown in Table~\ref{misabase}. The effective @@ -601,12 +605,12 @@ respectively. For RV32 systems, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32. -For RV64 and RV128 systems, if S-mode is not supported, then SXL is hardwired +For RV64 systems, if S-mode is not supported, then SXL is hardwired to zero. Otherwise, it is a \warl\ field that encodes the current value of SXLEN. In particular, the implementation may hardwire SXL so that SXLEN=MXLEN. -For RV64 and RV128 systems, if U-mode is not supported, then UXL is hardwired +For RV64 systems, if U-mode is not supported, then UXL is hardwired to zero. Otherwise, it is a \warl\ field that encodes the current value of UXLEN. In particular, the implementation may hardwire UXL so that UXLEN=MXLEN or UXLEN=SXLEN. @@ -1437,8 +1441,8 @@ machine-mode register, {\tt mtime}. {\tt mtime} must run at constant frequency, and the platform must provide a mechanism for determining the timebase of {\tt mtime}. -The {\tt mtime} register has a 64-bit precision on all RV32, RV64, and -RV128 systems. Platforms provide a 64-bit memory-mapped machine-mode +The {\tt mtime} register has a 64-bit precision on all RV32 and RV64 +systems. Platforms provide a 64-bit memory-mapped machine-mode timer compare register ({\tt mtimecmp}), which causes a timer interrupt to be posted when the {\tt mtime} register contains a value greater than or equal to the value in the {\tt mtimecmp} register. @@ -1541,7 +1545,7 @@ M-mode includes a basic hardware performance-monitoring facility. The processor core on which the hart is running. The {\tt minstret} CSR counts the number of instructions the hart has retired. The {\tt mcycle} and {\tt minstret} registers have 64-bit -precision on all RV32, RV64, and RV128 systems. +precision on all RV32 and RV64 systems. The counter registers have an arbitrary value after system reset, and can be written with a given value. Any CSR write takes effect after @@ -1576,7 +1580,7 @@ both the counter and its corresponding event selector to 0. \caption{Hardware performance monitor counters.} \end{figure} -All of these counters have 64-bit precision on RV32, RV64, and RV128. +All of these counters have 64-bit precision on RV32 and RV64. On RV32 only, reads of the {\tt mcycle}, {\tt minstret}, and {\tt mhpmcounter{\em n}} CSRs return the low 32 bits, while reads of the {\tt @@ -1603,22 +1607,27 @@ mcycleh}, {\tt minstreth}, and {\tt mhpmcounter{\em n}h} CSRs return bits \caption{Upper 32 bits of hardware performance monitor counters, RV32 only.} \end{figure} -On RV128 systems, the 64-bit values in {\tt mcycle}, {\tt minstret}, and -{\tt mhpmcounter{\em n}} are sign-extended to 128-bits when read. -\begin{samepage-commentary} -On RV128 systems, both signed and unsigned 64-bit values are held in a -canonical form with bit 63 repeated in all higher bit positions. The -counters are 64-bit values even in RV128, and so the counter CSR reads -preserve the sign-extension invariant. Implementations may choose to -implement fewer bits of the counters, provided software would be unlikely -to experience wraparound (e.g., $2^{63}$ instructions executed) -and thereby avoid having to actually implement the sign-extension -circuitry. -\end{samepage-commentary} +%On RV128 systems, the 64-bit values in {\tt mcycle}, {\tt minstret}, and +%{\tt mhpmcounter{\em n}} are sign-extended to 128-bits when read. +%\begin{samepage-commentary} +%On RV128 systems, both signed and unsigned 64-bit values are held in a +%canonical form with bit 63 repeated in all higher bit positions. The +%counters are 64-bit values even in RV128, and so the counter CSR reads +%preserve the sign-extension invariant. Implementations may choose to +%implement fewer bits of the counters, provided software would be unlikely +%to experience wraparound (e.g., $2^{63}$ instructions executed) +%and thereby avoid having to actually implement the sign-extension +%circuitry. +%\end{samepage-commentary} \subsection{Counter-Enable Registers ({\tt [m|s]counteren})} \label{sec:mcounteren} +The counter-enable registers {\tt mcounteren} and {\tt scounteren} +are 32-bit registers that +control the availability of the hardware performance-monitoring +counters to the next-lowest privileged mode. + \begin{figure*}[h!] {\footnotesize \begin{center} @@ -1655,11 +1664,6 @@ circuitry. \label{mcounteren} \end{figure*} -The counter-enable registers {\tt mcounteren} and {\tt scounteren} -are 32-bit registers that -control the availability of the hardware performance-monitoring -counters to the next-lowest privileged mode. - The settings in these registers only control accessibility. The act of reading or writing these registers does not affect the underlying counters, which continue to increment even when not accessible. -- cgit v1.1