From 151cb119a8d6e9c35218269f7f979ad11edca2ad Mon Sep 17 00:00:00 2001 From: Charlie Jenkins Date: Fri, 21 Jul 2023 11:47:09 -0700 Subject: Make "Integer Register-Immediate Operations" Consistent Properly align the ADDI16SP immediate in wavedrom. Remove the bit brackets from the immediates because the instructions do not uniformly follow the same immediate format. Signed-off-by: Charlie Jenkins --- src/images/wavedrom/c-int-reg-immed.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/images/wavedrom') diff --git a/src/images/wavedrom/c-int-reg-immed.adoc b/src/images/wavedrom/c-int-reg-immed.adoc index a804555..b72b5a1 100644 --- a/src/images/wavedrom/c-int-reg-immed.adoc +++ b/src/images/wavedrom/c-int-reg-immed.adoc @@ -4,9 +4,9 @@ .... {reg: [ {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1', 'C1']}, - {bits: 5, name: 'imm[4:0]', type: 1, attr: ['5','imm[4:0]', 'imm[4:0], imm[4|6|8:7|5]']}, + {bits: 5, name: 'imm', type: 1, attr: ['5','imm[4:0]', 'imm[4:0]', 'imm[4|6|8:7|5]']}, {bits: 5, name: 'rd/rs1', type: 5, attr: ['5','dest≠0', 'dest≠0', '2']}, - {bits: 1, name: 'imm[5]', type: 5, attr: ['1','imm[5]', 'imm[5]', 'imm[9]']}, + {bits: 1, name: 'imm', type: 5, attr: ['1','imm[5]', 'imm[5]', 'imm[9]']}, {bits: 3, name: 'funct3', type: 5, attr: ['3','C.ADDI', 'C.ADDIW', 'C.ADDI16SP']}, ], config: {bits: 16}} .... -- cgit v1.1