From 791d73f0a6eda08057bd5fb57678a954bb4c6732 Mon Sep 17 00:00:00 2001
From: Krste Asanovic <krste@eecs.berkeley.edu>
Date: Mon, 16 Jul 2018 02:18:00 -0700
Subject: Updates to HINT sections.

---
 src/c.tex | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

(limited to 'src/c.tex')

diff --git a/src/c.tex b/src/c.tex
index dcb22c3..ed95669 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -1144,7 +1144,7 @@ valid C instructions will eventually complete.
 A portion of the RVC encoding space is reserved for microarchitectural HINTs.
 Like the HINTs in the RV32I base ISA (see Section~\ref{sec:rv32i-hints}),
 these instructions do not modify any architectural state, except for advancing
-the {\tt pc} and the instructions-retired counter {\tt instret}.  HINTs are
+the {\tt pc} and any applicable performance counters.  HINTs are
 executed as no-ops on implementations that ignore them.
 
 RVC HINTs are encoded as computational instructions that do not modify the
@@ -1163,9 +1163,12 @@ example, \mbox{C.ADD {\em x0}, {\em t0}} might not encode the same HINT
 as \mbox{ADD {\em x0}, {\em x0}, {\em t0}}.
 
 \begin{commentary}
-We expect the static and dynamic frequency of HINT code points will vary
-dramatically.  Decoupling the RVC and RVI HINT mappings allows the scarce RVC
-HINT space to be allocated to the most popular HINTs.
+The primary reason to not require an RVC HINT to expand to an RVI HINT
+is that HINTs are unlikely to be compressible in the same manner as
+the underlying computational instruction.  Also, decoupling the RVC
+and RVI HINT mappings allows the scarce RVC HINT space to be allocated
+to the most popular HINTs, and in particular, to HINTs that are
+amenable to macro-op fusion.
 \end{commentary}
 
 Table~\ref{tab:rvc-hints} lists all RVC HINT code points.  For RV32C, 78\% of
-- 
cgit v1.1

