From 71597dd3ad89a2262d240680793586a8ebdec308 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 4 Oct 2018 15:06:29 -0700 Subject: Add marchid management document (#234) * Fix broken link * Add marchid document --- README.md | 3 +++ marchid.md | 21 +++++++++++++++++++++ src/rv32.tex | 2 +- 3 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 marchid.md diff --git a/README.md b/README.md index a7a14b6..ad70a00 100644 --- a/README.md +++ b/README.md @@ -17,3 +17,6 @@ https://riscv.org/specifications/ Compiled versions of the most recent drafts of the specifications are available at https://github.com/riscv/riscv-isa-manual/releases/latest + +The canonical list of open-source RISC-V implementations' marchid CSR values +is available at https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md diff --git a/marchid.md b/marchid.md new file mode 100644 index 0000000..6dd41aa --- /dev/null +++ b/marchid.md @@ -0,0 +1,21 @@ +Open-Source RISC-V Architecture IDs +======================================== + +Every RISC-V hart provides an marchid CSR that encodes its base +microarchitecture. Any hart may report an architecture ID of 0, indicating +unspecified origin. Commercial implementations (those with nonzero mvendorid) +may encode any value in marchid with the most-significant bit set, with the +low-order bits formatted in a vendor-specific manner. Open-source +implementations (which may or may not have a nonzero mvendorid) have the +most-significant bit clear, with a globally unique pattern in the low-order +bits. + +This document contains the canonical list of open-source RISC-V implementations +and their architecture IDs. Open-source project maintainers may make pull +requests against this repository to request the allocation of an architecture +ID. + +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Project Name | Maintainers | Point of Contact | Architecture ID | Project URL +-------------|-------------------------------|---------------------------------------------------------|-----------------|--------------------------------------------------- +Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/freechipsproject/rocket-chip diff --git a/src/rv32.tex b/src/rv32.tex index 60723b6..0aab4f5 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -202,7 +202,7 @@ U-type \\ The RISC-V ISA keeps the source ({\em rs1} and {\em rs2}) and destination ({\em rd}) registers at the same position in all formats to simplify decoding. Except for the 5-bit immediates used in CSR -instructions (Section~\ref{sec:csrinsts}), immediates are always +instructions (Chapter~\ref{csrinsts}), immediates are always sign-extended, and are generally packed towards the leftmost available bits in the instruction and have been allocated to reduce hardware complexity. In particular, the sign bit for all immediates is always -- cgit v1.1 From 4bf712347e6fede7c9119faed2d66b9bd9741a42 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 4 Oct 2018 15:18:27 -0700 Subject: Allocate Spike marchid --- marchid.md | 1 + 1 file changed, 1 insertion(+) diff --git a/marchid.md b/marchid.md index 6dd41aa..f1787c5 100644 --- a/marchid.md +++ b/marchid.md @@ -19,3 +19,4 @@ ID. Project Name | Maintainers | Point of Contact | Architecture ID | Project URL -------------|-------------------------------|---------------------------------------------------------|-----------------|--------------------------------------------------- Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/freechipsproject/rocket-chip +Spike | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 5 | https://github.com/riscv/riscv-isa-sim -- cgit v1.1 From f0d5969f9f9ba4ac2420f7b392d7ad04ecd2528f Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Thu, 4 Oct 2018 18:51:30 -0700 Subject: Update marchid.md. (#235) Add BOOM. --- marchid.md | 1 + 1 file changed, 1 insertion(+) diff --git a/marchid.md b/marchid.md index f1787c5..0c27dfb 100644 --- a/marchid.md +++ b/marchid.md @@ -19,4 +19,5 @@ ID. Project Name | Maintainers | Point of Contact | Architecture ID | Project URL -------------|-------------------------------|---------------------------------------------------------|-----------------|--------------------------------------------------- Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/freechipsproject/rocket-chip +BOOM | UC Berkeley | [Christopher Celio](mailto:celio@berkeley.edu) | 2 | https://github.com/ucb-bar/riscv-boom Spike | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 5 | https://github.com/riscv/riscv-isa-sim -- cgit v1.1 From 0339a73a7dc5f8fb4a15800d9b2dc6e56f1e639a Mon Sep 17 00:00:00 2001 From: Florian Zaruba Date: Sun, 7 Oct 2018 01:24:06 +0200 Subject: Add PULP cores to marchid.md (#236) * Add Ariane to marchid * Add RI5CY to marchid.md --- marchid.md | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/marchid.md b/marchid.md index 0c27dfb..4dbbfbd 100644 --- a/marchid.md +++ b/marchid.md @@ -15,9 +15,11 @@ and their architecture IDs. Open-source project maintainers may make pull requests against this repository to request the allocation of an architecture ID. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -Project Name | Maintainers | Point of Contact | Architecture ID | Project URL --------------|-------------------------------|---------------------------------------------------------|-----------------|--------------------------------------------------- -Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/freechipsproject/rocket-chip -BOOM | UC Berkeley | [Christopher Celio](mailto:celio@berkeley.edu) | 2 | https://github.com/ucb-bar/riscv-boom -Spike | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 5 | https://github.com/riscv/riscv-isa-sim +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Project Name | Maintainers | Point of Contact | Architecture ID | Project URL +------------- | ------------------------------- | ----------------------------------------------------------- | ----------------- | --------------------------------------------------- +Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/freechipsproject/rocket-chip +BOOM | UC Berkeley | [Christopher Celio](mailto:celio@berkeley.edu) | 2 | https://github.com/ucb-bar/riscv-boom +Ariane | PULP Platform | [Florian Zaruba](mailto:zarubaf@iis.ee.ethz.ch), ETH Zurich | 3 | https://github.com/pulp-platform/ariane +RI5CY | PULP Platform | [Frank K. Gürkaynak](mailto:kgf@iis.ee.ethz.ch), ETH Zurich | 4 | https://github.com/pulp-platform/riscv +Spike | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 5 | https://github.com/riscv/riscv-isa-sim -- cgit v1.1