From ccf18a8bfcd5baedbba7c097178dc12b2164f77b Mon Sep 17 00:00:00 2001
From: Krste Asanovic <krste@eecs.berkeley.edu>
Date: Wed, 3 May 2017 07:48:04 -0700
Subject: Moved chapters into canonical extension listing order.

---
 src/preface.tex    | 2 +-
 src/riscv-spec.tex | 2 +-
 src/v.tex          | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/preface.tex b/src/preface.tex
index d77007e..f3b0bb0 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -23,7 +23,7 @@ versions of the RISC-V ISA modules:
     Q        & 2.0 & Y \\
     L        & 0.0 & N \\
     C        & 1.9 & N \\
-    V        & 0.1 & N \\
+    V        & 0.2 & N \\
     B        & 0.0 & N \\
     J        & 0.0 & N \\
     T        & 0.0 & N \\
diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex
index c27c4f5..1478961 100644
--- a/src/riscv-spec.tex
+++ b/src/riscv-spec.tex
@@ -75,11 +75,11 @@
 \input{q}
 \input{l}
 \input{c}
-\input{v}
 \input{b}
 \input{j}
 \input{t}
 \input{p}
+\input{v}
 \input{gmaps}
 \input{assembly}
 \input{extensions}
diff --git a/src/v.tex b/src/v.tex
index 95a80ce..d48c04c 100644
--- a/src/v.tex
+++ b/src/v.tex
@@ -1,4 +1,4 @@
-\chapter{``V'' Standard Extension for Vector Operations, Version 0.1}
+\chapter{``V'' Standard Extension for Vector Operations, Version 0.2}
 \label{sec:bits}
 
 This chapter presents a proposal for the RISC-V vector instruction set
-- 
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