From 85e1d20c52849ca8f6157add4f020abc0dc94d0d Mon Sep 17 00:00:00 2001 From: Kersten Richter Date: Wed, 17 Apr 2024 20:47:01 -0500 Subject: Update sstc.adoc Signed-off-by: Kersten Richter --- src/sstc.adoc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/sstc.adoc b/src/sstc.adoc index a96ea87..5c72ada 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -27,7 +27,7 @@ and the VS-level vstimecmp CSR. === Machine and Supervisor Level Additions -==== *Supervisor Timer Register (stimecmp)* +==== Supervisor Timer (stimecmp) Register This extension adds this new CSR. @@ -66,7 +66,7 @@ existing S-mode software that uses this SEE facility, while new S-mode software takes advantage of stimecmp directly.) ==== -==== Machine Interrupt Registers (mip and mie) +==== Machine Interrupt (mip and mie) Registers This extension modifies the description of the STIP/STIE bits in these registers as follows: @@ -80,7 +80,7 @@ implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp. This timer interrupt signal is cleared by writing stimecmp with a value greater than the current time value. -==== Supervisor Interrupt Registers (sip and sie) +==== Supervisor Interrupt (sip and sie) Registers This extension modifies the description of the STIP/STIE bits in these registers as follows: @@ -94,7 +94,7 @@ interrupts generated by stimecmp, is set and cleared by writing stimecmp with a value that respectively is less than or equal to, or greater than, the current time value. -==== Machine Counter-Enable Register (mcounteren) +==== Machine Counter-Enable (mcounteren) Register This extension adds to the description of the TM bit in this register as follows: @@ -109,7 +109,7 @@ hcounteren. === Hypervisor Extension Additions -==== *Virtual Supervisor Timer Register (vstimecmp)* +==== Virtual Supervisor Timer (vstimecmp) Register This extension adds this new CSR. @@ -141,7 +141,7 @@ ensures compatibility with existing guest VS-mode software that uses this SEE facility, while new VS-mode software takes advantage of vstimecmp directly.) ==== -==== Hypervisor Interrupt Registers (hvip, hip, and hie) +==== Hypervisor Interrupt (hvip, hip, and hie) Registers This extension modifies the description of the VSTIP/VSTIE bits in the hip/hie registers as follows: @@ -155,7 +155,7 @@ vstimecmp with a value that respectively is less than or equal to, or greater than, the current (time + htimedelta) value. The hip.VSTIP bit remains defined while V=0 as well as V=1. -==== Hypervisor Counter-Enable Register (hcounteren) +==== Hypervisor Counter-Enable (hcounteren) Register This extension adds to the description of the TM bit in this register as follows: -- cgit v1.1