From 562dccda796e2a12ea4fd8aa4d5f49a887faa73f Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 7 May 2017 14:51:43 -0700
Subject: Misaligned superpages generate page-fault exceptions

h/t Anthony Coulter
---
 src/supervisor.tex | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/src/supervisor.tex b/src/supervisor.tex
index a16504a..2450a28 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -1155,21 +1155,18 @@ follows:
   current privilege mode and the value of the SUM and MXR fields of
   the {\tt mstatus} register.  If not, stop and raise a page-fault exception.
 
-\item If $pte.a=0$, perform either of the following two actions:
-  \begin{itemize}
-    \item Atomically with respect to the permission check in step 5,
-      set $pte.a$ to 1. If this access violates a PMA or PMP check, raise
-      an access exception.
-    \item Raise a page-fault exception.
-  \end{itemize}
+\item If $i>0$ and $pa.ppn[i-1:0]\neq 0$, this is a misaligned superpage;
+      stop and raise a page-fault exception.
 
-\item If the memory access is a store and $pte.d=0$, perform either of the
-  following two actions:
+\item If $pte.a=0$, or if the memory access is a store and $pte.d=0$, either
+  raise a page-fault exception or:
   \begin{itemize}
-    \item Atomically with respect to the permission check in step 5 and
-      the access to $pte.a$ in step 6, set $pte.d$ to 1. If this access
-      violates a PMA or PMP check, raise an access exception.
-    \item Raise a page-fault exception.
+  \item Set $pte.a$ to 1 and, if the memory access is a store, also set
+    $pte.d$ to 1.
+  \item If this access violates a PMA or PMP check, raise an access exception.
+  \item This update and the loading of $pte$ in step 2 must be atomic; in
+    particular, no intervening store to the PTE may be perceived to have
+    occurred in-between.
   \end{itemize}
 
 \item The translation is successful. The translated physical address is
-- 
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