From 22c8813c7a05bd9d54892995b43e95f25f9df883 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 4 Oct 2021 16:45:29 -0700 Subject: Clarify order in which PMP CSRs must be implemented --- src/machine.tex | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/machine.tex b/src/machine.tex index 043d584..2ae1756 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -3346,7 +3346,8 @@ PMP entries are described by an 8-bit configuration register and one MXLEN-bit address register. Some PMP settings additionally use the address register associated with the preceding PMP entry. Up to 64 PMP entries are supported. -Implementations may implement zero, 16, or 64 PMP CSRs. +Implementations may implement zero, 16, or 64 PMP CSRs; the lowest-numbered +PMP CSRs must be implemented first. All PMP CSR fields are \warl\ and may be hardwired to zero. PMP CSRs are only accessible to M-mode. -- cgit v1.1