From 1ff8f5e3db057687425d9804fadba59ce722106a Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 16 Sep 2022 19:54:26 -0700
Subject: Tighten description of FCVTMOD exception behavior

---
 src/zfa.tex | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/zfa.tex b/src/zfa.tex
index 8f2803e..41ae40c 100644
--- a/src/zfa.tex
+++ b/src/zfa.tex
@@ -181,7 +181,8 @@ Bits 31:0 are taken from the rounded, unbounded two's complement result,
 then sign-extended to XLEN bits and written to integer register {\em rd}.
 $\pm\infty$ and NaN are converted to zero.
 
-Floating-point exception flags are raised in the same manner as for FCVT.W.D.
+Floating-point exception flags are raised the same as they would be for
+FCVT.W.D with the same input operand.
 
 This instruction is only provided if the D extension is implemented.
 It is encoded like FCVT.W.D, but with the {\rm rs2} field set to 8
-- 
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