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2024-05-28Flatten changelog as v1.13 (#1424)riscv-isa-release-1bec7d3-2024-05-28Bill Traynor10-70/+32
* Flatten changelog as v1.13 Integrated changelog for 1.13 with last document version changes which consisted of integration of ratified specs. * Fix a table. Table row wasn't spanning enough columns. * strip third digit from priv version numbers * fix version number of supervisor ISA * bump priv version to 20240528 * reorganize priv preface --------- Co-authored-by: Andrew Waterman <andrew@sifive.com>
2024-05-28Clarify CBO access size (#1431)David Kruckemyer1-0/+3
Define access size to be size of cache block for PMP/PMA checks
2024-05-26Update cmo.adoc (#1428)David Kruckemyer1-2/+19
- wrap lines - add notes re: performing a flush instead of clean/inval
2024-05-26Using reference symbol style consistent with rest of document (in intro)Peter-Herrmann1-1/+3
2024-05-26intro table declarations matching style from rest of docPeter-Herrmann1-6/+4
2024-05-26wrong number of columns specified in rvwmo tablePeter-Herrmann1-1/+1
2024-05-26removing [[instlengthcode, Table 1]] from rv32IPeter-Herrmann1-1/+0
2024-05-26removed table 2 specifyer from table - incorrect numberingPeter-Herrmann1-1/+1
2024-05-22Update B extension description to remove mention of sub extensions grouped ↵Jordan Carlin1-3/+2
for review (#1419) Signed-off-by: Jordan Carlin <jordanmcarlin@gmail.com>
2024-05-22Clarify the behavior of mcountinhibit CSR (#1422)Xu, Zefan1-3/+3
Use mcycle, minstret, mhpmcountern to replace cycle, instret, hpmcountern in mcountinhibit spec. This will not changing any meaning because of "read-only shadow".
2024-05-22Fix errors in CSR address-mapping conventions tableAndrew Waterman1-6/+6
Resolves #1421
2024-05-16Slightly clean up *envcfg bit spec (#1417)Ved Shanbhogue2-17/+6
2024-05-16remove superflous statement (#1416)Ved Shanbhogue1-2/+1
2024-05-15Remove c.zext.h prerequisites and operation from c.sext.b (#1415)Jordan Carlin1-20/+0
The c.zext.h prerequisites and operation were duplicated at the end of the c.sext.b section. Signed-off-by: Jordan Carlin <jordanmcarlin@gmail.com>
2024-05-15Correct grammar (#1410)Mukund Sivaraman1-1/+1
2024-05-14Update prefaces to reflect removal of vacant regionsriscv-isa-release-221bd85-2024-05-14Andrew Waterman2-3/+3
2024-05-14Remove "vacant" class of memory region (#1408)Andrew Waterman3-15/+16
Represent them as never-accessible main memory or I/O regions instead.
2024-05-14Remove nonexistent N extension from prefaceAndrew Waterman1-1/+0
2024-05-14Fixing instances of "frozen". (#1405)riscv-isa-release-1524be1-2024-05-14Bill Traynor2-259/+225
Several places where extensions were marked as frozen when they were actually ratified.
2024-05-14Remove outdated draft warnings/ratification explanationsAndrew Waterman2-15/+2
2024-05-14Merge pull request #1398 from Ioan-Cristian/mainBill Traynor2-0/+4
Added support for EPUB3
2024-05-14Merge pull request #1388 from riscv/dev/kbroch/listing-prefixed-caption-labelriscv-isa-release-11d72c2-2024-05-14Bill Traynor2-82/+84
Change listing prefixed label caption to "Listing"
2024-05-131394 formatting issues in version 20240411 (#1401)riscv-isa-release-5b9ee70-2024-05-13Bill Traynor1-14/+14
* Fix bolding of extension names. The extension names in the table listing what's included should all be bold. * Fixed bolding of Zce Missed Zce in my last fix, so fixing bolding here.
2024-05-12Added support for EPUB3Ioan-Cristian CÎRSTEA2-0/+4
This pull requests adds support for building EPUB3 versions of the RISC-V ISA manuals. To achieve this, `asciidoctor-epub3` extension has been used. Known issues: some eBook readers are not capable of rendering embedded images. The solution to this problem is disabling embedded image altogether. The `README.md` file provides more details on how to achieve this. Signed-off-by: Ioan-Cristian CÎRSTEA <ioan-cristian.cirstea@tutanota.com>
2024-05-10Clarify the ordering of Additional Standard Unprivileged Extensions (#1391)Yangyu Chen1-7/+5
Fixed some problems mentioned in #1390 and #415 Signed-off-by: Yangyu Chen <cyy@cyyself.name>
2024-05-08Change listing prefixed label to "Listing" and add example prefixed labelKevin Broch2-82/+84
relates to https://github.com/riscv-admin/docs-sig/issues/40 Signed-off-by: Kevin Broch <kbroch@rivosinc.com>
2024-05-07remove references to smcofpmf, which doesn't exist (#1387)riscv-isa-release-7b8ddc9-2024-05-07Beeman Strong1-2/+2
2024-05-06Maintain acronym and update acronym expansion. (#1283)riscv-isa-release-2d1a43e-2024-05-06Bill Traynor1-2/+2
* Change MMWP to MMDD Change Machine Mode Whitelist Policy to Machine Mode Default Deny * Keep MMWP acronym but change change acronym expansion. Change Machine-Mode Whitelist Policy to Machine-Mode When-no-PMP-match Policy to maintain acronym. * Update smepmp.adoc Co-authored-by: Kersten Richter <kersten@riscv.org> Signed-off-by: Bill Traynor <wmat@riscv.org> * Set MMWP as alloWlist Set expansion of MMWP to Machine-Mode alloWlist Policy --------- Signed-off-by: Bill Traynor <wmat@riscv.org> Co-authored-by: Kersten Richter <kersten@riscv.org>
2024-05-03Update supervisor.adoc (#1382)riscv-isa-release-87edab7-2024-05-04Kersten Richter1-2/+2
https://github.com/riscv/riscv-isa-manual/issues/1370 Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Integrate Zicfilp and Zicfiss extension specs (#1380)Ved Shanbhogue18-435/+1607
- Updates CSR, Machine, Supervisor and Hypervisor chapters - Adds CFI chapter to Priv. and Unpriv.
2024-05-02Merge pull request #1378 from riscv/kersten1-patch-2riscv-isa-release-ed61a8d-2024-05-02Kersten Richter1-14/+8
Update to PMP R, W, and X bits
2024-05-02Update pmpcfg.adocKersten Richter1-1/+0
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-6/+7
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-6/+6
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-12/+6
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-6/+6
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/smcntrpmf.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-01wordsmithingAndrew Waterman1-1/+1
2024-05-01Clarify EBREAK behavior applies in absence of debug moduleAndrew Waterman1-2/+3
2024-05-01Clarify that CSR implicit write ordering rule isn't specific to incrementsAndrew Waterman1-1/+2
See https://github.com/riscv/riscv-debug-spec/issues/1026#issuecomment-2088872276
2024-04-30Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>