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2021-11-28Split RV32 [v]sstatus figures into two rowsAndrew Waterman2-32/+57
2021-11-26Fix typoAndrew Waterman1-1/+1
2021-11-26Specify a sequence to regain coherence wrt. mismatched PBMTsAndrew Waterman1-12/+33
2021-11-26Avoid use of "timebase"Andrew Waterman1-1/+1
2021-11-26Clarify definition of [m]time CSRAndrew Waterman1-9/+14
2021-11-26Incorporate @pdonahue-ventana's feedbackAndrew Waterman1-4/+4
2021-11-26Merge branch 'jhauser-2021-CSRFieldMods' of https://github.com/jhauser-us/ris...Andrew Waterman1-0/+36
2021-11-26Clarify when SFENCE.VMA/HFENCE.GVMA need be executedAndrew Waterman2-3/+5
2021-11-24Clarify effect of changing the set of legal values for a CSR fieldJohn Hauser1-0/+36
2021-11-19Extension is "implemented", not "enabled" (in Svinval) (#780)John Hauser1-1/+1
2021-11-19Explain why mstatus.TVM doesn't affect vsatp, HFENCE.VVMA (#779)John Hauser1-0/+29
2021-11-18H extension requires page-based address translation (#778)John Hauser1-1/+2
2021-11-17Non-normatively remark that high-order PPN bits aren't ignoredAndrew Waterman1-0/+5
2021-11-15Revert "Separate transformation for HLV instructions (#777)"Andrew Waterman1-33/+3
2021-11-15Fix typoAndrew Waterman1-1/+1
2021-11-15Separate transformation for HLV instructions (#777)John Hauser1-3/+33
2021-11-15Memory access traps may write zero to stval (#776)John Hauser1-1/+2
2021-11-12Accesses to pages with mismatched attrs are I/O _and_ memory wrt FENCE (#774)Andrew Waterman1-6/+8
2021-11-12Rename hstatus.HU (#770)John Hauser1-1/+1
2021-11-12Allow more bits of hideleg to be writable (#772)John Hauser1-3/+4
2021-11-12Clarify condition when virtual instruction trap will occur (#773)John Hauser1-1/+1
2021-11-12CSR mideleg masks hideleg, hip, and hie (#771)John Hauser1-0/+3
2021-11-11Rewrite most instances of "hardwire" as "read-only" (#768)John Hauser4-74/+74
2021-11-10Remove trailing whitespace from a.tex (#767)Axel Heider1-1/+1
2021-11-05Document version 20211105-signoffAndrew Waterman1-2/+2
2021-11-04Further relax PMP/address-translation caching interactionsAndrew Waterman1-8/+12
2021-11-02Remove reference to consecutive-SFENCE idiomAndrew Waterman1-5/+0
2021-11-02minor grammatical and stylistic changesAndrew Waterman2-9/+9
2021-11-02Add the Svinval standard extensionDaniel Lustig5-10/+252
2021-11-02Add the Svpbmt standard extensionDaniel Lustig2-20/+128
2021-11-02Add the Svnapot standard extensionDaniel Lustig2-17/+161
2021-11-01Add Sv57 and Sv57x4Daniel Lustig3-27/+205
2021-11-01Merge branch 'master' of github.com:riscv/riscv-isa-manualAndrew Waterman5-49/+255
2021-11-01Merge pull request #759 from riscv/virtual-memory-assortedAndrew Waterman5-49/+255
2021-11-01Remove M-mode details from S-mode chapterAndrew Waterman1-2/+2
2021-11-01Various minor virtual memory clarificationsDaniel Lustig5-49/+255
2021-11-01Back to draft statusAndrew Waterman1-1/+1
2021-10-29Define the Zicntr and Zihpm extensionsAndrew Waterman1-10/+14
2021-10-29Improve text in Zicntr sectionAndrew Waterman1-4/+8
2021-10-28Document version 20211028-signoffAndrew Waterman1-2/+2
2021-10-28Incorporate Steve's feedbackAndrew Waterman1-1/+1
2021-10-25No valid LR/SC reservation upon resetAndrew Waterman1-0/+2
2021-10-05Fix editing error in mtval/stval definitionAndrew Waterman2-71/+53
2021-10-04Clarify order in which PMP CSRs must be implementedAndrew Waterman1-1/+2
2021-10-01Fix permissions of *envcfg CSRsAndrew Waterman1-3/+3
2021-09-30Improve description of FENCE.TSOAndrew Waterman1-5/+4
2021-09-21Add example to clarify mip.SEIP behaviorAndrew Waterman1-0/+8
2021-09-21Bump priv version numberAndrew Waterman1-1/+1
2021-09-15Priv-1.12 spec for public reviewriscv-privileged-20210915-public-reviewAndrew Waterman2-8/+7
2021-09-15JohnH is an editor of the priv specAndrew Waterman1-1/+1
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