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2018-08-30Remove text stating C.ADDI4SPN is RV32C/RV64C-only (#223)Andrew1-3/+3
2018-08-29Generalized description of counter behavior when not accessible.Krste Asanovic1-3/+1
2018-08-29Clarify that mtval/mepc are set on interrupts, tooAndrew Waterman2-5/+5
2018-08-28F/D extensions to v2.2Andrew Waterman3-4/+16
2018-08-27Move out-of-date vector encoding to V chapterAndrew Waterman3-735/+742
2018-08-26Clarified that counter-enable fields don't change underlying counter values.Krste Asanovic1-0/+6
2018-08-26Clarified description of CSR writes to counters per Nikhil's suggestion.Krste Asanovic1-8/+7
2018-08-26Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic2-7/+9
2018-08-26Updated several "user" references to "unprivileged".Krste Asanovic5-12/+13
2018-08-25Clarify that FENCE opcode bits aren't required to be 0Andrew Waterman1-7/+5
2018-08-25Add semihosting noteAndrew Waterman1-0/+4
2018-08-12Fix typoAndrew Waterman1-1/+1
2018-08-12Minor tweaksAndrew Waterman2-4/+4
2018-08-12Improve RV64 32x32->64 text; move to commentaryAndrew Waterman1-4/+9
2018-08-12Tweaks to M extension chapterAndrew Waterman1-8/+8
2018-08-12Removed redundant text that LR can reserve a different subset on each invocat...Krste Asanovic1-3/+1
2018-08-09Added specification that xRET instructions may, but are notKrste Asanovic2-1/+14
2018-08-09Added description of hardware performance counters.Krste Asanovic1-0/+21
2018-08-09Clarified reservation range and that SC only pairs with immediately preceding...Krste Asanovic1-20/+25
2018-08-08Fix spelling errorsAndrew Waterman3-6/+6
2018-08-07Use \geq instead of >=Andrew Waterman2-2/+2
2018-08-07Made cleanup pass over floating-point extensionsKrste Asanovic4-15/+18
2018-08-07Broke out actual perf counters into separate chapter.Krste Asanovic4-179/+201
2018-08-07Clarified A definitions.Krste Asanovic2-29/+20
2018-08-06Removed obsolete commentary.Krste Asanovic1-11/+0
2018-08-06Removed statement that *W instructions are RV64 only.Krste Asanovic1-2/+2
2018-08-06Added comment that we might consider different pattern for RV128 to improve c...Krste Asanovic1-0/+7
2018-08-06Clarified wording in last sentence of Priv Spec section 3.1.12 (mtvec alignme...Rishiyur S. Nikhil1-1/+1
2018-08-06Clarified FENCE.TSO under base implementation.Krste Asanovic1-5/+17
2018-08-06Fix Typo: Recover a lost brace in assembly.tex (#219)Columbus2401-1/+1
2018-08-06Fix typo in syntactic-dependence tableAndrew Waterman1-1/+1
2018-08-06Cleaned up RV64 chapter to remove platform-specific mandates.Krste Asanovic2-8/+18
2018-08-06CSR instructions file.Krste Asanovic1-0/+277
2018-08-06Cleaned up RV32E to remove platform-specific mandates.Krste Asanovic1-40/+14
2018-08-06Moved CSR instructions into separate chapter.Krste Asanovic4-355/+111
2018-08-05Provide new description of misaligned load/store behavior compatible with pri...Krste Asanovic3-82/+122
2018-08-05Minor cleanups and clarifications.Krste Asanovic1-34/+44
2018-08-05update preface.Krste Asanovic1-1/+2
2018-08-05Moved XLEN definition to intro.Krste Asanovic2-11/+12
2018-08-04Updated trap section with feedback from jhauser.Krste Asanovic1-22/+47
2018-08-02Minor change to the operational memory model (#216)Shaked Flur1-1/+2
2018-07-31Improved/revised interrupt/trap terminology.Krste Asanovic1-72/+85
2018-07-30Adding terminology for categories of traps and interrupts.Krste Asanovic1-22/+57
2018-07-30clarificationKrste Asanovic1-1/+1
2018-07-29Minor clarifications.Krste Asanovic1-11/+13
2018-07-29Clarified that AUIPC uses PC of AUIPC instruction itself.Krste Asanovic1-10/+12
2018-07-29Clarified difference between interrupts and traps, and behavior ofKrste Asanovic1-7/+13
2018-07-29Big-endian or bi-endian memory systems should notKrste Asanovic1-7/+7
2018-07-29Added more commentary on illegal instruction encodings.Krste Asanovic1-11/+28
2018-07-29Provide explanation for multiple base ISAs, and ADD/ADDW discrepancy.Krste Asanovic2-14/+86
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