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2018-11-06Version ready for ratification process.Krste Asanovic2-17/+12
2018-11-06CSRRx is called ZicsrAndrew Waterman1-1/+1
2018-11-06Updated status of counters. Not ready for ratification as there are issues o...Krste Asanovic3-5/+9
2018-11-06Separate FENCE.I and CSRRx from RV32I tableAndrew Waterman1-179/+232
2018-11-06Define new RVC format CA; state that C.AND, etc. use itAndrew Waterman1-6/+14
2018-11-06mcycle counts cycles across the entire core, like rdcycleAndrew Waterman1-1/+2
2018-11-06Make pmaddr=FF..FF well-definedAndrew Waterman1-1/+1
2018-11-06Stated bytes are 8 bits and using IEC80000-13:2008Krste Asanovic1-1/+2
2018-11-06Allow access exceptions to be reported on misaligned atomic memory operations...Krste Asanovic2-10/+20
2018-11-06Bumped base I version number to 2.1 to reflect ratified memory model, exclusi...Krste Asanovic3-4/+8
2018-11-06Moved zifencetso back into main I chapter, as does not extend base ISA spec.Krste Asanovic4-80/+17
2018-11-06Gave CSR instruction module a name and a version, and made clear these are be...Krste Asanovic2-4/+5
2018-11-06Made clear that this is only the first standard calling convention.Krste Asanovic1-2/+11
2018-11-05Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic2-15/+15
2018-11-05Update preface for unemulatable misaligned excpetions reported as access exce...Krste Asanovic1-1/+2
2018-11-05Allowed certain un-emulatable misaligned accesses to be reported with access ...Krste Asanovic1-7/+10
2018-11-05tweaksAndrew Waterman1-11/+11
2018-11-05Fix spellingAndrew Waterman2-3/+3
2018-11-05The S in SBI stands for supervisorAndrew Waterman1-1/+1
2018-11-04Moved FENCE.I out of base I chapter into separate Zifencei chapter.Krste Asanovic4-105/+169
2018-11-04Forgot in add new file.Krste Asanovic1-0/+77
2018-11-04Made clear fence.tso is an optional extensionKrste Asanovic1-2/+2
2018-11-03Moved fence.tso out of base ISA chapter and into separate chapter.Krste Asanovic2-17/+2
2018-11-03Clarified language around action of execution environment with misaligned-add...Krste Asanovic1-6/+8
2018-11-03Removed text regarding big or bi-endian operation. For now, only specifying ...Krste Asanovic2-32/+15
2018-11-01Clarify that FP loads/stores don't mutate NaN payloadsAndrew Waterman3-0/+9
2018-11-01Clarification on the meaning of the annotationsAndrew Waterman1-0/+2
2018-10-29Clarify that most integer instructions operate on XLEN bits in RV64Andrew Waterman1-0/+1
2018-10-26A pair of somewhat pedantic changes to the wording of C.NOP (#248)Palmer Dabbelt1-2/+2
2018-10-18WIP on hypervisorAndrew Waterman1-224/+592
2018-10-11Fix an ambiguity in PLIC specAndrew Waterman1-3/+4
2018-10-09Clarify interrupt delegation semantics (#158)Andrew Waterman2-3/+11
2018-10-09Some edits and fixes to memory model sections. (#238)Prashanth Mundkur2-11/+11
2018-10-09Added rationale for fused mul-add instructions.Krste Asanovic1-8/+20
2018-10-09Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-1/+1
2018-10-04Add marchid management document (#234)Andrew Waterman1-1/+1
2018-10-02Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-7/+5
2018-09-26Custom interrupt priorities are customAndrew Waterman1-4/+4
2018-09-24SFENCE behavior is independent of privilege modeAndrew Waterman1-3/+1
2018-09-24Improving lanuage.Krste Asanovic2-7/+7
2018-09-24Made clear that sepc written on exception or interrupt.Krste Asanovic1-4/+4
2018-09-23No need for WIRI definition anymoreAndrew Waterman1-11/+0
2018-09-23Unused PMP fields are WARL 0, not WIRIAndrew Waterman2-2/+3
2018-09-23unused mip fields are wpri instead of wiriAndrew Waterman4-12/+13
2018-09-23unused misa fields are wlrl, not wiriAndrew Waterman2-1/+2
2018-09-23Fix an off-by-one error in defining coarse-grained PMPs for NAPOTAndrew Waterman1-6/+7
2018-09-23hart IDs must be uniqueAndrew Waterman1-1/+1
2018-09-18Fix Figure A.2 to make it draw the correct test (#228)Daniel Lustig3-15/+17
2018-09-10Add ECALL from S-mode cause to SCAUSE tableAndrew Waterman1-2/+3
2018-08-31Removed text that implied there was a maximum alignment requirementKrste Asanovic4-9/+18
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