index
:
riscv-isa-manual.git
1437-update-generated-filenames-to-be-more-desciptive
1454-fix-merge-and-release-workflow
1532-lack-of-list-of-figures-tables
Sv57
Svinval
Svnapot
Svpbmt
antora-refactor
aswaterman-patch-1
atomics-wording-v2
bonzini-hpmdelta
cnop
convert2adoc_rvwmo
csr-wip
dev/beeman/smctr-ssctr
fix-adoc-IDs
fix-fedora-build
hypervisor
kersten1-patch-3
latex
lrsc
main
misa-ztso
msip
mtime-optional
n-ext
pmp
ratified-priv-v1.11-sans-hypervisor-draft
sail-inclusion-example
sfence-asid
smpmpmt
svkt
tmp
trap
v20240411
virtual-memory
wfmi
zam
zfb
ztso-ratification
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2018-01-23
Added commentary on fixed interrupt priority scheme for mip/mie.
Krste Asanovic
1
-0
/
+42
2018-01-23
Standardized on pseudoinstruction.
Krste Asanovic
4
-20
/
+20
2018-01-23
Clarified when mip/mie bits are hardwired to zero when user mode present.
Krste Asanovic
3
-268
/
+537
2018-01-23
Use y instead of a in PMP addresses
Andrew Waterman
1
-8
/
+8
2018-01-10
Instructions with bits [ILEN-1:0] all ones are illegal (#123)
Andrew Waterman
1
-2
/
+6
2018-01-03
Fix typo
Andrew Waterman
1
-2
/
+2
2017-12-28
WIRI/WPRI fields should be hardwired to 0 (#121)
Andrew Waterman
1
-4
/
+8
2017-12-27
Admit that the V extension exists
Andrew Waterman
1
-2
/
+2
2017-12-13
Fix typo
Daniel Lustig
1
-1
/
+1
2017-12-12
Add memory consistency model draft proposal
Andrew Waterman
4
-401
/
+373
2017-12-12
Add (but don't integrate) memory model chapter
Andrew Waterman
1
-0
/
+1838
2017-12-12
Update history
Andrew Waterman
1
-3
/
+15
2017-12-12
Fix inconsistency between RVC text and opcode table
Andrew Waterman
1
-3
/
+3
2017-12-12
Fix typo
Andrew Waterman
1
-1
/
+1
2017-12-12
Describe optional support for misaligned AMOs (#117)
Andrew Waterman
4
-9
/
+49
2017-12-12
Disambiguate
Andrew Waterman
1
-1
/
+1
2017-12-12
hcounteren doesn't exist
Andrew Waterman
1
-1
/
+1
2017-12-11
Fix xIE descriptive error
Andrew Waterman
3
-2
/
+4
2017-12-06
Make explicit that 0xFFFF is an illegal opcode
Andrew Waterman
1
-1
/
+2
2017-12-06
Constrain all harts to use same A/D-bit management scheme
Andrew Waterman
2
-2
/
+2
2017-12-06
Add commentary that FENCE.I doesn't work for migrated threads
Andrew Waterman
1
-0
/
+7
2017-12-03
Merge branch 'master' of github.com:riscv/riscv-isa-manual
Krste Asanovic
5
-5
/
+42
2017-11-27
Add R-type format to priv-instr-table
Andrew Waterman
1
-0
/
+10
2017-11-12
Clarify WLRL semantics
Andrew Waterman
1
-1
/
+1
2017-11-12
Mark useless PMP NAPOT case as reserved
Andrew Waterman
1
-0
/
+1
2017-11-09
Make MPP/SPP WARL fields
Andrew Waterman
2
-3
/
+7
2017-11-09
State that writable-but-not-readable PMPs are reserved
Andrew Waterman
1
-1
/
+2
2017-11-09
Specify meaning of R/W/X bits in PMP
Andrew Waterman
1
-0
/
+8
2017-11-09
Specify meaning of R/W/X bits in PTE
Andrew Waterman
1
-0
/
+13
2017-11-09
Merge branch 'master' of github.com:riscv/riscv-isa-manual
Krste Asanovic
8
-22
/
+1133
2017-11-09
Add hypervisor draft proposal
Andrew Waterman
3
-5
/
+1097
2017-11-09
fix typos
Andrew Waterman
4
-8
/
+8
2017-11-01
Document the 'DYN' mnemonic for dynamic rounding mode (#111)
Alex Bradbury
1
-1
/
+1
2017-10-30
tweak wording
Andrew Waterman
1
-1
/
+1
2017-10-21
Update contributors
Andrew Waterman
1
-1
/
+1
2017-10-20
Specify that user-ISA LR/SC constraints apply to main memory
Andrew Waterman
1
-0
/
+8
2017-10-20
Remove privileged architecture detail from user spec
Andrew Waterman
1
-3
/
+11
2017-10-20
Put the onus on software to align pc/epc when clearing misa.C
Andrew Waterman
1
-0
/
+3
2017-10-11
Fix outdated commentary on mcounteren
Andrew Waterman
1
-2
/
+2
2017-09-26
Generalize an Sv32 sentence to apply to SvXX
Andrew Waterman
1
-1
/
+1
2017-09-21
Merge branch 'master' of github.com:riscv/riscv-isa-manual
Krste Asanovic
3
-17
/
+33
2017-09-20
Remove potential ambiguity in JALR commentary
Andrew Waterman
1
-2
/
+2
2017-09-20
Clarify mtval; allow platform to specify when it's written
Andrew Waterman
2
-15
/
+27
2017-09-20
Describe MSIE/SSIE/USIE
Andrew Waterman
1
-0
/
+4
2017-09-15
Merge branch 'master' of github.com:riscv/riscv-isa-manual
Krste Asanovic
1
-2
/
+2
2017-09-13
Sv48 must imply Sv39
Andrew Waterman
1
-2
/
+2
2017-09-10
Merge branch 'master' of github.com:riscv/riscv-isa-manual
Krste Asanovic
1
-0
/
+4
2017-09-10
Changed names of XnnU to Unn.
Krste Asanovic
1
-14
/
+14
2017-08-31
Update v.tex
respasa
1
-0
/
+4
2017-08-17
Always order interrupt priority by privilege mode
Andrew Waterman
2
-5
/
+5
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