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2018-11-26Clarify which instructions have RM field but don't use itAndrew Waterman1-3/+3
2018-11-26Add FENCE to HINT tableAndrew Waterman1-1/+2
2018-11-21Clarify that mtimecmp writes aren't synchronous with MTIP readsAndrew Waterman1-0/+12
2018-11-21note that xtval is written upon a trapAndrew Waterman1-1/+3
2018-11-21Add counter-inhibit mechanismAndrew Waterman2-0/+65
2018-11-21fix typosAndrew Waterman1-2/+2
2018-11-20Fix colliding labelsAndrew Waterman5-12/+4
2018-11-20Fix minor typos in the operational model. (#277)Prashanth Mundkur1-8/+8
2018-11-20Don't duplicate ECALL/EBREAK encodings between Vols. I and IIAndrew Waterman2-25/+3
2018-11-19Remove comment about side effects on writesAndrew Waterman1-4/+3
2018-11-16Improved wording.Krste Asanovic1-2/+2
2018-11-16Clarified that LR/SC forward progress guarantee might only hold for a subset ...Krste Asanovic1-3/+5
2018-11-16Change funct to funct2 in the CA format (#262)Luís Marques1-2/+2
2018-11-16Clarified behavior of CSR instructions with respect to read and write side ef...Krste Asanovic1-4/+48
2018-11-09WFI is not a HINTAndrew Waterman2-4/+3
2018-11-07Re-version spec to 20181221-Public-Review-draftAndrew Waterman1-1/+1
2018-11-07Describe the AMOs as "bitwise", not "logical" (#259)Palmer Dabbelt1-2/+2
2018-11-06spelling20181106-Base-RatificationAndrew Waterman2-2/+2
2018-11-06Version ready for ratification process.Krste Asanovic2-17/+12
2018-11-06CSRRx is called ZicsrAndrew Waterman1-1/+1
2018-11-06Updated status of counters. Not ready for ratification as there are issues o...Krste Asanovic3-5/+9
2018-11-06Separate FENCE.I and CSRRx from RV32I tableAndrew Waterman1-179/+232
2018-11-06Define new RVC format CA; state that C.AND, etc. use itAndrew Waterman1-6/+14
2018-11-06mcycle counts cycles across the entire core, like rdcycleAndrew Waterman1-1/+2
2018-11-06Make pmaddr=FF..FF well-definedAndrew Waterman1-1/+1
2018-11-06Stated bytes are 8 bits and using IEC80000-13:2008Krste Asanovic1-1/+2
2018-11-06Allow access exceptions to be reported on misaligned atomic memory operations...Krste Asanovic2-10/+20
2018-11-06Bumped base I version number to 2.1 to reflect ratified memory model, exclusi...Krste Asanovic3-4/+8
2018-11-06Moved zifencetso back into main I chapter, as does not extend base ISA spec.Krste Asanovic4-80/+17
2018-11-06Gave CSR instruction module a name and a version, and made clear these are be...Krste Asanovic2-4/+5
2018-11-06Made clear that this is only the first standard calling convention.Krste Asanovic1-2/+11
2018-11-05Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic2-15/+15
2018-11-05Update preface for unemulatable misaligned excpetions reported as access exce...Krste Asanovic1-1/+2
2018-11-05Allowed certain un-emulatable misaligned accesses to be reported with access ...Krste Asanovic1-7/+10
2018-11-05tweaksAndrew Waterman1-11/+11
2018-11-05Fix spellingAndrew Waterman2-3/+3
2018-11-05The S in SBI stands for supervisorAndrew Waterman1-1/+1
2018-11-04Moved FENCE.I out of base I chapter into separate Zifencei chapter.Krste Asanovic4-105/+169
2018-11-04Forgot in add new file.Krste Asanovic1-0/+77
2018-11-04Made clear fence.tso is an optional extensionKrste Asanovic1-2/+2
2018-11-03Moved fence.tso out of base ISA chapter and into separate chapter.Krste Asanovic2-17/+2
2018-11-03Clarified language around action of execution environment with misaligned-add...Krste Asanovic1-6/+8
2018-11-03Removed text regarding big or bi-endian operation. For now, only specifying ...Krste Asanovic2-32/+15
2018-11-01Clarify that FP loads/stores don't mutate NaN payloadsAndrew Waterman3-0/+9
2018-11-01Clarification on the meaning of the annotationsAndrew Waterman1-0/+2
2018-10-29Clarify that most integer instructions operate on XLEN bits in RV64Andrew Waterman1-0/+1
2018-10-26A pair of somewhat pedantic changes to the wording of C.NOP (#248)Palmer Dabbelt1-2/+2
2018-10-18WIP on hypervisorAndrew Waterman1-224/+592
2018-10-11Fix an ambiguity in PLIC specAndrew Waterman1-3/+4
2018-10-09Clarify interrupt delegation semantics (#158)Andrew Waterman2-3/+11
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