riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2017-05-05	Remove option to hardwire UXL/SXL to 0	Andrew Waterman	2	-14/+17

2017-05-05	PPN LSBs must be clear for superpage PTEs	Andrew Waterman	1	-1/+6

2017-05-05	Remove redundant clause in SFENCE.VMA description	Andrew Waterman	1	-3/+1

2017-05-04	Reserve D/A/U bits	Andrew Waterman	1	-0/+3

2017-05-03	Clarified result of REM*W on divide by zero.	Krste Asanovic	1	-15/+18

2017-05-03	Changed front page of spec to follow move to Creative Commons License.	Krste Asanovic	2	-10/+34

2017-05-02	Clarify commentary	Andrew Waterman	1	-1/+1

2017-05-02	Incorporate Anthony Coulter's feedback	Andrew Waterman	2	-10/+25

2017-04-27	Improve ECALL text	Andrew Waterman	1	-1/+1

2017-04-27	Describe ECALL/EBREAK operation in privileged architecture	Andrew Waterman	2	-1/+74

2017-04-25	Clean up JALR hint text	Andrew Waterman	2	-7/+9

2017-04-24	Modified behavior of JALR hint bits to better support macro-op fusion of ↵	Krste Asanovic	3	-9/+53
	LUI;JALR pair.
2017-04-20	Make mcause table easier to understand	Andrew Waterman	1	-6/+6

2017-04-20	Improve stval/mtval warl text	Andrew Waterman	2	-10/+16

2017-04-17	Recommend LR for sequentially consistent loads	Andrew Waterman	1	-6/+6

2017-04-17	mepc, sepc, mtval, and stval are WARL	Andrew Waterman	2	-0/+20
	Closes #49.
2017-04-16	Define the behavior of FMA(inf, 0, qNaN)	Andrew Waterman	2	-0/+9

2017-04-16	Formatting fixes	Andrew Waterman	1	-5/+5

2017-04-14	Fix FMV.X.W/FMV.W.X in instruction listings	Andrew Waterman	1	-2/+2

2017-04-13	Renamed FMV.X.S/S.X to FMV.X.W/W.X to be more consistent with load/store ↵	Krste Asanovic	4	-17/+29
	instructions.
2017-04-13	Clarified transfers out of f registers and conversion instructions.	Krste Asanovic	1	-1/+10

2017-04-13	Added the NaN-boxing scheme for narrower floating-point values held in wider ↵	Krste Asanovic	4	-38/+97
	floating-point values.
2017-04-11	stval is optionally written with bad instruction, as with mtval	Andrew Waterman	1	-0/+14

2017-04-11	mtval/stval are zeroed for other exceptions	Andrew Waterman	2	-3/+6
	Closes #47.
2017-04-11	Clarify [s/m][epc/tval/cause] are only written on exceptions into that mode	Andrew Waterman	2	-17/+41

2017-04-11	SPTBR -> SATP	Andrew Waterman	4	-33/+35
	Closes #24.
2017-04-10	Make immediate signs explicit in RVC table	Andrew Waterman	2	-56/+56
	Adapted from @DSHorner's #31
2017-04-10	Clarify WFI w.r.t. interrupt delegation	Andrew Waterman	1	-4/+5

2017-04-09	Fix typo	Andrew Waterman	1	-1/+1

2017-04-09	Fix typo	Andrew Waterman	1	-1/+1

2017-04-07	Reserve LSBs of stvec.	Andrew Waterman	1	-3/+5

2017-04-07	Add vectored interrupts	Andrew Waterman	1	-17/+40
	Closes #6.
2017-04-02	Improved rationale for AMO selection.	Krste Asanovic	2	-12/+17

2017-04-02	Added rationale for choice of divide overflow results.	Krste Asanovic	1	-0/+8

2017-03-31	Incorporate PMP feedback	Andrew Waterman	2	-3/+6

2017-03-31	Commentary on 'mtval' refers to 'mtbadinst' instead of 'mtval'	Michael Clark	1	-1/+1

2017-03-30	Update PMP CSR listing	Andrew Waterman	1	-4/+8

2017-03-30	Modify PMP encoding and improve description	Andrew Waterman	1	-67/+59

2017-03-30	PMP cleanup	Andrew Waterman	1	-6/+8

2017-03-29	Clarify that misaligned accesses violating PMPs become partially visible	Andrew Waterman	1	-3/+11

2017-03-29	Fix typo	Andrew Waterman	1	-1/+1

2017-03-29	Add PMP to preface	Andrew Waterman	1	-0/+1

2017-03-29	Improve PMP section	Andrew Waterman	2	-45/+241

2017-03-28	First draft of PMP spec	Andrew Waterman	1	-20/+149

2017-03-28	Renamed mbadbits to mtval (for "Trap Value") to be more generic name for ↵	Krste Asanovic	3	-23/+23
	register containing data related to the current trap.
2017-03-28	Add preface entry for page fault cause renumbering	Andrew Waterman	1	-0/+4

2017-03-28	Separate access faults from VM faults	Andrew Waterman	2	-24/+62

2017-03-27	Added David Horner's suggestion of faster way to test for base ISA width if ↵	Krste Asanovic	1	-2/+4
	misa is zero.
2017-03-26	Replaced mbadaddr with mbadbits register, which can now capture bad	Krste Asanovic	4	-21/+75
	instruction bits on an illegal instruction fault.
2017-03-24	Simplified MXL/SXL/UXL design. Now, no checks for monotonically decreasing ↵	Krste Asanovic	1	-36/+53
	XLEN with lower privilege modes, and no state propagation between CSRs.