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2017-03-21Added rationale for removal of machine-mode base-and-bounds schemes for now.Krste Asanovic1-2/+9
2017-03-20Small changes.Krste Asanovic1-5/+5
2017-03-20Specify encoding of mvendorid fieldAndrew Waterman1-4/+16
2017-03-20Clarified that RISC-V uses two's-complement arithmetic for signed integer val...Krste Asanovic1-1/+3
2017-03-20Changed mvendorid to hold the JEDEC manufacturer code for the core vendor as ...Krste Asanovic2-8/+14
2017-03-20Now mideleg /medeleg only exist if lower privilege mode exists and can take t...Krste Asanovic2-2/+12
2017-03-20Removed explicit convention on shadow CSRs.Krste Asanovic3-20/+29
2017-03-20Add changelog entries for PUM -> SUM and MXRAndrew Waterman1-0/+3
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman2-37/+49
2017-03-19fix typoAndrew Waterman1-2/+2
2017-03-19Excised H-mode from spec.Krste Asanovic10-289/+280
2017-03-19Fixed up licence and contributor details on front page.Krste Asanovic2-15/+38
2017-03-18Software shouldn't use misaligned accesses on non-idempotent regionsAndrew Waterman1-0/+7
2017-03-16Simplify interrupt-stack disciplineAndrew Waterman3-9/+7
2017-03-13Add TSR mechanismAndrew Waterman1-6/+21
2017-03-13Fix setvl descriptionAndrew Waterman1-4/+4
2017-03-13C.SLLI takes both rs1 and rd argsAndrew Waterman1-2/+2
2017-03-10Fix quadrant for C.ADD/C.MV/C.EBREAKAndrew Waterman1-3/+3
2017-03-07Update UXL/SXL languageAndrew Waterman1-25/+21
2017-03-07Make some supervisor fields WPRIAndrew Waterman2-20/+79
2017-03-06One liners to correct register designation in rvc-instr-tableDavid Horner1-3/+3
2017-03-06fix typoAndrew Waterman1-1/+1
2017-03-03misa Base => MXLAndrew Waterman2-15/+15
2017-03-01Added placeholder for J extension.Krste Asanovic6-2/+18
2017-02-27Fix typoAndrew Waterman2-2/+3
2017-02-26Add TW bitAndrew Waterman1-12/+24
2017-02-26Incorporate more Hauser feedbackAndrew Waterman3-23/+28
2017-02-26Expand PPN to 44 bits in Sv39/Sv48 PTEsAndrew Waterman1-15/+15
2017-02-26SX -> SXLAndrew Waterman2-25/+25
2017-02-25Expand sptbr.MODE field; don't spec Sv57/Sv64 for nowAndrew Waterman1-285/+23
2017-02-25Add Paolo to acknowledgementsAndrew Waterman1-1/+1
2017-02-24Incorporate most of Hauser's feedbackAndrew Waterman3-6/+155
2017-02-24Clarify that traps don't delegate downwardsAndrew Waterman2-2/+11
2017-02-23Clarify FS=Off behaviorAndrew Waterman1-3/+6
2017-02-22Add Sv57 and Sv64Andrew Waterman1-20/+295
2017-02-21Move counter-enable CSRs to trap-setup CSR spaceAndrew Waterman1-9/+3
2017-02-20mhcounteren -> mcounteren; mucounteren -> scounterenAndrew Waterman4-19/+90
2017-02-19Make hardware management of A/D bits optionalAndrew Waterman2-14/+29
2017-02-15Add signed array bounds comparison noteAndrew Waterman1-0/+5
2017-02-15Fix unsigned overflow exampleAndrew Waterman1-1/+1
2017-02-15Expanded explanation of handling integer overflow with base ISA.Krste Asanovic1-15/+24
2017-02-15Improve signed overflow commentaryAndrew Waterman1-10/+15
2017-02-14Add priv-1.10 prefaceAndrew Waterman2-1/+15
2017-02-14First draft of SFENCE.VMAAndrew Waterman2-97/+133
2017-02-14typoKrste Asanovic1-1/+1
2017-02-14Typo.Krste Asanovic1-1/+1
2017-02-13Remove mstatus.VM, Mbb, Mbbid; add sptbr.MODEAndrew Waterman3-305/+64
2017-02-13Clarified instruction misaligned exceptions on JAL/JALR.Krste Asanovic2-9/+15
2017-02-13Updated copyright/licence information.Krste Asanovic2-17/+19
2017-02-02Clarify behavior of FCSR MSBsAndrew Waterman2-1/+8
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