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2018-07-06Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic2-6/+13
2018-07-06C extension is no longer a draft proposal.Krste Asanovic1-1/+1
2018-07-06Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194)Alexandre Joannou2-6/+13
2018-07-06Remove sbi.tex from the root directory. (#211)Atish Patra1-77/+0
2018-07-06Two more small bits of memory model commentary. (#210)Daniel Lustig1-6/+10
2018-07-06Changes to intro as part of rationalizing ISA into ISA-only versus platform-m...Krste Asanovic3-22/+28
2018-07-06Explain how addressing works when UXLEN < SXLENAndrew Waterman1-0/+5
2018-07-06Merge branch 'misc-fixes' of https://github.com/tymcauley/riscv-isa-manual in...Andrew Waterman6-7/+7
2018-07-05FST -> FSDAndrew Waterman2-3/+3
2018-07-05Version the appendices.Daniel Lustig1-5/+9
2018-07-05FLD and FST are not atomic unless XLEN>=64Daniel Lustig2-3/+6
2018-07-05Small updates to the Ztso specDaniel Lustig1-7/+11
2018-07-05Address some feedback from Ken DockserDaniel Lustig1-6/+9
2018-07-02For the hypervisor extension, change the names of S-mode and U-mode (#206)jhauser-us1-96/+100
2018-06-26Clarification of NOP descriptionwdc-pnl1-2/+4
2018-06-25Typo: Figure A.7 -> Table A.7Daniel Lustig1-1/+1
2018-06-25Correct some memory model explanation typos.Daniel Lustig1-3/+3
2018-06-22Fixed spelling error in memory.tex.Tynan McAuley1-1/+1
2018-06-20Clarify reserved FENCE.TSO settings, per #186Daniel Lustig1-4/+7
2018-06-20Clarify that AMOs are always semantically storesDaniel Lustig1-1/+1
2018-06-18Clarified description of fused multiply-add instructions. (#200)tymcauley1-8/+12
2018-06-18Correct an instance of lr{w|d}.aq.rl to lr{w|d}.aqrl (#199)Alex Bradbury1-1/+1
2018-06-18Strengthen guidance on the need to clear a reservation using SC (#198)Alex Bradbury1-2/+3
2018-06-16Fixed register name formatting error in c.tex.Tynan McAuley1-1/+1
2018-06-16Fixed instruction formatting error in rv32.tex.Tynan McAuley1-1/+1
2018-06-16Fixed spelling error in rvwmo.tex.Tynan McAuley1-1/+1
2018-06-16Fixed register name formatting error in rv32.tex.Tynan McAuley1-1/+1
2018-06-16Fixed grammar inconsistency in a.tex.Tynan McAuley1-1/+1
2018-06-16Fixed spelling error in intro.tex.Tynan McAuley1-1/+1
2018-06-14Fix outdated commentary about LR/SC and context switchingAndrew Waterman1-6/+2
2018-06-11Remove misleading note about AMOSWAP elisionAndrew Waterman1-6/+0
2018-06-11Explicitly mention that FS may be imprecise (#192)Andrew Waterman1-0/+13
2018-06-10Switch to active voice (#191)Cornelius Diekmann1-2/+2
2018-06-10Fix some typos in v.tex (#190)Felix Yan1-2/+2
2018-06-07FENCE.TSO is not a pseudoinstructionAndrew Waterman1-1/+0
2018-06-07FENCE.TSO takes no operandsAndrew Waterman1-1/+1
2018-06-06Clarify sign-extension of offsets in assembly manualAndrew Waterman2-16/+18
2018-06-06fix typoAndrew Waterman1-1/+1
2018-06-06Expand divide-by-0 table to cover the *W instructionsAndrew Waterman1-22/+21
2018-06-01Add Alexandre Joannou to contributorsAndrew Waterman1-1/+2
2018-06-01Clarify order of MULHSU operandsAndrew Waterman1-2/+3
2018-05-30ILEN is always a multiple of IALIGNAndrew Waterman1-1/+1
2018-05-30Hyphenate "instruction set" when it's part of a noun phraseAndrew Waterman11-16/+16
2018-05-30FDIV.S and FSUB.S disambiguation (#180)Alexandre Joannou1-6/+7
2018-05-30Disambiguate division operands (#179)Alexandre Joannou1-2/+2
2018-05-25PMP changes need an SFENCE when VM is enabledAndrew Waterman1-0/+25
2018-05-23Add files not present in some TeX distributionsAndrew Waterman2-0/+1635
2018-05-19Added commentary on purpose of static rounding modes.draft-20180524001518-9981ad7Krste Asanovic1-1/+6
2018-05-08Specify operand order for sub instruction (#172)Alexandre Joannou1-3/+4
2018-05-06Luke's feedbackAndrew Waterman2-2/+3
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