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AgeCommit message (Expand)AuthorFilesLines
2019-06-25Don't mandate that multiple harts on a core share mcyclePalmer Dabbelt1-1/+1
2019-06-25Indicate that mcycle can be shared between hartsPalmer Dabbelt1-2/+6
2019-06-21Merge pull request #397 from riscv/endiannessAndrew Waterman5-15/+90
2019-06-21Clarify PC behavior when XLEN < max supported XLENAndrew Waterman1-0/+2
2019-06-21State endianness assumption of code exampleAndrew Waterman1-2/+3
2019-06-21Clarify sign of REM; add commentaryAndrew Waterman2-2/+10
2019-06-21Changes to unprivileged spec for bi[g]-endian supportAndrew Waterman4-13/+38
2019-06-21Bump version of unprivileged spec to 20190621-draftAndrew Waterman2-2/+52
2019-06-21Fix bad RV32I chapter formattingAndrew Waterman1-48/+48
2019-06-21Clarify SBE/SFENCE interactionAndrew Waterman1-1/+12
2019-06-21Update contributorsAndrew Waterman1-1/+2
2019-06-21Fix preface styleAndrew Waterman1-2/+2
2019-06-21Add mstatush to prefaceAndrew Waterman1-0/+2
2019-06-21Need SFENCE after change to SBEAndrew Waterman1-0/+3
2019-06-21SpellingAndrew Waterman2-2/+2
2019-06-21Bi-endian systems reset as little-endianAndrew Waterman1-0/+2
2019-06-21Add commentaryAndrew Waterman1-0/+9
2019-06-19Add endianness control proposal to priv specAndrew Waterman4-37/+198
2019-06-16Bump priv spec to v1.12-draftAndrew Waterman2-6/+40
2019-06-16Hypervisor v0.4 draftAndrew Waterman3-314/+379
2019-06-08Added text to indicate this is the ratified 1.11 version of the spec.Ratified-IMFDQC-and-Priv-v1.11Krste Asanovic2-6/+7
2019-06-08Updated preface to indicate this is now ratified spec.Krste Asanovic2-19/+19
2019-05-31Tiny editorial fixPhilipp Wagner1-1/+1
2019-05-21Adding FENCE to the table of RV64 HINT instructions (#387)Luís Marques1-1/+2
2019-05-15Correct iteration in LR/SC CAS example. (#384)David-Horner1-2/+3
2019-05-14zimm -> uimm in CSR instruction listingAndrew Waterman1-3/+3
2019-05-09Clarify reserved/HINT encodings in C chapter text (#382)Andrew Waterman1-21/+54
2019-05-07Clarify the behaviour of LR.W/D and SC.W/DColumbus2401-7/+9
2019-05-06Add note about FLE vs. BGE inconsistencyAndrew Waterman1-0/+7
2019-05-04Typos (#379)Alexandre Joannou2-2/+2
2019-04-23Update contributorsAndrew Waterman1-1/+1
2019-04-20Merge pull request #373 from riscv/hellwig-sbiKrste Asanovic2-33/+24
2019-04-20Express stvec alignment constraint more clearlyAndrew Waterman1-5/+4
2019-04-19Don't reference the SBI in normative privileged spec sectionsAndrew Waterman2-33/+24
2019-04-19Clarify hypervisor/PLIC sentimentAndrew Waterman1-4/+8
2019-04-19Remove outdated clause indicating incorrect exception prioritiesAndrew Waterman1-3/+4
2019-04-18Fix erroneous captionAndrew Waterman1-1/+1
2019-04-17Finesse ligatures to work with Adobe Acrobat Reader search and cut-and-pastePaul Donahue2-0/+8
2019-04-15Update CSR access ordering section to clarify ordering is two-sidedAndrew Waterman1-8/+10
2019-04-11clarify in commentary that environment break == EBREAKAndrew Waterman1-1/+1
2019-04-11Explain when sideleg/sedeleg must existAndrew Waterman1-0/+6
2019-04-11forgot to bump hypervisor spec draft versionAndrew Waterman1-1/+1
2019-04-08Elucidate two uses of the word "error"Andrew Waterman2-2/+4
2019-04-05Version 20190405-Priv-MSU-Ratification for ratification votePriv-MSU-Ratification-20190405Andrew Waterman1-2/+2
2019-04-05Privileged Spec: Add dscratch0/1 to CSR listing (#361)Philipp Wagner1-1/+2
2019-04-05mtime is a read-write registerAndrew Waterman1-1/+1
2019-03-28mhpmcounters are WARLAndrew Waterman1-1/+7
2019-03-26Add preface entry for mcountinhibit CSRAndrew Waterman1-0/+2
2019-03-26Minor grammar fix (#357)pdonahue-ventana1-1/+1
2019-03-25Change "pc" to "address" for clarityAndrew Waterman2-6/+7
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