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2022-03-01Svpbmt cannot override vacant PMA regions. (#826)Paul Donahue1-0/+2
2022-02-23Improve description of SvnapotAndrew Waterman1-6/+6
2021-12-03Relax Svpbmt sequence slightlyAndrew Waterman1-3/+1
2021-11-30Rework the description of exceptions for Svinval (#786)John Hauser1-8/+9
2021-11-29Priv specs are ratifiedAndrew Waterman1-1/+1
2021-11-29Remark that Svnapot and Svpbmt require Sv39Andrew Waterman1-0/+4
2021-11-29Move SFENCE.VMA/satp.MODE remark to better locationAndrew Waterman1-4/+4
2021-11-28Add VS fieldAndrew Waterman1-2/+2
2021-11-28Split RV32 [v]sstatus figures into two rowsAndrew Waterman1-17/+29
2021-11-26Specify a sequence to regain coherence wrt. mismatched PBMTsAndrew Waterman1-12/+33
2021-11-26Clarify when SFENCE.VMA/HFENCE.GVMA need be executedAndrew Waterman1-1/+2
2021-11-19Extension is "implemented", not "enabled" (in Svinval) (#780)John Hauser1-1/+1
2021-11-17Non-normatively remark that high-order PPN bits aren't ignoredAndrew Waterman1-0/+5
2021-11-15Fix typoAndrew Waterman1-1/+1
2021-11-12Accesses to pages with mismatched attrs are I/O _and_ memory wrt FENCE (#774)Andrew Waterman1-6/+8
2021-11-11Rewrite most instances of "hardwire" as "read-only" (#768)John Hauser1-8/+8
2021-11-02Remove reference to consecutive-SFENCE idiomAndrew Waterman1-5/+0
2021-11-02minor grammatical and stylistic changesAndrew Waterman1-6/+6
2021-11-02Add the Svinval standard extensionDaniel Lustig1-0/+190
2021-11-02Add the Svpbmt standard extensionDaniel Lustig1-20/+125
2021-11-02Add the Svnapot standard extensionDaniel Lustig1-13/+154
2021-11-01Add Sv57 and Sv57x4Daniel Lustig1-7/+150
2021-11-01Remove M-mode details from S-mode chapterAndrew Waterman1-2/+2
2021-11-01Various minor virtual memory clarificationsDaniel Lustig1-41/+201
2021-10-05Fix editing error in mtval/stval definitionAndrew Waterman1-30/+26
2021-09-10Generalize SSIP to support forthcoming interrupt controllers (#726)Andrew Waterman1-5/+2
2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman1-0/+116
2021-09-08FIOM may be hardwired when satp is hardwiredAndrew Waterman1-0/+2
2021-09-02Describe purpose of FIOM mechanismAndrew Waterman1-0/+39
2021-09-01Clarify widths of privileged CSRs (#728)John Hauser1-23/+28
2021-08-29FIOM affects aq/rl, tooAndrew Waterman1-0/+5
2021-08-29Add henvcfg/senvcfg CSRsAndrew Waterman1-0/+70
2021-08-11Interrupt conditions are also evaluated on falling edgesAndrew Waterman1-1/+2
2021-08-11Generalize interrupt trap condition evaluation conditions (#705)Andrew Waterman1-1/+2
2021-08-06Clarify mepc invalid address conversionAndrew Waterman1-4/+6
2021-08-05Improve description of interrupt traps (#701)Andrew Waterman1-7/+14
2021-07-06Clarify that SFENCE.VMA isn't required for SbareAndrew Waterman1-0/+4
2021-06-26Add non-normative text about VIPT caches not being exposedAndrew Waterman1-0/+9
2021-05-23Fix hyphenationAndrew Waterman1-1/+1
2021-04-23Minor mstatus and sstatus layout edits. (#642)Steven Bellock1-9/+9
2021-04-21SUM should be hardwired to 0 for cores without paging (#641)Andrew Waterman1-0/+2
2020-10-13Both HWBPs and EBREAKs populate mtval (#601)Andrew Waterman1-2/+3
2020-09-28Clarify that "exception code" is used for both exceptions and interruptsAndrew Waterman1-1/+1
2020-09-28Revert "Add VA canonicalization check to Translation Process section"Andrew Waterman1-15/+7
2020-08-25Change "hardwired to other field" to "read-only field" (#571)John Hauser1-3/+4
2020-08-24TweakAndrew Waterman1-2/+2
2020-08-24Clarify that ASIDs are (currently) local to a hartAndrew Waterman1-12/+11
2020-08-14Change "reserved for custom" to "designated for custom" (#566)John Hauser1-6/+6
2020-08-03Fix formatting of 2^XLENAndrew Waterman1-1/+1
2020-07-31Add missing wordAndrew Waterman1-1/+1
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