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AgeCommit message (Expand)AuthorFilesLines
2017-12-06Constrain all harts to use same A/D-bit management schemeAndrew Waterman1-2/+1
2017-11-09Specify meaning of R/W/X bits in PTEAndrew Waterman1-0/+13
2017-11-09fix typosAndrew Waterman1-3/+3
2017-09-26Generalize an Sv32 sentence to apply to SvXXAndrew Waterman1-1/+1
2017-09-20Clarify mtval; allow platform to specify when it's writtenAndrew Waterman1-7/+13
2017-09-13Sv48 must imply Sv39Andrew Waterman1-2/+2
2017-08-15Load address misaligned exceptions *can* occur in S-modeAndrew Waterman1-8/+9
2017-07-26Fix typo in stvec figureAndrew Waterman1-1/+1
2017-06-12Clarify access exception type in page-table walk algorithmAndrew Waterman1-2/+3
2017-06-12Fix word case, typos and word choicePaul Wise1-1/+1
2017-06-03Fix typoJacob Bachmeyer1-1/+1
2017-06-03Tweak SUM commentaryAndrew Waterman1-19/+14
2017-06-03Forbid S-mode execution from user memoryJacob Bachmeyer1-4/+25
2017-06-03Incorporate Allen's feedbackAndrew Waterman1-4/+6
2017-05-15Fix some orphaned/widowed commentary sectionsAndrew Waterman1-2/+2
2017-05-15Add ILEN to simplify descriptions of {m,s}tval CSRsJacob Bachmeyer1-13/+16
2017-05-07Add stvec vectoringAndrew Waterman1-8/+45
2017-05-07Misaligned superpages generate page-fault exceptionsAndrew Waterman1-13/+10
2017-05-06Added note about dropping config string for now. Some other cleanups.Krste Asanovic1-5/+1
2017-05-06Fixed some lingering references to bad address register.Krste Asanovic1-2/+2
2017-05-06Cleaned up description of SEIP/UEIP.Krste Asanovic1-14/+19
2017-05-05Attempt to explain SEIP disciplineAndrew Waterman1-4/+18
2017-05-05Remove option to hardwire UXL/SXL to 0Andrew Waterman1-4/+7
2017-05-05PPN LSBs must be clear for superpage PTEsAndrew Waterman1-1/+6
2017-05-05Remove redundant clause in SFENCE.VMA descriptionAndrew Waterman1-3/+1
2017-05-04Reserve D/A/U bitsAndrew Waterman1-0/+3
2017-05-02Incorporate Anthony Coulter's feedbackAndrew Waterman1-8/+22
2017-04-20Improve stval/mtval warl textAndrew Waterman1-5/+8
2017-04-17mepc, sepc, mtval, and stval are WARLAndrew Waterman1-0/+10
2017-04-11stval is optionally written with bad instruction, as with mtvalAndrew Waterman1-0/+14
2017-04-11mtval/stval are zeroed for other exceptionsAndrew Waterman1-2/+4
2017-04-11Clarify [s/m][epc/tval/cause] are only written on exceptions into that modeAndrew Waterman1-11/+22
2017-04-11SPTBR -> SATPAndrew Waterman1-28/+28
2017-04-07Reserve LSBs of stvec.Andrew Waterman1-3/+5
2017-03-29Fix typoAndrew Waterman1-1/+1
2017-03-29Improve PMP sectionAndrew Waterman1-4/+4
2017-03-28Separate access faults from VM faultsAndrew Waterman1-19/+45
2017-03-26Replaced mbadaddr with mbadbits register, which can now capture badKrste Asanovic1-5/+5
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman1-22/+33
2017-03-19Excised H-mode from spec.Krste Asanovic1-1/+1
2017-03-16Simplify interrupt-stack disciplineAndrew Waterman1-7/+4
2017-03-07Make some supervisor fields WPRIAndrew Waterman1-19/+78
2017-03-03misa Base => MXLAndrew Waterman1-1/+1
2017-02-26Incorporate more Hauser feedbackAndrew Waterman1-7/+7
2017-02-26Expand PPN to 44 bits in Sv39/Sv48 PTEsAndrew Waterman1-15/+15
2017-02-26SX -> SXLAndrew Waterman1-2/+2
2017-02-25Expand sptbr.MODE field; don't spec Sv57/Sv64 for nowAndrew Waterman1-285/+23
2017-02-24Incorporate most of Hauser's feedbackAndrew Waterman1-0/+10
2017-02-22Add Sv57 and Sv64Andrew Waterman1-20/+295
2017-02-20mhcounteren -> mcounteren; mucounteren -> scounterenAndrew Waterman1-0/+53
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