| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2018-12-20 | Clarify that PTE updates aren't atomic w.r.t. the ultimate access (#308) | Andrew Waterman | 1 | -3/+9 | |
| I claim that this follows from the text in the following section, but it is clearly deserving of clarification. https://groups.google.com/a/groups.riscv.org/forum/?utm_medium=email&utm_source=footer#!msg/isa-dev/EQQGObY1bQM/xm6imw-aCwAJ | |||||
| 2018-12-04 | Version of priv spec ready for ratification process | Andrew Waterman | 1 | -1/+1 | |
| 2018-12-03 | Mostly remove RV128 from priv spec, for now | Andrew Waterman | 1 | -4/+4 | |
| 2018-12-03 | S-mode edits | Andrew Waterman | 1 | -5/+5 | |
| 2018-12-02 | Use date-based versioning scheme for priv spec | Andrew Waterman | 1 | -1/+1 | |
| 2018-11-30 | Add commentary about MTIP etc. in sip/sie | Andrew Waterman | 1 | -0/+5 | |
| Closes #240 | |||||
| 2018-11-27 | Remove upper bound on stvec.MODE=Vectored alignment, like mtvec | Andrew Waterman | 1 | -2/+1 | |
| 2018-11-27 | Misc. address translation clarifications | Andrew Waterman | 1 | -8/+9 | |
| Courtesy @gameboo in #205 | |||||
| 2018-11-05 | Fix spelling | Andrew Waterman | 1 | -1/+1 | |
| 2018-11-05 | The S in SBI stands for supervisor | Andrew Waterman | 1 | -1/+1 | |
| Resolves #251 | |||||
| 2018-09-24 | Improving lanuage. | Krste Asanovic | 1 | -3/+3 | |
| Closed #215 | |||||
| 2018-09-24 | Made clear that sepc written on exception or interrupt. | Krste Asanovic | 1 | -4/+4 | |
| 2018-09-23 | unused mip fields are wpri instead of wiri | Andrew Waterman | 1 | -3/+3 | |
| 2018-09-10 | Add ECALL from S-mode cause to SCAUSE table | Andrew Waterman | 1 | -2/+3 | |
| This won't ever happen if medeleg[9] is hardwired to 0, but medeleg[9] isn't required to be hardwired to 0. | |||||
| 2018-07-12 | Add commentary that we favor zero-extension unless SW demands otherwise | Andrew Waterman | 1 | -0/+10 | |
| 2018-07-06 | Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194) | Alexandre Joannou | 1 | -2/+4 | |
| * Help the reader by pointing at TVM and TW in the relevant sections * Mention TSR field in SRET description * Avoid leaking M-mode details in S-mode text. * Added a ref in SFENCE.VMA paragraph (PMP synchronization) | |||||
| 2018-07-06 | Explain how addressing works when UXLEN < SXLEN | Andrew Waterman | 1 | -0/+5 | |
| 2018-04-25 | SvXX instruction addresses are checked for sign extension, too | Andrew Waterman | 1 | -2/+4 | |
| 2018-04-17 | Misaligned superpage exception occurs if pte.ppn[i−1:0]!=0 | Premjith | 1 | -1/+1 | |
| 2018-04-13 | Remove hyphen from M-XLEN etc. | Andrew Waterman | 1 | -18/+18 | |
| 2018-04-13 | Resolve XLEN vs. S-XLEN ambiguities | Andrew Waterman | 1 | -34/+34 | |
| 2018-03-30 | Make it explicit that the page-fault exceptions from address translation ↵ | Prashanth Mundkur | 1 | -5/+8 | |
| correspond to the original access type, as is done for access exceptions. | |||||
| 2018-03-26 | Clarify that SUM does not permit supervisor execution from user pages | Andrew Waterman | 1 | -0/+1 | |
| This is already written in the SUM section, but it's better to have it in both places. | |||||
| 2018-03-21 | John Hauser's alternative writable-misa.C proposal | Andrew Waterman | 1 | -2/+8 | |
| This one removes implementation-defined behavior but is still sane to implement. | |||||
| 2018-02-22 | Fix mepc/sepc definitions w.r.t. IALIGN | Andrew Waterman | 1 | -3/+2 | |
| 2017-12-06 | Constrain all harts to use same A/D-bit management scheme | Andrew Waterman | 1 | -2/+1 | |
| 2017-11-09 | Specify meaning of R/W/X bits in PTE | Andrew Waterman | 1 | -0/+13 | |
| 2017-11-09 | fix typos | Andrew Waterman | 1 | -3/+3 | |
| 2017-09-26 | Generalize an Sv32 sentence to apply to SvXX | Andrew Waterman | 1 | -1/+1 | |
| 2017-09-20 | Clarify mtval; allow platform to specify when it's written | Andrew Waterman | 1 | -7/+13 | |
| 2017-09-13 | Sv48 must imply Sv39 | Andrew Waterman | 1 | -2/+2 | |
| 2017-08-15 | Load address misaligned exceptions *can* occur in S-mode | Andrew Waterman | 1 | -8/+9 | |
| because of the load-reserved instruction. | |||||
| 2017-07-26 | Fix typo in stvec figure | Andrew Waterman | 1 | -1/+1 | |
| Closes #95 | |||||
| 2017-06-12 | Clarify access exception type in page-table walk algorithm | Andrew Waterman | 1 | -2/+3 | |
| 2017-06-12 | Fix word case, typos and word choice | Paul Wise | 1 | -1/+1 | |
| Suggested-by: codespell Suggested-by: spellintian | |||||
| 2017-06-03 | Fix typo | Jacob Bachmeyer | 1 | -1/+1 | |
| 2017-06-03 | Tweak SUM commentary | Andrew Waterman | 1 | -19/+14 | |
| 2017-06-03 | Forbid S-mode execution from user memory | Jacob Bachmeyer | 1 | -4/+25 | |
| 2017-06-03 | Incorporate Allen's feedback | Andrew Waterman | 1 | -4/+6 | |
| 2017-05-15 | Fix some orphaned/widowed commentary sections | Andrew Waterman | 1 | -2/+2 | |
| 2017-05-15 | Add ILEN to simplify descriptions of {m,s}tval CSRs | Jacob Bachmeyer | 1 | -13/+16 | |
| 2017-05-07 | Add stvec vectoring | Andrew Waterman | 1 | -8/+45 | |
| 2017-05-07 | Misaligned superpages generate page-fault exceptions | Andrew Waterman | 1 | -13/+10 | |
| h/t Anthony Coulter | |||||
| 2017-05-06 | Added note about dropping config string for now. Some other cleanups. | Krste Asanovic | 1 | -5/+1 | |
| 2017-05-06 | Fixed some lingering references to bad address register. | Krste Asanovic | 1 | -2/+2 | |
| 2017-05-06 | Cleaned up description of SEIP/UEIP. | Krste Asanovic | 1 | -14/+19 | |
| 2017-05-05 | Attempt to explain SEIP discipline | Andrew Waterman | 1 | -4/+18 | |
| Closes #53 | |||||
| 2017-05-05 | Remove option to hardwire UXL/SXL to 0 | Andrew Waterman | 1 | -4/+7 | |
| 2017-05-05 | PPN LSBs must be clear for superpage PTEs | Andrew Waterman | 1 | -1/+6 | |
| 2017-05-05 | Remove redundant clause in SFENCE.VMA description | Andrew Waterman | 1 | -3/+1 | |
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index : riscv-isa-manual.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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