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AgeCommit message (Expand)AuthorFilesLines
2019-06-21SpellingAndrew Waterman1-1/+1
2019-06-19Add endianness control proposal to priv specAndrew Waterman1-8/+49
2019-04-20Merge pull request #373 from riscv/hellwig-sbiKrste Asanovic1-19/+18
2019-04-20Express stvec alignment constraint more clearlyAndrew Waterman1-5/+4
2019-04-19Don't reference the SBI in normative privileged spec sectionsAndrew Waterman1-19/+18
2019-04-19Remove outdated clause indicating incorrect exception prioritiesAndrew Waterman1-3/+4
2019-04-08Elucidate two uses of the word "error"Andrew Waterman1-1/+3
2019-03-13Improve wording of satp/ASID/caching/speculation paragraphAndrew Waterman1-5/+16
2019-03-08SFENCE.VMA orders visible stores, not just local storesAndrew Waterman1-5/+5
2019-03-07Update mcause/scause tables to allocate some custom exception causesAndrew Waterman1-6/+11
2019-03-07Add software constraint for future global-ASID extensionAndrew Waterman1-0/+16
2019-03-07SFENCE.VMA clarificationsAndrew Waterman1-3/+8
2019-02-28Describe page-table walk speculation and SFENCE use casesAndrew Waterman1-0/+49
2019-02-19tweak A/D bit wordingAndrew Waterman1-1/+1
2019-01-21A/D updates are globally orderedAndrew Waterman1-1/+4
2018-12-20Clarify that PTE updates aren't atomic w.r.t. the ultimate access (#308)Andrew Waterman1-3/+9
2018-12-04Version of priv spec ready for ratification processAndrew Waterman1-1/+1
2018-12-03Mostly remove RV128 from priv spec, for nowAndrew Waterman1-4/+4
2018-12-03S-mode editsAndrew Waterman1-5/+5
2018-12-02Use date-based versioning scheme for priv specAndrew Waterman1-1/+1
2018-11-30Add commentary about MTIP etc. in sip/sieAndrew Waterman1-0/+5
2018-11-27Remove upper bound on stvec.MODE=Vectored alignment, like mtvecAndrew Waterman1-2/+1
2018-11-27Misc. address translation clarificationsAndrew Waterman1-8/+9
2018-11-05Fix spellingAndrew Waterman1-1/+1
2018-11-05The S in SBI stands for supervisorAndrew Waterman1-1/+1
2018-09-24Improving lanuage.Krste Asanovic1-3/+3
2018-09-24Made clear that sepc written on exception or interrupt.Krste Asanovic1-4/+4
2018-09-23unused mip fields are wpri instead of wiriAndrew Waterman1-3/+3
2018-09-10Add ECALL from S-mode cause to SCAUSE tableAndrew Waterman1-2/+3
2018-07-12Add commentary that we favor zero-extension unless SW demands otherwiseAndrew Waterman1-0/+10
2018-07-06Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194)Alexandre Joannou1-2/+4
2018-07-06Explain how addressing works when UXLEN < SXLENAndrew Waterman1-0/+5
2018-04-25SvXX instruction addresses are checked for sign extension, tooAndrew Waterman1-2/+4
2018-04-17Misaligned superpage exception occurs if pte.ppn[i−1:0]!=0Premjith1-1/+1
2018-04-13Remove hyphen from M-XLEN etc.Andrew Waterman1-18/+18
2018-04-13Resolve XLEN vs. S-XLEN ambiguitiesAndrew Waterman1-34/+34
2018-03-30Make it explicit that the page-fault exceptions from address translation corr...Prashanth Mundkur1-5/+8
2018-03-26Clarify that SUM does not permit supervisor execution from user pagesAndrew Waterman1-0/+1
2018-03-21John Hauser's alternative writable-misa.C proposalAndrew Waterman1-2/+8
2018-02-22Fix mepc/sepc definitions w.r.t. IALIGNAndrew Waterman1-3/+2
2017-12-06Constrain all harts to use same A/D-bit management schemeAndrew Waterman1-2/+1
2017-11-09Specify meaning of R/W/X bits in PTEAndrew Waterman1-0/+13
2017-11-09fix typosAndrew Waterman1-3/+3
2017-09-26Generalize an Sv32 sentence to apply to SvXXAndrew Waterman1-1/+1
2017-09-20Clarify mtval; allow platform to specify when it's writtenAndrew Waterman1-7/+13
2017-09-13Sv48 must imply Sv39Andrew Waterman1-2/+2
2017-08-15Load address misaligned exceptions *can* occur in S-modeAndrew Waterman1-8/+9
2017-07-26Fix typo in stvec figureAndrew Waterman1-1/+1
2017-06-12Clarify access exception type in page-table walk algorithmAndrew Waterman1-2/+3
2017-06-12Fix word case, typos and word choicePaul Wise1-1/+1
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