| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-01-20 | Add Zihintntl hints to HINT Instruction tables | Tsukasa OI | 1 | -4/+11 | |
| Compressed design of non-temporal locality hints is chosen to fit all HINT instructions in RV64I to one page (as oversized tables can cause various problems). | |||||
| 2022-01-20 | Remove "no hints are defined" text in RV64I | Tsukasa OI | 1 | -2/+2 | |
| This is a port of rv32.tex in commit ea9410a6a5ea ("Add PAUSE instruction") to rv64.tex. | |||||
| 2020-12-15 | Add FENCE with fm=0, pred or succ=0, and rs1/rd != 0 to HINT table | Andrew Waterman | 1 | -2/+13 | |
| 2020-08-14 | Change "reserved for custom" to "designated for custom" (#566) | John Hauser | 1 | -2/+2 | |
| 2020-05-11 | Improve description of RV64 *W instructions | Andrew Waterman | 1 | -7/+8 | |
| 2020-04-06 | Clarify offset range in RV64I (#501) | Nick Knight | 1 | -3/+3 | |
| Claire Wolf pointed out in email to [isa-dev] that "The 2048 points missing on the higher [end] are "tacked on" on the lower end". This PR adds this detail to the previous commentary. | |||||
| 2020-04-05 | RV64 -> RV64I | Andrew Waterman | 1 | -1/+1 | |
| 2020-04-05 | Add note about AUIPC+JALR range in RV64 | Andrew Waterman | 1 | -0/+6 | |
| 2020-03-03 | Merge pull request #453 from riscv/u-immediate | Krste Asanovic | 1 | -6/+7 | |
| Consistently claim that U-immediate is 32 bits, not 20 bits | |||||
| 2019-11-05 | Improve commentary environment page-break behavior | Andrew Waterman | 1 | -1/+1 | |
| h/t JohnH | |||||
| 2019-10-19 | Consistently claim that U-immediate is 32 bits, not 20 bits | Andrew Waterman | 1 | -6/+7 | |
| The text vacillates between describing the U-immediate as a 20-bit quantity, and as a 32-bit quantity whose lower 12 bits are zero. Standardize on the latter. Note the discrepancy in the ASM syntax. Resolves #452 | |||||
| 2019-05-21 | Adding FENCE to the table of RV64 HINT instructions (#387) | Luís Marques | 1 | -1/+2 | |
| 2019-03-25 | Change "pc" to "address" for clarity | Andrew Waterman | 1 | -3/+3 | |
| Resolves #356 | |||||
| 2019-03-07 | Tweaks suggested by Bill Huffman | Andrew Waterman | 1 | -1/+1 | |
| 2018-11-06 | Bumped base I version number to 2.1 to reflect ratified memory model, ↵ | Krste Asanovic | 1 | -1/+1 | |
| exclusion of fence.i, CSR instructions, and counters. | |||||
| 2018-10-29 | Clarify that most integer instructions operate on XLEN bits in RV64 | Andrew Waterman | 1 | -0/+1 | |
| h/t Olof Kindgren Resolves #247. | |||||
| 2018-08-06 | Cleaned up RV64 chapter to remove platform-specific mandates. | Krste Asanovic | 1 | -8/+11 | |
| 2018-08-06 | Moved CSR instructions into separate chapter. | Krste Asanovic | 1 | -8/+0 | |
| 2018-07-15 | More work on HINTs | Andrew Waterman | 1 | -0/+54 | |
| 2018-07-15 | Fix spelling of "pseudoinstruction" | Andrew Waterman | 1 | -1/+1 | |
| 2018-01-23 | Standardized on pseudoinstruction. | Krste Asanovic | 1 | -2/+2 | |
| Closes #122 | |||||
| 2017-02-01 | Reorganize directory structure | Andrew Waterman | 1 | -0/+253 | |
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index : riscv-isa-manual.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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