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2022-01-20Add Zihintntl hints to HINT Instruction tablesTsukasa OI1-3/+10
Compressed design of non-temporal locality hints is chosen to fit all HINT instructions in RV64I to one page (as oversized tables can cause various problems).
2021-09-30Improve description of FENCE.TSOAndrew Waterman1-5/+4
The description of FENCE.TSO as "optional" was incorrect. It has always been a mandatory instruction (because of the requirement that unused patterns in the fm field be treated as though fm=0).
2021-08-30Revert "Replace "EEI" with "execution environment" (#723)"Andrew Waterman1-19/+14
This reverts commit 8551bd20be39c27f9cead6231c6b6858ec8c2232 at @kasanovic's request.
2021-08-28Replace "EEI" with "execution environment" (#723)John Hauser1-14/+19
Make the manual more correct and consistent by dropping the term _execution environment interface_ and its abbreviation _EEI_ and replacing them everywhere with just _execution environment_.
2021-06-06Clarifying FENCE operation behavior for external devices. (#657)Krste Asanovic1-1/+18
* Clarifying FENCE operation behavior for external devices. * Improved description of FENCE effect on external devices.
2021-05-25Use plural "base ISAs" rather than "base ISA" when appropriateAndrew Waterman1-3/+3
cc @gfavor @kasanovic
2021-05-25Fix capitalization of HINTsAndrew Waterman1-1/+1
2021-02-11Merge pull request #398 from riscv/pauseAndrew Waterman1-12/+37
Add PAUSE hint
2021-01-14Delete duplicate (and now inconsistent) version number given in body text.Krste Asanovic1-2/+1
Closes #618.
2020-12-16Further improve HINT text w.r.t. FENCE HINTsAndrew Waterman1-7/+18
2020-12-15Add FENCE with fm=0, pred or succ=0, and rs1/rd != 0 to HINT tableAndrew Waterman1-7/+17
2020-10-17Update HINT table to indicate PAUSE HINT allocationAndrew Waterman1-3/+7
2020-10-17Add PAUSE instructionAndrew Waterman1-3/+3
2020-10-17fm=0 for FENCE HINTsAndrew Waterman1-1/+2
2020-08-18Remove assembly manualAndrew Waterman1-0/+5
It is to be migrated to https://github.com/riscv/riscv-asm-manual See #540
2020-08-14Change "reserved for custom" to "designated for custom" (#566)John Hauser1-2/+2
2020-08-14Improve table of RAS hints for JALR instructions (#563)John Hauser1-10/+11
2020-07-22Pmp wording fix (#545)Stef O'Rear1-11/+12
* Consistently use "access-fault exception" for PMPs Except for discussions of the xcause code itself which are "access fault". * Clarify behavior of locked TOR PMPs
2020-04-16Make misaligned exception text more generic than RV32Andrew Waterman1-3/+3
2020-04-16Clarify that the EEI defines misaligned FP ld/st behaviorAndrew Waterman1-0/+1
2020-03-03Merge pull request #453 from riscv/u-immediateKrste Asanovic1-3/+6
Consistently claim that U-immediate is 32 bits, not 20 bits
2019-12-24Clarify that access exceptions on jump targets are reported on the targetAndrew Waterman1-0/+4
2019-11-05Improve commentary environment page-break behaviorAndrew Waterman1-1/+0
h/t JohnH
2019-10-22Add platform note about UNSPECIFIED behavior decoding reserved opcodesAndrew Waterman1-0/+6
2019-10-22Merge branch 'unspecified' of ↵Andrew Waterman1-0/+2
https://github.com/pdonahue-ventana/riscv-isa-manual into pdonahue-ventana-unspecified
2019-10-19Consistently claim that U-immediate is 32 bits, not 20 bitsAndrew Waterman1-3/+6
The text vacillates between describing the U-immediate as a 20-bit quantity, and as a 32-bit quantity whose lower 12 bits are zero. Standardize on the latter. Note the discrepancy in the ASM syntax. Resolves #452
2019-10-14Describe what we mean by endiannessAndrew Waterman1-3/+23
2019-10-02Use effective address consistentlyAndrew Waterman1-1/+1
2019-09-06Remove outdated commentaryAndrew Waterman1-1/+1
There's no reason for simple pedagogical implementations to trap FENCE; they can probably just execute it as a NOP. (In situations where that statement is false, the implementation isn't simple!) I think the sentence was written with FENCE.I in mind, but since that instruction has been moved to an extension, the sentence doesn't apply in this context anymore.
2019-07-30Use consistent terms for exception typesAndrew Waterman1-1/+1
@jscheid-ventana originally contributed this, but I tweaked the hyphenation. Resolves #422
2019-06-21Changes to unprivileged spec for bi[g]-endian supportAndrew Waterman1-1/+2
2019-06-21Fix bad RV32I chapter formattingAndrew Waterman1-48/+48
2019-05-04Typos (#379)Alexandre Joannou1-1/+1
* Fix typo ">" to "$>$" * typo of -> on
2019-05-03Added UNSPECIFIEDPaul Donahue1-1/+1
2019-05-01Introduce the term UNSPECIFIED.Paul Donahue1-0/+2
2019-03-25Change "pc" to "address" for clarityAndrew Waterman1-3/+4
Resolves #356
2019-03-07Restate FENCE.TSO constraints from Table 2.1 in the textAndrew Waterman1-1/+3
2019-03-04Fix formattingAndrew Waterman1-3/+3
Closes #349
2019-02-07Fix typos. (#337)Josh Scheid1-1/+1
2019-01-21Fix typo. (#326)Prashanth Mundkur1-1/+1
2018-12-21tweaksAndrew Waterman1-1/+1
2018-12-20tweaksAndrew Waterman1-4/+5
2018-12-20Merge pull request #311 from brucehoult/ra-sp-cleanupKrste Asanovic1-6/+22
Clean up description of x registers. Add commentary about ABI
2018-12-20ABIs could dedicate other JALR base registersAndrew Waterman1-1/+3
Closes #309
2018-12-20Clean up description of x registers. Add commentary about ABIBruce Hoult1-6/+22
2018-12-19Update commentary to reflect MIPS r6 conditional branchesBruce Hoult1-2/+2
2018-12-13Make branch immediate description more similar to jumpsAndrew Waterman1-2/+3
Closes #306 h/t @wdc-pnl
2018-12-11Restate that conditional branches can raise misaligned exceptions in RVIAndrew Waterman1-0/+12
This is a bit redundant, since we state this at the front of the chapter. But since we also restate it for JAL/JALR, it's better to maintain symmetry and restate it for branches, too. Closes #303 h/t @benjaminselfridge
2018-11-26Add FENCE to HINT tableAndrew Waterman1-1/+2
2018-11-09WFI is not a HINTAndrew Waterman1-2/+1
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