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rv32.tex
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Author
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Lines
2019-03-25
Change "pc" to "address" for clarity
Andrew Waterman
1
-3
/
+4
2019-03-07
Restate FENCE.TSO constraints from Table 2.1 in the text
Andrew Waterman
1
-1
/
+3
2019-03-04
Fix formatting
Andrew Waterman
1
-3
/
+3
2019-02-07
Fix typos. (#337)
Josh Scheid
1
-1
/
+1
2019-01-21
Fix typo. (#326)
Prashanth Mundkur
1
-1
/
+1
2018-12-21
tweaks
Andrew Waterman
1
-1
/
+1
2018-12-20
tweaks
Andrew Waterman
1
-4
/
+5
2018-12-20
Merge pull request #311 from brucehoult/ra-sp-cleanup
Krste Asanovic
1
-6
/
+22
2018-12-20
ABIs could dedicate other JALR base registers
Andrew Waterman
1
-1
/
+3
2018-12-20
Clean up description of x registers. Add commentary about ABI
Bruce Hoult
1
-6
/
+22
2018-12-19
Update commentary to reflect MIPS r6 conditional branches
Bruce Hoult
1
-2
/
+2
2018-12-13
Make branch immediate description more similar to jumps
Andrew Waterman
1
-2
/
+3
2018-12-11
Restate that conditional branches can raise misaligned exceptions in RVI
Andrew Waterman
1
-0
/
+12
2018-11-26
Add FENCE to HINT table
Andrew Waterman
1
-1
/
+2
2018-11-09
WFI is not a HINT
Andrew Waterman
1
-2
/
+1
2018-11-06
Bumped base I version number to 2.1 to reflect ratified memory model, exclusi...
Krste Asanovic
1
-1
/
+1
2018-11-06
Moved zifencetso back into main I chapter, as does not extend base ISA spec.
Krste Asanovic
1
-0
/
+17
2018-11-05
Allowed certain un-emulatable misaligned accesses to be reported with access ...
Krste Asanovic
1
-7
/
+10
2018-11-04
Moved FENCE.I out of base I chapter into separate Zifencei chapter.
Krste Asanovic
1
-72
/
+9
2018-11-03
Moved fence.tso out of base ISA chapter and into separate chapter.
Krste Asanovic
1
-17
/
+1
2018-11-03
Clarified language around action of execution environment with misaligned-add...
Krste Asanovic
1
-6
/
+8
2018-10-04
Add marchid management document (#234)
Andrew Waterman
1
-1
/
+1
2018-08-25
Add semihosting note
Andrew Waterman
1
-0
/
+4
2018-08-12
Minor tweaks
Andrew Waterman
1
-2
/
+2
2018-08-06
Clarified FENCE.TSO under base implementation.
Krste Asanovic
1
-5
/
+17
2018-08-06
Moved CSR instructions into separate chapter.
Krste Asanovic
1
-338
/
+110
2018-08-05
Provide new description of misaligned load/store behavior compatible with pri...
Krste Asanovic
1
-23
/
+49
2018-08-05
Minor cleanups and clarifications.
Krste Asanovic
1
-34
/
+44
2018-08-05
Moved XLEN definition to intro.
Krste Asanovic
1
-3
/
+1
2018-07-29
Minor clarifications.
Krste Asanovic
1
-11
/
+13
2018-07-29
Clarified that AUIPC uses PC of AUIPC instruction itself.
Krste Asanovic
1
-10
/
+12
2018-07-29
Provide explanation for multiple base ISAs, and ADD/ADDW discrepancy.
Krste Asanovic
1
-0
/
+10
2018-07-16
Updates to HINT sections.
Krste Asanovic
1
-14
/
+19
2018-07-15
More work on HINTs
Andrew Waterman
1
-9
/
+9
2018-07-15
Fix spelling of "pseudoinstruction"
Andrew Waterman
1
-3
/
+3
2018-07-15
Add section on RV32I HINTs
Andrew Waterman
1
-0
/
+63
2018-07-09
Make JALR assembly format consistent with binutils (#209)
Andrew Waterman
1
-2
/
+2
2018-07-06
Merge branch 'misc-fixes' of https://github.com/tymcauley/riscv-isa-manual in...
Andrew Waterman
1
-2
/
+2
2018-06-26
Clarification of NOP description
wdc-pnl
1
-2
/
+4
2018-06-20
Clarify reserved FENCE.TSO settings, per #186
Daniel Lustig
1
-4
/
+7
2018-06-16
Fixed instruction formatting error in rv32.tex.
Tynan McAuley
1
-1
/
+1
2018-06-16
Fixed register name formatting error in rv32.tex.
Tynan McAuley
1
-1
/
+1
2018-06-06
Clarify sign-extension of offsets in assembly manual
Andrew Waterman
1
-2
/
+2
2018-05-30
Hyphenate "instruction set" when it's part of a noun phrase
Andrew Waterman
1
-2
/
+2
2018-05-08
Specify operand order for sub instruction (#172)
Alexandre Joannou
1
-3
/
+4
2018-05-02
Updates to the memory consistency model spec
Daniel Lustig
1
-235
/
+37
2018-02-27
Added commentary on counter/timers.
Krste Asanovic
1
-1
/
+64
2018-02-09
Added clearer definitions of execution environments and harts.
Krste Asanovic
1
-0
/
+6
2018-02-08
Clarify description of unused FENCE bits
Andrew Waterman
1
-4
/
+4
2018-01-23
Standardized on pseudoinstruction.
Krste Asanovic
1
-11
/
+11
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