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path: root/src/rv32.tex
AgeCommit message (Expand)AuthorFilesLines
2018-12-19Update commentary to reflect MIPS r6 conditional branchesBruce Hoult1-2/+2
2018-12-13Make branch immediate description more similar to jumpsAndrew Waterman1-2/+3
2018-12-11Restate that conditional branches can raise misaligned exceptions in RVIAndrew Waterman1-0/+12
2018-11-26Add FENCE to HINT tableAndrew Waterman1-1/+2
2018-11-09WFI is not a HINTAndrew Waterman1-2/+1
2018-11-06Bumped base I version number to 2.1 to reflect ratified memory model, exclusi...Krste Asanovic1-1/+1
2018-11-06Moved zifencetso back into main I chapter, as does not extend base ISA spec.Krste Asanovic1-0/+17
2018-11-05Allowed certain un-emulatable misaligned accesses to be reported with access ...Krste Asanovic1-7/+10
2018-11-04Moved FENCE.I out of base I chapter into separate Zifencei chapter.Krste Asanovic1-72/+9
2018-11-03Moved fence.tso out of base ISA chapter and into separate chapter.Krste Asanovic1-17/+1
2018-11-03Clarified language around action of execution environment with misaligned-add...Krste Asanovic1-6/+8
2018-10-04Add marchid management document (#234)Andrew Waterman1-1/+1
2018-08-25Add semihosting noteAndrew Waterman1-0/+4
2018-08-12Minor tweaksAndrew Waterman1-2/+2
2018-08-06Clarified FENCE.TSO under base implementation.Krste Asanovic1-5/+17
2018-08-06Moved CSR instructions into separate chapter.Krste Asanovic1-338/+110
2018-08-05Provide new description of misaligned load/store behavior compatible with pri...Krste Asanovic1-23/+49
2018-08-05Minor cleanups and clarifications.Krste Asanovic1-34/+44
2018-08-05Moved XLEN definition to intro.Krste Asanovic1-3/+1
2018-07-29Minor clarifications.Krste Asanovic1-11/+13
2018-07-29Clarified that AUIPC uses PC of AUIPC instruction itself.Krste Asanovic1-10/+12
2018-07-29Provide explanation for multiple base ISAs, and ADD/ADDW discrepancy.Krste Asanovic1-0/+10
2018-07-16Updates to HINT sections.Krste Asanovic1-14/+19
2018-07-15More work on HINTsAndrew Waterman1-9/+9
2018-07-15Fix spelling of "pseudoinstruction"Andrew Waterman1-3/+3
2018-07-15Add section on RV32I HINTsAndrew Waterman1-0/+63
2018-07-09Make JALR assembly format consistent with binutils (#209)Andrew Waterman1-2/+2
2018-07-06Merge branch 'misc-fixes' of https://github.com/tymcauley/riscv-isa-manual in...Andrew Waterman1-2/+2
2018-06-26Clarification of NOP descriptionwdc-pnl1-2/+4
2018-06-20Clarify reserved FENCE.TSO settings, per #186Daniel Lustig1-4/+7
2018-06-16Fixed instruction formatting error in rv32.tex.Tynan McAuley1-1/+1
2018-06-16Fixed register name formatting error in rv32.tex.Tynan McAuley1-1/+1
2018-06-06Clarify sign-extension of offsets in assembly manualAndrew Waterman1-2/+2
2018-05-30Hyphenate "instruction set" when it's part of a noun phraseAndrew Waterman1-2/+2
2018-05-08Specify operand order for sub instruction (#172)Alexandre Joannou1-3/+4
2018-05-02Updates to the memory consistency model specDaniel Lustig1-235/+37
2018-02-27Added commentary on counter/timers.Krste Asanovic1-1/+64
2018-02-09Added clearer definitions of execution environments and harts.Krste Asanovic1-0/+6
2018-02-08Clarify description of unused FENCE bitsAndrew Waterman1-4/+4
2018-01-23Standardized on pseudoinstruction.Krste Asanovic1-11/+11
2017-12-12Add memory consistency model draft proposalAndrew Waterman1-174/+365
2017-12-06Add commentary that FENCE.I doesn't work for migrated threadsAndrew Waterman1-0/+7
2017-09-20Remove potential ambiguity in JALR commentaryAndrew Waterman1-2/+2
2017-07-27Make RV32 SRAI description match RV64Andrew Waterman1-1/+1
2017-06-26Change remaining SCALL/SBREAK reference to ECALL/EBREAKsal1-1/+1
2017-05-19Clarify RAS pop-push orderingAndrew Waterman1-2/+2
2017-05-07SB/UJ -> B/JAndrew Waterman1-3/+3
2017-05-07Actioned Robert Watson's feedback.Krste Asanovic1-43/+50
2017-05-06Updated to define and use hart more consistently.Krste Asanovic1-37/+55
2017-04-25Clean up JALR hint textAndrew Waterman1-6/+8
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