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AgeCommit message (Expand)AuthorFilesLines
2018-11-27Add Hauser's definition of "memory access"Andrew Waterman1-1/+1
2018-11-06spelling20181106-Base-RatificationAndrew Waterman1-1/+1
2018-11-06Version ready for ratification process.Krste Asanovic1-16/+11
2018-11-06Updated status of counters. Not ready for ratification as there are issues o...Krste Asanovic1-1/+5
2018-11-06Allow access exceptions to be reported on misaligned atomic memory operations...Krste Asanovic1-0/+2
2018-11-06Bumped base I version number to 2.1 to reflect ratified memory model, exclusi...Krste Asanovic1-2/+6
2018-11-06Moved zifencetso back into main I chapter, as does not extend base ISA spec.Krste Asanovic1-2/+0
2018-11-06Gave CSR instruction module a name and a version, and made clear these are be...Krste Asanovic1-3/+4
2018-11-05Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-13/+13
2018-11-05Update preface for unemulatable misaligned excpetions reported as access exce...Krste Asanovic1-1/+2
2018-11-05tweaksAndrew Waterman1-11/+11
2018-11-05Fix spellingAndrew Waterman1-2/+2
2018-11-04Moved FENCE.I out of base I chapter into separate Zifencei chapter.Krste Asanovic1-32/+47
2018-11-04Made clear fence.tso is an optional extensionKrste Asanovic1-2/+2
2018-11-03Removed text regarding big or bi-endian operation. For now, only specifying ...Krste Asanovic1-0/+2
2018-08-28F/D extensions to v2.2Andrew Waterman1-2/+6
2018-08-26Updated several "user" references to "unprivileged".Krste Asanovic1-6/+7
2018-08-07Made cleanup pass over floating-point extensionsKrste Asanovic1-1/+4
2018-08-07Broke out actual perf counters into separate chapter.Krste Asanovic1-1/+1
2018-08-06Cleaned up RV64 chapter to remove platform-specific mandates.Krste Asanovic1-0/+7
2018-08-05Provide new description of misaligned load/store behavior compatible with pri...Krste Asanovic1-1/+8
2018-08-05update preface.Krste Asanovic1-1/+2
2018-07-06Changes to intro as part of rationalizing ISA into ISA-only versus platform-m...Krste Asanovic1-2/+7
2018-05-30Hyphenate "instruction set" when it's part of a noun phraseAndrew Waterman1-2/+2
2018-05-02Tweaks to prefaceAndrew Waterman1-3/+3
2018-05-02Updates to the memory consistency model specDaniel Lustig1-3/+6
2018-03-21John Hauser's alternative writable-misa.C proposalAndrew Waterman1-0/+2
2018-02-09Added clearer definitions of execution environments and harts.Krste Asanovic1-1/+4
2018-01-23Clarified when mip/mie bits are hardwired to zero when user mode present.Krste Asanovic1-1/+1
2017-12-12Describe optional support for misaligned AMOs (#117)Andrew Waterman1-0/+3
2017-11-09fix typosAndrew Waterman1-2/+2
2017-06-05FMIN/FMAX now implement minimumNumber/maximumNumber, not minNum/maxNumAndrew Waterman1-1/+53
2017-05-07C -> 2.0Andrew Waterman1-1/+2
2017-05-06Forgot to add note to preface.Krste Asanovic1-3/+5
2017-05-05Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-1/+2
2017-05-03Moved chapters into canonical extension listing order.Krste Asanovic1-1/+1
2017-05-03Added note indicating that the P extension might be reworkedKrste Asanovic1-0/+3
2017-05-03Reordered chapters to be somewhat more logical.Krste Asanovic1-1/+2
2017-05-03Changed front page of spec to follow move to Creative Commons License.Krste Asanovic1-0/+4
2017-04-25Clean up JALR hint textAndrew Waterman1-1/+1
2017-04-24Modified behavior of JALR hint bits to better support macro-op fusion of LUI;...Krste Asanovic1-0/+2
2017-04-16Define the behavior of FMA(inf, 0, qNaN)Andrew Waterman1-0/+1
2017-04-13Renamed FMV.X.S/S.X to FMV.X.W/W.X to be more consistent with load/store inst...Krste Asanovic1-1/+5
2017-04-13Added the NaN-boxing scheme for narrower floating-point values held in wider ...Krste Asanovic1-2/+3
2017-03-01Added placeholder for J extension.Krste Asanovic1-0/+1
2017-02-02Clarify behavior of FCSR MSBsAndrew Waterman1-0/+1
2017-02-02Remove calling convention chapterAndrew Waterman1-0/+2
2017-02-01Reorganize directory structureAndrew Waterman1-0/+154
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